HEF4027BT,653 [NXP]
HEF4027B - Dual JK flip-flop SOP 16-Pin;型号: | HEF4027BT,653 |
厂家: | NXP |
描述: | HEF4027B - Dual JK flip-flop SOP 16-Pin 光电二极管 逻辑集成电路 触发器 |
文件: | 总14页 (文件大小:104K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
HEF4027B
Dual JK flip-flop
Rev. 9 — 18 November 2011
Product data sheet
1. General description
The HEF4027B is a edge-triggered dual JK flip-flop which features independent set-direct
(SD), clear-direct (CD), clock (CP) inputs and outputs (Q, Q). Data is accepted when CP is
LOW, and transferred to the output on the positive-going edge of the clock. The active
HIGH asynchronous clear-direct (CD) and set-direct (SD) inputs are independent and
override the J, K, and CP inputs. The outputs are buffered for best system performance.
Schmitt trigger action makes the clock input highly tolerant of slower rise and fall times.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
2. Features and benefits
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Specified from 40 C to +85 C
Complies with JEDEC standard JESD 13-B
3. Applications
Registers
Counters
Control circuits
4. Ordering information
Table 1.
Ordering information
Tamb from 40 C to +85 C.
Type number
Package
Name
Description
Version
HEF4027BP
HEF4027BT
DIP16
SO16
plastic dual in-line package; 16 leads (300 mil)
plastic small outline package; 16 leads; body width 3.9 mm
SOT38-4
SOT109-1
HEF4027B
NXP Semiconductors
Dual JK flip-flop
5. Functional diagram
FF 1
1SD
9
10
13
11
1J
1Q
1Q
15
14
1CP
1K
1CD
12
7
FF 2
2SD
6
3
5
2J
2Q
2Q
1
2
2CP
2K
2CD
4
001aae593
Fig 1. Functional diagram
CP
Q
C
C
C
C
C
C
C
C
C
J
C
Q
K
CD
SD
001aae595
Fig 2. Logic diagram of one flip-flop
HEF4027B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 9 — 18 November 2011
2 of 14
HEF4027B
NXP Semiconductors
Dual JK flip-flop
6. Pinning information
6.1 Pinning
HEF4027B
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
2Q
2Q
V
DD
1Q
2CP
2CD
2K
1Q
1CP
1CD
1K
2J
2SD
1J
V
SS
1SD
001aae594
Fig 3. Pin configuration
6.2 Pin description
Table 2.
Symbol
VSS
Pin description
Pin
Description
ground supply voltage
8
1SD, 2SD
1J, 2J
9, 7
10, 6
11, 5
12, 4
13, 3
14, 2
15, 1
16
asynchronous set-direct input (active HIGH)
synchronous input
1K, 2K
1CD, 2CD
1CP, 2CP
1Q, 2Q
1Q, 2Q
VDD
synchronous input
asynchronous clear-direct input (active HIGH)
clock input (LOW-to-HIGH edge-triggered)
complement output
true output
supply voltage
7. Functional description
Table 3.
Function table[1]
Inputs
Outputs
nQ
nSD
H
nCD
L
nCP
X
nJ
X
nK
X
nQ
L
H
L
L
H
X
X
X
H
H
H
X
X
X
H
H
HEF4027B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 9 — 18 November 2011
3 of 14
HEF4027B
NXP Semiconductors
Dual JK flip-flop
Table 3.
Function table[1] …continued
Inputs
Outputs
nSD
nCD
nCP
nJ
L
nK
L
nQ
nQ
L
L
L
L
L
L
L
L
no change
no change
H
L
L
H
L
H
H
L
H
H
nQ
nQ
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.; = positive-going transition.
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDD
IIK
Parameter
Conditions
Min
0.5
-
Max
Unit
V
supply voltage
+18
input clamping current
input voltage
VI < 0.5 V or VI > VDD + 0.5 V
VO < 0.5 V or VO > VDD + 0.5 V
10
mA
V
VI
0.5
-
VDD + 0.5
10
IOK
output clamping current
input/output current
supply current
mA
mA
mA
C
II/O
-
10
IDD
-
50
Tstg
Tamb
Ptot
storage temperature
ambient temperature
total power dissipation
65
40
+150
+85
in free air
C
Tamb 40 C to +85 C
DIP16 package
SO16 package
per output
[1]
[2]
-
-
-
750
500
100
mW
mW
mW
P
power dissipation
[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C.
[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
9. Recommended operating conditions
Table 5.
Symbol
VDD
Recommended operating conditions
Parameter
Conditions
Min
Max
15
Unit
V
supply voltage
3
VI
input voltage
0
VDD
+85
3.75
0.5
V
Tamb
ambient temperature
input transition rise and fall rate
in free air
40
C
t/V
VDD = 5 V
VDD = 10 V
VDD = 15 V
-
-
-
s/V
s/V
s/V
0.08
HEF4027B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 9 — 18 November 2011
4 of 14
HEF4027B
NXP Semiconductors
Dual JK flip-flop
10. Static characteristics
Table 6.
Static characteristics
VSS = 0 V; VI = VSS or VDD; unless otherwise specified.
Symbol Parameter
Conditions
VDD
Tamb = 40 C Tamb = 25 C Tamb = 85 C Unit
Min
Max
-
Min
Max
-
Min
Max
VIH
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
LOW-level output voltage
HIGH-level output current
IO < 1 A
5 V
10 V
15 V
5 V
3.5
3.5
3.5
-
-
V
V
V
V
V
V
V
V
V
V
V
V
7.0
-
7.0
-
7.0
11.0
-
11.0
-
11.0
-
VIL
IO < 1 A
IO < 1 A
IO < 1 A
-
1.5
3.0
4.0
-
-
1.5
3.0
4.0
-
-
1.5
3.0
4.0
-
10 V
15 V
5 V
-
-
-
-
-
-
VOH
VOL
IOH
4.95
4.95
4.95
10 V
15 V
5 V
9.95
-
9.95
-
9.95
-
14.95
-
14.95
-
14.95
-
-
0.05
0.05
0.05
1.7
0.52
1.3
3.6
-
-
0.05
0.05
0.05
1.4
0.44
1.1
3.0
-
-
0.05
0.05
0.05
10 V
15 V
5 V
-
-
-
-
-
-
VO = 2.5 V
VO = 4.6 V
VO = 9.5 V
VO = 13.5 V
VO = 0.4 V
VO = 0.5 V
VO = 1.5 V
-
-
-
1.1 mA
0.36 mA
0.9 mA
2.4 mA
5 V
-
-
-
10 V
15 V
5 V
-
-
-
-
-
-
IOL
LOW-level output current
0.52
0.44
0.36
-
-
-
mA
mA
mA
10 V
15 V
15 V
5 V
1.3
-
1.1
-
0.9
3.6
-
3.0
-
2.4
II
input leakage current
supply current
-
-
-
-
-
0.3
4.0
8.0
16.0
-
-
-
-
-
-
0.3
4.0
8.0
16.0
7.5
-
-
-
-
-
1.0 A
IDD
IO = 0 A
30
60
A
A
10 V
15 V
-
120 A
pF
CI
input capacitance
-
HEF4027B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 9 — 18 November 2011
5 of 14
HEF4027B
NXP Semiconductors
Dual JK flip-flop
11. Dynamic characteristics
Table 7.
Dynamic characteristics
VSS = 0 V; Tamb = 25 C; for test circuit see Figure 7; unless otherwise specified.
Symbol Parameter
tPHL HIGH to LOW
Conditions
CP Q, Q;
VDD
5 V
Extrapolation formula[1]
78 ns + (0.55 ns/pF)CL
29 ns + (0.23 ns/pF)CL
22 ns + (0.16 ns/pF)CL
93 ns + (0.55 ns/pF)CL
33 ns + (0.23 ns/pF)CL
27 ns + (0.16 ns/pF)CL
113 ns + (0.55 ns/pF)CL
44 ns + (0.23 ns/pF)CL
32 ns + (0.16 ns/pF)CL
58 ns + (0.55 ns/pF)CL
27 ns + (0.23 ns/pF)CL
22 ns + (0.16 ns/pF)CL
48 ns + (0.55 ns/pF)CL
24 ns + (0.23 ns/pF)CL
17 ns + (0.16 ns/pF)CL
43 ns + (0.55 ns/pF)CL
19 ns + (0.23 ns/pF)CL
17 ns + (0.16 ns/pF)CL
10 ns + (1.00 ns/pF)CL
9 ns + (0.42 ns/pF)CL
6 ns + (0.28 ns/pF)CL
Min
Typ
105
40
30
120
45
35
140
55
40
85
35
30
75
35
25
70
30
25
60
30
20
25
10
5
Max
210
80
60
240
90
70
280
110
80
170
70
60
150
70
50
140
60
50
120
60
40
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
propagation delay see Figure 4
10 V
15 V
5 V
-
-
CD Q;
see Figure 4
-
10 V
15 V
5 V
-
-
SD Q;
see Figure 4
-
10 V
15 V
5 V
-
-
tPLH
LOW to HIGH
CP Q, Q;
-
propagation delay see Figure 4
10 V
15 V
5 V
-
-
CD Q;
see Figure 4
-
10 V
15 V
5 V
-
-
SD Q;
see Figure 4
-
10 V
15 V
5 V
-
-
[2]
tt
transition time
set-up time
hold time
see Figure 4
-
10 V
15 V
5 V
-
-
tsu
J, K CP;
see Figure 5
50
30
20
25
20
15
80
30
24
90
40
30
+20
+15
+10
10 V
15 V
5 V
-
-
th
J, K CP;
see Figure 5
0
-
10 V
15 V
5 V
0
-
5
-
tW
pulse width
CP LOW;
minimum width
see Figure 5
40
15
12
45
20
15
15
10
5
-
10 V
15 V
5 V
-
-
SD, CD HIGH;
minimum width
see Figure 6
-
10 V
15 V
5 V
-
-
trec
recovery time
SD, CD inputs;
see Figure 6
-
10 V
15 V
-
-
HEF4027B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 9 — 18 November 2011
6 of 14
HEF4027B
NXP Semiconductors
Dual JK flip-flop
Table 7.
Dynamic characteristics …continued
VSS = 0 V; Tamb = 25 C; for test circuit see Figure 7; unless otherwise specified.
Symbol Parameter
Conditions
VDD
5 V
Extrapolation formula[1]
Min
4
Typ
8
Max
Unit
MHz
MHz
MHz
fmax
maximum
frequency
CP input;
J = K = HIGH;
see Figure 5
-
-
-
10 V
15 V
12
15
25
30
[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).
[2] tt is the same as tTLH and tTHL
.
Table 8.
Dynamic power dissipation PD
PD can be calculated from the formulas shown. VSS = 0 V; tr = tf 20 ns; Tamb = 25 C.
Symbol
Parameter
VDD
5 V
Typical formula for PD (W)
PD = 900 fi + (fo CL) VDD
Where:
2
PD
dynamic power
dissipation
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
2
10 V
15 V
PD = 4500 fi + (fo CL) VDD
2
PD = 13200 fi + (fo CL) VDD
VDD = supply voltage in V;
(fo CL) = sum of the outputs.
12. Waveforms
t
t
f
r
V
I
90 %
SD, CD or CP
INPUT
V
M
10 %
0 V
t
t
PHL
PLH
V
OH
90 %
Q or Q
OUTPUT
V
M
10 %
V
OL
t
t
TLH
THL
001aah863
VOH and VOL are typical output voltages levels that occur with the output load.
Measurement points are given in Table 9.
Fig 4. Waveforms showing rise, fall and transition times and propagation delays
1/f
max
t
W
CP INPUT
V
M
t
h
J,K INPUT
V
M
t
su
001aae596
Measurement points are given in Table 9.
Fig 5. Waveforms showing set-up and hold times and minimum clock pulse width
HEF4027B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 9 — 18 November 2011
7 of 14
HEF4027B
NXP Semiconductors
Dual JK flip-flop
V
I
SD INPUT
0 V
V
M
t
W
V
I
V
CD INPUT
0 V
M
t
W
t
t
rec
rec
V
I
CP INPUT
0 V
V
M
V
OH
Q OUTPUT
V
OL
001aae597
VOH and VOL are typical output voltages levels that occur with the output load.
Measurement points are given in Table 9.
Fig 6. Waveforms showing pulse widths and recovery times
Table 9.
Measurement points
Supply voltage
VDD
Input
VM
Output
VM
5 V to 15 V
0.5VDD
0.5VDD
V
DD
V
V
O
I
G
DUT
C
L
R
T
001aag182
Test data is given in Table 10.
Definitions for test circuit:
DUT = Device Under Test.
CL = load capacitance including jig and probe capacitance.
RT = termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig 7. Test circuit
Table 10. Test data
Supply voltage
VDD
Input
Load
CL
VI
tr, tf
5 V to 15 V
VSS or VDD
20 ns
50 pF
HEF4027B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 9 — 18 November 2011
8 of 14
HEF4027B
NXP Semiconductors
Dual JK flip-flop
13. Package outline
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
b
2
16
9
M
H
pin 1 index
E
1
8
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
Z
A
A
A
2
(1)
(1)
1
w
UNIT
mm
b
b
b
c
D
E
e
e
L
M
M
H
1
2
1
E
max.
min.
max.
max.
1.73
1.30
0.53
0.38
1.25
0.85
0.36
0.23
19.50
18.55
6.48
6.20
3.60
3.05
8.25
7.80
10.0
8.3
4.2
0.51
3.2
2.54
0.1
7.62
0.3
0.254
0.01
0.76
0.068 0.021 0.049 0.014
0.051 0.015 0.033 0.009
0.77
0.73
0.26
0.24
0.14
0.12
0.32
0.31
0.39
0.33
inches
0.17
0.02
0.13
0.03
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
95-01-14
03-02-13
SOT38-4
Fig 8. Package outline SOT38-4 (DIP16)
HEF4027B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 9 — 18 November 2011
9 of 14
HEF4027B
NXP Semiconductors
Dual JK flip-flop
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
v
c
y
H
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT109-1
076E07
MS-012
Fig 9. Package outline SOT109-1 (SO16)
HEF4027B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 9 — 18 November 2011
10 of 14
HEF4027B
NXP Semiconductors
Dual JK flip-flop
14. Revision history
Table 11. Revision history
Document ID
HEF4027B v.9
Modifications:
Release date
20111118
Data sheet status
Change notice
Supersedes
Product data sheet
-
HEF4027B v.8
• Legal pages updated.
• Changes in “General description” and “Features and benefits”.
HEF4027B v.8
20111010
20091125
20090624
20081110
20080703
19950101
19950101
Product data sheet
Product data sheet
Product data sheet
Product data sheet
Product specification
Product specification
Product specification
-
-
-
-
-
-
-
HEF4027B v.7
HEF4027B v.6
HEF4027B v.5
HEF4027B v.4
HEF4027B_CNV v.3
HEF4027B_CNV v.2
-
HEF4027B v.7
HEF4027B v.6
HEF4027B v.5
HEF4027B v.4
HEF4027B_CNV v.3
HEF4027B_CNV v.2
HEF4027B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 9 — 18 November 2011
11 of 14
HEF4027B
NXP Semiconductors
Dual JK flip-flop
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
15.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
15.3 Disclaimers
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
HEF4027B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 9 — 18 November 2011
12 of 14
HEF4027B
NXP Semiconductors
Dual JK flip-flop
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
HEF4027B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 9 — 18 November 2011
13 of 14
HEF4027B
NXP Semiconductors
Dual JK flip-flop
17. Contents
1
2
3
4
5
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 11
8
9
10
11
12
13
14
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 12
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 13
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 18 November 2011
Document identifier: HEF4027B
相关型号:
HEF4027BT-Q100,118
J-K Flip-Flop, 4000/14000/40000 Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO16
NXP
HEF4027BT-T
IC 4000/14000/40000 SERIES, DUAL POSITIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, 3.90 MM, PLASTIC, MS-012, SOT109-1, SOP-16, FF/Latch
NXP
HEF4028BDB
IC 4000/14000/40000 SERIES, DECIMAL DECODER/DRIVER, TRUE OUTPUT, CDIP16, Decoder/Driver
NXP
HEF4028BDF
IC 4000/14000/40000 SERIES, DECIMAL DECODER/DRIVER, TRUE OUTPUT, CDIP16, CERAMIC, DIP-16, Decoder/Driver
NXP
©2020 ICPDF网 联系我们和版权申明