HEF4049BP.652 [NXP]
Hex inverting buffers; HEX反相缓冲器
| 型号： | HEF4049BP.652 |
| 厂家： | 
NXP |
| 描述： | Hex inverting buffers |
| 文件： | 总12页 (文件大小：141K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HEF4049B
Hex inverting buffers
Rev. 9 — 18 November 2011
Product data sheet
1. General description
The HEF4049B provides six inverting buffers with high current output capability suitable
for driving TTL or high capacitive loads. Since input voltages in excess of the buffers’
supply voltage are permitted, the buffers may also be used to convert logic levels of up to
15 V to standard TTL levels. Their guaranteed fan-out into common bipolar logic elements
is shown in Table 3.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
2. Features and benefits
Accepts input voltages in excess of the supply voltage
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Specified from 40 C to +85 C
Complies with JEDEC standard JESD 13-B
3. Applications
LOCMOS (Local Oxidation CMOS) to DTL/TTL converter
HIGH sink current for driving two TTL loads
HIGH-to-LOW level logic conversion
4. Ordering information
Table 1.
Ordering information
All types operate from 40 C to +85 C.
Type number
Package
Name
Description
Version
HEF4049BP
HEF4049BT
DIP16
SO16
plastic dual in-line package; 16 leads (300 mil)
plastic small outline package; 16 leads; body width 3.9 mm
SOT38-4
SOT109-1
HEF4049B
NXP Semiconductors
Hex inverting buffers
5. Functional diagram
3
2
4
1A
2A
3A
4A
5A
6A
1Y
2Y
3Y
4Y
5Y
6Y
5
7
6
9
10
12
15
11
14
input
Y
A
V
SS
001aai331
mna341
001aae604
Fig 1. Logic symbol
Fig 2. Logic diagram for one gate
Fig 3. Input protection circuit
6. Pinning information
6.1 Pinning
HEF4049B
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
n.c.
6Y
6A
n.c.
5Y
5A
4Y
4A
DD
1Y
1A
2Y
2A
3Y
3A
V
SS
001aae602
Fig 4. Pin configuration
6.2 Pin description
Table 2.
Symbol
VDD
Pin description
Pin
Description
supply voltage
output
1
1Y to 6Y
2, 4, 6, 10, 12, 15
HEF4049B
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 9 — 18 November 2011
2 of 12
HEF4049B
NXP Semiconductors
Hex inverting buffers
Table 2.
Symbol
1A to 6A
VSS
Pin description …continued
Pin
Description
input
3, 5, 7, 9, 11, 14
8
ground supply voltage
not connected
n.c.
13, 16
7. Functional description
Table 3.
Guaranteed fan-out
Driven element
Standard TTL
74 LS
Guaranteed fan-out
2
9
74 L
16
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDD
IIK
Parameter
Conditions
Min
0.5
-
Max
Unit
V
supply voltage
+18
input clamping current
input voltage
VI < 0.5 V or VI > VDD + 0.5 V
VO < 0.5 V or VO > VDD + 0.5 V
10
mA
V
VI
0.5
-
VDD + 0.5
10
IOK
output clamping current
input/output current
supply current
mA
mA
mA
C
II/O
-
10
IDD
-
50
Tstg
Tamb
Ptot
storage temperature
ambient temperature
total power dissipation
65
40
+150
+85
C
Tamb 40 C to +85 C
DIP16 package
SO16 package
per output
[1]
[2]
-
-
-
750
500
100
mW
mW
mW
P
power dissipation
[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C.
[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
9. Recommended operating conditions
Table 5.
Symbol
VDD
Recommended operating conditions
Parameter
Conditions
Min
3
Typ
Max
15
Unit
supply voltage
input voltage
-
-
-
V
VI
0
VDD
+85
V
Tamb
ambient temperature
in free air
40
C
HEF4049B
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 9 — 18 November 2011
3 of 12
HEF4049B
NXP Semiconductors
Hex inverting buffers
Table 5.
Symbol
t/V
Recommended operating conditions …continued
Parameter
Conditions
VDD = 5 V
Min
Typ
Max
3.75
0.5
Unit
s/V
s/V
s/V
input transition rise and fall rate
-
-
-
-
-
-
VDD = 10 V
VDD = 15 V
0.08
10. Static characteristics
Table 6.
Static characteristics
VSS = 0 V; VI = VSS or VDD unless otherwise specified.
Symbol Parameter
Conditions
VDD
Tamb = 40 C Tamb = 25 C Tamb = 85 C Unit
Min
Max
-
Min
Max
-
Min
Max
VIH
HIGH-level input voltage
IO < 1 A
5 V
10 V
15 V
5 V
3.5
3.5
3.5
-
-
V
V
V
V
V
V
V
V
V
V
V
V
7.0
-
7.0
-
7.0
11.0
-
11.0
-
11.0
-
VIL
LOW-level input voltage
IO < 1 A
-
1.5
3.0
4.0
-
-
1.5
3.0
4.0
-
-
1.5
3.0
4.0
-
10 V
15 V
5 V
-
-
-
-
-
-
VOH
VOL
IOH
HIGH-level output voltage IO < 1 A
4.95
4.95
4.95
10 V
15 V
5 V
9.95
-
9.95
-
9.95
-
14.95
-
14.95
-
14.95
-
LOW-level output voltage
HIGH-level output current
IO < 1 A
-
0.05
0.05
0.05
1.7
0.52
1.3
3.6
-
-
0.05
0.05
0.05
1.4
0.44
1.1
3.0
-
-
0.05
0.05
0.05
10 V
15 V
5 V
-
-
-
-
-
-
VO = 2.5 V
VO = 4.6 V
VO = 9.5 V
VO = 13.5 V
VO = 0.4 V
VO = 0.5 V
VO = 1.5 V
VDD = 15 V
IO = 0 A
-
-
-
1.1 mA
0.36 mA
0.9 mA
2.4 mA
5 V
-
-
-
10 V
15 V
-
-
-
-
-
-
IOL
LOW-level output current
4.75 V
3.5
2.9
2.3
-
-
-
mA
mA
mA
10 V
15 V
15 V
5 V
12.0
-
10.0
-
8.0
24.0
-
20.0
-
16.0
II
input leakage current
supply current
-
-
-
-
-
0.3
4.0
8.0
16.0
-
-
-
-
-
-
0.3
4.0
8.0
16.0
7.5
-
-
-
-
-
1.0 A
IDD
30
60
A
A
10 V
15 V
120 A
pF
CI
input capacitance
-
HEF4049B
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 9 — 18 November 2011
4 of 12
HEF4049B
NXP Semiconductors
Hex inverting buffers
11. Dynamic characteristics
Table 7.
Dynamic characteristics
VSS = 0 V; CL = 50 pF; tr = tf 20 ns; Tamb = 25 C; unless otherwise specified.
Symbol Parameter
Conditions
VDD
5 V
Extrapolation formula
26 ns + (0.18 ns/pF)CL
11 ns + (0.08 ns/pF)CL
9 ns + (0.05 ns/pF)CL
23 ns + (0.55 ns/pF)CL
14 ns + (0.23 ns/pF)CL
12 ns + (0.16 ns/pF)CL
3 ns + (0.35 ns/pF)CL
3 ns + (0.14 ns/pF)CL
2 ns + (0.09 ns/pF)CL
10 ns + (1.00 ns/pF)CL
9 ns + (0.42 ns/pF)CL
6 ns + (0.28 ns/pF)CL
Min
Typ
35
15
12
50
25
20
20
10
7
Max Unit
[1]
[1]
[1]
[1]
tPHL
HIGH to LOW
nA to nY;
see Figure 5
-
-
-
-
-
-
-
-
-
-
-
-
70
30
25
100
50
40
40
20
14
120
60
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
propagation delay
10 V
15 V
5 V
tPLH
tTHL
tTLH
LOW to HIGH
propagation delay
nA to nY;
see Figure 5
10 V
15 V
5 V
HIGH to LOW output see Figure 5
transition time
10 V
15 V
5 V
LOW to HIGH output see Figure 5
transition time
60
30
20
10 V
15 V
[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).
Table 8.
Dynamic power dissipation PD
PD can be calculated from the formulas shown. VSS = 0 V; tr = tf 20 ns; Tamb = 25 C.
Symbol
Parameter
VDD
5 V
Typical formula for PD (W)
where:
2
PD
dynamic power
dissipation
PD = 2500 fi + (fo CL) VDD
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VDD = supply voltage in V;
(fo CL) = sum of the outputs.
2
2
10 V
15 V
PD = 11000 fi + (fo CL) VDD
PD = 35000 fi + (fo CL) VDD
HEF4049B
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 9 — 18 November 2011
5 of 12
HEF4049B
NXP Semiconductors
Hex inverting buffers
12. Waveforms
t
t
f
r
V
I
90 %
input
V
M
10 %
0 V
t
t
PLH
PHL
V
OH
90 %
output
V
M
10 %
V
OL
t
t
THL
TLH
001aai336
Measurement points are given in Table 9.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 5. Input (nA) to output (nY) propagation delays and transition times
Table 9.
Input
VM
Measurement points
Output
VM
VI
VX
VY
0.5VDD
0 V to VDD
0.5VDD
0.1VDD
0.9VDD
V
DD
V
V
O
I
G
DUT
C
L
R
T
001aag182
Test data is given in Table 10.
Definitions for test circuit:
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
Fig 6. Load circuitry for switching times
Table 10. Test data
Supply voltage
Input
VI
Load
CL
VM
tr, tf
5 V to 15 V
VDD
0.5VI
20 ns
50 pF
HEF4049B
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 9 — 18 November 2011
6 of 12
HEF4049B
NXP Semiconductors
Hex inverting buffers
13. Package outline
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
b
2
16
9
M
H
pin 1 index
E
1
8
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
Z
A
A
A
2
(1)
(1)
1
w
UNIT
mm
b
b
b
c
D
E
e
e
L
M
M
H
1
2
1
E
max.
min.
max.
max.
1.73
1.30
0.53
0.38
1.25
0.85
0.36
0.23
19.50
18.55
6.48
6.20
3.60
3.05
8.25
7.80
10.0
8.3
4.2
0.51
3.2
2.54
0.1
7.62
0.3
0.254
0.01
0.76
0.068 0.021 0.049 0.014
0.051 0.015 0.033 0.009
0.77
0.73
0.26
0.24
0.14
0.12
0.32
0.31
0.39
0.33
inches
0.17
0.02
0.13
0.03
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
95-01-14
03-02-13
SOT38-4
Fig 7. Package outline SOT38-4 (DIP16)
HEF4049B
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 9 — 18 November 2011
7 of 12
HEF4049B
NXP Semiconductors
Hex inverting buffers
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
c
y
H
v
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT109-1
076E07
MS-012
Fig 8. Package outline SOT109-1 (SO16)
HEF4049B
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 9 — 18 November 2011
8 of 12
HEF4049B
NXP Semiconductors
Hex inverting buffers
14. Abbreviations
Table 11. Abbreviations
Acronym
DTL
Description
Diode Transistor Logic
Device Under Test
DUT
LOCMOS
TTL
Local Oxidation CMOS
Transistor Transistor Logic
15. Revision history
Table 12. Revision history
Document ID
HEF4049B v.9
Modifications:
Release date
20111118
Data sheet status
Change notice
Supersedes
Product data sheet
-
HEF4049B v.8
• Table 6: IOH minimum values changed to maximum
• Table 11: Added DUT
HEF4049B v.8
20091202
20090721
20090325
20081111
20080704
19950101
19950101
Product data sheet
Product data sheet
Product data sheet
Product data sheet
Product data sheet
Product specification
Product specification
-
-
-
-
-
-
-
HEF4049B v.7
HEF4049B v.6
HEF4049B v.5
HEF4049B v.4
HEF4049B_CNV v.3
HEF4049B_CNV v.2
-
HEF4049B v.7
HEF4049B v.6
HEF4049B v.5
HEF4049B v.4
HEF4049B_CNV v.3
HEF4049B_CNV v.2
HEF4049B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 9 — 18 November 2011
9 of 12
HEF4049B
NXP Semiconductors
Hex inverting buffers
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
16.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
16.3 Disclaimers
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
HEF4049B
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 9 — 18 November 2011
10 of 12
HEF4049B
NXP Semiconductors
Hex inverting buffers
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
HEF4049B
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 9 — 18 November 2011
11 of 12
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NXP Semiconductors
Hex inverting buffers
18. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2
7
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
Recommended operating conditions. . . . . . . . 3
Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
Dynamic characteristics . . . . . . . . . . . . . . . . . . 5
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 7
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Revision history. . . . . . . . . . . . . . . . . . . . . . . . . 9
8
9
10
11
12
13
14
15
16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 10
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 10
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 11
16.1
16.2
16.3
16.4
17
18
Contact information. . . . . . . . . . . . . . . . . . . . . 11
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 18 November 2011
Document identifier: HEF4049B
相关型号：
HEF4049BT-Q100
4000/14000/40000 SERIES, HEX 1-INPUT INVERT GATE, PDSO16, 3.90 MM, PLASTIC, MS-012, SOT109-1, SOP-16
NXP
HEF4049BT-T
IC 4000/14000/40000 SERIES, HEX 1-INPUT INVERT GATE, PDSO16, 3.90 MM, PLASTIC, MS-012, SOT109-1, SOP-16, Gate
NXP
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