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HEF4051BTS,118 [NXP]

HEF4051B - 8-channel analog multiplexer/demultiplexer SSOP1 16-Pin;
HEF4051BTS,118
型号： HEF4051BTS,118
厂家： NXP    NXP
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HEF4051B - 8-channel analog multiplexer/demultiplexer SSOP1 16-Pin

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HEF4051B  
8-channel analog multiplexer/demultiplexer  
Rev. 10 — 17 November 2011  
Product data sheet  
1. General description  
The HEF4051B is an 8-channel analog multiplexer/demultiplexer with three address  
inputs (S1 to S3), an active LOW enable input (E), eight independent inputs/outputs  
(Y0 to Y7) and a common input/output (Z). The device contains eight bidirectional analog  
switches, each with one side connected to an independent input/output (Y0 to Y7) and the  
other side connected to a common input/output (Z). With E LOW, one of the eight  
switches is selected (low-impedance ON-state) by S1 to S3. With E HIGH, all switches  
are in the high-impedance OFF-state, independent of S1 to S3. If break before make is  
needed, then it is necessary to use the enable input.  
VDD and VSS are the supply voltage connections for the digital control inputs (S1 to S3,  
and E). The VDD to VSS range is 3 V to 15 V. The analog inputs/outputs (Y0 to Y7, and Z)  
can swing between VDD as a positive limit and VEE as a negative limit. VDD VEE may not  
exceed 15 V. Unused inputs must be connected to VDD, VSS, or another input. For  
operation as a digital multiplexer/demultiplexer, VEE is connected to VSS (typically  
ground). VEE and VSS are the supply voltage connections for the switches.  
2. Features and benefits  
Fully static operation  
5 V, 10 V, and 15 V parametric ratings  
Standardized symmetrical output characteristics  
Specified from 40 C to +85 C and 40 C to +125 C  
Complies with JEDEC standard JESD 13-B  
3. Applications  
Analog multiplexing and demultiplexing  
Digital multiplexing and demultiplexing  
Signal gating  
 
 
 
HEF4051B  
NXP Semiconductors  
8-channel analog multiplexer/demultiplexer  
4. Ordering information  
Table 1.  
Ordering information  
All types operate from 40 C to +125 C.  
Type number  
Package  
Name  
Description  
Version  
HEF4051BP  
HEF4051BT  
HEF4051BTS  
HEF4051BTT  
DIP16  
plastic dual in-line package; 16 leads (300 mil)  
SOT38-4  
SO16  
plastic small outline package; 16 leads; body width 3.9 mm  
plastic shrink small outline package; 16 leads; body width 5.3 mm  
plastic thin shrink small outline package; 16 leads; body width 4.4 mm  
SOT109-1  
SOT338-1  
SOT403-1  
SSOP16  
TSSOP16  
5. Functional diagram  
V
DD  
16  
13 Y0  
14 Y1  
15 Y2  
12 Y3  
S1 11  
S2 10  
LOGIC  
LEVEL  
CONVERSION  
1
5
2
4
3
Y4  
Y5  
Y6  
Y7  
Z
1 − OF − 8  
DECODER  
S3  
9
6
E
8
7
V
SS  
V
001aac277  
EE  
Fig 1. Functional diagram  
HEF4051B  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 10 — 17 November 2011  
2 of 23  
 
 
HEF4051B  
NXP Semiconductors  
8-channel analog multiplexer/demultiplexer  
Yn  
V
DD  
V
DD  
Z
V
EE  
001aac281  
Fig 2. Schematic diagram (one switch)  
11  
10  
9
1
0
7
X
3
Y0  
13  
6
EN  
S1  
S2  
S3  
Y1  
Y2  
Y3  
Y4  
Y5  
Y6  
Y7  
11  
10  
9
14  
15  
12  
1
MUX/DMUX  
13  
14  
15  
12  
1
0
1
2
3
4
5
6
5
3
2
E
6
4
5
3
Z
2
001aac278  
4
7
001aac279  
Fig 3. Logic symbol  
Fig 4. IEC logic symbol  
HEF4051B  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 10 — 17 November 2011  
3 of 23  
HEF4051B  
NXP Semiconductors  
8-channel analog multiplexer/demultiplexer  
Y0  
Y1  
Y2  
Y3  
Y4  
Y5  
Y6  
Y7  
LEVEL  
CONVERTER  
S1  
LEVEL  
CONVERTER  
S2  
S3  
E
LEVEL  
CONVERTER  
LEVEL  
CONVERTER  
Z
001aac280  
Fig 5. Logic diagram  
HEF4051B  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 10 — 17 November 2011  
4 of 23  
HEF4051B  
NXP Semiconductors  
8-channel analog multiplexer/demultiplexer  
6. Pinning information  
6.1 Pinning  
HEF4051B  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
Y4  
Y6  
Z
V
DD  
Y2  
Y1  
Y0  
Y3  
S1  
S2  
S3  
HEF4051B  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
Y4  
Y6  
Z
V
DD  
Y7  
Y5  
E
Y2  
Y1  
Y0  
Y3  
S1  
S2  
S3  
Y7  
Y5  
E
V
EE  
SS  
V
EE  
SS  
V
V
001aak508  
001aac282  
Fig 6. Pin configuration SOT38-4 and SOT109-1  
Fig 7. Pin configuration SOT338-1 and SOT403-1  
6.2 Pin description  
Table 2.  
Symbol  
E
Pin description  
Pin  
Description  
6
enable input (active LOW)  
supply voltage  
VEE  
7
VSS  
8
ground supply voltage  
select input  
S1, S2, S3  
11, 10, 9  
Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7 13, 14, 15, 12, 1, 5, 2, 4 independent input or output  
Z
3
common output or input  
supply voltage  
VDD  
16  
HEF4051B  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 10 — 17 November 2011  
5 of 23  
 
 
 
HEF4051B  
NXP Semiconductors  
8-channel analog multiplexer/demultiplexer  
7. Functional description  
7.1 Function table  
Table 3.  
Function table[1]  
Input  
Channel ON  
E
L
L
L
L
L
L
L
L
H
S3  
L
S2  
L
S1  
L
Y0 to Z  
Y1 to Z  
Y2 to Z  
Y3 to Z  
Y4 to Z  
Y5 to Z  
Y6 to Z  
Y7 to Z  
switches off  
L
L
H
L
L
H
H
L
L
H
L
H
H
H
H
X
L
H
L
H
H
X
H
X
[1] H = HIGH voltage level;  
L = LOW voltage level;  
X = don’t care.  
8. Limiting values  
Table 4.  
Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground).  
Symbol  
VDD  
Parameter  
Conditions  
Min  
0.5  
18  
-
Max  
+18  
+0.5  
10  
Unit  
V
supply voltage  
supply voltage  
input clamping current  
[1]  
VEE  
referenced to VDD  
V
IIK  
pins Sn and E;  
mA  
VI < 0.5 V or VI > VDD + 0.5 V  
VI  
input voltage  
0.5  
-
VDD + 0.5  
10  
V
II/O  
input/output current  
supply current  
mA  
mA  
C  
C  
IDD  
Tstg  
Tamb  
Ptot  
-
50  
storage temperature  
ambient temperature  
total power dissipation  
65  
40  
+150  
+125  
[2]  
Tamb = 40 C to +125 C  
DIP16 package  
-
-
-
-
-
750  
500  
500  
500  
100  
mW  
mW  
mW  
mW  
mW  
SO16 package  
SSOP16 package  
TSSOP16 package  
per output  
P
power dissipation  
[1] To avoid drawing VDD current out of terminal Z, when switch current flows into terminals Y, the voltage drop across the bidirectional  
switch must not exceed 0.4 V. If the switch current flows into terminal Z, no VDD current will flow out of terminals Y, and in this case there  
is no limit for the voltage drop across the switch, but the voltages at Y and Z may not exceed VDD or VEE  
.
[2] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C.  
HEF4051B  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 10 — 17 November 2011  
6 of 23  
 
 
 
 
 
 
HEF4051B  
NXP Semiconductors  
8-channel analog multiplexer/demultiplexer  
For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.  
For SSOP16 and TSSOP16 packages: Ptot derates linearly with 5.5 mW/K above 60 C.  
9. Recommended operating conditions  
Table 5.  
Symbol  
VDD  
Recommended operating conditions  
Parameter  
Conditions  
Min  
Typ  
Max  
15  
Unit  
V
supply voltage  
input voltage  
see Figure 8  
3
-
-
-
-
-
-
VI  
0
VDD  
+125  
3.75  
0.5  
V
Tamb  
ambient temperature  
in free air  
40  
C  
t/V  
input transition rise and fall VDD = 5 V  
-
-
-
s/V  
s/V  
s/V  
rate  
VDD = 10 V  
VDD = 15 V  
0.08  
001aac285  
15  
V
DD  
− V  
SS  
(V)  
10  
operating area  
5
0
0
5
10  
15  
V
− V (V)  
EE  
DD  
Fig 8. Operating area as a function of the supply voltages  
10. Static characteristics  
Table 6.  
Static characteristics  
VSS = VEE = 0 V; VI = VSS or VDD unless otherwise specified.  
Symbol Parameter  
Conditions  
VDD  
Tamb = 40 C Tamb = 25 C Tamb = 85 C Tamb = 125 C Unit  
Min  
Max  
-
Min  
Max  
-
Min  
Max  
-
Min  
Max  
-
VIH  
HIGH-level  
input voltage  
IO< 1 A  
5 V  
10 V  
15 V  
5 V  
3.5  
3.5  
3.5  
3.5  
V
V
V
V
V
V
7.0  
-
7.0  
-
7.0  
-
7.0  
-
11.0  
-
11.0  
-
11.0  
-
11.0  
-
VIL  
LOW-level  
input voltage  
IO< 1 A  
-
-
-
-
1.5  
3.0  
4.0  
0.1  
-
-
-
-
1.5  
3.0  
4.0  
0.1  
-
-
-
-
1.5  
3.0  
4.0  
1.0  
-
-
-
-
1.5  
3.0  
4.0  
10 V  
15 V  
15 V  
II  
input leakage  
current  
1.0 A  
HEF4051B  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 10 — 17 November 2011  
7 of 23  
 
 
 
HEF4051B  
NXP Semiconductors  
8-channel analog multiplexer/demultiplexer  
Table 6.  
Static characteristics …continued  
VSS = VEE = 0 V; VI = VSS or VDD unless otherwise specified.  
Symbol Parameter  
Conditions  
VDD  
Tamb = 40 C Tamb = 25 C Tamb = 85 C Tamb = 125 C Unit  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
IS(OFF)  
OFF-state  
leakage  
current  
Z port;  
all channels OFF;  
see Figure 9  
15 V  
-
-
-
1000  
-
-
-
-
nA  
nA  
Y port;  
15 V  
-
-
-
200  
-
-
-
-
per channel;  
see Figure 10  
IDD  
supply current IO = 0 A  
5 V  
10 V  
15 V  
-
-
-
-
-
5
10  
20  
-
-
-
-
-
5
-
-
-
-
150  
300  
600  
-
-
-
-
-
150 A  
300 A  
600 A  
10  
20  
7.5  
CI  
input  
Sn, E inputs  
-
pF  
capacitance  
10.1 Test circuits  
V
DD  
S1 to S3  
V
or V  
SS  
DD  
Z
E
Yn  
I
S
V
= V  
EE  
SS  
V
DD  
V
V
O
I
001aak513  
Fig 9. Test circuit for measuring OFF-state leakage current Z port  
V
DD  
S1 to S3  
Y0  
Yn  
1
2
V
or V  
DD  
SS  
switch  
I
S
Z
E
V
SS  
= V  
EE  
V
SS  
V
V
I
O
001aak514  
Fig 10. Test circuit for measuring OFF-state leakage current Yn port  
HEF4051B  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 10 — 17 November 2011  
8 of 23  
 
 
 
HEF4051B  
NXP Semiconductors  
8-channel analog multiplexer/demultiplexer  
10.2 ON resistance  
Table 7.  
ON resistance  
Tamb = 25 C; ISW = 200 A; VSS = VEE = 0 V.  
Symbol Parameter  
Conditions  
VI = 0 V to VDD VEE  
see Figure 11 and Figure 12  
VDD VEE Typ  
Max  
2500  
245  
175  
340  
160  
115  
365  
200  
155  
-
Unit  
RON(peak) ON resistance (peak)  
;
5 V  
350  
80  
60  
115  
50  
40  
120  
65  
50  
25  
10  
5
10 V  
15 V  
RON(rail)  
ON resistance (rail)  
VI = 0 V; see Figure 11 and Figure 12 5 V  
10 V  
15 V  
5 V  
VI = VDD VEE  
;
see Figure 11 and Figure 12  
10 V  
15 V  
5 V  
RON  
ON resistance mismatch  
between channels  
VI = 0 V to VDD VEE; see Figure 11  
10 V  
15 V  
-
-
10.2.1 ON resistance waveform and test circuit  
V
V
V
SW  
DD  
S1 to S3  
V
or V  
DD  
SS  
Z
E
Yn  
V
= V  
EE  
SS  
V
SS  
I
V
SW  
I
001aak512  
RON = VSW / ISW  
.
Fig 11. Test circuit for measuring RON  
HEF4051B  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 10 — 17 November 2011  
9 of 23  
 
 
 
HEF4051B  
NXP Semiconductors  
8-channel analog multiplexer/demultiplexer  
001aae648  
400  
R
ON  
(Ω)  
V
= 5 V  
DD  
300  
200  
100  
0
10 V  
15 V  
0
5
10  
15  
V (V)  
I
Fig 12. Typical RON as a function of input voltage  
11. Dynamic characteristics  
Table 8.  
Dynamic characteristics  
Tamb = 25 C; VSS = VEE = 0 V; for test circuit see Figure 16.  
Symbol Parameter Conditions  
tPHL  
VDD  
5 V  
Typ  
15  
5
Max  
30  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
HIGH to LOW propagation delay Yn, Z to Z, Yn; see Figure 13  
Sn to Yn, Z; see Figure 14  
10 V  
15 V  
5 V  
10  
5
10  
150  
60  
45  
15  
5
300  
120  
90  
10 V  
15 V  
5 V  
tPLH  
LOW to HIGH propagation delay Yn, Z to Z, Yn; see Figure 13  
Sn to Yn, Z; see Figure 14  
30  
10 V  
15 V  
5 V  
10  
5
10  
150  
65  
45  
120  
90  
85  
140  
55  
40  
145  
120  
115  
300  
130  
90  
10 V  
15 V  
5 V  
tPHZ  
tPZH  
tPLZ  
HIGH to OFF-state  
propagation delay  
E to Yn, Z; see Figure 15  
E to Yn, Z; see Figure 15  
E to Yn, Z; see Figure 15  
240  
180  
170  
280  
110  
80  
10 V  
15 V  
5 V  
OFF-state to HIGH  
propagation delay  
10 V  
15 V  
5 V  
LOW to OFF-state  
propagation delay  
290  
240  
230  
10 V  
15 V  
HEF4051B  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 10 — 17 November 2011  
10 of 23  
 
HEF4051B  
NXP Semiconductors  
8-channel analog multiplexer/demultiplexer  
Table 8.  
Dynamic characteristics …continued  
Tamb = 25 C; VSS = VEE = 0 V; for test circuit see Figure 16.  
Symbol Parameter  
tPZL OFF-state to LOW  
propagation delay  
Conditions  
VDD  
5 V  
Typ  
140  
55  
Max  
280  
110  
80  
Unit  
ns  
E to Yn, Z; see Figure 15  
10 V  
15 V  
ns  
40  
ns  
11.1 Waveforms and test circuit  
V
DD  
Yn or Z  
input  
V
V
M
DD  
Sn input  
V
M
V
V
EE  
V
V
SS  
t
t
PLH  
PHL  
t
t
PHL  
PLH  
V
V
O
O
90 %  
Yn or Z  
output  
Z or Yn  
output  
V
M
10 %  
switch ON  
EE  
switch OFF  
switch OFF  
EE  
001aak509  
001aak510  
Measurement points are given in Table 9.  
Measurement points are given in Table 9.  
Fig 13. Yn, Z to Z, Yn propagation delays  
Fig 14. Sn to Yn, Z propagation delays  
V
DD  
E input  
V
M
V
V
V
SS  
t
t
PLZ  
PZL  
V
O
90 %  
Yn or Z output  
LOW-to-OFF  
OFF-to-LOW  
10 %  
EE  
t
t
PHZ  
PZH  
V
O
90 %  
Yn or Z output  
HIGH-to-OFF  
OFF-to-HIGH  
10 %  
switch ON  
001aak511  
EE  
switch ON  
switch OFF  
Measurement points are given in Table 9.  
Fig 15. Enable and disable times  
Table 9. Measurement points  
Supply voltage  
VDD  
Input  
VM  
Output  
VM  
5 V to 15 V  
0.5VDD  
0.5VDD  
HEF4051B  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 10 — 17 November 2011  
11 of 23  
 
 
 
HEF4051B  
NXP Semiconductors  
8-channel analog multiplexer/demultiplexer  
t
W
V
I
90 %  
negative  
pulse  
V
V
V
M
M
10 %  
0 V  
t
t
r
f
t
t
f
r
V
I
90 %  
M
positive  
pulse  
V
M
10 %  
0 V  
t
W
V
V
DD  
V
V
I
DD  
V
I
S1  
O
R
L
PULSE  
GENERATOR  
open  
DUT  
R
T
C
L
V
V
SS  
EE  
001aaj903  
Test data is given in Table 10.  
Definitions:  
DUT = Device Under Test.  
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.  
CL = Load capacitance including test jig and probe.  
RL = Load resistance.  
Fig 16. Test circuit for measuring switching times  
Table 10. Test data  
Input  
Yn, Z  
Load  
CL  
S1 position  
[1]  
Sn and E tr, tf  
VM  
RL  
tPHL  
tPLH  
tPZH, tPHZ tPZL, tPLZ other  
VEE VDD VEE  
VDD or VEE VDD or VSS 20 ns  
0.5VDD  
50 pF  
10 k  
VDD or VEE VEE  
[1] For Yn to Z or Z to Yn propagation delays use VEE. For Sn to Yn or Z propagation delays use VDD  
.
HEF4051B  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 10 — 17 November 2011  
12 of 23  
 
 
HEF4051B  
NXP Semiconductors  
8-channel analog multiplexer/demultiplexer  
11.2 Additional dynamic parameters  
Table 11. Additional dynamic characteristics  
VSS = VEE = 0 V; Tamb = 25 C.  
Symbol  
Parameter  
Conditions  
VDD  
Typ  
0.25  
0.04  
0.04  
13  
Max  
Unit  
%
[1]  
[1]  
[1]  
[1]  
[1]  
[1]  
[1]  
THD  
total harmonic distortion  
see Figure 17; RL = 10 k; CL = 15 pF; 5 V  
channel ON; VI = 0.5VDD (p-p);  
fi = 1 kHz  
-
-
-
-
-
-
-
10 V  
%
15 V  
5 V  
%
f(3dB)  
3 dB frequency response see Figure 18; RL = 1 k; CL = 5 pF;  
MHz  
MHz  
MHz  
dB  
channel ON; VI = 0.5VDD (p-p)  
10 V  
15 V  
10 V  
40  
70  
iso  
isolation (OFF-state)  
crosstalk voltage  
crosstalk  
see Figure 19; fi = 1 MHz; RL = 1 k;  
CL = 5 pF; channel OFF;  
VI = 0.5VDD (p-p)  
50  
Vct  
digital inputs to switch; see Figure 20; 10 V  
RL = 10 k; CL = 15 pF;  
E or Sn = VDD (square-wave)  
50  
-
mV  
dB  
[1]  
Xtalk  
between switches; see Figure 21;  
fi = 1 MHz; RL = 1 k;  
10 V  
50  
-
VI = 0.5VDD (p-p)  
[1] fi is biased at 0.5 VDD; VI = 0.5VDD (p-p).  
Table 12. Dynamic power dissipation PD  
PD can be calculated from the formulas shown; VEE = VSS = 0 V; tr = tf 20 ns; Tamb = 25 C.  
Symbol  
Parameter  
VDD  
5 V  
Typical formula for PD (W)  
PD = 1000 fi + (fo CL) VDD  
PD = 5500 fi + (fo CL) VDD  
where:  
2
2
PD  
dynamic power  
dissipation  
fi = input frequency in MHz;  
fo = output frequency in MHz;  
10 V  
15 V  
2
CL = output load capacitance in pF;  
DD = supply voltage in V;  
(CL fo) = sum of the outputs.  
PD = 15000 fi + (fo CL) VDD  
V
11.2.1 Test circuits  
V
V
DD  
DD  
S1 to S3  
S1 to S3  
V
or V  
V
or V  
DD  
DD  
SS  
SS  
Z
E
Yn  
Z
E
Yn  
V
= V  
V
= V  
SS EE  
SS  
EE  
V
V
SS  
SS  
R
L
C
L
R
L
C
L
D
dB  
f
f
i
i
001aak516  
001aak517  
Fig 17. Test circuit for measuring total harmonic  
distortion  
Fig 18. Test circuit for measuring frequency response  
HEF4051B  
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Product data sheet  
Rev. 10 — 17 November 2011  
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8-channel analog multiplexer/demultiplexer  
V
DD  
S1 to S3  
Y0  
Yn  
1
2
V
or V  
DD  
SS  
switch  
Z
E
V
SS  
= V  
EE  
V
SS  
R
L
C
L
dB  
f
i
001aak518  
Fig 19. Test circuit for measuring isolation (OFF-state)  
0.5V  
V
DD  
DD  
R
L
S1 to S3  
Y0  
Yn  
1
switch  
Z
E
2
G
V
SS  
= V  
EE  
R
L
C
L
V
O
V
V
or V  
SS  
DD  
001aak519  
a. Test circuit  
logic  
input (Sn, E)  
off  
on  
off  
V
V
ct  
O
001aaj908  
b. Input and output pulse definitions  
Fig 20. Test circuit for measuring crosstalk voltage between digital inputs and switch  
HEF4051B  
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Product data sheet  
Rev. 10 — 17 November 2011  
14 of 23  
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NXP Semiconductors  
8-channel analog multiplexer/demultiplexer  
V
DD  
V
DD  
S1 to S3  
Y0  
Yn  
S1 to S3  
Y0  
Yn  
V
DD  
or V  
SS  
SS  
V
or V  
DD  
SS  
Z
E
Z
E
V
= V  
EE  
SS  
V
= V  
EE  
SS  
V
V
R
L
I
V
SS  
R
L
V
R
L
O
R
L
V
O
V
I
001aak520  
001aak521  
a. Switch closed condition  
Fig 21. Test circuit for measuring crosstalk between switches  
b. Switch open condition  
HEF4051B  
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Product data sheet  
Rev. 10 — 17 November 2011  
15 of 23  
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8-channel analog multiplexer/demultiplexer  
12. Package outline  
DIP16: plastic dual in-line package; 16 leads (300 mil)  
SOT38-4  
D
M
E
A
2
A
A
1
L
c
e
w M  
Z
b
1
(e )  
1
b
b
2
16  
9
M
H
pin 1 index  
E
1
8
0
5
10 mm  
scale  
DIMENSIONS (inch dimensions are derived from the original mm dimensions)  
(1)  
A
A
A
2
(1)  
(1)  
Z
1
w
UNIT  
mm  
b
b
b
c
D
E
e
e
L
M
M
H
1
2
1
E
max.  
min.  
max.  
max.  
1.73  
1.30  
0.53  
0.38  
1.25  
0.85  
0.36  
0.23  
19.50  
18.55  
6.48  
6.20  
3.60  
3.05  
8.25  
7.80  
10.0  
8.3  
4.2  
0.51  
3.2  
2.54  
0.1  
7.62  
0.3  
0.254  
0.01  
0.76  
0.068 0.021 0.049 0.014  
0.051 0.015 0.033 0.009  
0.77  
0.73  
0.26  
0.24  
0.14  
0.12  
0.32  
0.31  
0.39  
0.33  
inches  
0.17  
0.02  
0.13  
0.03  
Note  
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
95-01-14  
03-02-13  
SOT38-4  
Fig 22. Package outline SOT38-4 (DIP16)  
HEF4051B  
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Product data sheet  
Rev. 10 — 17 November 2011  
16 of 23  
 
HEF4051B  
NXP Semiconductors  
8-channel analog multiplexer/demultiplexer  
SO16: plastic small outline package; 16 leads; body width 3.9 mm  
SOT109-1  
D
E
A
X
v
c
y
H
M
A
E
Z
16  
9
Q
A
2
A
(A )  
3
A
1
pin 1 index  
θ
L
p
L
1
8
e
w
M
detail X  
b
p
0
2.5  
scale  
5 mm  
DIMENSIONS (inch dimensions are derived from the original mm dimensions)  
A
(1)  
(1)  
(1)  
UNIT  
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.  
0.25  
0.10  
1.45  
1.25  
0.49  
0.36  
0.25  
0.19  
10.0  
9.8  
4.0  
3.8  
6.2  
5.8  
1.0  
0.4  
0.7  
0.6  
0.7  
0.3  
mm  
1.27  
0.05  
1.05  
0.041  
1.75  
0.25  
0.01  
0.25  
0.01  
0.25  
0.1  
8o  
0o  
0.010 0.057  
0.004 0.049  
0.019 0.0100 0.39  
0.014 0.0075 0.38  
0.16  
0.15  
0.244  
0.228  
0.039 0.028  
0.016 0.020  
0.028  
0.012  
inches  
0.069  
0.01 0.004  
Note  
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
99-12-27  
03-02-19  
SOT109-1  
076E07  
MS-012  
Fig 23. Package outline SOT109-1 (SO16)  
HEF4051B  
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Product data sheet  
Rev. 10 — 17 November 2011  
17 of 23  
HEF4051B  
NXP Semiconductors  
8-channel analog multiplexer/demultiplexer  
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm  
SOT338-1  
D
E
A
X
c
y
H
v
M
A
E
Z
9
16  
Q
A
2
A
(A )  
3
A
1
pin 1 index  
θ
L
p
L
8
1
detail X  
w
M
b
p
e
0
2.5  
5 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
(1)  
(1)  
(1)  
UNIT  
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
E
max.  
8o  
0o  
0.21  
0.05  
1.80  
1.65  
0.38  
0.25  
0.20  
0.09  
6.4  
6.0  
5.4  
5.2  
7.9  
7.6  
1.03  
0.63  
0.9  
0.7  
1.00  
0.55  
mm  
2
0.25  
0.65  
1.25  
0.2  
0.13  
0.1  
Note  
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
99-12-27  
03-02-19  
SOT338-1  
MO-150  
Fig 24. Package outline SOT338-1 (SSOP16)  
HEF4051B  
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Product data sheet  
Rev. 10 — 17 November 2011  
18 of 23  
HEF4051B  
NXP Semiconductors  
8-channel analog multiplexer/demultiplexer  
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm  
SOT403-1  
D
E
A
X
c
y
H
v
M
A
E
Z
9
16  
Q
(A )  
3
A
2
A
A
1
pin 1 index  
θ
L
p
L
1
8
detail X  
w
M
b
p
e
0
2.5  
5 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
(1)  
(2)  
(1)  
UNIT  
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.  
8o  
0o  
0.15  
0.05  
0.95  
0.80  
0.30  
0.19  
0.2  
0.1  
5.1  
4.9  
4.5  
4.3  
6.6  
6.2  
0.75  
0.50  
0.4  
0.3  
0.40  
0.06  
mm  
1.1  
0.65  
0.25  
1
0.2  
0.13  
0.1  
Notes  
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.  
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
99-12-27  
03-02-18  
SOT403-1  
MO-153  
Fig 25. Package outline SOT403-1 (TSSOP16)  
HEF4051B  
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© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 10 — 17 November 2011  
19 of 23  
HEF4051B  
NXP Semiconductors  
8-channel analog multiplexer/demultiplexer  
13. Revision history  
Table 13. Revision history  
Document ID  
HEF4051B v.10  
Modifications:  
Release date  
20111117  
Data sheet status  
Change notice  
Supersedes  
Product data sheet  
-
HEF4051B v.9  
• Legal pages updated.  
• Changes in “General description”, “Features and benefits” and “Applications”.  
HEF4051B v.9  
20100325  
20100301  
20091127  
20090924  
20090826  
20050112  
19950101  
19950101  
Product data sheet  
Product data sheet  
Product data sheet  
Product data sheet  
Product data sheet  
Product data sheet  
Product specification  
Product specification  
-
-
-
-
-
-
-
-
HEF4051B v.8  
HEF4051B v.7  
HEF4051B v.6  
HEF4051B v.5  
HEF4051B v.4  
HEF4051B_CNV v.3  
HEF4051B_CNV v.2  
-
HEF4051B v.8  
HEF4051B v.7  
HEF4051B v.6  
HEF4051B v.5  
HEF4051B v.4  
HEF4051B_CNV v.3  
HEF4051B_CNV v.2  
HEF4051B  
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Product data sheet  
Rev. 10 — 17 November 2011  
20 of 23  
 
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14. Legal information  
14.1 Data sheet status  
Document status[1][2]  
Product status[3]  
Development  
Definition  
Objective [short] data sheet  
This document contains data from the objective specification for product development.  
This document contains data from the preliminary specification.  
This document contains the product specification.  
Preliminary [short] data sheet Qualification  
Product [short] data sheet Production  
[1]  
[2]  
[3]  
Please consult the most recently issued document before initiating or completing a design.  
The term ‘short data sheet’ is explained in section “Definitions”.  
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status  
information is available on the Internet at URL http://www.nxp.com.  
malfunction of an NXP Semiconductors product can reasonably be expected  
14.2 Definitions  
to result in personal injury, death or severe property or environmental  
damage. NXP Semiconductors accepts no liability for inclusion and/or use of  
NXP Semiconductors products in such equipment or applications and  
therefore such inclusion and/or use is at the customer’s own risk.  
Draft — The document is a draft version only. The content is still under  
internal review and subject to formal approval, which may result in  
modifications or additions. NXP Semiconductors does not give any  
representations or warranties as to the accuracy or completeness of  
information included herein and shall have no liability for the consequences of  
use of such information.  
Applications — Applications that are described herein for any of these  
products are for illustrative purposes only. NXP Semiconductors makes no  
representation or warranty that such applications will be suitable for the  
specified use without further testing or modification.  
Short data sheet — A short data sheet is an extract from a full data sheet  
with the same product type number(s) and title. A short data sheet is intended  
for quick reference only and should not be relied upon to contain detailed and  
full information. For detailed and full information see the relevant full data  
sheet, which is available on request via the local NXP Semiconductors sales  
office. In case of any inconsistency or conflict with the short data sheet, the  
full data sheet shall prevail.  
Customers are responsible for the design and operation of their applications  
and products using NXP Semiconductors products, and NXP Semiconductors  
accepts no liability for any assistance with applications or customer product  
design. It is customer’s sole responsibility to determine whether the NXP  
Semiconductors product is suitable and fit for the customer’s applications and  
products planned, as well as for the planned application and use of  
customer’s third party customer(s). Customers should provide appropriate  
design and operating safeguards to minimize the risks associated with their  
applications and products.  
Product specification — The information and data provided in a Product  
data sheet shall define the specification of the product as agreed between  
NXP Semiconductors and its customer, unless NXP Semiconductors and  
customer have explicitly agreed otherwise in writing. In no event however,  
shall an agreement be valid in which the NXP Semiconductors product is  
deemed to offer functions and qualities beyond those described in the  
Product data sheet.  
NXP Semiconductors does not accept any liability related to any default,  
damage, costs or problem which is based on any weakness or default in the  
customer’s applications or products, or the application or use by customer’s  
third party customer(s). Customer is responsible for doing all necessary  
testing for the customer’s applications and products using NXP  
Semiconductors products in order to avoid a default of the applications and  
the products or of the application or use by customer’s third party  
customer(s). NXP does not accept any liability in this respect.  
14.3 Disclaimers  
Limiting values — Stress above one or more limiting values (as defined in  
the Absolute Maximum Ratings System of IEC 60134) will cause permanent  
damage to the device. Limiting values are stress ratings only and (proper)  
operation of the device at these or any other conditions above those given in  
the Recommended operating conditions section (if present) or the  
Characteristics sections of this document is not warranted. Constant or  
repeated exposure to limiting values will permanently and irreversibly affect  
the quality and reliability of the device.  
Limited warranty and liability — Information in this document is believed to  
be accurate and reliable. However, NXP Semiconductors does not give any  
representations or warranties, expressed or implied, as to the accuracy or  
completeness of such information and shall have no liability for the  
consequences of use of such information.  
In no event shall NXP Semiconductors be liable for any indirect, incidental,  
punitive, special or consequential damages (including - without limitation - lost  
profits, lost savings, business interruption, costs related to the removal or  
replacement of any products or rework charges) whether or not such  
damages are based on tort (including negligence), warranty, breach of  
contract or any other legal theory.  
Terms and conditions of commercial sale — NXP Semiconductors  
products are sold subject to the general terms and conditions of commercial  
sale, as published at http://www.nxp.com/profile/terms, unless otherwise  
agreed in a valid written individual agreement. In case an individual  
agreement is concluded only the terms and conditions of the respective  
agreement shall apply. NXP Semiconductors hereby expressly objects to  
applying the customer’s general terms and conditions with regard to the  
purchase of NXP Semiconductors products by customer.  
Notwithstanding any damages that customer might incur for any reason  
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards  
customer for the products described herein shall be limited in accordance  
with the Terms and conditions of commercial sale of NXP Semiconductors.  
Right to make changes — NXP Semiconductors reserves the right to make  
changes to information published in this document, including without  
limitation specifications and product descriptions, at any time and without  
notice. This document supersedes and replaces all information supplied prior  
to the publication hereof.  
No offer to sell or license — Nothing in this document may be interpreted or  
construed as an offer to sell products that is open for acceptance or the grant,  
conveyance or implication of any license under any copyrights, patents or  
other industrial or intellectual property rights.  
Export control — This document as well as the item(s) described herein  
may be subject to export control regulations. Export might require a prior  
authorization from competent authorities.  
Suitability for use — NXP Semiconductors products are not designed,  
authorized or warranted to be suitable for use in life support, life-critical or  
safety-critical systems or equipment, nor in applications where failure or  
HEF4051B  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 10 — 17 November 2011  
21 of 23  
 
 
 
 
HEF4051B  
NXP Semiconductors  
8-channel analog multiplexer/demultiplexer  
Non-automotive qualified products — Unless this data sheet expressly  
states that this specific NXP Semiconductors product is automotive qualified,  
the product is not suitable for automotive use. It is neither qualified nor tested  
in accordance with automotive testing or application requirements. NXP  
Semiconductors accepts no liability for inclusion and/or use of  
NXP Semiconductors’ specifications such use shall be solely at customer’s  
own risk, and (c) customer fully indemnifies NXP Semiconductors for any  
liability, damages or failed product claims resulting from customer design and  
use of the product for automotive applications beyond NXP Semiconductors’  
standard warranty and NXP Semiconductors’ product specifications.  
non-automotive qualified products in automotive equipment or applications.  
In the event that customer uses the product for design-in and use in  
automotive applications to automotive specifications and standards, customer  
(a) shall use the product without NXP Semiconductors’ warranty of the  
product for such automotive applications, use and specifications, and (b)  
whenever customer uses the product for automotive applications beyond  
14.4 Trademarks  
Notice: All referenced brands, product names, service names and trademarks  
are the property of their respective owners.  
15. Contact information  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
HEF4051B  
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© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 10 — 17 November 2011  
22 of 23  
 
 
HEF4051B  
NXP Semiconductors  
8-channel analog multiplexer/demultiplexer  
16. Contents  
1
2
3
4
5
General description. . . . . . . . . . . . . . . . . . . . . . 1  
Features and benefits . . . . . . . . . . . . . . . . . . . . 1  
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Ordering information. . . . . . . . . . . . . . . . . . . . . 2  
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2  
6
6.1  
6.2  
Pinning information. . . . . . . . . . . . . . . . . . . . . . 5  
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5  
7
7.1  
8
Functional description . . . . . . . . . . . . . . . . . . . 6  
Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6  
Recommended operating conditions. . . . . . . . 7  
9
10  
Static characteristics. . . . . . . . . . . . . . . . . . . . . 7  
Test circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
ON resistance. . . . . . . . . . . . . . . . . . . . . . . . . . 9  
ON resistance waveform and test circuit . . . . . 9  
10.1  
10.2  
10.2.1  
11  
Dynamic characteristics . . . . . . . . . . . . . . . . . 10  
Waveforms and test circuit . . . . . . . . . . . . . . . 11  
Additional dynamic parameters . . . . . . . . . . . 13  
Test circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
11.1  
11.2  
11.2.1  
12  
13  
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16  
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 20  
14  
Legal information. . . . . . . . . . . . . . . . . . . . . . . 21  
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 21  
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
14.1  
14.2  
14.3  
14.4  
15  
16  
Contact information. . . . . . . . . . . . . . . . . . . . . 22  
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
Please be aware that important notices concerning this document and the product(s)  
described herein, have been included in section ‘Legal information’.  
© NXP B.V. 2011.  
All rights reserved.  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
Date of release: 17 November 2011  
Document identifier: HEF4051B  
 

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