HEF4059BF [NXP]
Programmable divide-by-n counter; 可编程分频N计数器
| 型号： | HEF4059BF |
| 厂家： | 
NXP |
| 描述： | Programmable divide-by-n counter |
| 文件： | 总7页 (文件大小：60K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4059B
LSI
Programmable divide-by-n counter
January 1995
Product specification
File under Integrated Circuits, IC04
Philips Semiconductors
Product specification
HEF4059B
LSI
Programmable divide-by-n counter
wide pulse and occurs at a rate equal to the input
DESCRIPTION
frequency divided by n. The single output (O) has TTL
drive capability. The down counter is preset by means of
16 jam inputs (J1 to J16); continued on next page.
The HEF4059B is a divide-by-n counter which can be
programmed to divide an input frequency by any number
n from 3 to 15 999. The output signal is a one clock-cycle
Fig.1 Functional block diagram.
PINNING
CP
clock input
Ka, Kb, Kc
J1 to J16
EL
mode select inputs
programmable jam inputs (BCD)
latch enable input
O
divide-by-n output
HEF4059BP(N): 24-lead DIL; plastic (SOT101-1)
HEF4059BD(F): 24-lead DIL; ceramic (cerdip) (SOT94)
HEF4059BT(D): 24-lead SO; plastic (SOT137-1)
( ): Package Designator North America
Fig.2 Pinning diagram.
FAMILY DATA, IDD LIMITS category LSI
See Family Specifications
January 1995
2
Philips Semiconductors
Product specification
HEF4059B
LSI
Programmable divide-by-n counter
The three mode selection inputs Ka, Kb and Kc determine
the modulus (‘divide-by’ number) of the first and last
counting sections in accordance with Table 1.
Every time the first (fastest) counting section goes through
one cycle, it reduces, by 1, the number that has been
preset (jammed) into the three decades of the intermediate
counting section and into the last counting section (which
consists of flip-flops that are not needed for operating the
first counting section).
For example, in the ÷ 2 mode, only one flip-flop is needed
in the first counting section. Therefore the last (5th)
counting section has three flip-flops that can be preset to a
maximum count of seven with a place value of thousands.
This counting mode is selected when Ka, Kb and Kc are set
to HIGH. In this case input J1 is used to preset the first
counting section and J2 to J4 are used to preset the last
(5th) counting section.
If ÷ 10 mode is desired for the first section, Ka is set HIGH,
Kb to HIGH and Kc to LOW. The jam inputs J1 to J4 are
used to preset the first counting section and there is no last
counting section. The intermediate counting section
consists of three cascaded BCD decade (÷ 10) counters,
presettable by means of the jam inputs J5 to J16.
When clock pulses are applied to the clock input after a
number n has been preset into the counter, the counter
counts down until the DETECTION circuit detects the zero
state. At this time the PRESET ENABLE circuit is enabled
to preset again the number n into the counter and to
produce an output pulse.
The preset of the counter to a desired ÷ n is achieved as
follows:
n = (MODE*) (1000 × decade 5 preset +
100 × decade 4 preset + 10 × decade 3 preset +
1 × decade 2 preset) + decade 1 preset.
* MODE = first counting section divider (10, 8, 5, 4 or 2).
To calculate preset values for any n count, divide the
n count by the selected mode. The resultant is the
corresponding preset values of the 5th to the 2nd decade
with the remainder being equal to the 1st decade value.
˙
n
---------------
preset value =
.
mode
If n = 8479, and the selected mode = 5, the preset value
= 8479 ÷ 5 = 1695 with a remainder of 4, thus the jam
inputs must be set as follows:
4
J2
L
1
J4
H
5
9
6
J1
L
J3
H
J5
H
J6
L
J7
H
J8
L
J9
H
J10
L
J11
L
J12
H
J13
L
J14
H
J15
H
J16
L
The mode select inputs permit frequency-synthesizer
channel separations of 10, 12,5, 20, 25 and 50 parts.
The last counting section can be preset to a maximum of
1, with a place value of 1000. The total of these numbers
(2665) times 8 equals 21 320. The first counting section
can be preset to a maximum of 7. Therefore, 21 327 is the
maximum possible count in the ÷ 8 mode. The highest
count of the various modes is shown in Table 1, in the
column entitled ‘extended counter range’. Control inputs
Kb and Kc can be used to initiate and lock the counter in
the ‘master preset’ mode. In this condition the flip-flops in
the counter are preset in accordance with the jam inputs
and the counter remains in that mode as long as Kb and
Kc both remain LOW. The counter begins to run down from
the preset state when a counting mode other than the
‘master preset’ mode is selected. Whenever the ‘master
preset’ mode is used, control signals Kb = L and Kc = L
must be applied for at least 3 full clock pulses. After the
master preset mode inputs have been changed to one of
the counting modes, the next positive-going clock
These inputs set the maximum value of n at 9999 (when
the first counting section divides by 5 or 10) or at 15 999
(when the first counting section divides by 8, 4 or 2).
The three decades of the intermediate counting section
can be preset to a binary 15 instead of a binary 9. In this
case the first cycle of a counter consists of 15 count
pulses, the next cycles consisting of 10 count pulses. Thus
the place value of the three decades are still 1, 10 and 100.
For example, in the ÷ 8 mode, the number from which the
intermediate counting section begins to count-down can
be preset to:
3rd decade: 1500
2nd decade:
1st decade:
150
15
transition changes an internal flip-flop so that the
count-down can begin at the second positive-going clock
transition. Thus, after a ‘master preset’ mode, there is
always one extra count before the output goes HIGH.
1665
January 1995
3
Philips Semiconductors
Product specification
HEF4059B
LSI
Programmable divide-by-n counter
Figure 3 illustrates the operation of the counter in mode ÷ 8 starting from the preset state 3.
CP INPUT
Kc INPUT
(Ka, Kb = LOW)
internal state
of counter
O OUTPUT
Fig.3 Total count of 3.
If the ‘master preset’ mode is started two clock cycles or
less before an output pulse, the output pulse will appear at
the time due. If the ‘master preset’ mode is not used the
counter is preset in accordance with the ‘jam inputs when
the output pulse appears. A HIGH level at the latch enable
input (EL) will cause the counter output to go HIGH once
an output pulse occurs, and remain in the HIGH state until
EL input returns to LOW. If the EL input is LOW, the output
pulse will remain HIGH for only one cycle of the clock input
signal.
When Ka = L, Kb = H, Kc = L and EL = L, the counter
operates in the ‘preset inhibit’ mode, with which the
dividend of the counter is fixed to 10 000, independent of
the state of the jam inputs.
When in the same state of mode select inputs EL = H, the
counter operates in the normal ÷ 10 mode, however,
without the latch operation at the output.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
January 1995
4
Philips Semiconductors
Product specification
HEF4059B
LSI
Programmable divide-by-n counter
FUNCTION TABLE
LATCH
ENABLE
INPUT
MODE
SELECT
INPUTS
FIRST COUNTING
SECTION
LAST COUNTING
SECTION
COUNTER
RANGE
DECADE 1
DECADE 5
OPERATION
MAX.
Ka Kb Kc MODE PRESET INPUTS
STATE USED
JAM
MAX.
JAM
DIVIDE
BY
BCD
MAX.
BINARY
MAX.
LE
PRESET INPUTS
STATE
USED
J2J3J4
J3J4
J4
H
H
H
H
H
L
H
L
H
H
L
H
H
H
H
L
2
1
J1
8
4
2
2
1
8
4
2
2
1
1
7
15 999 17 331
15 999 18 663
9 999 13 329 timer mode
15 999 21 327
9 999 16 659
4
3
4
7
9
1
3
4
7
9
9
J1J2
3
1
1
0
7
3
1
1
0
0
H
L
5
J1J2J3
J1J2J3
J1J2J3J4
J1
L
8
J4
H
H
L
H
H
H
L
10
2
−
H
H
H
H
L
J2J3J4
J3J4
J4
15 999 17 331
15 999 18 663
9 999 13 329
L
4
J1J2
L
H
L
5
J1J2J3
J1J2J3
J1J2J3J4
J1J2J3J4
divide-by-n mode
L
L
8
J4
15 999 21 327
9 999 16 659
9 999 16 659
L
H
L
H
H
10
10
−
H
L
−
fixed
−
divide-by-10 000
mode
L
L
H
L
L
L
preset inhibited
master preset
preset inhibited
master preset
10 000
−
−
master preset
mode
X
X
Note
1. It is recommended that the device is in the master preset mode (Kb = Kc = logic 0) in order to correctly initialize the
device prior to start up.
2. H = HIGH voltage level
L = LOW voltage level
X = don’t care
DC CHARACTERISTICS
VSS = 0 V
Tamb (°C)
VDD
V
SYMBOL
UNIT
−40
MIN.
+ 25
MIN.
+ 85
MIN.
Output (sink)
current LOW
4,75
10
15
5
2,7
9,5
24
2,3
8
1,8
6,3
16
mA
mA
mA
mA
mA
mA
VO = 0,4 V; VI = 0 or 4,75 V
VO = 0,5 V; VI = 0 or 10 V
VO = 1,5 V; VI = 0 or 15 V
VO = 4,6 V; VI = 0 or 5 V
VO = 9,5 V; VI = 0 or 10 V
VO = 13,5 V; VI = 0 or 15 V
IOL
20
0,7
2
Output (source)
current HIGH
0,8
2,4
8,4
0,5
1,6
5,6
10
15
−IOH
7
Output (source)
current HIGH
5
−IOH
2,4
2
5
1,6
mA
VO = 2,5 V; VI = 0 or 5 V
January 1995
Philips Semiconductors
Product specification
HEF4059B
LSI
Programmable divide-by-n counter
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; input transition times ≤ 20 ns
VDD
V
TYPICAL FORMULA FOR P (µW)
2
Dynamic power
5
1 100 fi + ∑(foCL) × VDD
where
2
dissipation per
10
15
5
5 500 fi + ∑(foCL) × VDD
fi = input freq. (MHz)
2
package (P); n = 3
15 000 fi + ∑(foCL) × VDD
fo = output freq. (MHz)
CL = load capacitance (pF)
∑(foCL) = sum of outputs
VDD = supply voltage (V)
2
500 fi + ∑(foCL) × VDD
3 500 fi + ∑(foCL) × VDD
9 000 fi + ∑(foCL) × VDD
2
2
n = 1000
10
15
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
TYPICAL EXTRAPOLATION
FORMULA
SYMBOL MIN.
TYP.
MAX.
Propagation delays
CP → O
5
90
45
35
100
50
40
30
15
10
45
25
16
7
180
90
ns
78 ns
40 ns
32 ns
76 ns
40 ns
33 ns
10 ns
6 ns
+
+
+
+
+
+
+
+
+
+
+
+
(0,25 ns/pF) CL
(0,10 ns/pF) CL
(0,07 ns/pF) CL
(0,48 ns/pF) CL
(0,20 ns/pF) CL
(0,15 ns/pF) CL
(0,40 ns/pF) CL
(0,18 ns/pF) CL
(0,13 ns/pF) CL
(0,70 ns/pF) CL
(0,33 ns/pF) CL
(0,23 ns/pF) CL
10
15
5
tPHL
ns
HIGH to LOW
70
ns
200
100
80
ns
LOW to HIGH
10
15
5
tPLH
tTHL
tTLH
ns
ns
Output transition times
HIGH to LOW
60
ns
10
15
5
30
ns
20
ns
4 ns
90
ns
10 ns
9 ns
LOW to HIGH
10
15
5
50
ns
32
ns
5 ns
Maximum clock
pulse frequency
3,5
MHz
MHz
MHz
10
15
fmax
7,5
15
20
10,0
January 1995
6
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