HEF4066BT-Q100J [NXP]
HEF4066B-Q100 - Quad single-pole single-throw analog switch SOIC 14-Pin;
| 型号： | HEF4066BT-Q100J |
| 厂家： | 
NXP |
| 描述： | HEF4066B-Q100 - Quad single-pole single-throw analog switch SOIC 14-Pin |
| 文件： | 总15页 (文件大小：171K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HEF4066B-Q100
Quad single-pole single-throw analog switch
Rev. 1 — 7 August 2012
Product data sheet
1. General description
The HEF4066B-Q100 provides four single-pole, single-throw analog switch functions.
Each switch has two input/output terminals (nY and nZ) and an active HIGH enable input
(nE). When nE is LOW, the analog switch is turned off.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
ESD protection:
MIL-STD-833, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Inputs and outputs are protected against electrostatic effects
Complies with JEDEC standard JESD 13-B
3. Applications
Industrial and automotive
Analog multiplexing and demultiplexing
Digital multiplexing and demultiplexing
Signal gating
4. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
HEF4066BT-Q100
40 C to +125 C
SO14
plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
HEF4066B-Q100
NXP Semiconductors
Quad single-pole single-throw analog switch
5. Functional diagram
1
2
1Y
1Z
13
4
1E
2Y
2E
3Y
3E
nY
3
9
2Z
3Z
nE
5
8
V
V
DD
DD
6
11
12
10
4Y
4E
4Z
V
nZ
SS
001aag200
001aag201
Fig 1. Functional diagram
Fig 2. Logic diagram (one switch)
6. Pinning information
6.1 Pinning
HEF4066B-Q100
1
2
3
4
5
6
7
14
13
12
11
10
9
1Y
1Z
VDD
1E
4E
4Y
4Z
2Z
2Y
2E
3E
3Z
VSS
8
3Y
aaa-003549
Fig 3. Pin configuration
6.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
1Y, 2Y, 3Y, 4Y
1Z, 2Z, 3Z, 4Z
1E, 2E, 3E, 4E
VSS
1, 4, 8, 11
2, 3, 9, 10
13, 5, 6, 12
7
independent input or output
independent input or output
enable input (active HIGH)
ground (0 V)
VDD
14
supply voltage
HEF4066B_Q100
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 7 August 2012
2 of 15
HEF4066B-Q100
NXP Semiconductors
Quad single-pole single-throw analog switch
7. Functional description
Table 3.
Function table[1]
Input nE
Switch
ON
H
L
OFF
[1] H = HIGH voltage level; L = LOW voltage level.
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground).
Symbol Parameter
Conditions
Min
0.5
-
Max
+18
Unit
V
VDD
IIK
supply voltage
input clamping current
input voltage
VI < 0.5 V or VI > VDD + 0.5 V
10
mA
V
VI
0.5
-
VDD + 0.5
10
[1]
[2]
II/O
Tstg
Tamb
Ptot
P
input/output current
storage temperature
ambient temperature
total power dissipation
power dissipation
mA
C
65
40
-
+150
+85
C
Tamb = 40 C to +85 C
500
mW
mW
per switch
-
100
[1] To avoid drawing VDD current out of terminal nZ, when switch current flows into terminals nY, the voltage drop across the bidirectional
switch must not exceed 0.4 V. If the switch current flows into terminal nZ, no VDD current flows out of terminals nY. In this case, there is
no limit for the voltage drop across the switch, but the voltages at nY and nZ may not exceed VDD or VSS
.
[2] For SO14 packages: above Tamb = 70 C, Ptot derates linearly with 8 mW/K.
9. Recommended operating conditions
Table 5.
Symbol
VDD
Recommended operating conditions
Parameter
Conditions
Min
Typ
Max
15
Unit
V
supply voltage
input voltage
3
-
-
-
-
-
-
VI
0
VDD
+125
3.75
0.5
V
Tamb
ambient temperature
in free air
40
C
t/V
input transition rise and fall VDD = 5 V
-
-
-
s/V
s/V
s/V
rate
VDD = 10 V
VDD = 15 V
0.08
HEF4066B_Q100
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 7 August 2012
3 of 15
HEF4066B-Q100
NXP Semiconductors
Quad single-pole single-throw analog switch
10. Static characteristics
Table 6.
Static characteristics
VSS = 0 V; VI = VSS or VDD unless otherwise specified.
Symbol Parameter
Conditions
VDD
Tamb = 40 C Tamb = 25 C Tamb = 85 C Tamb = 125 C Unit
Min
Max
-
Min
Max
-
Min
Max
-
Min
Max
-
VIH
HIGH-level
input voltage
IO < 1 A
5 V
10 V
15 V
5 V
3.5
3.5
3.5
3.5
V
V
V
V
V
V
7.0
-
7.0
-
7.0
-
7.0
-
11.0
-
11.0
-
11.0
-
11.0
-
VIL
LOW-level
input voltage
IO < 1 A
-
-
-
-
1.5
3.0
4.0
0.1
-
-
-
-
1.5
3.0
4.0
0.1
-
-
-
-
1.5
3.0
4.0
1.0
-
-
-
-
1.5
3.0
4.0
10 V
15 V
15 V
II
input leakage
current
1.0 A
IS(OFF)
OFF-state
leakage
current
per channel;
see Figure 4
15 V
-
-
-
200
-
-
-
-
nA
IDD
supply current all valid input
combinations
5 V
10 V
15 V
-
-
-
-
-
1.0
2.0
4.0
-
-
-
-
-
1.0
2.0
4.0
7.5
-
-
-
-
7.5
15.0
30.0
-
-
-
-
-
7.5 A
15.0 A
30.0 A
CI
input
nE input
-
pF
capacitance
10.1 Test circuit
V
DD
nE
nZ
V
IL
nY
I
S
V
V
V
O
I
SS
001aak669
Fig 4. Test circuit for measuring OFF-state leakage current
HEF4066B_Q100
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 7 August 2012
4 of 15
HEF4066B-Q100
NXP Semiconductors
Quad single-pole single-throw analog switch
10.2 ON resistance
Table 7.
ON resistance
Tamb = 25 C; ISW = 200 A; VSS = 0 V.
Symbol Parameter
Conditions
VDD
5 V
Typ
350
80
Max
2500
245
175
340
160
115
365
200
155
-
Unit
RON(peak) ON resistance (peak)
VI = 0 V to VDD; see Figure 5 and
Figure 6
10 V
15 V
5 V
60
RON(rail)
ON resistance (rail)
VI = 0 V; see Figure 5 and Figure 6
VI = VDD; see Figure 5 and Figure 6
VI = 0 V to VDD; see Figure 5
115
50
10 V
15 V
5 V
40
120
65
10 V
15 V
5 V
50
RON
ON resistance mismatch
between channels
25
10 V
15 V
10
-
5
-
10.2.1 ON resistance waveform and test circuit
001aak671
400
R
ON
(Ω)
(1)
300
V
SW
200
100
0
V
DD
nE
nY
V
IH
(2)
(3)
nZ
V
V
I
SW
I
SS
0
5
10
15
V (V)
I
001aak670
RON = VSW / ISW
.
ISW = 200 A.
VDD = 5 V
(1)
(2) VDD = 10 V
(3) VDD = 15 V
Fig 5. Test circuit for measuring RON
Fig 6. Typical RON as a function of input voltage
HEF4066B_Q100
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 7 August 2012
5 of 15
HEF4066B-Q100
NXP Semiconductors
Quad single-pole single-throw analog switch
11. Dynamic characteristics
Table 8.
Dynamic characteristics
Tamb = 25 C; VSS = 0 V; for test circuit see Figure 9.
Symbol Parameter Conditions
VDD
5 V
Typ
10
5
Max
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tPHL
HIGH to LOW propagation delay nY, nZ to nZ, nY; see Figure 7
nY, nZ to nZ, nY; see Figure 7
10 V
15 V
5 V
10
5
10
10
5
20
10 V
15 V
5 V
10
5
10
tPHZ
tPZH
tPLZ
tPZL
HIGH to OFF-state
propagation delay
nE to nY, nZ; see Figure 8
nE to nY, nZ; see Figure 8
nE to nY, nZ; see Figure 8
nE to nY, nZ; see Figure 8
80
65
60
40
20
15
80
70
70
45
20
15
160
130
120
80
10 V
15 V
5 V
OFF-state to HIGH
propagation delay
10 V
15 V
5 V
40
30
LOW to OFF-state
propagation delay
160
140
140
90
10 V
15 V
5 V
OFF-state to LOW
propagation delay
10 V
15 V
40
30
Table 9.
Dynamic power dissipation PD
PD can be calculated from the formulas shown; VSS = 0 V; tr = tf 20 ns; Tamb = 25 C.
Symbol
Parameter
VDD
5 V
Typical formula for PD (W)
where:
2
PD
dynamic power
dissipation
PD = 2500 fi + (fo CL) VDD
fi = input frequency in MHz;
fo = output frequency in MHz;
2
2
10 V
15 V
PD = 11500 fi + (fo CL) VDD
CL = output load capacitance in pF;
DD = supply voltage in V;
(CL fo) = sum of the outputs.
PD = 29000 fi + (fo CL) VDD
V
HEF4066B_Q100
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 7 August 2012
6 of 15
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NXP Semiconductors
Quad single-pole single-throw analog switch
11.1 Waveforms and test circuit
V
I
V
V
M
input nY or nZ
0 V
M
t
t
PLH
PHL
V
O
V
V
M
output nZ or nY
M
0 V
001aak672
Measurement points are given in Table 10.
Fig 7. nY or nZ to nZ or nY propagation delays
V
I
V
V
M
input nE
output nY or nZ
output nY or nZ
M
0 V
t
t
PZL
PLZ
V
DD
90 %
10 %
0 V
t
t
PZH
PHZ
V
DD
90 %
10 %
switch ON
0 V
switch ON
switch OFF
001aak673
Measurement points are given in Table 10.
Fig 8. Enable and disable times
Table 10. Measurement points
Supply voltage
VDD
Input
VM
Output
VM
5 V to 15 V
0.5VDD
0.5VDD
HEF4066B_Q100
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 7 August 2012
7 of 15
HEF4066B-Q100
NXP Semiconductors
Quad single-pole single-throw analog switch
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
V
V
DD
DD
I
V
V
O
I
S1
R
L
G
open
DUT
R
T
C
L
V
SS
001aak674
Test data is given in Table 11.
Definitions:
DUT = Device Under Test.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including test jig and probe.
RL = Load resistance.
Fig 9. Test circuit for measuring switching times
Table 11. Test data
Supply voltage Input
Load
CL
S1 position
tPHL, tPLH
VSS
VDD
VI
tr, tf
RL
tPZH, tPHZ
tPZL, tPLZ
5 V to 15 V
0 V or VDD
20 ns
50 pF
10 k
VSS
VDD
11.2 Additional dynamic parameters
Table 12. Additional dynamic characteristics
VSS = 0 V; Tamb = 25 C.
Symbol
Parameter
Conditions
VDD
Typ
Max
Unit
[1]
THD
total harmonic distortion
see Figure 10; RL = 10 k; CL = 15 pF; 5 V
0.25
-
-
-
-
%
channel ON; VI = 0.5VDD (p-p);
fi = 1 kHz
[1]
10 V
0.04
%
[1]
15 V
10 V
0.04
%
Vct
crosstalk voltage
nE input to switch; see Figure 11;
RL = 10 k; CL = 15 pF;
50
mV
nE = VDD (square-wave)
HEF4066B_Q100
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 7 August 2012
8 of 15
HEF4066B-Q100
NXP Semiconductors
Quad single-pole single-throw analog switch
Table 12. Additional dynamic characteristics …continued
VSS = 0 V; Tamb = 25 C.
Symbol
Parameter
Conditions
VDD
Typ
Max
Unit
[1]
Xtalk
crosstalk
between switches; see Figure 12;
fi = 1 MHz; RL = 1 k;
10 V
50
-
dB
VI = 0.5VDD (p-p)
[1]
[1]
iso
isolation (OFF-state)
see Figure 13; fi = 1 MHz; RL = 1 k;
CL = 5 pF; VI = 0.5VDD (p-p)
10 V
10 V
50
-
-
dB
f(3dB)
3 dB frequency response see Figure 14; RL = 1 k; CL = 5 pF;
90
MHz
VI = 0.5VDD (p-p)
[1] fi is biased at 0.5VDD
.
11.2.1 Test circuits
V
DD
nE
nY
V
IH
nZ
V
SS
R
L
C
L
f
D
i
001aak675
Fig 10. Test circuit for measuring total harmonic distortion
0.5V
V
DD
DD
R
L
nE
nY
nZ
V
SS
G
R
L
C
L
V
V
O
001aak676
a. Test circuit
logic
input nE
off
on
off
V
O
V
ct
001aak677
b. Input and output pulse definitions
Fig 11. Test circuit for measuring crosstalk voltage between digital input and switch
HEF4066B_Q100
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 7 August 2012
9 of 15
HEF4066B-Q100
NXP Semiconductors
Quad single-pole single-throw analog switch
V
DD
1E
V
IH
1Y or 1Z
1Z or 1Y
CHANNEL
ON
V
R
L
V
V
O1
I
nE
V
IL
nY or nZ
nZ or nY
CHANNEL
OFF
R
L
R
L
V
V
O2
V
SS
001aak678
20 log10 (VO2 / VO1) or 20 log10 (VO1 / VO2).
Fig 12. Test circuit for measuring crosstalk between switches
V
V
DD
DD
nE
nY
nE
nY
V
V
IH
IL
nZ
nZ
V
V
SS
SS
R
L
C
L
R
L
C
L
f
f
i
dB
dB
i
001aak679
001aak680
Adjust fi voltage to obtain 0 dBm level at input.
Adjust fi voltage to obtain 0 dBm level at output. Increase
fi frequency until dB meter reads 3 dB.
Fig 13. Test circuit for measuring isolation (OFF-state) Fig 14. Test circuit for measuring frequency response
HEF4066B_Q100
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 7 August 2012
10 of 15
HEF4066B-Q100
NXP Semiconductors
Quad single-pole single-throw analog switch
12. Package outline
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A
X
v
c
y
H
M
A
E
Z
8
14
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
7
e
detail X
w
M
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.75
1.27
0.05
1.05
0.25
0.01
0.25
0.1
0.25
0.01
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.024
0.028
0.012
inches
0.041
0.01 0.004
0.069
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT108-1
076E06
MS-012
Fig 15. Package outline SOT108-1 (SO14)
HEF4066B_Q100
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 7 August 2012
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Quad single-pole single-throw analog switch
13. Abbreviations
Table 13. Abbreviations
Acronym
HBM
ESD
Description
Human Body Model
ElectroStatic Discharge
Machine Model
Military
MM
MIL
14. Revision history
Table 14. Revision history
Document ID
Release date Data sheet status
20120807 Product specification
Change notice
Supersedes
HEF4066B_Q100 v.1
-
-
HEF4066B_Q100
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Product data sheet
Rev. 1 — 7 August 2012
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Quad single-pole single-throw analog switch
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use in automotive applications — This NXP
15.2 Definitions
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
HEF4066B_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 7 August 2012
13 of 15
HEF4066B-Q100
NXP Semiconductors
Quad single-pole single-throw analog switch
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
HEF4066B_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 7 August 2012
14 of 15
HEF4066B-Q100
NXP Semiconductors
Quad single-pole single-throw analog switch
17. Contents
1
2
3
4
5
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2
7
8
9
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
Recommended operating conditions. . . . . . . . 3
10
Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
Test circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
ON resistance. . . . . . . . . . . . . . . . . . . . . . . . . . 5
ON resistance waveform and test circuit . . . . . 5
10.1
10.2
10.2.1
11
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
Waveforms and test circuit . . . . . . . . . . . . . . . . 7
Additional dynamic parameters . . . . . . . . . . . . 8
Test circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
11.1
11.2
11.2.1
12
13
14
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 12
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 12
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 13
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 14
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2012.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 7 August 2012
Document identifier: HEF4066B_Q100
相关型号：
HEF4066BT-T
IC QUAD 1-CHANNEL, SGL POLE SGL THROW SWITCH, PDSO14, 3.90 MM, PLASTIC, MS-012, SOT108-1, SOP-14, Multiplexer or Switch
NXP
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