HEF4067BT-Q100J [NXP]
HEF4067B-Q100 - 16-channel analog multiplexer/demultiplexer SOP 24-Pin;
| 型号： | HEF4067BT-Q100J |
| 厂家： | 
NXP |
| 描述： | HEF4067B-Q100 - 16-channel analog multiplexer/demultiplexer SOP 24-Pin 光电二极管 |
| 文件： | 总17页 (文件大小：144K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HEF4067B-Q100
16-channel analog multiplexer/demultiplexer
Rev. 1 — 24 September 2013
Product data sheet
1. General description
The HEF4067B-Q100 is a 16-channel analog multiplexer/demultiplexer. It has four
address inputs (A0 to A3), an active LOW enable input (E), 16 independent inputs/outputs
(Y0 to Y15) and a common input/output (Z). The device contains 16 bidirectional analog
switches. Each switch has one side connected to an independent input/output (Y0 to
Y15) and the other side connected to the common input/output (Z). With E LOW, one of
the 16 switches is selected (low-impedance ON-state) by A0 to A3. All unselected
switches are in the high-impedance OFF-state. With E HIGH all switches are in the
high-impedance OFF-state, independent of A0 to A3. The analog inputs/outputs (Y0 to
Y15 and Z) can swing between VDD as a positive limit and VSS as a negative limit. VDD to
V
SS may not exceed 15 V.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 3) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 3)
Specified from 40 C to +85 C
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Complies with JEDEC standard JESD 13-B
3. Applications
Analog multiplexing and demultiplexing
Digital multiplexing and demultiplexing
Signal gating
NXP Semiconductors
HEF4067B-Q100
16-channel analog multiplexer/demultiplexer
4. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name Description
Version
HEF4067BT-Q100 40 C to +85 C
SO24
plastic small outline package; 24 leads; body width 7.5 mm SOT137-1
5. Functional diagram
9
8
7
6
5
4
3
2
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
A0 10
A1 11
A2 14
A3 13
23 Y8
1-OF-16
DECODER
22 Y9
21 Y10
20 Y11
19 Y12
18 Y13
17 Y14
16 Y15
E
15
1
Z
001aag123
Fig 1. Functional diagram
Yn
V
DD
V
DD
Z
V
SS
001aag126
Fig 2. Schematic diagram (one switch)
HEF4067B_Q100
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 24 September 2013
2 of 17
NXP Semiconductors
HEF4067B-Q100
16-channel analog multiplexer/demultiplexer
Y0
Y1
Y2
Y3
Y4
A0
A1
A2
A3
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
E
Z
001aag125
Fig 3. Logic diagram
HEF4067B_Q100
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 24 September 2013
3 of 17
NXP Semiconductors
HEF4067B-Q100
16-channel analog multiplexer/demultiplexer
6. Pinning information
6.1 Pinning
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Fig 4. Pin configuration
6.2 Pin description
Table 2.
Symbol
Z
Pin description
Pin
Description
1
common input/output
independent input/output
address input
Y0 to Y15
A0 to A3
VSS
9, 8, 7, 6, 5, 4, 3, 2, 23, 22, 21, 20, 19, 18, 17, 16
10, 11, 14, 13
12
15
24
ground (0 V)
E
enable input (active LOW)
supply voltage
VDD
HEF4067B_Q100
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 24 September 2013
4 of 17
NXP Semiconductors
HEF4067B-Q100
16-channel analog multiplexer/demultiplexer
7. Functional description
Table 3.
Function table[1]
Control
Address
Channel ON
E
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
A3
L
A2
L
A1
L
A0
L
Y0 = Z
Y1 = Z
Y2 = Z
Y3 = Z
Y4 = Z
Y5 = Z
Y6 = Z
Y7 = Z
Y8 = Z
Y9 = Z
Y10 = Z
Y11 = Z
Y12 = Z
Y13 = Z
Y14 = Z
Y15 = Z
none
L
L
L
H
L
L
L
H
H
L
L
L
H
L
L
H
H
H
H
L
L
L
H
L
L
H
H
L
L
H
L
H
H
H
H
H
H
H
H
X
L
L
H
L
L
H
H
L
L
H
L
H
H
H
H
X
L
H
L
H
H
X
H
X
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground).
Symbol Parameter
Conditions
Min
0.5
-
Max
+18
10
Unit
V
VDD
IIK
supply voltage
input clamping current
pins An and E;
mA
VI < 0.5 V or VI > VDD + 0.5 V
VI
input voltage
0.5
VDD + 0.5
10
V
[1]
[2]
II/O
IDD
Tstg
Tamb
Ptot
P
input/output current
supply current
-
mA
mA
C
-
50
storage temperature
ambient temperature
total power dissipation
power dissipation
65
+150
+85
40
C
Tamb = 40 C to +125 C
-
-
500
mW
mW
per output
100
[1] To avoid drawing VDD current from terminal Z, when switch current flows into terminals Yn, the voltage drop across the bidirectional
switch must not exceed 0.4 V. If the switch current flows into terminal Z, no VDD current flows from terminals Yn. In this case, there is no
limit for the voltage drop across the switch, but the voltages at Y and Z may not exceed VDD or VSS
.
[2] For SO24 packages: above Tamb = 70 C, Ptot derates linearly at 8 mW/K.
HEF4067B_Q100
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 24 September 2013
5 of 17
NXP Semiconductors
HEF4067B-Q100
16-channel analog multiplexer/demultiplexer
9. Recommended operating conditions
Table 5.
Symbol
VDD
Recommended operating conditions
Parameter
Conditions
Min
Typ
Max
15
Unit
V
supply voltage
3
-
-
-
-
-
-
VI
input voltage
0
VDD
+85
3.75
0.5
V
Tamb
ambient temperature
input transition rise and fall rate
in free air
40
C
t/V
VDD = 5 V
VDD = 10 V
VDD = 15 V
-
-
-
s/V
s/V
s/V
0.08
10. Static characteristics
Table 6.
Static characteristics
VSS = 0 V; VI = VSS or VDD; unless otherwise specified.
Symbol Parameter Conditions
VDD
Tamb = 40 C Tamb = +25 C Tamb = +85 C Unit
Min
Max
Min
Max
Min
Max
VIL
LOW-level input IO < 1 A
voltage
VO = 0.5 V or 4.5 V
5 V
-
-
-
1
2
-
-
-
1
2
-
-
-
1
2
V
V
V
VO = 1.0 V or 9.0 V
VO = 1.5 V or 13.5 V
10 V
15 V
2.5
2.5
2.5
VIH
HIGH-level input IO < 1 A
voltage
VO = 0.5 V or 4.5 V
VO = 1.0 V or 9.0 V
VO = 1.5 V or 13.5 V
VI = 0 V or 15 V
5 V
4
8
-
4
8
-
4
8
-
-
-
V
V
V
10 V
15 V
15 V
-
-
-
-
12.5
-
12.5
-
12.5
-
II
input leakage
current
0.3
0.3
1.0 A
IOZ
OFF-state output output at VDD
15 V
15 V
15 V
-
-
-
1.6
1.6
-
-
-
-
1.6
-
-
-
12.0 A
12.0 A
current
output at VSS
1.6
1000
IS(OFF)
OFF-state
Z port; all channels OFF;
-
nA
leakage current
see Figure 5
Yn port; per channel;
see Figure 6
15 V
-
-
-
200
-
-
nA
IDD
supply current
all valid input combinations; 5 V
IO = 0 A
-
-
-
-
20
40
80
-
-
-
-
-
20
40
80
7.5
-
-
-
-
150 A
300 A
600 A
10 V
15 V
15 V
CI
input capacitance digital inputs
-
pF
HEF4067B_Q100
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 24 September 2013
6 of 17
NXP Semiconductors
HEF4067B-Q100
16-channel analog multiplexer/demultiplexer
10.1 Test circuits
V
DD
A0 to A3
V
or V
DD
SS
Z
E
Yn
IS
V
SS
V
DD
V
V
I
O
001aal616
Fig 5. Test circuit for measuring OFF-state leakage current Z port
V
DD
A0 to A3
Y0
Yn
1
2
V
or V
V
switch
DD
SS
IS
Z
E
V
SS
SS
V
V
O
I
001aal617
Fig 6. Test circuit for measuring OFF-state leakage current Yn port
10.2 On resistance
Table 7.
ON resistance
Tamb = 25 C; ISW = 200 A; VSS = 0 V.
Symbol Parameter
Conditions
VDD
5 V
Typ
350
80
Max
2500
245
175
340
160
115
365
200
155
-
Unit
RON(peak) ON resistance (peak)
VI = 0 V to VDD; see Figure 7 and
Figure 8
10 V
15 V
5 V
60
RON(rail)
ON resistance (rail)
VI = 0 V; see Figure 7 and Figure 8
VI = VDD; see Figure 7 and Figure 8
VI = 0 V to VDD; see Figure 7
115
50
10 V
15 V
5 V
40
120
65
10 V
15 V
5 V
50
RON
ON resistance mismatch
between channels
25
10 V
15 V
10
-
5
-
HEF4067B_Q100
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 24 September 2013
7 of 17
NXP Semiconductors
HEF4067B-Q100
16-channel analog multiplexer/demultiplexer
10.2.1 On resistance waveform and test circuit
001aae648
400
R
ON
(Ω)
V
= 5 V
DD
300
V
SW
V
200
100
0
V
DD
A0 to A3
V
or V
V
DD
SS
10 V
Z
E
Yn
15 V
V
SS
SS
I
V
I
SW
0
5
10
15
V (V)
I
001aag127
RON = VSW / ISW
.
Iis = 200 A; VSS = 0 V.
Fig 7. Test circuit for measuring RON
Fig 8. Typical RON as a function of input voltage
11. Dynamic characteristics
Table 8.
Dynamic characteristics
Tamb = 25 C; VSS = 0 V; for test circuit, see Figure 12.
Symbol
Parameter
Conditions
Yn, Z to Z, Yn; see Figure 9 5 V
10 V
VDD
Min Typ Max Unit
tPHL
HIGH to LOW propagation delay
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
30
15
10
60
25
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15 V
5 V
An to Yn, Z; see Figure 10
190 380
10 V
15 V
70
50
25
10
10
145
100
50
tPLH
LOW to HIGH propagation delay
Yn, Z to Z, Yn; see Figure 9 5 V
10 V
20
15 V
5 V
20
An to Yn, Z; see Figure 10
175 345
10 V
15 V
5 V
70
50
140
100
tPHZ
HIGH to OFF-state propagation delay E to Yn, Z; see Figure 11
LOW to OFF-state propagation delay E to Yn, Z; see Figure 11
195 385
140 280
130 260
215 435
180 355
170 340
10 V
15 V
5 V
tPLZ
10 V
15 V
HEF4067B_Q100
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 24 September 2013
8 of 17
NXP Semiconductors
HEF4067B-Q100
16-channel analog multiplexer/demultiplexer
Table 8.
Dynamic characteristics …continued
Tamb = 25 C; VSS = 0 V; for test circuit, see Figure 12.
Symbol
Parameter
Conditions
VDD
5 V
Min Typ Max Unit
tPZH
OFF-state to HIGH propagation delay E to Yn, Z; see Figure 11
-
-
-
-
-
-
155 315
ns
ns
ns
ns
ns
ns
10 V
15 V
5 V
70
50
135
100
E to Yn, Z; see Figure 11
tPZL
OFF-state to LOW propagation delay
170 340
10 V
15 V
70
50
140
100
11.1 Waveforms and test circuit
V
DD
V
I
Yn or Z
input
V
M
V
M
An input
V
V
M
M
V
V
SS
0 V
t
t
PHL
PLH
t
t
PHL
PLH
V
O
V
Y
Yn or Z
output
V
OH
Yn or Z
output
V
X
V
V
M
M
SS
switch OFF
switch ON
switch OFF
001aal618
V
OL
001aag199
Measurement points are given in Table 9.
Measurement points are given in Table 9.
VOL and VOH are typical output voltage levels that occur
with the output load.
Fig 9. Yn, Z to Z, Yn propagation delays
Fig 10. Sn to Yn, Z propagation delays
V
I
V
V
M
E input
M
0 V
t
t
PZL
PLZ
V
DD
Yn or Z output
V
M
V
V
X
OL
t
t
PHZ
PZH
V
OH
V
Y
Yn or Z output
V
M
0 V
switch ON
switch OFF
switch ON
001aag198
Measurement points are shown in Table 9.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 11. Enable and disable times
HEF4067B_Q100
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 24 September 2013
9 of 17
NXP Semiconductors
HEF4067B-Q100
16-channel analog multiplexer/demultiplexer
Table 9.
Measurement points
Supply voltage
VCC
Input
VM
Output
VM
VI
VX
VY
5 V to 15 V
0.5VDD
GND to VDD
0.5VDD
10%
90%
V
V
DD
DD
V
I
V
O
S1
R
L
PULSE
GENERATOR
open
DUT
C
L
R
T
001aag183
Test data is given in Table 10.
Definitions test circuit:
RT = termination resistance should be equal to output impedance Zo of the pulse generator
CL = load capacitance including jig and probe capacitance
RL = load resistor
S1 = test selection switch
Fig 12. Test circuit for measuring switching times
Table 10. Test data
Input
Yn, Z
Load
CL
S1 position
[1]
An and E tr, tf
VM
RL
tPHL
tPLH
tPZH, tPHZ tPZL, tPLZ other
VDD or VSS VDD or VSS 20 ns
0.5VDD
50 pF
10 k
VDD or VSS VSS
VSS
VDD
VSS
[1] For Yn to Z or Z to Yn propagation delays, use VSS. For An or to Yn or Z propagation delays, use VDD
.
HEF4067B_Q100
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 24 September 2013
10 of 17
NXP Semiconductors
HEF4067B-Q100
16-channel analog multiplexer/demultiplexer
11.2 Additional dynamic parameters
Table 11. Additional dynamic characteristics
VSS = 0 V; Tamb = 25 C.
Symbol
Parameter
Conditions
VDD
Typ
0.25
0.04
0.04
13
Max
Unit
%
[1]
[1]
[1]
[1]
[1]
[1]
[1]
THD
total harmonic distortion
see Figure 13; RL = 10 k; CL = 15 pF; 5 V
channel ON; VI = 0.5VDD (p-p);
fi = 1 kHz
-
-
-
-
-
-
-
10 V
%
15 V
5 V
%
f(3dB)
3 dB frequency response see Figure 14; RL = 1 k; CL = 5 pF;
MHz
MHz
MHz
dB
channel ON; VI = 0.5VDD (p-p)
10 V
15 V
10 V
40
70
iso
isolation (OFF-state)
crosstalk voltage
crosstalk
see Figure 15; fi = 1 MHz; RL = 1 k;
CL = 5 pF; channel OFF;
VI = 0.5VDD (p-p)
50
Vct
digital inputs to switch; see Figure 16; 10 V
RL = 10 k; CL = 15 pF;
E or An = VDD (square-wave)
50
-
mV
dB
[1]
Xtalk
between switches; see Figure 17;
fi = 1 MHz; RL = 1 k;
10 V
50
-
VI = 0.5VDD (p-p)
[1] fi is biased at 0.5 VDD; VI = 0.5VDD (p-p).
Table 12. Dynamic power dissipation PD
PD can be calculated from the formulas shown; VSS = 0 V; tr = tf 20 ns; Tamb = 25 C.
Symbol
Parameter
VDD
5 V
Typical formula for PD (W)
PD = 1000 fi + (fo CL) VDD
PD = 5500 fi + (fo CL) VDD
where:
2
2
PD
dynamic power
dissipation
fi = input frequency in MHz;
fo = output frequency in MHz;
10 V
15 V
2
CL = output load capacitance in pF;
DD = supply voltage in V;
(CL fo) = sum of the outputs.
PD = 15000 fi + (fo CL) VDD
V
11.2.1 Test circuits
V
V
DD
DD
A0 to A3
A0 to A3
V
or V
V
V
or V
V
DD
SS
DD
SS
Z
E
Yn
Z
E
Yn
V
SS
V
SS
SS
SS
R
L
C
L
R
L
C
L
D
dB
fi
fi
001aag129
001aag235
Fig 13. Test circuit for measuring total harmonic
distortion
Fig 14. Test circuit for measuring frequency response
HEF4067B_Q100
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 24 September 2013
11 of 17
NXP Semiconductors
HEF4067B-Q100
16-channel analog multiplexer/demultiplexer
V
DD
A0 to A3
Y0
Yn
1
2
V
or V
V
switch
DD
SS
Z
E
V
SS
R
L
C
L
dB
SS
fi
001aal619
Fig 15. Test circuit for measuring isolation (OFF-state)
0.5V
V
DD
DD
R
L
A0 to A3
Y0
Yn
1
2
switch
Z
E
V
SS
V
DD
or V
SS
R
L
C
L
V
V
O
G
001aag128
a. Test circuit
logic
input (An, E)
off
on
off
V
O
Vct
001aal620
b. Input and output pulse definitions
Fig 16. Test circuit for measuring crosstalk voltage between digital inputs and switch
V
V
DD
DD
A0 to A3
Y0
Yn
A0 to A3
Y0
Yn
V
or V
V
V
or V
V
DD
SS
DD
SS
Z
E
Z
E
V
SS
V
SS
SS
SS
R
L
V
R
L
V
R
L
O
I
V
R
L
V
O
I
001aag130
001aag131
a. Switch closed condition
Fig 17. Test circuit for measuring crosstalk between switches
b. Switch open condition
HEF4067B_Q100
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 24 September 2013
12 of 17
NXP Semiconductors
HEF4067B-Q100
16-channel analog multiplexer/demultiplexer
12. Package outline
SO24: plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
D
E
A
X
c
H
v
M
A
E
y
Z
24
13
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
12
w
detail X
e
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(1)
(1)
UNIT
mm
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.3
0.1
2.45
2.25
0.49
0.36
0.32
0.23
15.6
15.2
7.6
7.4
10.65
10.00
1.1
0.4
1.1
1.0
0.9
0.4
2.65
0.1
0.25
0.01
1.27
0.05
1.4
0.25 0.25
0.01
0.1
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.61
0.014 0.009 0.60
0.30
0.29
0.419
0.394
0.043 0.043
0.016 0.039
0.035
0.016
inches
0.055
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT137-1
075E05
MS-013
Fig 18. Package outline SOT137-1 (SO24)
HEF4067B_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 24 September 2013
13 of 17
NXP Semiconductors
HEF4067B-Q100
16-channel analog multiplexer/demultiplexer
13. Abbreviations
Table 13. Abbreviations
Acronym
HBM
ESD
Description
Human Body Model
ElectroStatic Discharge
Machine Model
Military
MM
MIL
14. Revision history
Table 14. Revision history
Document ID
Release date
20130924
Data sheet status
Change notice
Supersedes
HEF4067B-Q100 v.1
Product data sheet
-
-
HEF4067B_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 24 September 2013
14 of 17
NXP Semiconductors
HEF4067B-Q100
16-channel analog multiplexer/demultiplexer
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use in automotive applications — This NXP
15.2 Definitions
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
HEF4067B_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 24 September 2013
15 of 17
NXP Semiconductors
HEF4067B-Q100
16-channel analog multiplexer/demultiplexer
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
HEF4067B_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 24 September 2013
16 of 17
NXP Semiconductors
HEF4067B-Q100
16-channel analog multiplexer/demultiplexer
17. Contents
1
2
3
4
5
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
7
8
9
Functional description . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 6
10
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Test circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
On resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 7
On resistance waveform and test circuit. . . . . . 8
10.1
10.2
10.2.1
11
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms and test circuit . . . . . . . . . . . . . . . . 9
Additional dynamic parameters . . . . . . . . . . . 11
Test circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . 11
11.1
11.2
11.2.1
12
13
14
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 14
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 14
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 15
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 16
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2013.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 24 September 2013
Document identifier: HEF4067B_Q100
相关型号：
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