HEF4068BT,652 [NXP]

HEF4068B - 8-input NAND gate SOIC 14-Pin;
HEF4068BT,652
型号: HEF4068BT,652
厂家: NXP    NXP
描述:

HEF4068B - 8-input NAND gate SOIC 14-Pin

栅 光电二极管 逻辑集成电路 触发器
文件: 总3页 (文件大小:33K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
INTEGRATED CIRCUITS  
DATA SHEET  
For a complete data sheet, please also download:  
The IC04 LOCMOS HE4000B Logic  
Family Specifications HEF, HEC  
The IC04 LOCMOS HE4000B Logic  
Package Outlines/Information HEF, HEC  
HEF4068B  
gates  
8-input NAND gate  
January 1995  
Product specification  
File under Integrated Circuits, IC04  
Philips Semiconductors  
Product specification  
HEF4068B  
gates  
8-input NAND gate  
DESCRIPTION  
The HEF4068B provides the 8-input NAND function. The  
outputs are fully buffered for highest noise immunity and  
pattern insensitivity of output impedance.  
Fig.2 Pinning diagram.  
Fig.1 Functional diagram.  
HEF4068BP(N): 14-lead DIL; plastic  
(SOT27-1)  
HEF4068BD(F): 14-lead DIL; ceramic (cerdip)  
(SOT73)  
HEF4068BT(D): 14-lead SO; plastic  
(SOT108-1)  
( ): Package Designator North America  
Fig.3 Logic diagram.  
FAMILY DATA, IDD LIMITS category GATES  
See Family Specifications  
January 1995  
2
Philips Semiconductors  
Product specification  
HEF4068B  
gates  
8-input NAND gate  
AC CHARACTERISTICS  
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times 20 ns  
VDD  
V
TYPICAL EXTRAPOLATION  
FORMULA  
SYMBOL TYP.  
MAX.  
Propagation delays  
In O  
HIGH to LOW  
5
95  
195  
85  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
68 ns  
29 ns  
22 ns  
53 ns  
24 ns  
22 ns  
10 ns  
9 ns  
+
+
+
+
+
+
+
+
+
+
+
+
(0,55 ns/pF) CL  
(0,23 ns/pF) CL  
(0,16 ns/pF) CL  
(0,55 ns/pF) CL  
(0,23 ns/pF) CL  
(0,16 ns/pF) CL  
(1,0 ns/pF) CL  
(0,42 ns/pF) CL  
(0,28 ns/pF) CL  
(1,0 ns/pF) CL  
(0,42 ns/pF) CL  
(0,28 ns/pF) CL  
10  
15  
5
tPHL  
tPLH  
tTHL  
tTLH  
40  
30  
80  
35  
30  
60  
30  
20  
60  
30  
20  
65  
165  
70  
LOW to HIGH  
10  
15  
5
60  
Output transition times  
HIGH to LOW  
120  
60  
10  
15  
5
40  
6 ns  
120  
60  
10 ns  
9 ns  
LOW to HIGH  
10  
15  
40  
6 ns  
VDD  
V
TYPICAL FORMULA FOR P (µW)  
2
Dynamic power  
dissipation per  
package (P)  
5
10  
15  
700 fi + ∑(foCL) × VDD  
where  
2
2900 fi + ∑(foCL) × VDD  
fi = input freq. (MHz)  
2
7200 fi + ∑(foCL) × VDD  
fo = output freq. (MHz)  
CL = load capacitance (pF)  
(foCL) = sum of outputs  
V
DD = supply voltage (V)  
January 1995  
3

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