HEF4070BN [NXP]
Quadruple exclusive-OR gate; 四倍异或门
| 型号： | HEF4070BN |
| 厂家： | 
NXP |
| 描述： | Quadruple exclusive-OR gate |
| 文件： | 总4页 (文件大小：35K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4070B
gates
Quadruple exclusive-OR gate
January 1995
Product specification
File under Integrated Circuits, IC04
Philips Semiconductors
Product specification
HEF4070B
gates
Quadruple exclusive-OR gate
DESCRIPTION
The HEF4070B provides the positive quadruple
exclusive-OR function. The outputs are fully buffered for
highest noise immunity and pattern insensitivity of output
impedance.
Fig.2 Pinning diagram.
HEF4070BP(N): 14-lead DIL; plastic
(SOT27-1)
HEF4070BD(F): 14-lead DIL; ceramic (cerdip)
(SOT73)
HEF4070BT(D): 14-lead SO; plastic
(SOT108-1)
( ): Package Designator North America
Fig.1 Functional diagram.
Fig.3 Logic diagram (one gate).
APPLICATION INFORMATION
TRUTH TABLE
Some examples of applications for the HEF4070B are:
• Logical comparators
I1
I2
O1
L
H
L
L
L
L
H
H
L
• Parity checkers and generators
H
H
FAMILY DATA, IDD LIMITS category GATES
H
See Family Specifications
Note
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
January 1995
2
Philips Semiconductors
Product specification
HEF4070B
gates
Quadruple exclusive-OR gate
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
TYPICAL EXTRAPOLATION
FORMULA
SYMBOL
TYP.
MAX.
Propagation delays
In → On
HIGH to LOW
5
85
35
30
75
30
25
60
30
20
60
30
20
175
75
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
58 ns
24 ns
21 ns
48 ns
19 ns
17 ns
10 ns
9 ns
+
+
+
+
+
+
+
+
+
+
+
+
(0,55 ns/pF) CL
(0,23 ns/pF) CL
(0,16 ns/pF) CL
(0,55 ns/pF) CL
(0,23 ns/pF) CL
(0,16 ns/pF) CL
(1,0 ns/pF) CL
(0,42 ns/pF) CL
(0,28 ns/pF) CL
(1,0 ns/pF) CL
(0,42 ns/pF) CL
(0,28 ns/pF) CL
10
15
5
tPHL
55
150
65
LOW to HIGH
10
15
5
tPLH
tTHL
tTLH
50
Output transition times
HIGH to LOW
120
60
10
15
5
40
6 ns
120
60
10 ns
9 ns
LOW to HIGH
10
15
40
6 ns
VDD
V
TYPICAL FORMULA FOR P (µW)
2
Dynamic power
dissipation per
package (P)
5
10
15
1100 fi + ∑ (foCL) × VDD
where
2
4900 fi + ∑ (foCL) × VDD
fi = input freq. (MHz)
2
14 400 fi + ∑ (foCL) × VDD
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (foCL) = sum of outputs
VDD = supply voltage (V)
January 1995
3
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相关型号：
HEF4070BP-Q100
4000/14000/40000 SERIES, QUAD 2-INPUT XOR GATE, PDIP14, 0.300 INCH, PLASTIC, MO-001, SC501-14, SOT27-1, DIP-14
NXP
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