HEF4071BT,653 [NXP]
HEF4071B - Quad 2-input OR gate SOIC 14-Pin;
| 型号： | HEF4071BT,653 |
| 厂家： | 
NXP |
| 描述： | HEF4071B - Quad 2-input OR gate SOIC 14-Pin 栅 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总11页 (文件大小：103K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HEF4071B
Quad 2-input OR gate
Rev. 06 — 1 December 2009
Product data sheet
1. General description
The HEF4071B is a quad 2-input OR gate. The outputs are fully buffered for highest noise
immunity and pattern insensitivity to output impedance variations.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
It is also suitable for use over both the industrial (−40 °C to +85 °C) and automotive
(−40 °C to +125 °C) temperature ranges.
2. Features
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Inputs and outputs are protected against electrostatic effects
Operates across the automotive temperature range from −40 °C to +125 °C
Complies with JEDEC standard JESD 13-B
3. Applications
Automotive and industrial
4. Ordering information
Table 1.
Ordering information
All types operate from −40 °C to +125 °C.
Type number
Package
Name
Description
Version
HEF4071BP
HEF4071BT
DIP14
SO14
plastic dual in-line package; 14 leads (300 mil)
plastic small outline package; 14 leads; body width 3.9 mm
SOT27-1
SOT108-1
HEF4071B
NXP Semiconductors
Quad 2-input OR gate
5. Functional diagram
1
2
1A
1B
1Y
2Y
3Y
3
4
5
6
2A
2B
8
9
3A
3B
10
11
12 4A
13 4B
4Y
nA
nB
nY
001aaj110
001aaj108
Fig 1. Functional diagram
Fig 2. Logic diagram (one gate)
6. Pinning information
6.1 Pinning
HEF4071B
1
2
3
4
5
6
7
14
13
12
11
10
9
1A
1B
1Y
2Y
2A
2B
V
DD
4B
4A
4Y
3Y
3B
3A
8
V
SS
001aaj107
Fig 3. Pin configuration
6.2 Pin description
Table 2.
Symbol
1A to 4A
1B to 4B
1Y to 4Y
VSS
Pin description
Pin
Description
input
1, 5, 8, 12
2, 6, 9, 13
3, 4, 10, 11
7
input
output
ground (0 V)
supply voltage
VDD
14
HEF4071B_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 1 December 2009
2 of 11
HEF4071B
NXP Semiconductors
Quad 2-input OR gate
7. Functional description
Table 3.
Function table[1]
Input
nA
L
Output
nB
L
nY
L
L
H
L
H
H
H
H
H
H
[1] H = HIGH voltage level; L = LOW voltage level.
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground).
Symbol Parameter
Conditions
Min
−0.5
-
Max
+18
Unit
V
VDD
IIK
supply voltage
input clamping current
input voltage
VI < −0.5 V or VI > VDD + 0.5 V
VO < −0.5 V or VO > VDD + 0.5 V
±10
mA
V
VI
−0.5
-
VDD + 0.5
±10
IOK
II/O
output clamping current
input/output current
supply current
mA
mA
mA
°C
-
±10
IDD
Tstg
Tamb
Ptot
-
50
storage temperature
ambient temperature
total power dissipation
−65
−40
+150
+125
°C
Tamb = −40 °C to + 125 °C
[1]
[2]
DIP14
SO14
-
-
-
750
500
100
mW
mW
mW
P
power dissipation
per output
[1] For DIP14 packages: above Tamb = 70 °C, Ptot derates linearly with 12 mW/K.
[2] For SO14 packages: above Tamb = 70 °C, Ptot derates linearly with 8 mW/K.
9. Recommended operating conditions
Table 5.
Symbol
VDD
Recommended operating conditions
Parameter
Conditions
Min
Max
15
Unit
supply voltage
3
V
VI
input voltage
0
VDD
+125
3.75
0.5
V
Tamb
ambient temperature
input transition rise and fall rate
in free air
−40
°C
Δt/ΔV
VDD = 5 V
VDD = 10 V
VDD = 15 V
-
-
-
μs/V
μs/V
μs/V
0.08
HEF4071B_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 1 December 2009
3 of 11
HEF4071B
NXP Semiconductors
Quad 2-input OR gate
10. Static characteristics
Table 6.
Static characteristics
VSS = 0 V; VI = VSS or VDD; unless otherwise specified.
Symbol Parameter
Conditions
VDD
Tamb = −40 °C Tamb = +25 °C Tamb = +85 °C Tamb = +125 °C Unit
Min
3.5
7.0
11.0
-
Max
Min
3.5
7.0
11.0
-
Max
Min
3.5
7.0
11.0
-
Max
Min
3.5
7.0
11.0
-
Max
VIH
HIGH-level
input voltage
|IO| < 1 μA
|IO| < 1 μA
|IO| < 1 μA
|IO| < 1 μA
5 V
10 V
15 V
5 V
-
-
-
-
V
-
-
-
-
V
-
-
-
-
V
VIL
LOW-level
input voltage
1.5
1.5
1.5
1.5
V
10 V
15 V
5 V
-
3.0
-
3.0
-
3.0
-
3.0
V
-
4.0
-
4.0
-
4.0
-
4.0
V
VOH
VOL
IOH
HIGH-level
output voltage
4.95
9.95
14.95
-
-
4.95
9.95
14.95
-
-
4.95
9.95
14.95
-
-
4.95
9.95
14.95
-
-
V
10 V
15 V
5 V
-
-
-
-
V
-
-
-
-
V
LOW-level
output voltage
0.05
0.05
0.05
0.05
V
10 V
15 V
5 V
-
0.05
-
0.05
-
0.05
-
0.05
V
-
0.05
-
0.05
-
0.05
-
0.05
V
HIGH-level
output current
VO = 2.5 V
VO = 4.6 V
VO = 9.5 V
VO = 13.5 V
VO = 0.4 V
VO = 0.5 V
VO = 1.5 V
−1.7
−0.64
−1.6
−4.2
0.64
1.6
4.2
-
-
−1.4
−0.5
−1.3
−3.4
0.5
1.3
3.4
-
-
−1.1
−0.36
−0.9
−2.4
0.36
0.9
2.4
-
-
−1.1
−0.36
−0.9
−2.4
0.36
0.9
2.4
-
-
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
mA
5 V
-
-
-
10 V
15 V
5 V
-
-
-
-
-
-
IOL
LOW-level
output current
-
-
-
10 V
15 V
15 V
-
-
-
-
-
-
II
input leakage
current
±0.1
±0.1
±1.0
±1.0 μA
IDD
supply current all valid input
combinations;
5 V
10 V
15 V
-
-
-
-
0.25
0.5
1.0
-
-
-
-
-
0.25
0.5
-
-
-
-
7.5
15.0
30.0
-
-
-
-
-
7.5 μA
15.0 μA
30.0 μA
IO = 0 A
1.0
CI
input
7.5
-
pF
capacitance
HEF4071B_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 1 December 2009
4 of 11
HEF4071B
NXP Semiconductors
Quad 2-input OR gate
11. Dynamic characteristics
Table 7.
T
Dynamic characteristics
amb = 25 °C; waveforms see Figure 4; test circuit see Figure 5; unless otherwise specified. [1]
Symbol Parameter Conditions VDD Extrapolation formula Min
nA or nB to nY 5 V
Typ
55
25
20
45
20
15
60
30
20
Max
115
50
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
tPHL
HIGH to LOW
28 ns + (0.55 ns/pF)CL
15 ns + (0.23 ns/pF)CL
12 ns + (0.16 ns/pF)CL
18 ns + (0.55 ns/pF)CL
9 ns + (0.23 ns/pF)CL
7 ns + (0.16 ns/pF)CL
10 ns + (1.00 ns/pF)CL
9 ns + (0.42 ns/pF)CL
6 ns + (0.28 ns/pF)CL
-
-
-
-
-
-
-
-
-
propagation delay
10 V
15 V
35
tPLH
LOW to HIGH
nA or nB to nY 5 V
90
propagation delay
10 V
15 V
5 V
45
30
[2]
tt
transition time
120
60
10 V
15 V
40
[1] The typical value of the propagation delay and output transition time can be calculated with the extrapolation formula (CL in pF).
[2] tt is the same as tTHL and tTLH
.
Table 8.
Dynamic power dissipation
VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C.
Symbol Parameter
VDD Typical formula
where:
PD
dynamic power dissipation
5 V PD = 1150 × fi + Σ(fo × CL) × VDD2 (μW) fi = input frequency in MHz;
10 V PD = 4800 × fi + Σ(fo × CL) × VDD2 (μW)
fo = output frequency in MHz;
15 V PD = 19700 × fi + Σ(fo × CL) × VDD2 (μW)
CL = output load capacitance in pF;
Σ(fo × CL) = sum of the outputs;
VDD = supply voltage in V.
12. Waveforms
t
r
t
f
V
I
90 %
nA, nB input
V
M
10 %
0 V
t
t
PHL
PLH
V
OH
90 %
nY output
V
M
10 %
V
OL
t
t
TLH
THL
001aai140
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 4. Input to output propagation delay and output transition times
HEF4071B_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 1 December 2009
5 of 11
HEF4071B
NXP Semiconductors
Quad 2-input OR gate
Table 9.
Measurement points
Supply voltage
VDD
Input
VM
Output
VM
5 V to 15 V
0.5VDD
0.5VDD
V
DD
V
I
V
O
G
DUT
C
L
R
T
001aag182
Test data is given in Table 10.
Definitions for test circuit:
DUT = Device Under Test.
CL = load capacitance including jig and probe capacitance.
RT = termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig 5. Test circuit
Table 10. Test data
Supply voltage
VDD
Input
Load
VI
tr, tf
CL
5 V to 15 V
VSS or VDD
≤ 20 ns
50 pF
HEF4071B_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 1 December 2009
6 of 11
HEF4071B
NXP Semiconductors
Quad 2-input OR gate
13. Package outline
DIP14: plastic dual in-line package; 14 leads (300 mil)
SOT27-1
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
M
H
14
8
pin 1 index
E
1
7
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
Z
A
A
A
2
(1)
(1)
1
UNIT
mm
b
b
c
D
E
e
e
L
M
M
H
w
1
1
E
max.
min.
max.
max.
1.73
1.13
0.53
0.38
0.36
0.23
19.50
18.55
6.48
6.20
3.60
3.05
8.25
7.80
10.0
8.3
4.2
0.51
3.2
2.54
0.1
7.62
0.3
0.254
0.01
2.2
0.068
0.044
0.021
0.015
0.014
0.009
0.77
0.73
0.26
0.24
0.14
0.12
0.32
0.31
0.39
0.33
inches
0.17
0.02
0.13
0.087
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-13
SOT27-1
050G04
MO-001
SC-501-14
Fig 6. Package outline SOT27-1 (DIP14)
HEF4071B_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 1 December 2009
7 of 11
HEF4071B
NXP Semiconductors
Quad 2-input OR gate
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
7
e
detail X
w
M
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.75
1.27
0.05
1.05
0.25
0.01
0.25
0.1
0.25
0.01
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.024
0.028
0.012
inches
0.041
0.01 0.004
0.069
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT108-1
076E06
MS-012
Fig 7. Package outline SOT108-1 (SO14)
HEF4071B_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 1 December 2009
8 of 11
HEF4071B
NXP Semiconductors
Quad 2-input OR gate
14. Revision history
Table 11. Revision history
Document ID
Release date
20091201
Data sheet status
Change notice
Supersedes
HEF4071B_6
Product data sheet
-
HEF4071B_5
Modifications:
• Section 9 “Recommended operating conditions” Δt/ΔV values updated.
HEF4071B_5
20090728
20081128
19950101
19950101
Product data sheet
Product data sheet
Product specification
Product specification
-
-
-
-
HEF4071B_4
HEF4071B_CNV_3
HEF4071B_CNV_2
-
HEF4071B_4
HEF4071B_CNV_3
HEF4071B_CNV_2
HEF4071B_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 1 December 2009
9 of 11
HEF4071B
NXP Semiconductors
Quad 2-input OR gate
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
HEF4071B_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 1 December 2009
10 of 11
HEF4071B
NXP Semiconductors
Quad 2-input OR gate
17. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2
7
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
Recommended operating conditions. . . . . . . . 3
Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
Dynamic characteristics . . . . . . . . . . . . . . . . . . 5
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 7
Revision history. . . . . . . . . . . . . . . . . . . . . . . . . 9
8
9
10
11
12
13
14
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 10
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 10
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 10
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 10
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 1 December 2009
Document identifier: HEF4071B_6
相关型号：
HEF4071BT-T
4000/14000/40000 SERIES, QUAD 2-INPUT OR GATE, PDSO14, 3.90 MM, PLASTIC, MS-012, SOT108-1, SOP-14
NXP
HEF4071BTD-T
IC 4000/14000/40000 SERIES, QUAD 2-INPUT OR GATE, PDSO14, PLASTIC, SOT-108-1, SO-14, Gate
NXP
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