HEF4073BD [NXP]
Triple 3-input AND gate; 三路3输入与门型号: | HEF4073BD |
厂家: | NXP |
描述: | Triple 3-input AND gate |
文件: | 总4页 (文件大小:31K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4073B
gates
Triple 3-input AND gate
January 1995
Product specification
File under Integrated Circuits, IC04
Philips Semiconductors
Product specification
HEF4073B
gates
Triple 3-input AND gate
DESCRIPTION
The HEF4073B provides the positive triple 3-input AND
function. The outputs are fully buffered for highest noise
immunity and pattern insensitivity of output impedance.
Fig.2 Pinning diagram.
HEF4073BP(N): 14-lead DIL; plastic
(SOT27-1)
HEF4073BD(F): 14-lead DIL; ceramic (cerdip)
(SOT73)
HEF4073BT(D): 14-lead SO; plastic
(SOT108-1)
Fig.1 Functional diagram.
( ): Package Designator North America
Fig.3 Logic diagram (one gate).
FAMILY DATA, IDD LIMITS category GATES
See Family Specifications
January 1995
2
Philips Semiconductors
Product specification
HEF4073B
gates
Triple 3-input AND gate
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
TYPICAL EXTRAPOLATION
FORMULA
SYMBOL
TYP.
MAX.
Propagation delays
In → On
HIGH to LOW
5
55
25
20
45
20
15
60
30
20
60
30
20
110
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
23 ns
14 ns
12 ns
13 ns
9 ns
+
+
+
+
+
+
+
+
+
+
+
+
(0,55 ns/pF) CL
(0,23 ns/pF) CL
(0,16 ns/pF) CL
(0,55 ns/pF) CL
(0,23 ns/pF) CL
(0,16 ns/pF) CL
(1,0 ns/pF) CL
(0,42 ns/pF) CL
(0,28 ns/pF) CL
(1,0 ns/pF) CL
(0,42 ns/pF) CL
(0,28 ns/pF) CL
10
15
5
tPHL
40
90
LOW to HIGH
10
15
5
tPLH
tTHL
tTLH
40
30
7 ns
Output transition times
HIGH to LOW
120
60
10 ns
9 ns
10
15
5
40
6 ns
120
60
10 ns
9 ns
LOW to HIGH
10
15
40
6 ns
VDD
V
TYPICAL FORMULA FOR P (µW)
2
Dynamic power
dissipation per
package (P)
5
10
15
600 fi + ∑ (foCL) × VDD
where
2
2700 fi + ∑ (foCL) × VDD
fi = input freq. (MHz)
2
8400 fi + ∑ (foCL) × VDD
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (foCL) = sum of outputs
VDD = supply voltage (V)
January 1995
3
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