HEF4077B [NXP]
Quadruple exclusive-NOR gate; 四倍异非门
| 型号： | HEF4077B |
| 厂家： | 
NXP |
| 描述： | Quadruple exclusive-NOR gate |
| 文件： | 总4页 (文件大小：33K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4077B
gates
Quadruple exclusive-NOR gate
January 1995
Product specification
File under Integrated Circuits, IC04
Philips Semiconductors
Product specification
HEF4077B
gates
Quadruple exclusive-NOR gate
DESCRIPTION
The HEF4077B provides the exclusive-NOR function. The
outputs are fully buffered for best performance.
Fig.2 Pinning diagram.
Fig.1 Functional diagram.
HEF4077BP(N): 14-lead DIL; plastic
(SOT27-1)
HEF4077BD(F):
14-lead DIL; ceramic (cerdip)
(SOT73)
HEF4077BT(D):
14-lead SO; plastic
(SOT108-1)
( ): Package Designator North America
TRUTH TABLE
An
Bn
On
L
L
L
H
L
H
L
H
H
L
H
H
Note
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
Fig.3 Logic diagram (one gate).
FAMILY DATA, IDD LIMITS category GATES
See Family Specifications
January 1995
2
Philips Semiconductors
Product specification
HEF4077B
gates
Quadruple exclusive-NOR gate
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
TYPICAL EXTRAPOLATION
FORMULA
SYMBOL TYP. MAX.
V
Propagation delays
An, Bn → On
5
10
15
5
75
35
30
70
30
25
150
70
ns
ns
ns
ns
ns
ns
48 ns + (0,55 ns/pF) CL
24 ns + (0,23 ns/pF) CL
22 ns + (0,16 ns/pF) CL
43 ns + (0,55 ns/pF) CL
19 ns + (0,23 ns/pF) CL
17 ns + (0,16 ns/pF) CL
HIGH to LOW
tPHL
55
145
60
LOW to HIGH
10
15
tPLH
50
Output transition
times
5
10
15
5
60
30
20
60
30
20
120
60
ns
ns
ns
ns
ns
ns
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
HIGH to LOW
tTHL
40
120
60
LOW to HIGH
10
15
tTLH
40
VDD
V
TYPICAL FORMULA FOR P(µW)
2
Dynamic power
dissipation per
package (P)
5
10
15
850 fi + ∑ (foCL) × VDD
where
2
4 500 fi + ∑ (foCL) × VDD
fi = input freq. (MHz)
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (foCL) = sum of outputs
VDD = supply voltage (V)
2
14 700 fi + ∑ (foCL) × VDD
January 1995
3
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