HEF4081BT,118 [NXP]

AND Gate, 4000/14000/40000 Series, 4-Func, 2-Input, CMOS, PDSO14;


型号：	HEF4081BT,118
厂家：	NXP
描述：	AND Gate, 4000/14000/40000 Series, 4-Func, 2-Input, CMOS, PDSO14 栅光电二极管逻辑集成电路
文件：	总11页 (文件大小：120K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HEF4081B

Quad 2-input AND gate

Rev. 8 — 15 December 2015

Product data sheet

1. General description

The HEF4081B is a quad 2-input AND gate. The outputs are fully buffered for highest

noise immunity and pattern insensitivity to output impedance variations.

It operates over a recommended V_DDpower supply range of 3 V to 15 V referenced to V_SS

(usually ground). Unused inputs must be connected to V_DD, V_SS, or another input.

2. Features and benefits

 Fully static operation

 5 V, 10 V, and 15 V parametric ratings

 Standardized symmetrical output characteristics

 Inputs and outputs are protected against electrostatic effects

 Specified from40 C to +85 C and 40 C to +125 C

 Complies with JEDEC standard JESD 13-B

3. Ordering information

Table 1.

Ordering information

All types operate from 40 C to +125 C.

Type number

Package

Name

Description

Version

HEF4081BT

SO14

plastic small outline package; 14 leads; body width 3.9 mm

SOT108-1

4. Functional diagram

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Fig 1. Functional diagram

Fig 2. Logic diagram (one gate)

HEF4081B

NXP Semiconductors

Quad 2-input AND gate

5. Pinning information

5.1 Pinning

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Fig 3. Pin configuration

5.2 Pin description

Table 2.

Symbol

1A to 4A

1B to 4B

1Y to 4Y

V_SS

Pin description

Description

input

1, 5, 8, 12

2, 6, 9, 13

input

3, 4, 10, 11

output

ground (0 V)

V_DD

supply voltage

6. Functional description

Table 3.

Function table^[1]

Input

Output

[1] H = HIGH voltage level; L = LOW voltage level.

HEF4081B

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 8 — 15 December 2015

2 of 11

HEF4081B

NXP Semiconductors

Quad 2-input AND gate

7. Limiting values

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to V_SS= 0 V (ground).

Symbol Parameter

Conditions

Min

0.5

Max

+18

Unit

V_DD

I_IK

supply voltage

input clamping current

input voltage

V_I< 0.5 V or V_I> V_DD+ 0.5 V

V_O< 0.5 V or V_O> V_DD+ 0.5 V

10

V_I

0.5

V_DD+ 0.5

10

I_OK

I_I/O

output clamping current

input/output current

supply current

C

10

I_DD

T_stg

T_amb

P_tot

storage temperature

ambient temperature

total power dissipation

65

40

+150

+125

C

T_amb= 40 C to + 125 C

SO14

[1]

500

100

power dissipation

per output

[1] For SO14 packages: above T_amb= 70 C, P_totderates linearly with 8 mW/K.

8. Recommended operating conditions

Table 5.

Symbol

V_DD

Recommended operating conditions

Parameter

Conditions

Min

Max

Unit

supply voltage

V_I

input voltage

V_DD

+125

3.75

0.5

T_amb

ambient temperature

input transition rise and fall rate

in free air

40

C

t/V

V_DD= 5 V

V_DD= 10 V

V_DD= 15 V

s/V

0.08

HEF4081B

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 8 — 15 December 2015

3 of 11

HEF4081B

NXP Semiconductors

Quad 2-input AND gate

9. Static characteristics

Table 6.

Static characteristics

V_SS= 0 V; V_I= V_SSor V_DD; unless otherwise specified.

Symbol Parameter

Conditions

V_DD

T_amb= 40 C T_amb= +25 C T_amb= +85 C T_amb= +125 C Unit

Min

Max

Min

Max

Min

Max

Min

Max

V_IH

HIGH-level

input voltage

I_O < 1 A

5 V

3.5

10 V

15 V

5 V

7.0

11.0

V_IL

LOW-level

input voltage

1.5

3.0

4.0

1.5

3.0

4.0

1.5

3.0

4.0

1.5

3.0

4.0

10 V

15 V

5 V

V_OH

V_OL

I_OH

HIGH-level

output voltage

4.95

10 V

15 V

5 V

9.95

14.95

LOW-level

output voltage

0.05

1.7

0.64

1.6

4.2

0.05

1.4

0.5

1.3

3.4

0.05

1.1

0.36

0.9

2.4

0.05

10 V

15 V

5 V

HIGH-level

output current

V_O= 2.5 V

V_O= 4.6 V

V_O= 9.5 V

V_O= 13.5 V

V_O= 0.4 V

V_O= 0.5 V

V_O= 1.5 V

1.1 mA

0.36 mA

0.9 mA

2.4 mA

5 V

10 V

15 V

5 V

I_OL

LOW-level

output current

0.64

1.6

4.2

0.5

1.3

3.4

0.36

0.9

2.4

0.36

0.9

2.4

10 V

15 V

I_I

input leakage

current

0.1

1.0

1.0 A

I_DD

supply current all valid input 5 V

combinations;

0.25

0.5

1.0

0.25

0.5

7.5

15.0

30.0

7.5 A

10 V

15 V

15.0 A

30.0 A

I_O= 0 A

1.0

C_I

input

7.5

capacitance

HEF4081B

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Product data sheet

Rev. 8 — 15 December 2015

4 of 11

HEF4081B

NXP Semiconductors

Quad 2-input AND gate

10. Dynamic characteristics

Table 7.

Dynamic characteristics

_amb= 25 C; for waveforms see Figure 4; for test circuit see Figure 5; unless otherwise specified. ^[1]

Symbol Parameter

Conditions

V_DD

Extrapolation formula

28 ns + (0.55 ns/pF)C_L

14 ns + (0.23 ns/pF)C_L

12 ns + (0.16 ns/pF)C_L

18 ns + (0.55 ns/pF)C_L

9 ns + (0.23 ns/pF)C_L

7 ns + (0.16 ns/pF)C_L

10 ns + (1.0 ns/pF)C_L

9 ns + (0.42 ns/pF)C_L

6 ns + (0.28 ns/pF)C_L

10 ns + (1.00 ns/pF)C_L

9 ns + (0.42 ns/pF)C_L

6 ns + (0.28 ns/pF)C_L

Min

Typ

Max Unit

t_PHL

HIGH to LOW

nA or nB to nY 5 V

110

propagation delay

10 V

15 V

t_PLH

t_THL

t_TLH

LOW to HIGH

propagation delay

nA or nB to nY 5 V

10 V

15 V

5 V

HIGH to LOW output

transition time

120

10 V

15 V

5 V

LOW to HIGH output

transition time

120

10 V

15 V

[1] The typical value of the propagation delay and output transition time can be calculated with the extrapolation formula (C_Lin pF).

Table 8.

Dynamic power dissipation

V_SS= 0 V; t_r= t_f 20 ns; T_amb= 25 C.

Symbol Parameter

V_DDTypical formula

where:

P_D

dynamic power dissipation 5 V P_D= 450  f_i+ (f_o C_L)  V_DD²(W)

10 V P_D= 2900  f_i+ (f_o C_L)  V_DD²(W)

f_i= input frequency in MHz;

f_o= output frequency in MHz;

C_L= output load capacitance in pF;

(f_o C_L) = sum of the outputs;

15 V P_D= 11700  f_i+ (f_o C_L)  V_DD²(W)

V_DD= supply voltage in V.

HEF4081B

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Product data sheet

Rev. 8 — 15 December 2015

5 of 11

HEF4081B

NXP Semiconductors

Quad 2-input AND gate

11. Waveforms

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Measurement points are given in Table 9.

Logic levels: V_OLand V_OHare typical output voltage levels that occur with the output load.

Fig 4. Input to output propagation delay and output transition times

Table 9.

Measurement points

Supply voltage

V_DD

Input

V_M

Output

V_M

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Test data is given in Table 10.

Definitions for test circuit:

DUT = Device Under Test.

C_L= load capacitance including jig and probe capacitance.

R_T= termination resistance should be equal to the output impedance Z_oof the pulse generator.

Fig 5. Test circuit for measuring switching times

Table 10. Test data

Supply voltage

V_DD

Input

Load

V_I

t_r, t_f

C_L

5 V to 15 V

V_SSor V_DD

 20 ns

50 pF

HEF4081B

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Product data sheet

Rev. 8 — 15 December 2015

6 of 11

HEF4081B

NXP Semiconductors

Quad 2-input AND gate

12. Package outline

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Fig 6. Package outline SOT108-1 (SO14)

HEF4081B

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 8 — 15 December 2015

7 of 11

HEF4081B

NXP Semiconductors

Quad 2-input AND gate

13. Abbreviations

Table 11. Abbreviations

Acronym

Description

Device Under Test

DUT

14. Revision history

Table 12. Revision history

Document ID

Release date

20151215

Data sheet status

Change notice

Supersedes

HEF4081B v.8

Modifications:

Product data sheet

HEF4081B v.7

• Type number HEF4081BP (SOT27-1) removed.

20111116 Product data sheet

• Table 6: I_OHminimum values changed to maximum

HEF4081B v.7

Modifications:

HEF4081B v.6

HEF4081B v.5

HEF4081B v.4

HEF4081B_CNV v.3

HEF4081B_CNV v.2

20091202

20090629

20080526

19950101

Product data sheet

Product specification

HEF4081B v.5

HEF4081B v.4

HEF4081B_CNV v.3

HEF4081B_CNV v.2

HEF4081B

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Product data sheet

Rev. 8 — 15 December 2015

8 of 11

HEF4081B

NXP Semiconductors

Quad 2-input AND gate

15. Legal information

15.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

Suitability for use — NXP Semiconductors products are not designed,

15.2 Definitions

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

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Draft — The document is a draft version only. The content is still under

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Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

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punitive, special or consequential damages (including - without limitation - lost

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HEF4081B

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 8 — 15 December 2015

9 of 11

HEF4081B

NXP Semiconductors

Quad 2-input AND gate

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NXP Semiconductors’ specifications such use shall be solely at customer’s

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standard warranty and NXP Semiconductors’ product specifications.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

15.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

16. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

HEF4081B

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 8 — 15 December 2015

10 of 11

HEF4081B

NXP Semiconductors

Quad 2-input AND gate

17. Contents

General description. . . . . . . . . . . . . . . . . . . . . . 1

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 1

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 1

5.1

5.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 2

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2

Functional description . . . . . . . . . . . . . . . . . . . 2

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3

Recommended operating conditions. . . . . . . . 3

Static characteristics. . . . . . . . . . . . . . . . . . . . . 4

Dynamic characteristics . . . . . . . . . . . . . . . . . . 5

Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 7

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Revision history. . . . . . . . . . . . . . . . . . . . . . . . . 8

Legal information. . . . . . . . . . . . . . . . . . . . . . . . 9

Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 9

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 10

15.1

15.2

15.3

15.4

Contact information. . . . . . . . . . . . . . . . . . . . . 10

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 15 December 2015

Document identifier: HEF4081B

HEF4081BT,118 [NXP]

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