HEF4502BDF [NXP]
IC 4000/14000/40000 SERIES, 6-BIT DRIVER, INVERTED OUTPUT, CDIP16, SOT-74, CERDIP-16, Bus Driver/Transceiver;
| 型号： | HEF4502BDF |
| 厂家： | 
NXP |
| 描述： | IC 4000/14000/40000 SERIES, 6-BIT DRIVER, INVERTED OUTPUT, CDIP16, SOT-74, CERDIP-16, Bus Driver/Transceiver 驱动 CD 输出元件 逻辑集成电路 |
| 文件： | 总4页 (文件大小：40K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4502B
buffers
Strobed hex inverter/buffer
January 1995
Product specification
File under Integrated Circuits, IC04
Philips Semiconductors
Product specification
HEF4502B
buffers
Strobed hex inverter/buffer
DESCRIPTION
The HEF4502B consists of six inverter/buffers with 3-state
outputs. When the output enable input (EO) is HIGH all six
outputs (O1 to O6) are in the high impedance OFF-state.
When the enable input (E) is HIGH all six outputs are
switched to LOW. The outputs have a 2-TTL load drive
capability.
Fig.2 Pinning diagram.
HEF4502BP(N):
HEF4502BD(F):
HEF4502BT(D):
16-lead DIL; plastic (SOT38-1)
16-lead DIL; ceramic (cerdip) (SOT74)
16-lead SO; plastic (SOT109-1)
( ): Package Designator North America
PINNING
D1 to D6
E
data inputs
enable input
EO
output enable input
3-state outputs
O1 to O6
Fig.1 Functional diagram.
TRUTH TABLE
INPUTS
E
OUTPUT
On
Dn
EO
L
H
X
X
L
L
L
L
H
L
L
Z
Fig.3 Logic diagram.
H
X
L
H
Notes
FAMILY DATA, IDD LIMITS category BUFFERS
1. H = HIGH state (the more pos. voltage)
L = LOW state (the less pos. voltage)
X = state is immaterial
See Family Specifications
Z = high impedance off state
January 1995
2
Philips Semiconductors
Product specification
HEF4502B
buffers
Strobed hex inverter/buffer
DC CHARACTERISTICS
VSS = 0 V
Tamb (°C)
+ 25
VDD
V
VOH
V
VOL
V
SYMBOL
−40
+ 85
MIN. MAX.
MIN.
MAX.
MIN. MAX.
Output current
HIGH
5
10
15
4,6
9,5
1,2
3,8
1,0
3,2
0,8
2,5
8,0
mA
mA
mA
−IOH
13,5
12,0
10,0
Output current
HIGH
5
4,75
10
2,5
−IOH
3,8
3,5
3,2
2,9
2,5
2,3
mA
mA
mA
mA
Output current
LOW
0,4
0,5
1,5
IOL
12,0
24,0
10,0
20,0
8,0
15
16,0
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; input transition times ≤ 20 ns
VDD
V
TYPICAL FORMULA FOR P (µW)
2
Dynamic power
dissipation per
package (P)
5
10
15
5 000 fi + ∑ (foCL) × VDD
where
2
25 000 fi + ∑ (foCL) × VDD
fi = input freq. (MHz)
fo = output freq. (MHz)
2
85 000 fi + ∑ (foCL) × VDD
CL = load capacitance (pF)
∑ (foCL) = sum of outputs
VDD = supply voltage (V)
January 1995
3
Philips Semiconductors
Product specification
HEF4502B
buffers
Strobed hex inverter/buffer
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
TYPICAL EXTRAPOLATION
FORMULA
SYMBOL
TYP.
MAX.
Propagation delays
Dn, E → On
5
10
15
5
85
40
35
80
35
30
25
12
8
170 ns
77 ns + (0,17 ns/pF) CL
37 ns + (0,06 ns/pF) CL
33 ns + (0,04 ns/pF) CL
66 ns + (0,28 ns/pF) CL
28 ns + (0,13 ns/pF) CL
25 ns + (0,10 ns/pF) CL
10 ns + (0,30 ns/pF) CL
7 ns + (0,11 ns/pF) CL
5 ns + (0,07 ns/pF) CL
5 ns + (0,50 ns/pF) CL
3 ns + (0,24 ns/pF) CL
3 ns + (0,18 ns/pF) CL
HIGH to LOW
tPHL
80 ns
70 ns
160 ns
70 ns
60 ns
50 ns
24 ns
15 ns
60 ns
30 ns
24 ns
LOW to HIGH
10
15
5
tPLH
tTHL
tTLH
Output transition times
HIGH to LOW
10
15
5
30
15
12
LOW to HIGH
10
15
3-state propagation delays
Output disable times
EO → On
5
10
15
5
60
55
55
50
35
30
160 ns
140 ns
140 ns
100 ns
70 ns
HIGH
tPHZ
LOW
10
15
tPLZ
60 ns
Output enable times
EO → On
5
10
15
5
60
35
30
55
25
20
120 ns
70 ns
60 ns
110 ns
50 ns
40 ns
HIGH
tPZH
LOW
10
15
tPZL
January 1995
4
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