HEF4508BF [NXP]
Dual 4-bit latch; 双4位锁存器
| 型号： | HEF4508BF |
| 厂家： | 
NXP |
| 描述： | Dual 4-bit latch |
| 文件： | 总9页 (文件大小：111K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4508B
MSI
Dual 4-bit latch
January 1995
Product specification
File under Integrated Circuits, IC04
Philips Semiconductors
Product specification
HEF4508B
MSI
Dual 4-bit latch
data into the latch. A HIGH on the reset line forces the
outputs to a LOW level regardless of the state of the ST
input. The 3-state outputs are controlled by the
output-enable input. A HIGH on EO causes the outputs to
assume a high impedance OFF-state regardless of other
input conditions. This allows the outputs to interface
directly with bus orientated systems. When EO is LOW the
contents of the latches are available at the outputs.
DESCRIPTION
The HEF4508B is a dual 4-bit latch, which consists of two
identical independent 4-bit latches with separate strobe
(ST), master reset (MR), output-enable input (EO) and
3-state outputs (O).
With the ST input in the HIGH state, the data on the D
inputs appear at the corresponding outputs provided EO is
LOW. Changing the ST input to the LOW state locks the
Fig.1 Functional diagram.
FAMILY DATA, IDD LIMITS category MSI
See Family Specifications
January 1995
2
Philips Semiconductors
Product specification
HEF4508B
MSI
Dual 4-bit latch
Fig.2 Pinning diagram.
HEF4508BP(N):
HEF4508BD(F):
HEF4508BT(D):
24-lead DIL; plastic
(SOT101-1)
24-lead DIL; ceramic (cerdip)
(SOT94)
24-lead SO; plastic
(SOT137-1)
( ): Package Designator North America
PINNING
D0A to D3A, D0B to D3B
data inputs
STA , STB
MRA, MRB
EOA, EOB
strobe inputs
master reset inputs
output enable inputs
3-state outputs
O0A to O3A, O0B to O3B
FUNCTION TABLE
INPUTS
EO
OUTPUT
MR
ST
Dn
On
L
L
H
H
L
L
L
L
L
H
H
L
H
L
L
X
X
X
latched
H
X
X
X
L
Z
Notes
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
X = state is immaterial
Z = high impedance OFF state
January 1995
3
Philips Semiconductors
Product specification
HEF4508B
MSI
Dual 4-bit latch
Fig.3 Logic diagram (one 4-bit latch).
4
January 1995
Philips Semiconductors
Product specification
HEF4508B
MSI
Dual 4-bit latch
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns; see also waveforms Fig.4.
VDD
V
TYPICAL EXTRAPOLATION
FORMULA
SYMBOL
MIN. TYP. MAX.
Propagation delays
ST → On
HIGH to LOW
5
10
15
5
115
50
35
115
50
35
95
40
30
95
40
30
100
40
30
60
30
20
60
30
20
230
100
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
88 ns + (0,55 ns/pF) CL
39 ns + (0,23 ns/pF) CL
27 ns + (0,16 ns/pF) CL
88 ns + (0,55 ns/pF) CL
39 ns + (0,23 ns/pF) CL
27 ns + (0,16 ns/pF) CL
68 ns + (0,55 ns/pF) CL
29 ns + (0,23 ns/pF) CL
22 ns + (0,16 ns/pF) CL
68 ns + (0,55 ns/pF) CL
29 ns + (0,23 ns/pF) CL
22 ns + (0,16 ns/pF) CL
73 ns + (0,55 ns/pF) CL
29 ns + (0,23 ns/pF) CL
22 ns + (0,16 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
tPHL
230
100
70
LOW to HIGH
10
15
5
tPLH
tPHL
tPLH
tPHL
tTHL
tTLH
Dn → On
190
80
HIGH to LOW
10
15
5
60
190
80
LOW to HIGH
10
15
5
60
MR → On
200
80
HIGH to LOW
10
15
5
60
Output transition times
HIGH to LOW
120
60
10
15
5
40
120
60
LOW to HIGH
10
15
40
3-state propagation
delays
Output enable times
EO → On
5
10
15
5
45
20
18
45
20
18
90
40
36
90
40
36
ns
ns
ns
ns
ns
ns
HIGH
tPZH
LOW
10
15
tPZL
Output disable times
EO → On
5
10
15
5
35
20
18
45
20
18
70
40
36
90
40
36
ns
ns
ns
ns
ns
ns
HIGH
tPHZ
LOW
10
15
tPLZ
January 1995
5
Philips Semiconductors
Product specification
HEF4508B
MSI
Dual 4-bit latch
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
SYMBOL MIN. TYP. MAX.
V
Minimum ST
5
10
15
5
50
30
20
40
24
20
20
20
15
35
25
20
20
20
15
25
15
10
20
12
10
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pulse width; HIGH
tWSTH
tWMRH
tRMR
tsu
Minimum MR pulse
width; HIGH
10
15
5
Recovery time
for MR
10
15
5
0
see also waveforms Fig.4
0
Set-up times
10
5
Dn → ST
10
15
5
0
Hold times
0
Dn → ST
10
15
thold
0
0
VDD
V
TYPICAL FORMULA FOR P (µW)
2
Dynamic power
dissipation per
package (P)
5
10
15
2 000 fi + ∑ (foCL) × VDD
where
2
9 000 fi + ∑ (foCL) × VDD
fi = input freq. (MHz)
2
25 000 fi + ∑ (foCL) × VDD
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (foCL) = sum of outputs
VDD = supply voltage (V)
January 1995
6
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Fig.4 Waveforms showing minimum ST and MR pulse widths, set-up and hold times for Dn to ST, recovery time for MR and propagation
delays from ST to On, to Dn to On and MR to On.
Philips Semiconductors
Product specification
HEF4508B
MSI
Dual 4-bit latch
APPLICATION INFORMATION
Some examples of application for the HEF4508B are:
• Buffer storage
• Holding registers
• Data storage and multiplexing
Fig.5 Example of a bus register using HEF4508B and HEF4015B.
January 1995
8
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Fig.6 Example of a dual multiplexed bus register with function select using two HEF4508B and one HEF4019B.
FUNCTION SELECT
SA
L
SB
FUNCTION
L
L
inhibit (all L)
select A bus
select B bus
A1 + B1
H
L
H
H
H
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