HEF4510BP [NXP]
BCD up/down counter; BCD加/减计数器
| 型号： | HEF4510BP |
| 厂家： | 
NXP |
| 描述： | BCD up/down counter |
| 文件： | 总11页 (文件大小：137K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4510B
MSI
BCD up/down counter
January 1995
Product specification
File under Integrated Circuits, IC04
Philips Semiconductors
Product specification
HEF4510B
MSI
BCD up/down counter
DESCRIPTION
The HEF4510B is an edge-triggered synchronous
up/down BCD counter with a clock input (CP), an up/down
count control input (UP/DN), an active LOW count enable
input (CE), an asynchronous active HIGH parallel load
input (PL), four parallel inputs (P0 to P3), four parallel
outputs (O0 to O3), an active LOW terminal count output
(TC), and an overriding asynchronous master reset input
(MR).
Information on P0 to P3 is loaded into the counter while PL
is HIGH, independent of all other input conditions except
the MR input, which must be LOW. With PL LOW, the
counter changes on the LOW to HIGH transition of CP if
CE is LOW. UP/DN determines the direction of the count,
HIGH for counting up, LOW for counting down. When
counting up, TC is LOW when O0 and O3 are HIGH and
CE is LOW. When counting down, TC is LOW when O0 to
O3 and CE are LOW. A HIGH on MR resets the counter
(O0 to O3 = LOW) independent of all other input
conditions.
Fig.1 Functional diagram.
PINNING
HEF4510BP(N):
HEF4510BD(F):
HEF4510BT(D):
16-lead DIL; plastic
(SOT38-1)
PL
parallel load input (active HIGH)
parallel inputs
P0 to P3
CE
16-lead DIL; ceramic (cerdip)
(SOT74)
count enable input (active LOW)
CP
clock pulse input (LOW to HIGH,
edge triggered)
16-lead SO; plastic
(SOT109-1)
UP/DN
MR
up/down count control input
master reset input
( ): Package Designator North America
TC
terminal count output (active LOW)
parallel outputs
O0 to O3
FAMILY DATA, IDD LIMITS category MSI
See Family Specifications
Fig.2 Pinning diagram.
January 1995
2
Philips Semiconductors
Product specification
HEF4510B
MSI
BCD up/down counter
Fig.3 Logic diagram (continued in Fig.4).
3
January 1995
Philips Semiconductors
Product specification
HEF4510B
MSI
BCD up/down counter
Fig.4 Logic diagram (continued from Fig.3).
January 1995
4
Philips Semiconductors
Product specification
HEF4510B
MSI
BCD up/down counter
FUNCTION TABLE
MR
PL
UP/DN
CE
CP
MODE
L
L
L
H
L
L
X
X
L
X
H
L
X
X
parallel load
no change
count down
L
L
H
X
L
count up
reset
H
X
X
X
Notes
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
X = state is immaterial
= positive-going transition
Fig.5 State diagram.
Logic equation for terminal count:
TC = CE { (UP/DN) O0 O3 + (UP ⁄ DN ) O0 O1 O2 O3}
A.C. CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; input transition times ≤ 20 ns
VDD
V
TYPICAL FORMULA FOR P (µW)
2
2
Dynamic power
5
1000 fi + ∑ (foCL) × VDD
where
dissipation per
package (P)
10
15
4500 fi + ∑ (foCL) × VDD
fi = input freq. (MHz)
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (foCL) = sum of outputs
2
11 200 fi + ∑ (foCL) × VDD
V
DD = supply voltage (V)
January 1995
5
Philips Semiconductors
Product specification
HEF4510B
MSI
BCD up/down counter
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
TYPICAL EXTRAPOLATION
FORMULA
SYMBOL MIN. TYP. MAX.
V
Propagation delays
CP → On
5
10
15
5
145
60
290 ns
120 ns
90 ns
118 ns + (0,55 ns/pF) CL
49 ns + (0,23 ns/pF) CL
37 ns + (0,16 ns/pF) CL
128 ns + (0,55 ns/pF) CL
54 ns + (0,23 ns/pF) CL
37 ns + (0,16 ns/pF) CL
233 ns + (0,55 ns/pF) CL
94 ns + (0,23 ns/pF) CL
67 ns + (0,16 ns/pF) CL
153 ns + (0,55 ns/pF) CL
64 ns + (0,23 ns/pF) CL
47 ns + (0,16 ns/pF) CL
98 ns + (0,55 ns/pF) CL
44 ns + (0,23 ns/pF) CL
32 ns + (0,16 ns/pF) CL
143 ns + (0,55 ns/pF) CL
59 ns + (0,23 ns/pF) CL
42 ns + (0,16 ns/pF) CL
223 ns + (0,55 ns/pF) CL
99 ns + (0,23 ns/pF) CL
72 ns + (0,16 ns/pF) CL
223 ns + (0,55 ns/pF) CL
99 ns + (0,23 ns/pF) CL
72 ns + (0,16 ns/pF) CL
138 ns + (0,55 ns/pF) CL
54 ns + (0,23 ns/pF) CL
42 ns + (0,16 ns/pF) CL
118 ns + (0,55 ns/pF) CL
49 ns + (0,23 ns/pF) CL
37 ns + (0,16 ns/pF) CL
178 ns + (0,55 ns/pF) CL
54 ns + (0,23 ns/pF) CL
37 ns + (0,16 ns/pF) CL
198 ns + (0,55 ns/pF) CL
64 ns + (0,23 ns/pF) CL
42 ns + (0,16 ns/pF) CL
HIGH to LOW
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
45
155
65
310 ns
130 ns
90 ns
LOW to HIGH
10
15
5
45
CP → TC
260
105
75
525 ns
210 ns
150 ns
360 ns
150 ns
115 ns
255 ns
110 ns
85 ns
HIGH to LOW
10
15
5
180
75
LOW to HIGH
10
15
5
55
PL → On
125
55
HIGH to LOW
10
15
5
40
170
70
340 ns
140 ns
105 ns
500 ns
220 ns
160 ns
500 ns
220 ns
160 ns
330 ns
135 ns
100 ns
290 ns
125 ns
95 ns
LOW to HIGH
10
15
5
50
PL → TC
250
110
80
HIGH to LOW
10
15
5
250
110
80
LOW to HIGH
10
15
5
CE → TC
165
65
HIGH to LOW
10
15
5
50
145
60
LOW to HIGH
10
15
5
45
MR → On, TC
205
65
405 ns
130 ns
85 ns
HIGH to LOW
10
15
5
45
MR → TC
225
75
450 ns
150 ns
100 ns
LOW to HIGH
10
15
50
January 1995
6
Philips Semiconductors
Product specification
HEF4510B
MSI
BCD up/down counter
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
TYPICAL EXTRAPOLATION
FORMULA
SYMBOL MIN. TYP. MAX.
V
Output transition times
5
10
15
5
60
30
20
60
30
20
120 ns
60 ns
40 ns
120 ns
60 ns
40 ns
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
HIGH to LOW
tTHL
LOW to HIGH
10
15
tTLH
January 1995
7
Philips Semiconductors
Product specification
HEF4510B
MSI
BCD up/down counter
VDD
V
TYPICAL EXTRAPOLATION
FORMULA
SYMBOL MIN. TYP. MAX.
Minimum clock
5
10
15
5
95
35
25
105
45
35
120
50
40
130
45
30
150
50
30
100
50
40
250
100
75
120
40
25
10
5
45
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
pulse width; LOW
tWCPL
tWPLH
tWMRH
tRMR
tRPL
tsu
15
Minimum PL
55
pulse width; HIGH
10
15
5
25
15
Minimum MR
60
pulse width; HIGH
10
15
5
25
20
Recovery time
for MR
65
10
15
5
20
15
Recovery time
for PL
75
10
15
5
25
15
Set-up times
50
see also waveforms
Figs 6 and 7
Pn → PL
10
15
5
25
20
125
50
UP/DN → CP
CE → PL
10
15
5
tsu
35
60
10
15
5
tsu
20
10
Hold times
−40
−20
−20
−90
−35
−25
−40
−15
−10
10
Pn → PL
10
15
5
thold
thold
thold
fmax
0
35
15
15
20
5
UP/DN → CP
CE → CP
10
15
5
10
15
5
5
Maximum clock
pulse frequency
5
10
15
12
17
24
34
January 1995
8
Philips Semiconductors
Product specification
HEF4510B
MSI
BCD up/down counter
Fig.6 Waveforms showing minimum pulse width for CP, set-up and hold times for CE to CP and UP/DN to CP.
Fig.7 Waveforms showing minimum pulse width for PL and MR, recovery time for PL and MR and set-up and
hold times for Pn to PL.
January 1995
9
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Fig.8 Timing diagram.
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