HEF4512B [NXP]

8-input multiplexer with 3-state output; 8输入多路复用器与3态输出
HEF4512B
型号: HEF4512B
厂家: NXP    NXP
描述:

8-input multiplexer with 3-state output
8输入多路复用器与3态输出

复用器
文件: 总8页 (文件大小:72K)
中文:  中文翻译
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INTEGRATED CIRCUITS  
DATA SHEET  
For a complete data sheet, please also download:  
The IC04 LOCMOS HE4000B Logic  
Family Specifications HEF, HEC  
The IC04 LOCMOS HE4000B Logic  
Package Outlines/Information HEF, HEC  
HEF4512B  
MSI  
8-input multiplexer with 3-state  
output  
January 1995  
Product specification  
File under Integrated Circuits, IC04  
Philips Semiconductors  
Product specification  
HEF4512B  
MSI  
8-input multiplexer with 3-state output  
to interface directly with bus oriented systems (3-state).  
When the active LOW enable (E) is HIGH, it forces the  
output LOW provided EO is LOW. By proper manipulation  
of the inputs, the device can provide any logic functions of  
four variables. It cannot be used to multiplex analogue  
signals.  
DESCRIPTION  
The HEF4512B is an 8-input multiplexer with 8 binary  
inputs (I0 to I7), an enable input (E) and an output enable  
input (EO). One of eight binary inputs is selected by select  
inputs S0, S1 and S2, and is routed to the output O. A HIGH  
on EO causes O to assume a high impedance OFF-state,  
regardless of other input conditions. This allows the output  
Fig.2 Pinning diagram.  
HEF4512BP(N):  
HEF4512BD(F):  
HEF4512BT(D):  
16-lead DIL; plastic  
(SOT38-1)  
16-lead DIL; ceramic (cerdip)  
(SOT74)  
16-lead SO; plastic  
(SOT109-1)  
Fig.1 Functional diagram.  
( ): Package Designator North America  
PINNING  
S0, S1, S2  
select inputs  
EO  
E
output enable (active LOW)  
enable (active LOW)  
multiplexer inputs  
multiplexer output  
I0 to I7  
O
FAMILY DATA, IDD LIMITS category MSI  
See Family Specifications  
January 1995  
2
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Fig.3 Logic diagram.  
Philips Semiconductors  
Product specification  
HEF4512B  
MSI  
8-input multiplexer with 3-state output  
TRUTH TABLE  
INPUTS  
OUTPUT  
EO  
E
S2  
S1  
S0  
I0  
I1  
I2  
I3  
I4  
I5  
I6  
I7  
O
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
L
X
L
X
L
X
L
X
X
X
L
X
X
X
X
X
L
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
L
L
L
H
H
L
L
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
H
L
L
H
H
H
H
L
L
L
H
X
X
X
X
X
X
X
X
X
X
X
H
L
L
H
H
L
L
H
X
X
X
X
X
X
X
X
X
H
L
H
H
H
H
H
H
H
H
X
L
L
H
X
X
X
X
X
X
X
H
L
L
H
H
L
L
H
X
X
X
X
X
H
L
H
H
H
H
X
L
H
X
X
X
H
L
H
H
X
H
X
H
Z
Notes  
1. H = HIGH state (the more positive voltage)  
L = LOW state (the less positive voltage)  
X = state is immaterial  
Z = high impedance OFF-state  
AC CHARACTERISTICS  
VSS = 0 V; Tamb = 25 °C; input transition times 20 ns  
VDD  
V
TYPICAL FORMULA FOR P (µW)  
2
Dynamic power  
dissipation per  
package (P)  
5
500 fi + ∑ (foCL) × VDD  
where  
2
10  
15  
2100 fi + ∑ (foCL) × VDD  
fi = input freq. (MHz)  
2
5800 fi + ∑ (foCL) × VDD  
fo = output freq. (MHz)  
CL = load capacitance (pF)  
(foCL) = sum of outputs  
V
DD = supply voltage (V)  
January 1995  
4
Philips Semiconductors  
Product specification  
HEF4512B  
MSI  
8-input multiplexer with 3-state output  
AC CHARACTERISTICS  
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times 20 ns  
VDD  
TYPICAL EXTRAPOLATION  
FORMULA  
SYMBOL TYP. MAX.  
V
Propagation delays  
In O  
5
10  
15  
5
100  
40  
30  
100  
40  
30  
140  
55  
40  
150  
60  
40  
60  
25  
20  
55  
25  
20  
60  
30  
20  
60  
30  
20  
200  
80  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
73 ns  
29 ns  
22 ns  
73 ns  
29 ns  
22 ns  
113 ns  
44 ns  
32 ns  
123 ns  
49 ns  
32 ns  
33 ns  
14 ns  
12 ns  
28 ns  
14 ns  
12 ns  
10 ns  
9 ns  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
(0,55 ns/pF) CL  
(0,23 ns/pF) CL  
(0,16 ns/pF) CL  
(0,55 ns/pF) CL  
(0,23 ns/pF) CL  
(0,16 ns/pF) CL  
(0,55 ns/pF) CL  
(0,23 ns/pF) CL  
(0,16 ns/pF) CL  
(0,55 ns/pF) CL  
(0,23 ns/pF) CL  
(0,16 ns/pF) CL  
(0,55 ns/pF) CL  
(0,23 ns/pF) CL  
(0,16 ns/pF) CL  
(0,55 ns/pF) CL  
(0,23 ns/pF) CL  
(0,16 ns/pF) CL  
(1,0 ns/pF) CL  
(0,42 ns/pF) CL  
(0,28 ns/pF) CL  
(1,0 ns/pf) CL  
HIGH to LOW  
tPHL  
tPLH  
tPHL  
tPLH  
tPHL  
tPLH  
tTHL  
tTLH  
60  
200  
80  
LOW to HIGH  
10  
15  
5
60  
Sn O  
280  
110  
80  
HIGH to LOW  
10  
15  
5
300  
120  
80  
LOW to HIGH  
10  
15  
5
E O  
120  
50  
HIGH to LOW  
10  
15  
5
40  
110  
50  
LOW to HIGH  
10  
15  
5
40  
Output transition times  
HIGH to LOW  
120  
60  
10  
15  
5
40  
6 ns  
120  
60  
10 ns  
9 ns  
LOW to HIGH  
10  
15  
(0,42 ns/pF) CL  
(0,28 ns/pF) CL  
40  
6 ns  
3-state propagation delays  
Output disable times  
EO O  
5
10  
15  
5
35  
20  
15  
35  
15  
10  
70  
40  
30  
70  
30  
20  
ns  
ns  
ns  
ns  
ns  
ns  
HIGH  
tPHZ  
LOW  
10  
15  
tPLZ  
Output enable times  
EO O  
5
10  
15  
35  
15  
10  
70  
30  
20  
ns  
ns  
ns  
HIGH  
tPZH  
January 1995  
5
Philips Semiconductors  
Product specification  
HEF4512B  
MSI  
8-input multiplexer with 3-state output  
VDD  
V
TYPICAL EXTRAPOLATION  
FORMULA  
SYMBOL TYP. MAX.  
5
35  
20  
15  
70  
40  
30  
ns  
ns  
ns  
LOW  
10  
15  
tPZL  
APPLICATION INFORMATION  
Some examples of applications for the HEF4512B are:  
Signal gating  
Digital multiplexing  
Number sequence generation  
January 1995  
6
Philips Semiconductors  
Product specification  
HEF4512B  
MSI  
8-input multiplexer with 3-state output  
TRUTH TABLE for Fig. 4  
INPUT CONN.  
TO OUTPUT  
A4  
A3  
A2  
A1  
A0  
L
L
L
L
L
L
L
L
L
H
L
0
1
2
L
L
L
H
H
L
via  
IC  
0
L
L
L
H
L
3
4
L
L
H
H
H
H
L
L
L
L
H
L
5
L
L
H
H
L
6
L
L
H
L
7
L
H
H
H
H
H
H
H
H
L
8
L
L
L
H
L
9
L
L
H
H
L
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
via  
IC  
1
L
L
H
L
L
H
H
H
H
L
L
L
H
L
L
H
H
L
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
H
L
L
L
H
H
L
via  
IC  
2
L
L
H
L
L
H
H
H
H
L
L
L
H
L
L
H
H
L
L
H
L
H
H
H
H
H
H
H
H
L
L
H
L
L
H
H
L
via  
IC  
3
L
H
L
H
H
H
H
Fig.4 32-input multiplexer using 4 × HEF4512B  
and 1 × HEF4011B. The input is selected  
by 5-bit address (A4 to A0) and presented at  
the output.  
L
H
L
H
H
H
January 1995  
7
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