HEF4516BT-T [NXP]
IC 4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDSO16, 3.90 MM, PLASTIC, MO-012, SOT-109-1, SOP-16, Counter;
| 型号： | HEF4516BT-T |
| 厂家： | 
NXP |
| 描述： | IC 4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDSO16, 3.90 MM, PLASTIC, MO-012, SOT-109-1, SOP-16, Counter 计数器 |
| 文件： | 总16页 (文件大小：150K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HEF4516B
Binary up/down counter
Rev. 06 — 11 December 2009
Product data sheet
1. General description
The HEF4516B is an edge-triggered synchronous 4-bit binary up/down counter with a
clock input (CP), an up/down count control input (UP/DN), an active LOW count enable
input (CE), an asynchronous active HIGH parallel load input (PL), four parallel inputs
(D0 to D3), four parallel outputs (Q0 to Q3), an active LOW terminal count output (TC),
and an overriding asynchronous master reset input (MR).
Information on D0 to D3 is loaded into the counter while PL is HIGH, independent of all
other input conditions except for MR which must be LOW. When PL and CE are LOW, the
counter changes on the LOW-to-HIGH transition of CP. Input UP/DN determines the
direction of the count, counting up when HIGH and counting down when LOW. When
counting up, TC is LOW when Q0 and Q3 are HIGH and CE is LOW. When counting
down, TC is LOW when Q0 to Q3 and CE are LOW. A HIGH on MR resets the counter
(Q0 to Q3 = LOW) independent of all other input conditions.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input. It is
also suitable for use over the full industrial (−40 °C to +85 °C) temperature range.
2. Features
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Operates across the full industrial temperature range −40 °C to +85 °C
Complies with JEDEC standard JESD 13-B
3. Applications
Industrial
4. Ordering information
Table 1.
Ordering information
All types operate from −40 °C to +85 °C.
Type number
Package
Name
Description
Version
HEF4516BP
HEF4516BT
DIP16
SO16
plastic dual in-line package; 16-leads (300 mil)
plastic small outline package; 16 leads; body width 3.9 mm
SOT38-4
SOT109-1
HEF4516B
NXP Semiconductors
Binary up/down counter
5. Functional diagram
4
12
D1
13
D2
3
D0
D3
PL
1
PARALLEL LOAD CIRCUITRY
CP
S /C
D
D
15
5
CE
TC
UP/DOWN
COUNTER
7
UP/DN
MR
10
9
C
D
Q0
Q1
11
Q2
14
Q3
6
2
001aae667
Fig 1. Functional diagram
HEF4516B_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 11 December 2009
2 of 16
HEF4516B
NXP Semiconductors
Binary up/down counter
D1
D2
D3
D4
MR
PL
CP
UP/DN
CE
S
S
S
S
D
D
D
D
J
Q
Q
J
Q
Q
J
Q
Q
J
Q
Q
FF1
FF2
FF3
FF4
CP
CP
CP
CP
K
K
K
K
C
C
C
C
D
D
D
D
Q0
Q1
Q2
Q3
TC
001aaj798
Fig 2. Logic diagram
HEF4516B_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 11 December 2009
3 of 16
HEF4516B
NXP Semiconductors
Binary up/down counter
6. Pinning information
6.1 Pinning
HEF4516B
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PL
Q3
D3
D0
CE
Q0
TC
V
DD
CP
Q2
D2
D1
Q1
UP/DN
MR
V
SS
001aae689
Fig 3. Pin configuration
6.2 Pin description
Table 2.
Symbol
PL
Pin description
Pin
Description
1
parallel load input (active HIGH)
parallel input
D0 to D3
CE
4, 12, 13, 3
5
count enable input (active LOW)
parallel output
Q0 to Q3
VSS
6, 11, 14, 2
8
ground supply voltage
TC
7
terminal count output (active LOW)
master reset input
MR
9
UP/DN
CP
10
15
16
up/down count control input
clock pulse input (LOW to HIGH, edge triggered)
supply voltage
VDD
HEF4516B_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 11 December 2009
4 of 16
HEF4516B
NXP Semiconductors
Binary up/down counter
7. Functional description
Table 3.
Function table[1]
MR
L
PL
H
L
UP/DN
CE
X
CP
X
MODE
X
X
L
parallel load
no change
count down
count up
reset
L
H
L
X
L
L
↑
L
L
H
X
L
↑
H
X
X
X
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = positive-going transition.
CP
CE
UP/DN
MR
PL
V
V
DD
D0
D1
SS
D2
D3
Q0
Q1
Q2
Q3
TC
count
5
6
7
8
9
10 11 12 13 14 15
9
8
7
6
5
4
3
2
1
0
0
15 0
001aae693
Fig 4. Timing diagram
HEF4516B_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 11 December 2009
5 of 16
HEF4516B
NXP Semiconductors
Binary up/down counter
0
1
2
3
4
15
14
13
12
5
6
7
8
11
10
9
count up
count down
001aae692
Logic equation for terminal count:
TC = CE • {(UP ⁄ DN) • Q0 • Q1 • Q2 • Q3 + (UP ⁄ DN) • Q0 • Q1 • Q2 • Q3} .
Fig 5. State diagram
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDD
IIK
Parameter
Conditions
Min
Max
+18
Unit
V
supply voltage
−0.5
input clamping current
input voltage
VI < −0.5 V or VI > VDD + 0.5 V
VO < −0.5 V or VO > VDD + 0.5 V
-
±10
mA
V
VI
−0.5
VDD + 0.5
±10
IOK
output clamping current
input/output current
supply current
-
mA
mA
mA
°C
II/O
-
±10
IDD
-
50
Tstg
Tamb
Ptot
storage temperature
ambient temperature
total power dissipation
−65
+150
+85
−40
°C
[1]
[2]
DIP16 package
SO16 package
per output
-
-
-
750
mW
mW
mW
500
P
power dissipation
100
[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 °C.
[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 °C.
9. Recommended operating conditions
Table 5.
Symbol
VDD
Recommended operating conditions
Parameter
Conditions
Min
3
Typ
Max
15
Unit
supply voltage
input voltage
-
-
-
V
VI
0
VDD
+85
V
Tamb
ambient temperature
in free air
−40
°C
HEF4516B_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 11 December 2009
6 of 16
HEF4516B
NXP Semiconductors
Binary up/down counter
Table 5.
Symbol
Δt/ΔV
Recommended operating conditions …continued
Parameter
Conditions
VDD = 5 V
Min
Typ
Max
3.75
0.5
Unit
μs/V
μs/V
μs/V
input transition rise and fall rate
-
-
-
-
-
-
VDD = 10 V
VDD = 15 V
0.08
10. Static characteristics
Table 6.
Static characteristics
VSS = 0 V; VI = VSS or VDD unless otherwise specified.
Symbol Parameter Conditions
VDD
Tamb = −40 °C Tamb = 25 °C
Tamb = 85 °C Unit
Min
Max
Min
Max
Min
Max
VIH
HIGH-level input voltage |IO| < 1 μA
5 V
10 V
15 V
5 V
3.5
-
3.5
-
3.5
-
V
7.0
-
7.0
-
7.0
-
V
11.0
-
11.0
-
11.0
-
V
VIL
LOW-level input voltage
|IO| < 1 μA
-
1.5
-
1.5
-
1.5
V
10 V
15 V
5 V
-
3.0
-
3.0
-
3.0
V
-
4.0
-
4.0
-
4.0
V
VOH
VOL
IOH
HIGH-level output voltage |IO| < 1 μA;
VI = VSS or VDD
4.95
-
4.95
-
4.95
-
V
10 V
15 V
5 V
9.95
-
9.95
-
9.95
-
V
14.95
-
14.95
-
14.95
-
V
LOW-level output voltage |IO| < 1 μA;
VI = VSS or VDD
-
0.05
-
0.05
-
0.05
V
10 V
15 V
5 V
-
0.05
-
0.05
-
0.05
V
-
−1.7
−0.52
−1.3
−3.6
0.52
1.3
3.6
-
0.05
-
−1.4
−0.44
−1.1
−3.0
0.44
1.1
3.0
-
0.05
-
−1.1
−0.36
−0.9
−2.4
0.36
0.9
2.4
-
0.05
V
HIGH-level output current VO = 2.5 V
-
-
-
-
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
mA
VO = 4.6 V
VO = 9.5 V
5 V
-
10 V
15 V
5 V
-
-
VO = 13.5 V
-
-
-
IOL
LOW-level output current VO = 0.4 V
VO = 0.5 V
-
10 V
15 V
15 V
5 V
-
-
VO = 1.5 V
-
-
II
input leakage current
supply current
VDD = 15 V
±0.3
20
40
80
-
±0.3
20
40
80
7.5
±1.0 μA
150 μA
300 μA
600 μA
IDD
IO = 0 A;
-
-
-
VI = VSS or VDD
10 V
15 V
-
-
-
-
-
-
-
CI
input capacitance
-
-
-
-
pF
HEF4516B_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 11 December 2009
7 of 16
HEF4516B
NXP Semiconductors
Binary up/down counter
11. Dynamic characteristics
Table 7.
Dynamic characteristics
VSS = 0 V; Tamb = 25 °C; for test circuit see Figure 8; unless otherwise specified.
Symbol Parameter
Conditions
VDD
5 V
Extrapolation formula
118 ns + (0.55 ns/pF)CL
49 ns + (0.23 ns/pF)CL
37 ns + (0.16 ns/pF)CL
233 ns + (0.55 ns/pF)CL
94 ns + (0.23 ns/pF)CL
67 ns + (0.16 ns/pF)CL
98 ns + (0.55 ns/pF)CL
44 ns + (0.23 ns/pF)CL
32 ns + (0.16 ns/pF)CL
223 ns + (0.55 ns/pF)CL
99 ns + (0.23 ns/pF)CL
72 ns + (0.16 ns/pF)CL
138 ns + (0.55 ns/pF)CL
54 ns + (0.23 ns/pF)CL
42 ns + (0.16 ns/pF)CL
178 ns + (0.55 ns/pF)CL
54 ns + (0.23 ns/pF)CL
37 ns + (0.16 ns/pF)CL
128 ns + (0.55 ns/pF)CL
54 ns + (0.23 ns/pF)CL
37 ns + (0.16 ns/pF)CL
153 ns + (0.55 ns/pF)CL
64 ns + (0.23 ns/pF)CL
47 ns + (0.16 ns/pF)CL
143 ns + (0.55 ns/pF)CL
59 ns + (0.23 ns/pF)CL
42 ns + (0.16 ns/pF)CL
223 ns + (0.55 ns/pF)CL
99 ns + (0.23 ns/pF)CL
72 ns + (0.16 ns/pF)CL
118 ns + (0.55 ns/pF)CL
49 ns + (0.23 ns/pF)CL
37 ns + (0.16 ns/pF)CL
198 ns + (0.55 ns/pF)CL
64 ns + (0.23 ns/pF)CL
42 ns + (0.16 ns/pF)CL
Min
-
Typ
145
60
Max
290
120
90
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
[1]
tPHL
HIGH to LOW
CP to Qn
CP to TC
PL to Qn
PL to TC
CE to TC
MR to Qn, TC
CP to Qn
CP to TC
PL to Qn
PL to TC
CE to TC
MR to TC
propagation delay
10 V
15 V
5 V
-
-
45
-
260
105
75
525
210
150
255
110
85
10 V
15 V
5 V
-
-
-
125
55
10 V
15 V
5 V
-
-
40
-
250
110
80
500
220
160
330
135
100
405
130
85
10 V
15 V
5 V
-
-
-
165
65
10 V
15 V
5 V
-
-
50
-
205
65
10 V
15 V
5 V
-
-
45
[1]
tPLH
LOW to HIGH
-
155
65
310
130
90
propagation delay
10 V
15 V
5 V
-
-
45
-
180
75
360
150
115
340
140
105
500
220
160
290
125
95
10 V
15 V
5 V
-
-
55
-
170
70
10 V
15 V
5 V
-
-
50
-
250
110
80
10 V
15 V
5 V
-
-
-
145
60
10 V
15 V
5 V
-
-
45
-
225
75
450
150
100
10 V
15 V
-
-
50
HEF4516B_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 11 December 2009
8 of 16
HEF4516B
NXP Semiconductors
Binary up/down counter
Table 7.
Dynamic characteristics …continued
VSS = 0 V; Tamb = 25 °C; for test circuit see Figure 8; unless otherwise specified.
Symbol Parameter
Conditions
VDD
5 V
Extrapolation formula
10 ns + (1.00 ns/pF)CL
9 ns + (0.42 ns/pF)CL
6 ns + (0.28 ns/pF)CL
Min
-
Typ
60
Max
Unit
ns
ns
ns
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
[1]
tt
transition time
120
10 V
15 V
5 V
-
30
60
40
-
-
20
fmax
maximum frequency see Figure 6
3
6
10 V
15 V
5 V
7
14
-
9
18
-
tW
pulse width
CP input LOW;
minimum width;
see Figure 6
95
35
25
105
45
35
120
50
40
130
45
30
150
50
30
100
50
40
250
100
75
120
40
25
+10
+5
0
45
-
10 V
15 V
5 V
20
-
15
-
PL input HIGH;
minimum width;
see Figure 7
55
-
10 V
15 V
5 V
25
-
15
-
MR input HIGH;
minimum width;
see Figure 7
60
-
10 V
15 V
5 V
25
-
20
-
trec
recovery time
MR input;
see Figure 7
65
-
10 V
15 V
5 V
20
-
15
-
PL input;
see Figure 7
75
-
10 V
15 V
5 V
25
-
15
-
tsu
set-up time
Dn to PL;
see Figure 7
50
-
10 V
15 V
5 V
25
-
20
-
UP/DN to CP;
see Figure 6
125
50
-
10 V
15 V
5 V
-
35
-
CE to CP;
see Figure 6
60
-
10 V
15 V
5 V
20
-
10
-
th
hold time
Dn to PL;
see Figure 7
−40
−20
−20
−90
−35
−25
−40
−15
−10
-
10 V
15 V
5 V
-
-
UP/DN to CP;
see Figure 6
+35
+15
+15
+20
+5
+5
-
10 V
15 V
5 V
-
-
CE to CP;
see Figure 6
-
10 V
15 V
-
-
[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).
HEF4516B_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 11 December 2009
9 of 16
HEF4516B
NXP Semiconductors
Binary up/down counter
Table 8.
Dynamic power dissipation PD
PD can be calculated from the formulas shown. VSS = 0 V; CL = 50 pF; tr = tf ≤ 20 ns; Tamb = 25 °C.
Symbol
Parameter
VDD
5 V
Typical formula for PD (μW)
PD = 1000 × fi + Σ(fo × CL) × VDD
PD = 4500 × fi + Σ(fo × CL) × VDD
Where:
2
2
PD
dynamic power
dissipation
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
10 V
15 V
2
PD = 11200 × fi + Σ(fo × CL) × VDD
VDD = supply voltage in V;
Σ(fo × CL) = sum of the outputs.
12. Waveforms
t
W
V
I
CP input
V
M
V
SS
t
su
t
h
V
I
V
M
CE input
V
SS
t
t
h
t
su
t
h
su
V
I
UP/DN input
V
M
V
SS
001aae672
Measurement points are given in Table 9.
Fig 6. Waveforms showing minimum pulse width for CP, set-up and hold times for CE to CP and UP/DN to CP
V
I
CP input
V
M
V
SS
t
W
t
rec
V
I
V
M
PL input
V
SS
t
t
h
su
V
I
Dn input
V
M
V
SS
t
rec
V
I
V
M
MR input
V
SS
t
W
001aae673
Measurement points are given in Table 9.
Fig 7. Waveforms showing PL and MR minimum pulse widths and recovery times, and Dn to PL set-up and hold
times
HEF4516B_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 11 December 2009
10 of 16
HEF4516B
NXP Semiconductors
Binary up/down counter
t
W
V
I
90 %
negative
pulse
V
V
V
V
M
M
10 %
0 V
t
t
r
f
t
r
t
f
V
I
90 %
positive
pulse
M
M
10 %
0 V
t
W
001aaj781
a. Input waveforms
V
DD
V
I
V
O
G
DUT
C
L
R
T
001aag182
b. Test circuit
Test data is given in Table 9.
Definitions for test circuit:
DUT = Device Under Test
CL = Load capacitance including jig and probe capacitance;
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
Fig 8. Test circuit for measuring switching times
Table 9.
Measurement points and test data
Supply voltage
Input
VI
Load
CL
VM
tr, tf
5 V to 15 V
VDD
0.5VI
≤ 20 ns
50 pF
HEF4516B_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 11 December 2009
11 of 16
HEF4516B
NXP Semiconductors
Binary up/down counter
13. Package outline
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
b
2
16
9
M
H
pin 1 index
E
1
8
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
2
(1)
(1)
Z
1
w
UNIT
mm
b
b
b
c
D
E
e
e
L
M
M
H
1
2
1
E
max.
min.
max.
max.
1.73
1.30
0.53
0.38
1.25
0.85
0.36
0.23
19.50
18.55
6.48
6.20
3.60
3.05
8.25
7.80
10.0
8.3
4.2
0.51
3.2
2.54
0.1
7.62
0.3
0.254
0.01
0.76
0.068 0.021 0.049 0.014
0.051 0.015 0.033 0.009
0.77
0.73
0.26
0.24
0.14
0.12
0.32
0.31
0.39
0.33
inches
0.17
0.02
0.13
0.03
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
95-01-14
03-02-13
SOT38-4
Fig 9. Package outline SOT38-4 (DIP16)
HEF4516B_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 11 December 2009
12 of 16
HEF4516B
NXP Semiconductors
Binary up/down counter
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
c
y
H
v
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT109-1
076E07
MS-012
Fig 10. Package outline SOT109-1 (SO16)
HEF4516B_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 11 December 2009
13 of 16
HEF4516B
NXP Semiconductors
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14. Revision history
Table 10. Revision history
Document ID
Release date
20091211
Data sheet status
Change notice
Supersedes
HEF4516B_6
Product data sheet
-
HEF4516B_5
Modifications:
• Section 9 “Recommended operating conditions” Δt/ΔV values updated.
HEF4516B_5
20090812
20090312
19950101
19950101
Product data sheet
Product data sheet
Product specification
Product specification
-
-
-
-
HEF4516B_4
HEF4516B_CNV_3
HEF4516B_CNV_2
-
HEF4516B_4
HEF4516B_CNV_3
HEF4516B_CNV_2
HEF4516B_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 11 December 2009
14 of 16
HEF4516B
NXP Semiconductors
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15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
HEF4516B_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 11 December 2009
15 of 16
HEF4516B
NXP Semiconductors
Binary up/down counter
17. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
7
Functional description . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 14
8
9
10
11
12
13
14
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 15
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 15
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 11 December 2009
Document identifier: HEF4516B_6
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