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HEF4518BT-T [NXP]

IC 4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP DECADE COUNTER, PDSO16, 3.90 MM, PLASTIC, MS-012, SOT109-1, SOP-16, Counter;
HEF4518BT-T
型号： HEF4518BT-T
厂家： NXP    NXP
描述：

IC 4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP DECADE COUNTER, PDSO16, 3.90 MM, PLASTIC, MS-012, SOT109-1, SOP-16, Counter

输入元件 光电二极管 逻辑集成电路 触发器
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HEF4518B  
Dual BCD counter  
Rev. 06 — 10 December 2009  
Product data sheet  
1. General description  
The HEF4518B is a dual 4-bit internally synchronous BCD counter. The counter has an  
active HIGH clock input (nCP0) and an active LOW clock input (nCP1), buffered outputs  
from all four bit positions (nQ0 to nQ3) and an active HIGH overriding asynchronous  
master reset input (nMR). The counter advances on either the LOW-to-HIGH transition of  
the nCP0 input if nCP1 is HIGH or the HIGH-to-LOW transition of the nCP1 input if nCP0  
is LOW. Either nCP0 or nCP1 may be used as the clock input to the counter and the other  
clock input may be used as a clock enable input. A HIGH on nMR resets the counter (nQ0  
to nQ3 = LOW) independent of nCP0, nCP1. Schmitt trigger action in the clock input  
makes the circuit highly tolerant of slower clock rise and fall times.  
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS  
(usually ground). Unused inputs must be connected to VDD, VSS, or another input. It is  
also suitable for use over the full industrial (−40 °C to +85 °C) temperature range.  
2. Features  
„ Tolerant of slow clock rise and fall times  
„ Fully static operation  
„ 5 V, 10 V, and 15 V parametric ratings  
„ Standardized symmetrical output characteristics  
„ Operates across the full industrial temperature range −40 °C to +85 °C  
„ Complies with JEDEC standard JESD 13-B  
3. Applications  
„ Multistage synchronous counting  
„ Multistage asynchronous counting  
„ Frequency dividers  
4. Ordering information  
Table 1.  
Ordering information  
All types operate from −40 °C to +85 °C  
Type number  
Package  
Name  
Description  
Version  
HEF4518BP  
HEF4518BT  
DIP16  
SO16  
plastic dual in-line package; 16 leads (300 mil)  
plastic small outline package; 16 leads; body width 3.9 mm  
SOT38-4  
SOT109-1  
HEF4518B  
NXP Semiconductors  
Dual BCD counter  
5. Functional diagram  
1Q0  
1Q1  
1Q2  
1Q3  
3
4
5
6
1
2
1CP0  
1CP1  
7
9
1MR  
2Q0 11  
2Q1 12  
2Q2 13  
2Q3 14  
2CP0  
10 2CP1  
15 2MR  
001aae698  
Fig 1. Functional diagram  
Q0  
Q1  
Q2  
Q3  
Q
Q
Q
Q
Q
Q
FF4  
FF1  
FF2  
FF3  
CP1  
CP0  
T
T
T
T
Q
Q
C
D
C
C
D
C
D
D
MR  
001aae700  
Fig 2. Logic diagram for one counter  
HEF4518B_6  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 06 — 10 December 2009  
2 of 14  
HEF4518B  
NXP Semiconductors  
Dual BCD counter  
6. Pinning information  
6.1 Pinning  
HEF4518B  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
1CP0  
1CP1  
1Q0  
V
DD  
2MR  
2Q3  
1Q1  
2Q2  
1Q2  
2Q1  
1Q3  
2Q0  
1MR  
2CP1  
2CP0  
V
SS  
001aae699  
Fig 3. Pin configuration  
6.2 Pin description  
Table 2.  
Symbol  
1CP0, 2CP0  
1CP1, 2CP1  
1Q0, 2Q0  
1Q1,2Q1  
1Q2, 2Q2  
1Q3, 2Q3  
1MR, 2MR  
VDD  
Pin description  
Pin  
Description  
1, 9  
2, 10  
3,11  
4, 12  
5,13  
6, 14  
7, 15  
16  
clock input (LOW-to-HIGH triggered)  
clock input (HIGH-to-LOW triggered)  
output  
output  
output  
output  
master reset input  
supply voltage  
ground supply voltage  
VSS  
8
HEF4518B_6  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 06 — 10 December 2009  
3 of 14  
HEF4518B  
NXP Semiconductors  
Dual BCD counter  
7. Functional description  
Table 3.  
Function table[1]  
nCP0  
nCP1  
nMR  
Mode  
↑
L
H
↓
X
↑
L
L
L
L
L
L
L
H
counter advances  
counter advances  
no change  
↓
X
↑
H
X
no change  
no change  
↓
X
no change  
nQ0 to nQ3 = LOW  
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = positive-going transition; ↓ = negative-going transition.  
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10 11 12 13 14 15 16 17 18  
nCP0  
nCP1  
nMR  
0
1
2
3
4
5
6
7
8
9
0
nQ0  
nQ1  
nQ2  
nQ3  
001aae703  
Fig 4. Timing diagram  
HEF4518B_6  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 06 — 10 December 2009  
4 of 14  
HEF4518B  
NXP Semiconductors  
Dual BCD counter  
8. Limiting values  
Table 4.  
Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134).  
Symbol  
VDD  
IIK  
Parameter  
Conditions  
Min  
Max  
Unit  
V
supply voltage  
−0.5  
+18  
±10  
input clamping current  
input voltage  
VI < −0.5 V or VI > VDD + 0.5 V  
VO < −0.5 V or VO > VDD + 0.5 V  
-
mA  
V
VI  
−0.5  
VDD + 0.5  
±10  
IOK  
output clamping current  
input/output current  
supply current  
-
mA  
mA  
mA  
°C  
II/O  
-
±10  
IDD  
-
50  
Tstg  
Tamb  
Ptot  
storage temperature  
ambient temperature  
total power dissipation  
−65  
+150  
+85  
−40  
°C  
[1]  
[2]  
DIP16 package  
SO16 package  
per output  
-
-
-
750  
mW  
mW  
mW  
500  
P
power dissipation  
100  
[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 °C.  
[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 °C.  
9. Recommended operating conditions  
Table 5.  
Symbol  
VDD  
Recommended operating conditions  
Parameter  
Conditions  
Min  
Typ  
Max  
15  
Unit  
supply voltage  
3
-
-
-
-
-
-
V
VI  
input voltage  
0
VDD  
+85  
3.75  
0.5  
V
Tamb  
ambient temperature  
input transition rise and fall rate  
in free air  
VDD = 5 V  
VDD = 10 V  
VDD = 15 V  
−40  
°C  
Δt/ΔV  
-
-
-
μs/V  
μs/V  
μs/V  
0.08  
10. Static characteristics  
Table 6.  
Static characteristics  
VSS = 0 V; VI = VSS or VDD unless otherwise specified.  
Symbol Parameter Conditions  
VDD  
Tamb = −40 °C Tamb = 25 °C  
Tamb = 85 °C Unit  
Min  
3.5  
7.0  
11.0  
-
Max  
-
Min  
3.5  
7.0  
11.0  
-
Max  
-
Min  
3.5  
7.0  
11.0  
-
Max  
-
VIH  
HIGH-level input voltage |IO| < 1 μA  
5 V  
10 V  
15 V  
5 V  
V
V
V
V
V
V
-
-
-
-
-
-
VIL  
LOW-level input voltage  
|IO| < 1 μA  
1.5  
3.0  
4.0  
1.5  
3.0  
4.0  
1.5  
3.0  
4.0  
10 V  
15 V  
-
-
-
-
-
-
HEF4518B_6  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 06 — 10 December 2009  
5 of 14  
HEF4518B  
NXP Semiconductors  
Dual BCD counter  
Table 6.  
Static characteristics …continued  
VSS = 0 V; VI = VSS or VDD unless otherwise specified.  
Symbol Parameter  
Conditions  
VDD  
Tamb = −40 °C Tamb = 25 °C  
Tamb = 85 °C Unit  
Min  
Max  
Min  
Max  
Min  
Max  
VOH  
VOL  
IOH  
HIGH-level output voltage |IO| < 1 μA  
LOW-level output voltage |IO| < 1 μA  
5 V  
10 V  
15 V  
5 V  
4.95  
-
4.95  
-
4.95  
-
V
9.95  
-
9.95  
-
9.95  
-
V
14.95  
-
14.95  
-
14.95  
-
V
-
0.05  
-
0.05  
-
0.05  
V
10 V  
15 V  
5 V  
-
0.05  
-
0.05  
-
0.05  
V
-
−1.7  
−0.52  
−1.3  
−3.6  
0.52  
1.3  
3.6  
-
0.05  
-
−1.4  
−0.44  
−1.1  
−3.0  
0.5  
1.1  
3.0  
-
0.05  
-
−1.1  
−0.36  
−0.9  
−2.4  
0.36  
0.9  
2.4  
-
0.05  
V
HIGH-level output current VO = 2.5 V  
-
-
-
-
-
-
-
-
-
-
mA  
mA  
mA  
mA  
mA  
mA  
mA  
VO = 4.6 V  
VO = 9.5 V  
5 V  
-
10 V  
15 V  
5 V  
-
-
VO = 13.5 V  
-
-
-
IOL  
LOW-level output current VO = 0.4 V  
VO = 0.5 V  
-
10 V  
15 V  
15 V  
5 V  
-
-
VO = 1.5 V  
-
-
II  
input leakage current  
supply current  
VDD = 15 V  
IO = 0 A  
±0.3  
20  
40  
80  
-
±0.3  
20  
40  
80  
7.5  
±1.0 μA  
150 μA  
300 μA  
600 μA  
IDD  
-
-
-
10 V  
15 V  
-
-
-
-
-
-
CI  
input capacitance  
-
-
-
-
-
pF  
11. Dynamic characteristics  
Table 7.  
Dynamic characteristics  
VSS = 0 V; Tamb = 25 °C; for test circuit see Figure 6; unless otherwise specified.  
Symbol Parameter  
Conditions  
VDD  
5 V  
Extrapolation formula Min  
Typ  
120  
55  
Max Unit  
[1]  
tPHL  
HIGH to LOW  
nCP0, nCP1 to nQn;  
93 ns + (0.55 ns/pF)CL  
44 ns + (0.23 ns/pF)CL  
32 ns + (0.16 ns/pF)CL  
48 ns + (0.55 ns/pF)CL  
24 ns + (0.23 ns/pF)CL  
17 ns + (0.16 ns/pF)CL  
93 ns + (0.55 ns/pF)CL  
44 ns + (0.23 ns/pF)CL  
32 ns + (0.16 ns/pF)CL  
10 ns + (1.00 ns/pF)CL  
9 ns + (0.42 ns/pF)CL  
6 ns + (0.28 ns/pF)CL  
-
-
-
-
-
-
-
-
-
-
-
-
240  
110  
80  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
propagation delay see Figure 5  
10 V  
15 V  
5 V  
40  
nMR to nQn;  
see Figure 5  
75  
150  
70  
10 V  
15 V  
5 V  
35  
25  
50  
[1]  
[1]  
tPLH  
LOW to HIGH  
nCP0, nCP1 to nQn;  
120  
55  
240  
110  
80  
propagation delay see Figure 5  
10 V  
15 V  
5 V  
40  
tt  
transition time  
nQn; see Figure 5  
60  
120  
60  
10 V  
15 V  
30  
20  
40  
HEF4518B_6  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 06 — 10 December 2009  
6 of 14  
HEF4518B  
NXP Semiconductors  
Dual BCD counter  
Table 7.  
Dynamic characteristics …continued  
VSS = 0 V; Tamb = 25 °C; for test circuit see Figure 6; unless otherwise specified.  
Symbol Parameter  
Conditions  
VDD  
5 V  
Extrapolation formula Min  
Typ  
30  
15  
10  
30  
15  
10  
15  
10  
8
Max Unit  
tW  
pulse width  
nCP0 input LOW;  
minimum width;  
see Figure 5  
60  
30  
20  
60  
30  
20  
30  
20  
16  
50  
30  
20  
50  
30  
20  
50  
30  
20  
8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns  
10 V  
15 V  
5 V  
ns  
ns  
nCP1 input HIGH;  
minimum width;  
see Figure 5  
ns  
10 V  
15 V  
5 V  
ns  
ns  
nMR input HIGH;  
minimum width;  
see Figure 5  
ns  
10 V  
15 V  
ns  
ns  
trec  
recovery time  
set-up time  
nMR input; see Figure 5 5 V  
25  
15  
10  
25  
15  
10  
25  
15  
10  
16  
30  
40  
ns  
10 V  
15 V  
ns  
ns  
tsu  
nCP0 to nCP1;  
see Figure 5  
5 V  
10 V  
15 V  
5 V  
ns  
ns  
ns  
nCP1 to nCP0;  
see Figure 5  
ns  
10 V  
15 V  
5 V  
ns  
ns  
fmax  
maximum  
frequency  
nCP0, nCP1;  
see Figure 5  
MHz  
MHz  
MHz  
10 V  
15 V  
15  
20  
[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).  
Table 8.  
Dynamic power dissipation PD  
PD can be calculated from the formulas shown. VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C.  
Symbol  
Parameter  
VDD  
5 V  
Typical formula for PD (μW)  
PD = 750 × fi + Σ(fo × CL) × VDD  
Where:  
2
PD  
dynamic power  
dissipation  
fi = input frequency in MHz;  
fo = output frequency in MHz;  
CL = output load capacitance in pF;  
2
2
10 V  
15 V  
PD = 3300 × fi + Σ(fo × CL) × VDD  
PD = 8000 × fi + Σ(fo × CL) × VDD  
VDD = supply voltage in V;  
Σ(fo × CL) = sum of the outputs.  
HEF4518B_6  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 06 — 10 December 2009  
7 of 14  
HEF4518B  
NXP Semiconductors  
Dual BCD counter  
12. Waveforms  
V
I
V
M
nCP0 input  
0 V  
V
I
nCP1 input  
0 V  
V
M
0 V  
t
t
su  
su  
V
I
nMR input  
0 V  
V
M
t
t
t
PHL  
PHL  
PLH  
V
OH  
90 %  
nQn output  
V
M
10 %  
V
OL  
t
t
t
t
001aae702  
a. nCP0 and nCP1 set-up times, propagation delays and output transition times  
1/f  
max  
V
I
nCP1 input  
(nCP0 = LOW)  
V
M
0 V  
t
t
W
V
I
nCP0 input  
(nCP1 = HIGH)  
V
M
0 V  
W
V
I
V
M
nMR input  
0 V  
t
W
t
rec  
001aae701  
b. nMR recovery time, minimum nCP0, nCP1, and nMR pulse widths and maximum frequency  
Measurement points are given in table Table 9.  
The logic levels VOH and VOL are typical output voltage levels that occur with the output load.  
Fig 5. Waveforms showing measurements for switching times  
HEF4518B_6  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 06 — 10 December 2009  
8 of 14  
HEF4518B  
NXP Semiconductors  
Dual BCD counter  
t
W
V
I
90 %  
negative  
pulse  
V
V
V
V
M
M
10 %  
0 V  
t
t
r
f
t
r
t
f
V
I
90 %  
positive  
pulse  
M
M
10 %  
0 V  
t
W
001aaj781  
a. Input waveforms  
V
DD  
V
I
V
O
G
DUT  
C
L
R
T
001aag182  
b. Test circuit  
Test data is given in Table 9.  
Definitions for test circuit:  
CL = Load capacitance including jig and probe capacitance;  
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.  
Fig 6. Test circuit for switching times  
Table 9.  
Measurement points and test data  
Supply voltage  
Input  
VI  
Load  
CL  
VM  
tr, tf  
5 V to 15 V  
VDD  
0.5VI  
≤ 20 ns  
50 pF  
HEF4518B_6  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 06 — 10 December 2009  
9 of 14  
HEF4518B  
NXP Semiconductors  
Dual BCD counter  
13. Package outline  
DIP16: plastic dual in-line package; 16 leads (300 mil)  
SOT38-4  
D
M
E
A
2
A
A
1
L
c
e
w M  
Z
b
1
(e )  
1
b
b
2
16  
9
M
H
pin 1 index  
E
1
8
0
5
10 mm  
scale  
DIMENSIONS (inch dimensions are derived from the original mm dimensions)  
(1)  
Z
A
A
A
2
(1)  
(1)  
1
w
UNIT  
mm  
b
b
b
c
D
E
e
e
L
M
M
H
1
2
1
E
max.  
min.  
max.  
max.  
1.73  
1.30  
0.53  
0.38  
1.25  
0.85  
0.36  
0.23  
19.50  
18.55  
6.48  
6.20  
3.60  
3.05  
8.25  
7.80  
10.0  
8.3  
4.2  
0.51  
3.2  
2.54  
0.1  
7.62  
0.3  
0.254  
0.01  
0.76  
0.068 0.021 0.049 0.014  
0.051 0.015 0.033 0.009  
0.77  
0.73  
0.26  
0.24  
0.14  
0.12  
0.32  
0.31  
0.39  
0.33  
inches  
0.17  
0.02  
0.13  
0.03  
Note  
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
95-01-14  
03-02-13  
SOT38-4  
Fig 7. Package outline SOT38-4 (DIP16)  
HEF4518B_6  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 06 — 10 December 2009  
10 of 14  
HEF4518B  
NXP Semiconductors  
Dual BCD counter  
SO16: plastic small outline package; 16 leads; body width 3.9 mm  
SOT109-1  
D
E
A
X
v
c
y
H
M
A
E
Z
16  
9
Q
A
2
A
(A )  
3
A
1
pin 1 index  
L
p
L
1
8
e
w
M
detail X  
b
p
0
2.5  
scale  
5 mm  
DIMENSIONS (inch dimensions are derived from the original mm dimensions)  
A
(1)  
(1)  
(1)  
UNIT  
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
1
2
3
p
E
max.  
0.25  
0.10  
1.45  
1.25  
0.49  
0.36  
0.25  
0.19  
10.0  
9.8  
4.0  
3.8  
6.2  
5.8  
1.0  
0.4  
0.7  
0.6  
0.7  
0.3  
mm  
1.27  
0.05  
1.05  
0.041  
1.75  
0.25  
0.01  
0.25  
0.01  
0.25  
0.1  
8o  
0o  
0.010 0.057  
0.004 0.049  
0.019 0.0100 0.39  
0.014 0.0075 0.38  
0.16  
0.15  
0.244  
0.228  
0.039 0.028  
0.016 0.020  
0.028  
0.012  
inches  
0.069  
0.01 0.004  
Note  
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
99-12-27  
03-02-19  
SOT109-1  
076E07  
MS-012  
Fig 8. Package outline SOT109-1 (SO16)  
HEF4518B_6  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 06 — 10 December 2009  
11 of 14  
HEF4518B  
NXP Semiconductors  
Dual BCD counter  
14. Revision history  
Table 10. Revision history  
Document ID  
Release date  
20091210  
Data sheet status  
Change notice  
Supersedes  
HEF4518B_6  
Product data sheet  
-
HEF4518B_5  
Modifications:  
• Section 9 “Recommended operating conditions” Δt/ΔV values updated.  
HEF4518B_5  
20090727  
20090703  
19950101  
19950101  
Product data sheet  
Product data sheet  
Product specification  
Product specification  
-
-
-
-
HEF4518B_4  
HEF4518B_CNV_3  
HEF4518B_CNV_2  
-
HEF4518B_4  
HEF4518B_CNV_3  
HEF4518B_CNV_2  
HEF4518B_6  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 06 — 10 December 2009  
12 of 14  
HEF4518B  
NXP Semiconductors  
Dual BCD counter  
15. Legal information  
15.1 Data sheet status  
Document status[1][2]  
Product status[3]  
Development  
Definition  
Objective [short] data sheet  
This document contains data from the objective specification for product development.  
This document contains data from the preliminary specification.  
This document contains the product specification.  
Preliminary [short] data sheet Qualification  
Product [short] data sheet Production  
[1]  
[2]  
[3]  
Please consult the most recently issued document before initiating or completing a design.  
The term ‘short data sheet’ is explained in section “Definitions”.  
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status  
information is available on the Internet at URL http://www.nxp.com.  
damage. NXP Semiconductors accepts no liability for inclusion and/or use of  
NXP Semiconductors products in such equipment or applications and  
therefore such inclusion and/or use is at the customer’s own risk.  
15.2 Definitions  
Draft — The document is a draft version only. The content is still under  
internal review and subject to formal approval, which may result in  
modifications or additions. NXP Semiconductors does not give any  
representations or warranties as to the accuracy or completeness of  
information included herein and shall have no liability for the consequences of  
use of such information.  
Applications — Applications that are described herein for any of these  
products are for illustrative purposes only. NXP Semiconductors makes no  
representation or warranty that such applications will be suitable for the  
specified use without further testing or modification.  
Limiting values — Stress above one or more limiting values (as defined in  
the Absolute Maximum Ratings System of IEC 60134) may cause permanent  
damage to the device. Limiting values are stress ratings only and operation of  
the device at these or any other conditions above those given in the  
Characteristics sections of this document is not implied. Exposure to limiting  
values for extended periods may affect device reliability.  
Short data sheet — A short data sheet is an extract from a full data sheet  
with the same product type number(s) and title. A short data sheet is intended  
for quick reference only and should not be relied upon to contain detailed and  
full information. For detailed and full information see the relevant full data  
sheet, which is available on request via the local NXP Semiconductors sales  
office. In case of any inconsistency or conflict with the short data sheet, the  
full data sheet shall prevail.  
Terms and conditions of sale — NXP Semiconductors products are sold  
subject to the general terms and conditions of commercial sale, as published  
at http://www.nxp.com/profile/terms, including those pertaining to warranty,  
intellectual property rights infringement and limitation of liability, unless  
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of  
any inconsistency or conflict between information in this document and such  
terms and conditions, the latter will prevail.  
15.3 Disclaimers  
General — Information in this document is believed to be accurate and  
reliable. However, NXP Semiconductors does not give any representations or  
warranties, expressed or implied, as to the accuracy or completeness of such  
information and shall have no liability for the consequences of use of such  
information.  
No offer to sell or license — Nothing in this document may be interpreted or  
construed as an offer to sell products that is open for acceptance or the grant,  
conveyance or implication of any license under any copyrights, patents or  
other industrial or intellectual property rights.  
Right to make changes — NXP Semiconductors reserves the right to make  
changes to information published in this document, including without  
limitation specifications and product descriptions, at any time and without  
notice. This document supersedes and replaces all information supplied prior  
to the publication hereof.  
Export control — This document as well as the item(s) described herein  
may be subject to export control regulations. Export might require a prior  
authorization from national authorities.  
Suitability for use — NXP Semiconductors products are not designed,  
authorized or warranted to be suitable for use in medical, military, aircraft,  
space or life support equipment, nor in applications where failure or  
malfunction of an NXP Semiconductors product can reasonably be expected  
to result in personal injury, death or severe property or environmental  
15.4 Trademarks  
Notice: All referenced brands, product names, service names and trademarks  
are the property of their respective owners.  
16. Contact information  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
HEF4518B_6  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 06 — 10 December 2009  
13 of 14  
HEF4518B  
NXP Semiconductors  
Dual BCD counter  
17. Contents  
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1  
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Ordering information. . . . . . . . . . . . . . . . . . . . . 1  
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2  
6
6.1  
6.2  
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3  
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3  
7
Functional description . . . . . . . . . . . . . . . . . . . 4  
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5  
Recommended operating conditions. . . . . . . . 5  
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5  
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6  
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10  
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 12  
8
9
10  
11  
12  
13  
14  
15  
Legal information. . . . . . . . . . . . . . . . . . . . . . . 13  
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13  
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
15.1  
15.2  
15.3  
15.4  
16  
17  
Contact information. . . . . . . . . . . . . . . . . . . . . 13  
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Please be aware that important notices concerning this document and the product(s)  
described herein, have been included in section ‘Legal information’.  
© NXP B.V. 2009.  
All rights reserved.  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
Date of release: 10 December 2009  
Document identifier: HEF4518B_6  

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