HEF4527BN [NXP]
BCD rate multiplier; BCD率倍增
| 型号： | HEF4527BN |
| 厂家： | 
NXP |
| 描述： | BCD rate multiplier |
| 文件： | 总10页 (文件大小：97K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4527B
MSI
BCD rate multiplier
January 1995
Product specification
File under Integrated Circuits, IC04
Philips Semiconductors
Product specification
HEF4527B
MSI
BCD rate multiplier
A HIGH on CL resets the counter, independent of all other
input conditions and a rate of 10 pulses is available at O1
and O1 when SD is HIGH. When CE is HIGH, the counter
is disabled, the state of the outputs (O1, O1) depend on the
content of the counter.
DESCRIPTION
The HEF4527B is a BCD rate multiplier with two buffered
rate outputs (O1 and O1), two buffered terminal count
outputs (TC and TC), four BCD rate select inputs (SA, SB,
SC, SD), a common clock input (CP), a preset input (PL),
an overriding asynchronous clear input (CL), a strobe input
(STR), a cascade input (CAS) and an active LOW count
enable input (CE).
A HIGH on PL sets the counter in the ‘9’ state and TC
becomes HIGH.
A HIGH on STR inhibits the outputs O1 and O1. A HIGH on
CAS forces the output O1 to HIGH, while the state of
O1 depends on the inputs SA to SD (see lines 1 to 16 of
function table).
The BCD rate multiplier provides an output pulse rate
based upon the BCD input number. For example, if 6 is the
BCD number, there will be six output pulses for every ten
clock input pulses. The output is clocked on the
negative-going transition of the clock.
This device may be used to perform arithmetic operations.
For the add mode and multiply mode see Figs 5 and 6.
When CE, STR, CAS, CL and PL are LOW, the rate pulses
are available at the outputs O1 and O1, the terminal count
pulses at TC and TC.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
Fig.1 Functional diagram.
FAMILY DATA, IDD LIMITS category MSI
See Family Specifications
January 1995
2
Philips Semiconductors
Product specification
HEF4527B
MSI
BCD rate multiplier
HEF4527BP(N):
HEF4527BD(F):
HEF4527BT(D):
16-lead DIL; plastic
(SOT38-1)
16-lead DIL; ceramic (cerdip)
(SOT74)
16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
Fig.2 Pinning diagram.
PINNING
CP
clock input
PL
preset to ‘9’ input
CL
counter clear input
count enable input (active LOW)
strobe input
CE
STR
CAS
SA to SD
O1 to O1
TC
cascade input
rate select inputs
rate outputs
terminal count output (active HIGH)
terminal count output (active LOW)
TC
January 1995
3
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Fig.3 Logic diagram.
Philips Semiconductors
Product specification
HEF4527B
MSI
BCD rate multiplier
FUNCTION TABLE
INPUTS
OUTPUTS
NUMBER OF PULSES OR LOGIC LEVEL
NUMBER OF PULSES
OR LOGIC LEVEL
MODE OF OPERATION
SD SC SB SA CP CE STR CAS CL PL
O1
O1
TC
TC
L
L
L
L
L
L
L
H
L
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
H
L
1
2
3
4
5
6
7
8
9
8
9
8
9
8
H
1
2
3
4
5
6
7
8
9
8
9
8
9
8
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
H
1
1
H
H
L
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
L
L
H
H
L
L
L
H
L
L
H
H
H
H
L
L
L
H
L
L
H
H
L
rate pulses at the outputs
depend on the BCD input
number at SA to SD
L
H
L
H
H
H
H
H
H
H
H
X
X
X
H
L
L
L
H
L
L
H
H
L
L
H
L
H
H
H
H
X
X
X
X
X
X
L
H
L
H
H
X
X
X
X
X
X
H
X
X
X
X
X
X
9
(5)
9
(5)
1
(5)
CE = H; counter disabled
outputs O1 and O2 disabled
output O1 disabled
CL = H
10
10
10
X
L
H
10
L
H
(4)
1
1
L
L
H
10
H
counter reset
X
X
L
H
PL = H; preset to ‘9’
Notes
1. H = HIGH state (the more positive voltage)
2. L = LOW state (the less positive voltage)
3. X = state is immaterial
4. Same output as the first 16 lines of this function table (depends on the values of SA to SD).
5. Depends on internal state of the counter.
January 1995
5
Philips Semiconductors
Product specification
HEF4527B
MSI
BCD rate multiplier
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns.
VDD
V
TYPICAL EXTRAPOLATION
FORMULA
PARAMETER
SYMBOL
MIN.
TYP. MAX. UNIT
Propagation delays
CP → O1, O1
5
10
15
5
130
50
35
130
50
35
175
65
45
160
65
45
175
65
50
150
60
45
90
35
25
70
30
25
100
40
30
85
35
25
95
35
25
65
30
20
260 ns
100 ns
70 ns
103 ns + (0,55 ns/pF) CL
39 ns + (0,23 ns/pF) CL
27 ns + (0,16 ns/pF) CL
103 ns + (0,55 ns/pF) CL
39 ns + (0,23 ns/pF) CL
27 ns + (0,16 ns/pF) CL
148 ns + (0,55 ns/pF) CL
54 ns + (0,23 ns/pF) CL
37 ns + (0,16 ns/pF) CL
133 ns + (0,55 ns/pF) CL
54 ns + (0,23 ns/pF) CL
37 ns + (0,16 ns/pF) CL
148 ns + (0,55 ns/pF) CL
54 ns + (0,23 ns/pF) CL
42 ns + (0,16 ns/pF) CL
123 ns + (0,55 ns/pF) CL
49 ns + (0,23 ns/pF) CL
37 ns + (0,16 ns/pF) CL
63 ns + (0,55 ns/pF) CL
24 ns + (0,23 ns/pF) CL
17 ns + (0,16 ns/pF) CL
43 ns + (0,55 ns/pF) CL
19 ns + (0,23 ns/pF) CL
17 ns + (0,16 ns/pF) CL
73 ns + (0,55 ns/pF) CL
29 ns + (0,23 ns/pF) CL
22 ns + (0,16 ns/pF) CL
58 ns + (0,55 ns/pF) CL
24 ns + (0,23 ns/pF) CL
17 ns + (0,16 ns/pF) CL
68 ns + (0,55 ns/pF) CL
24 ns + (0,23 ns/pF) CL
17 ns + (0,16 ns/pF) CL
38 ns + (0,55 ns/pF) CL
19 ns + (0,23 ns/pF) CL
12 ns + (0,16 ns/pF) CL
HIGH to LOW
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
260 ns
100 ns
70 ns
LOW to HIGH
10
15
5
CP → TC
350 ns
130 ns
90 ns
HIGH to LOW
10
15
5
320 ns
130 ns
90 ns
LOW to HIGH
10
15
5
CP → TC
350 ns
130 ns
100 ns
300 ns
120 ns
90 ns
HIGH to LOW
10
15
5
LOW to HIGH
10
15
5
CAS → O1
180 ns
70 ns
HIGH to LOW
10
15
5
50 ns
140 ns
60 ns
LOW to HIGH
10
15
5
50 ns
STR → O1, O1
200 ns
80 ns
HIGH to LOW
10
15
5
60 ns
170 ns
70 ns
LOW to HIGH
10
15
5
50 ns
CE →TC
190 ns
70 ns
HIGH to LOW
10
15
5
50 ns
130 ns
60 ns
LOW to HIGH
10
15
40 ns
January 1995
6
Philips Semiconductors
Product specification
HEF4527B
MSI
BCD rate multiplier
VDD
V
TYPICAL EXTRAPOLATION
FORMULA
PARAMETER
SYMBOL
MIN.
TYP. MAX. UNIT
CL → O1
5
10
15
5
145
55
290 ns
110 ns
80 ns
118 ns + (0,55 ns/pF) CL
44 ns + (0,23 ns/pF) CL
32 ns + (0,16 ns/pF) CL
118 ns + (0,55 ns/pF) CL
44 ns + (0,23 ns/pF) CL
32 ns + (0,16 ns/pF) CL
HIGH to LOW
tPHL
40
CL → O1
145
55
290 ns
110 ns
80 ns
LOW to HIGH
10
15
tPLH
40
Propagation delays
PL → O1, O1
5
10
15
5
260
100
70
235
90
50
45
18
12
20
12
10
50
20
15
15
10
5
520 ns
200 ns
140 ns
470 ns
180 ns
100 ns
90 ns
36 ns
24 ns
40 ns
24 ns
20 ns
100 ns
40 ns
30 ns
ns
233 ns + (0,55 ns/pF) CL
89 ns + (0,23 ns/pF) CL
62 ns + (0,16 ns/pF) CL
208 ns + (0,55 ns/pF) CL
79 ns + (0,23 ns/pF) CL
42 ns + (0,16 ns/pF) CL
HIGH to LOW
tPHL
LOW to HIGH
10
15
5
tPLH
Minimum clock
pulse width
10
15
5
tWCPH
tWCLH
tWPLH
tsu
HIGH
Minimum CL
pulse width; HIGH
10
15
5
Minimum PL
pulse width; HIGH
10
15
5
Set-up times
30
20
12
20
16
10
80
36
25
4,5
11
16
CE → CP
10
15
5
ns
ns
Recovery times
10
8
ns
CL → CP
10
15
5
tRCL
ns
5
ns
40
18
10
9
ns
PL → CP
10
15
5
tRPL
ns
ns
Maximum clock
pulse frequency
MHz
10
15
fmax
22
32
MHz
MHz
January 1995
7
Philips Semiconductors
Product specification
HEF4527B
MSI
BCD rate multiplier
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; input transition times ≤ 20 ns
VDD
V
TYPICAL FORMULA FOR P (µW)
2
2
Dynamic power
5
1 050 fi + ∑ (foCL) × VDD
4 500 fi + ∑ (foCL) × VDD
where
dissipation per
package (P)
10
15
fi = input freq. (MHz)
2
10 500 fi + ∑ (foCL) × VDD
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (foCL) = sum of outputs
VDD = supply voltage (V)
January 1995
8
Philips Semiconductors
Product specification
HEF4527B
MSI
BCD rate multiplier
Fig.4 Timing diagram.
9
January 1995
Philips Semiconductors
Product specification
HEF4527B
MSI
BCD rate multiplier
APPLICATION INFORMATION
Add mode
Output rate = 10n (0,1 BCD1 + 0,01 BCD2 + 0,01 BCD3 + ........), in where n = number of cascaded RMs.
Example: RM1 preset to 9 and RM2 preset to 4, output rate is 102 (0,1 × 9 + 0,01 × 4) = 94.
Fig.5 Two HEF4527B cascaded in the add mode.
Multiply mode
Output rate = 10n (0,1 BCD1 × 0,1 BCD2 × 0,1 BCD3 × ........), in where n = number of cascaded RMs.
Example: RM1 preset to 9 and RM2 preset to 4, output rate is 102 (0,1 × 9 × 0,1 × 4) = 36.
Fig.6 Two HEF4527B cascaded in the multiply mode.
January 1995
10
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