HEF4531BT [NXP]
13-input parity checker/generator; 13路输入奇偶校验器/发电机型号: | HEF4531BT |
厂家: | NXP |
描述: | 13-input parity checker/generator |
文件: | 总4页 (文件大小:38K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4531B
MSI
13-input parity checker/generator
January 1995
Product specification
File under Integrated Circuits, IC04
Philips Semiconductors
Product specification
HEF4531B
MSI
13-input parity checker/generator
DESCRIPTION
The HEF4531B is a parity checker/generator with 13 parity
inputs (I0 to I12) and a parity output (O). When the number
of parity inputs that are HIGH is even, the output is LOW.
When the number of parity inputs that are HIGH is odd, the
output is HIGH. For words of 12 bits or less, the output can
be used to generate either odd or even parity by
appropriate termination of the unused parity input(s). For
words of 14 or more bits, the devices can be cascaded by
connecting the output of one device to any parity input of
another device. When cascading devices, it is
recommended that the output of one device be connected
to the I12 input of the other device since there is less delay
to the output from the I12 input than from any other input
(I0 to I11).
Fig.1 Functional diagram.
HEF4531BP(N): 16-lead DIL; plastic
(SOT38-1)
HEF4531BD(F):
HEF4531BT(D):
16-lead DIL; ceramic (cerdip)
(SOT74)
16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
FAMILY DATA, IDD LIMITS category MSI
Fig.2 Pinning diagram.
See Family Specifications
January 1995
2
Philips Semiconductors
Product specification
HEF4531B
MSI
13-input parity checker/generator
Fig.3 Logic diagram.
FUNCTION TABLE
INPUTS
OUTPUT
O
I0
I1
I2
I3
I4
I5
I6
I7
I8
I9
I10
I11
I12
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
any odd number of inputs HIGH
any even number of inputs HIGH
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Notes
1. H = HIGH state (the more positive voltage)
2. L = LOW state (the less positive voltage)
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; input transition times ≤ 20 ns
VDD
V
TYPICAL FORMULA FOR P (µW)
2
Dynamic power
dissipation per
package (P)
5
425 fi + ∑ (foCL) × VDD
where
2
10
15
2 400 fi + ∑ (foCL) × VDD
fi = input freq. (MHz)
2
7 700 fi + ∑ (foCL) × VDD
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (foCL) = sum of outputs
VDD = supply voltage (V)
January 1995
3
Philips Semiconductors
Product specification
HEF4531B
MSI
13-input parity checker/generator
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
TYPICAL EXTRAPOLATION
SYMBOL
TYP. MAX.
FORMULA
Propagation delays
I0 to I11 → O
5
10
15
5
145
60
45
135
55
45
105
45
35
85
35
25
60
30
20
60
30
20
290 ns
120 ns
90 ns
270 ns
110 ns
90 ns
210 ns
90 ns
70 ns
170 ns
70 ns
50 ns
120 ns
60 ns
40 ns
120 ns
60 ns
40 ns
118 ns + (0,55 ns/pF) CL
49 ns + (0,23 ns/pF) CL
37 ns + (0,16 ns/pF) CL
108 ns + (0,55 ns/pF) CL
44 ns + (0,23 ns/pF) CL
37 ns + (0,16 ns/pF) CL
78 ns + (0,55 ns/pF) CL
34 ns + (0,23 ns/pF) CL
27 ns + (0,16 ns/pF) CL
58 ns + (0,55 ns/pF) CL
24 ns + (0,23 ns/pF) CL
17 ns + (0,16 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
HIGH to LOW
tPHL
LOW to HIGH
10
15
5
tPLH
tPHL
tPLH
tTHL
tTLH
I12 → 0
HIGH to LOW
10
15
5
LOW to HIGH
10
15
5
Output transition times
HIGH to LOW
10
15
5
LOW to HIGH
10
15
January 1995
4
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