HEF4534BN [NXP]
Real time 5-decade counter; 实时5十进制计数器
| 型号： | HEF4534BN |
| 厂家： | 
NXP |
| 描述： | Real time 5-decade counter |
| 文件： | 总10页 (文件大小：130K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4534B
LSI
Real time 5-decade counter
January 1995
Product specification
File under Integrated Circuits, IC04
Philips Semiconductors
Product specification
HEF4534B
LSI
Real time 5-decade counter
scanner is triggered by a LOW to HIGH transition on the
scanner clock (CPS) and is reset (select ten thousand
counter) by a HIGH level on the scanner reset (MRsc).
DESCRIPTION
The HEF4534B is a 5-decade ripple counter. The binary
outputs of the decade counters are time-multiplexed by an
internal scanner on four BCD outputs (O0 to O3). The
selected decade is indicated by a logic HIGH on the
appropriate digit select output (OS0: units, 1; OS1: tens,
10; OS2: hundreds, 102; OS3: thousands, 103; OS4: ten
thousands, 104).
The counter can operate in four modes depending on the
state of the mode select inputs (SA, SB). The error detector
will detect an error when a positive edge on CPA is not
accompanied by a negative edge on the error detector
clock CPE or vice versa, within time limits adjusted by
external capacitors connected to Cext 1 and Cext 2. Three or
more detected errors result in a HIGH level on the error
output (OER). The error detector is reset by a HIGH level
on MR.
The binary outputs (O0 to O3) and the select outputs
(OS0 to OS4) are 3-state controlled via enable inputs
EO and EOS respectively, allowing interface with other
bus orientated devices. Cascading may be accomplished
by using the carry out (TC). The counter is triggered by a
LOW to HIGH transition on the decade clock (CPA) and is
reset by a HIGH level on the master reset (MR). The
Schmitt-trigger action in the clock inputs makes the circuit
highly tolerant to slower clock rise and fall times.
Fig.1 Pinning diagram.
PINNING
HEF4534BP(N): 24-lead DIL; plastic (SOT101-1)
O1 to O3
OS0 to OS3
OER
BCD outputs
HEF4534BD(F):
HEF4534BT(D):
24-lead DIL; ceramic (cerdip) (SOT94)
24-lead SO; plastic (SOT137-1)
digit select outputs
error output
( ): Package Designator North America
CPA
decade clock input
scanner clock input
error detector clock input
mode select inputs
master reset input
scanner reset input
carry out
CPS
CPE
SA, SB
MR
MRsc
TC
FAMILY DATA, IDD LIMITS category LSI
See Family Specifications
January 1995
2
Philips Semiconductors
Product specification
HEF4534B
LSI
Real time 5-decade counter
Fig.2 Functional block diagram.
3
January 1995
Philips Semiconductors
Product specification
HEF4534B
LSI
Real time 5-decade counter
MODE CONTROL FUNCTION TABLE
SELECT INPUTS 1ST DECADE CARRY TO 2ND STAGE CARRY TO 4TH STAGE
OUTPUT
MODE
SA
SB
normal count
and display
at 9 to 0 transition
of the 1st decade
at 9 to 0 transition
of the 3rd decade
5-decade
L
L
counter
test purposes:
clock directly into
stages 1, 2 and 4
4-decade counter
with ÷ 10 and round-
off at front end
L
H
H
H
H
L
inhibited
inhibited
input clock
input clock
at 4 to 5 transition
of the 1st decade
at 9 to 0 transition
of the 3rd decade
display counts:
3, 4, 5, 6, 7 = 5
8, 9, 0, 1, 2 = 0
at 7 to 8 transition
of the 1st decade
at 9 to 0 transition
of the 3rd decade
4-decade counter;
1⁄2-pence capability
Fig.3 Error detection timing diagram.
The skew time is the time difference between the LOW to
HIGH transition of CPA and the HIGH to LOW transition of
CPE or vice versa (see Fig.4). The skew time is typically
proportional to the external capacitor (Cext) connected
from Cext1 and Cext2 (pins 1 and 22) to VSS. The error
detector will count an error when a positive edge on the
counter clock CPA is not succeeded by a negative edge on
the error detector clock CPE within a skew time
tSK1 (adjustable by Cext1 at pin 1). The same holds for a
negative edge at CPE succeeded by a positive on CPA
within a skew time tSK2 (adjustable by Cext2 at pin 22). If
error detection is not needed, CPE must be either HIGH or
LOW and no Cext is applied. For further information see
Fig.5.
Fig.4 Skew times
timing diagram;
t
WCPA > tSK1
;
.
t
WCPE > tSK2
January 1995
4
Philips Semiconductors
Product specification
HEF4534B
LSI
Real time 5-decade counter
Note 1: Skew in this area results in counted error.
Note 2: Skew in the area between max. and min. curves may or may not result in counted error.
Note 3: Skew in this area results in no error counted.
Fig.5 Typical clock skew as a function of the supply voltage. This graph is accurate for Cext ≥ 100 pF and
amb = 25 °C.
T
Fig.6 Carry timing diagram.
5
January 1995
Philips Semiconductors
Product specification
HEF4534B
LSI
Real time 5-decade counter
Note: If SB = H, the 1st decade is inhibited and the cycle will be shortened to four stages (see dotted lines).
Fig.7 Scanner timing diagram.
Fig.8 Counter timing diagram.
January 1995
6
Philips Semiconductors
Product specification
HEF4534B
LSI
Real time 5-decade counter
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
TYPICAL EXTRAPOLATION
FORMULA
SYMBOL
MIN.
TYP. MAX.
Propagation delays
CPA → On
D1 selected
5
300
130
95
600 ns
283 ns + (0,55 ns/pF) CL
119 ns + (0,23 ns/pF) CL
87 ns + (0,16 ns/pF) CL
213 ns + (0,55 ns/pF) CL
89 ns + (0,23 ns/pF) CL
67 ns + (0,16 ns/pF) CL
523 ns + (0,55 ns/pF) CL
219 ns + (0,23 ns/pF) CL
162 ns + (0,16 ns/pF) CL
523 ns + (0,55 ns/pF) CL
219 ns + (0,23 ns/pF) CL
162 ns + (0,16 ns/pF) CL
393 ns + (0,55 ns/pF) CL
179 ns + (0,23 ns/pF) CL
132 ns + (0,16 ns/pF) CL
173 ns + (0,55 ns/pF) CL
74 ns + (0,23 ns/pF) CL
52 ns + (0,16 ns/pF) CL
113 ns + (0,55 ns/pF) CL
54 ns + (0,23 ns/pF) CL
42 ns + (0,16 ns/pF) CL
198 ns + (0,55 ns/pF) CL
84 ns + (0,23 ns/pF) CL
62 ns + (0,16 ns/pF) CL
198 ns + (0,55 ns/pF) CL
84 ns + (0,23 ns/pF) CL
62 ns + (0,16 ns/pF) CL
143 ns + (0,55 ns/pF) CL
59 ns + (0,23 ns/pF) CL
42 ns + (0,16 ns/pF) CL
143 ns + (0,55 ns/pF) CL
59 ns + (0,23 ns/pF) CL
42 ns + (0,16 ns/pF) CL
10
15
5
tPHL
tPLH
tPHL
tPLH
tPLH
tPHL
tPHL
tPHL
tPLH
tPHL
tPLH
260 ns
190 ns
480 ns
200 ns
150 ns
HIGH to LOW
240
100
75
LOW to HIGH
10
15
5
CPA → On
550 1100 ns
D5 selected
10
15
5
230
170
460 ns
340 ns
HIGH to LOW
550 1100 ns
LOW to HIGH
10
15
5
230
170
420
190
140
200
85
460 ns
340 ns
840 ns
380 ns
280 ns
400 ns
170 ns
120 ns
280 ns
130 ns
100 ns
450 ns
190 ns
140 ns
450 ns
190 ns
140 ns
340 ns
140 ns
100 ns
340 ns
140 ns
100 ns
CPA → TC
LOW to HIGH
10
15
5
MR → On
HIGH to LOW
10
15
5
60
MR → OER
140
65
HIGH to LOW
10
15
5
50
CPS → On
225
95
HIGH to LOW
10
15
5
70
225
95
LOW to HIGH
10
15
5
70
CPS → OSn
170
70
HIGH to LOW
10
15
5
50
CPS → OSn
170
70
LOW to HIGH
10
15
50
January 1995
7
Philips Semiconductors
Product specification
HEF4534B
LSI
Real time 5-decade counter
VDD
V
TYPICAL EXTRAPOLATION
FORMULA
SYMBOL
MIN.
TYP. MAX.
Output transition times
HIGH to LOW
5
60
30
20
60
30
20
120 ns
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
10
15
5
tTHL
60 ns
40 ns
120 ns
60 ns
40 ns
LOW to HIGH
10
15
tTLH
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
SYMBOL
MIN. TYP. MAX.
3-state propagation delays
Output disable times
EO → On;
5
30
25
20
40
25
20
60
50
40
80
50
40
ns
ns
ns
ns
ns
ns
EOS → OSn
HIGH
10
15
5
tPHZ
LOW
10
15
tPLZ
Output enable times
EO → On;
5
10
15
5
35
20
15
50
25
15
35
20
15
45
30
20
60
30
25
30
20
15
70
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
EOS → OSn
HIGH
tPZH
30
100
50
LOW
10
15
5
tPZL
30
Minimum clock pulse
width; CPA, CPS
HIGH
70
40
30
90
60
40
120
60
50
60
40
30
10
15
5
tWCPH
tWMRH
tRMR
tRMR
Minimum reset pulse
width; MR, MRsc
HIGH
10
15
5
Recovery time
for MR
10
15
5
Recovery time
for MRsc
10
15
January 1995
8
Philips Semiconductors
Product specification
HEF4534B
LSI
Real time 5-decade counter
VDD
V
SYMBOL
MIN. TYP. MAX.
Maximum clock
pulse frequency
CPA and CPS
5
2,5
6
5
12
16
MHz
MHz
MHz
10
15
fmax
8
VDD
V
TYPICAL FORMULA FOR P (µW)
2
Dynamic power
dissipation per
package (P)(1)
5
10
15
1 100 fi + ∑ (foCL) × VDD
where
2
4 800 fi + ∑ (foCL) × VDD
fi = input freq. (MHz)
fo = output freq. (MHz)
CL = load cap. (pF)
2
12 000 fi + ∑ (foCL) × VDD
∑ (foCL) = sum of outputs
V
DD = supply voltage (V)
Note
1. Cext = 0.
January 1995
9
Philips Semiconductors
Product specification
HEF4534B
LSI
Real time 5-decade counter
APPLICATION INFORMATION
Fig.9 Two HEF4534B ICs connected for cascade operation. TC is HIGH for a single clock period when all five
BCD decades go to zero. TC also goes HIGH when MR is applied.
Fig.10 Forcing a decade to the On outputs. When the On outputs of a given decade are required, this
configuration will lock-up the selected decade within four clock cycles. The select line feed back may be
hardwired or switched.
January 1995
10
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