HEF4541BT,112 [NXP]
HEF4541B - Programmable timer SOIC 14-Pin;型号: | HEF4541BT,112 |
厂家: | NXP |
描述: | HEF4541B - Programmable timer SOIC 14-Pin |
文件: | 总17页 (文件大小:636K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
HEF4541B
Programmable timer
Rev. 4 — 25 June 2012
Product data sheet
1. General description
The HEF4541B is a programmable timer which consists of a 16-stage binary counter, an
integrated oscillator to be used with external timing components, an automatic power-on
reset and output control logic. The frequency of the oscillator is determined by the external
components RTC and CTC within the frequency range 1 Hz to 100 kHz. This oscillator may
be replaced by an external clock signal at input RS, the timer advances on the
positive-going transition of RS. A LOW on the auto reset input (AR) and a LOW on the
master reset input (MR) enables the internal power-on reset. A HIGH level at input MR
resets the counter independent on all other inputs. Resetting disables the oscillator to
provide no active power dissipation.
A HIGH at input AR turns off the power-on reset to provide a low quiescent power
dissipation of the timer. The 16-stage counter divides the oscillator frequency by 28, 210,
213 or 216 depending on the state of the address inputs (A0, A1). The divided oscillator
frequency is available at output O. The phase input (PH) features a complementary output
signal. When the mode select input (MODE) is LOW the timer is a single transition timer
and when HIGH the timer is a 2n frequency divider.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
2. Features and benefits
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Operates across the automotive temperature range −40 °C to +85 °C
Complies with JEDEC standard JESD 13-B
3. Ordering information
Table 1.
Ordering information
All types operate from −40 °C to +85 °C.
Type number
Package
Name
Description
Version
HEF4541BP
HEF4541BT
DIP14
SO14
plastic dual in-line package; 14 leads (300 mil)
plastic small outline package; 14 leads; body width 3.9 mm
SOT27-1
SOT108-1
HEF4541B
NXP Semiconductors
Programmable timer
4. Functional diagram
RS
3
CTC
2
RTC
1
A0
12
A1
13
MODE
10
CONTROL INPUTS
CP
8
OUTPUT
STAGE
5
BINARY
COUNTER
O
AR
POWER-ON
RESET
C
D
6
9
MR
PH
001aai581
Fig 1. Functional diagram
CTC
RTC
8
2
COUNTER
RS
8
CP
2
RESET
8
2
COUNTER
CP
RESET 2
2
5
8
2
2
A0
A1
MUX
POWER-ON
RESET
AR
MR
LATCH
MODE
PH
O
001aai583
Fig 2. Logic diagram
HEF4541B
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 25 June 2012
2 of 17
HEF4541B
NXP Semiconductors
Programmable timer
5. Pinning information
5.1 Pinning
HEF4541B
1
2
3
4
5
6
7
14
13
12
11
10
9
RTC
CTC
RS
V
DD
A1
A0
n.c.
AR
n.c.
MODE
PH
MR
V
SS
8
O
001aai582
Fig 3. Pin configuration
5.2 Pin description
Table 2.
Symbol
RTC
CTC
RS
Pin description
Pin
Description
1
external resistor connection
external capacitor connection
2
3
external resistor connection (RS) or external clock input
not connected
nc
4, 11
AR
5
auto reset input (active low)
master reset input
ground (0 V)
MR
6
VSS
7
O
8
timer output
PH
9
phase input
MODE
A0, A1
VDD
10
mode select input
12, 13
14
address inputs
supply voltage
HEF4541B
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 25 June 2012
3 of 17
HEF4541B
NXP Semiconductors
Programmable timer
6. Functional description
Table 3.
Function table[1]
Input
AR
H
MODE
MR
L
PH
X
MODE
X
X
X
H
L
auto reset disabled
auto reset enabled[2]
master reset active
L
L
X
X
H
L
X
X
X
normal operation selected division to output
single-cycle mode[3]
X
L
X
X
L
L
X
X
output initially LOW after reset
output initially HIGH, after reset
X
L
H
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.
[2] For correct power-on reset, the supply voltage should be above 8.5 V. For VDD < 8.5 V, disable the autoreset and connect AR to VDD
.
[3] The timer is initialized on a reset pulse and the output changes state after 2n-1 counts and remains in that state (latched). Reset of this
latch is obtained by master reset or by a LOW to HIGH transition on the MODE input.
Table 4.
Frequency selection table
A0
A1
Number of counter stages n
fOSC
n
--------- = 2
fO
L
L
13
10
8
8192
1024
256
L
H
L
H
H
H
16
65536
7. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDD
IIK
Parameter
Conditions
Min
Max
+18
Unit
V
supply voltage
−0.5
-
input clamping current
input voltage
VI < −0.5 V or VI > VDD + 0.5 V
10
mA
V
VI
−0.5
-
VDD + 0.5
10
IOK
output clamping current
input/output current
storage temperature
ambient temperature
total power dissipation
VO < −0.5 V or VO > VDD + 0.5 V
mA
mA
°C
II/O
O output
-
10
Tstg
Tamb
Ptot
−65
−40
+150
+85
°C
Tamb = −40 °C to +85 °C
DIP14 package
[1]
[2]
-
-
-
750
500
100
mW
mW
mW
SO14 package
P
power dissipation
[1] For DIP14 package: Ptot derates linearly with 12 mW/K above 70 °C.
[2] For SO14 package: Ptot derates linearly with 8 mW/K above 70 °C.
HEF4541B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 25 June 2012
4 of 17
HEF4541B
NXP Semiconductors
Programmable timer
8. Recommended operating conditions
Table 6.
Symbol
VDD
Recommended operating conditions
Parameter
Conditions
Min
Max
15
Unit
V
supply voltage
3
VI
input voltage
0
VDD
+85
3.75
0.5
V
Tamb
ambient temperature
input transition rise and fall rate
in free air
−40
°C
Δt/ΔV
VDD = 5 V
VDD = 10 V
VDD = 15 V
-
-
-
μs/V
μs/V
μs/V
0.08
9. Static characteristics
Table 7.
Static characteristics
VSS = 0 V; VI = VSS or VDD; unless otherwise specified.
Symbol Parameter Conditions VDD
Tamb = −40 °C
Tamb = 25 °C
Tamb = 85 °C Unit
Min
Max
Min
Max
Min
Max
VIH
HIGH-level
input voltage
|IO| < 1 μA
|IO| < 1 μA
|IO| < 1 μA
|IO| < 1 μA
5 V
10 V
15 V
5 V
3.5
-
-
3.5
-
-
3.5
-
-
V
V
V
V
V
V
V
V
V
V
V
V
7.0
7.0
7.0
11.0
-
11.0
-
11.0
-
VIL
LOW-level
input voltage
-
1.5
3.0
4.0
-
-
1.5
3.0
4.0
-
-
1.5
3.0
4.0
-
10 V
15 V
5 V
-
-
-
-
-
-
VOH
VOL
IOH
HIGH-level
output voltage
4.95
4.95
4.95
10 V
15 V
5 V
9.95
-
9.95
-
9.95
-
14.95
-
14.95
-
14.95
-
LOW-level
output voltage
-
-
-
0.05
0.05
0.05
-
-
-
0.05
0.05
0.05
-
-
-
0.05
0.05
0.05
10 V
15 V
HIGH-level
output current
CTC, RTC;
VO = 2.5 V
VO = 4.6 V
VO = 9.5 V
VO = 13.5 V
O;
5 V
5 V
-
-
-
-
−1.4
−0.5
−1.4
−4.8
-
-
-
-
−1.2
−0.4
−1.2
−4.0
-
-
-
-
−0.95 mA
−0.3 mA
−0.95 mA
−3.2 mA
10 V
15 V
VO = 2.5 V
VO = 4.6 V
VO = 9.5 V
VO = 13.5 V
5 V
5 V
-
-
-
-
−1.7
−0.64
−1.6
-
-
-
-
−1.4
−0.5
−1.3
−3.4
-
-
-
-
−1.1 mA
−0.36 mA
−0.9 mA
−2.4 mA
10 V
15 V
−4.2
HEF4541B
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 25 June 2012
5 of 17
HEF4541B
NXP Semiconductors
Programmable timer
Table 7.
Static characteristics …continued
VSS = 0 V; VI = VSS or VDD; unless otherwise specified.
Symbol Parameter
Conditions
VDD
Tamb = −40 °C
Tamb = 25 °C
Tamb = 85 °C Unit
Min
Max
Min
Max
Min
Max
IOL
LOW-level
output current
CTC, RTC;
VO = 0.4 V
VO = 0.5 V
VO = 1.5 V
O;
5 V
10 V
15 V
0.33
1.0
-
-
-
0.27
0.85
2.7
-
-
-
0.20
0.68
2.3
-
-
-
mA
mA
mA
3.2
VO = 0.4 V
VO = 0.5 V
VO = 1.5 V
5 V
10 V
15 V
15 V
0.64
1.6
4.2
-
-
0.5
1.3
3.2
-
-
0.36
0.9
2.4
-
-
-
-
mA
mA
mA
-
-
-
-
II
input leakage
current
0.1
0.1
1.0 μA
IDD
supply current
IO = 0 A
5 V
10 V
15 V
-
-
-
-
-
5
10
20
-
-
-
-
-
5
-
-
-
-
150
300
600
-
μA
μA
μA
pF
10
20
7.5
CI
input capacitance
Table 8.
Reset characteristics
VSS = 0 V; VI = VSS or VDD; see Table 12 for test conditions; unless otherwise specified.
Symbol Parameter
Conditions
VDD
Tamb = −40 °C
Tamb = +25 °C
Tamb = +85 °C Unit
Min
Max
80
Min
Typ
20
Max
Min
Max
IDD
supply current supply current for
power-on reset
5 V
10 V
15 V
-
-
-
-
-
-
80
600
1.3
-
-
-
230 μA
700 μA
1.5 mA
750
1.6
250
0.5
enable;
AR = MR = 0 V; Other
inputs at 0 V or VDD
VDD
supply voltage supply voltage for
automatic reset
-
-
-
8.5
5
-
-
-
V
initialization;
AR = MR = 0 V; Other
inputs at 0 V or VDD
HEF4541B
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 25 June 2012
6 of 17
HEF4541B
NXP Semiconductors
Programmable timer
10. Dynamic characteristics
Table 9.
Dynamic characteristics
VSS = 0 V; Tamb = 25 °C unless otherwise specified. For test circuit, see Figure 5.
Symbol Parameter
tpd propagation delay
Conditions
VDD
5 V
Extrapolation formula
348 ns + (0.55 ns/pF)CL
139 ns + (0.23 ns/pF)CL
102 ns + (0.16 ns/pF)CL
398 ns + (0.55 ns/pF)CL
154 ns + (0.23 ns/pF)CL
112 ns + (0.16 ns/pF)CL
483 ns + (0.55 ns/pF)CL
179 ns + (0.23 ns/pF)CL
127 ns + (0.16 ns/pF)CL
548 ns + (0.55 ns/pF)CL
199 ns + (0.23 ns/pF)CL
142 ns + (0.16 ns/pF)CL
Min
Typ[1] Max
Unit
ns
[2]
RS to O;
28 selected;
see Figure 4
-
375
150
110
425
165
120
510
190
135
575
210
150
30
750
300
220
850
330
240
1020
380
270
1150
420
300
-
10 V
15 V
5 V
-
ns
-
ns
RS to O;
-
ns
2
10 selected;
10 V
15 V
5 V
-
ns
see Figure 4
-
ns
RS to O;
-
ns
2
13 selected;
10 V
15 V
5 V
-
ns
see Figure 4
-
ns
RS to O;
-
ns
2
16 selected;
10 V
15 V
5 V
-
ns
see Figure 4
-
ns
[3]
tW
pulse width
RS LOW;
MR HIGH;
see Figure 4
60
30
24
8
15
18
-
ns
10 V
15 V
5 V
15
-
ns
12
-
ns
fclk(max)
maximum clock
frequency
RS; see Figure 4
16
-
MHz
MHz
MHz
kHz
kHz
kHz
10 V
15 V
5 V
30
-
36
-
fosc
oscillator frequency Rt = 5 kΩ;
Ct = 1 nF;
90
-
10 V
15 V
-
90
-
RS = 10 kΩ;
see Figure 6
-
90
-
Rt = 56 kΩ;
Ct = 1 nF;
RS = 120 kΩ;
see Figure 6
5 V
10 V
15 V
-
-
-
8
8
8
-
-
-
kHz
kHz
kHz
[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).
[2] pd is the same as tPHL and tPLH
t
.
[3] tW is the same as tWL(min) and tWH(min)
.
HEF4541B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 25 June 2012
7 of 17
HEF4541B
NXP Semiconductors
Programmable timer
Table 10. Dynamic power dissipation
PD can be calculated from the formulas shown. VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C.
Symbol
Per package
PD
Parameter
VDD
Typical formula
dynamic power dissipation
5 V
10 V
15 V
PD = 1300 × fi + (fo × CL × VDD2) μW
PD = 5300 × fi + (fo × CL × VDD2) μW
PD = 12000 × fi + (fo × CL × VDD2) μW
Using the on-chip oscillator
PD(Tot) Total dynamic power dissipation
2
5 V
10 V
15 V
PD = 1300 × fosc + foCLVDD2 + 2CTCVDD fosc + 10VDD μW
2
PD = 5300 × fosc + foCLVDD2 + 2CTCVDD fosc + 100VDD μW
PD = 12000 × fosc + foCLVDD2 + 2CTCVDD fosc + 400VDD μW
2
[1] fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VDD = supply voltage in V;
fosc = oscillator frequency in MHz; CTC = timing capacitance in pF.
11. Waveforms
(1)
1/f
clk(max)
V
I
V
M
RS input
V
SS
t
WH(min)
t
t
t
PHL
PLH
WL(min)
V
OH
V
M
O output
V
OL
V
I
MR input
V
SS
t
WH(min)
aaa-003391
VOL and VOH are typical output voltage levels that occur with the output load.
Measurement are points given in Table 11, the test circuit in Figure 5 and the test data in Table 12
(1) 2n pulses as selected by address inputs (A0, A1).
Fig 4. Propagation delay clock (RS) to output (O), clock pulse width and maximum clock frequency
Table 11. Measurement points
Supply voltage
VDD
Input
VM
Output
VM
5 V to 15 V
0.5VDD
0.5VDD
HEF4541B
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 25 June 2012
8 of 17
HEF4541B
NXP Semiconductors
Programmable timer
V
DD
V
V
O
I
G
DUT
C
L
R
T
001aag182
Test data is given in Table 12.
Definitions for test circuit:
DUT - Device Under Test.
RL = Load resistance.
CL = load capacitance.
RT = Termination resistance should be equal to output impedance of Zo of the pulse generator.
Fig 5. Test circuit for measuring switching times
Table 12. Test data
Supply
VDD
Input
Load
CL
VI
tr, tf
5 V to 15 V
VSS or VDD
≤ 20 ns
50 pF
HEF4541B
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 25 June 2012
9 of 17
HEF4541B
NXP Semiconductors
Programmable timer
12. Application information
RC oscillator timing component limitations
The oscillator frequency is mainly determined by RTCCTC, provided RTC << RS and
RSC2 << RTCCTC. The function of RS is to minimize the influence of the forward voltage
across the input protection diodes on the frequency. The stray capacitance C2 should be
kept as small as possible. In consideration of accuracy, CTC must be larger than the
inherent stray capacitance. RTC must be larger than the LOCMOS ‘ON’ resistance in
series with it, which typically is 500 Ω at VDD = 5 V, 300 Ω at VDD = 10 V and 200 Ω at
VDD = 15 V.
The recommended values for these components to maintain agreement with the typical
oscillation formula are: CTC ≥ 100 pF, up to any typical value, 10 kΩ ≤ RTC ≤ 1 MΩ.
reset
clock to
from logic
counter
RS
3
CTC
2
RTC
1
R
C2
C
TC
R
TC
S
001aai584
1
Typical formula for oscillator frequency: fosc
=
.
---------------------------------------
2.3 × RTC × CTC
Fig 6. External component connection for RC oscillator; RS ≈ RTC
001aai586
001aai585
5
4
3
2
5
4
3
2
10
10
f
f
osc
(Hz)
osc
(Hz)
10
10
10
10
10
10
10
10
-4
-3
-2
-1
3
4
5
6
10
10
10
10
10
10
10
10
C
(μF)
R
(Ω)
TC
TC
a. CTC curve at RTC = 56 kΩ; RS = 120 kΩ.
b. RTC curve at CTC = 1 nF; RS = 2 RTC.
Fig 7. RC oscillator frequency as a function of RTC and CTC at VDD = 5 to 15 V; Tamb = 25 °C
HEF4541B
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 25 June 2012
10 of 17
HEF4541B
NXP Semiconductors
Programmable timer
001aai587
001aai588
10
10
∆f
(%)
∆f
(%)
5
5
0
V
= 15 V
DD
V
DD
= 15 V
10 V
0
-5
10 V
5 V
-5
5 V
-10
-10
-75
-75
-25
25
75
125
(°C)
-25
25
75
125
(°C)
T
amb
T
amb
a. RTC = 56 kΩ; CTC = 1 nF; RS = 0 Ω.
b. RTC = 56 kΩ; CTC = 1 nF; RS = 120 kΩ.
Fig 8. Frequency deviation (Δf) as a function of ambient temperature
HEF4541B
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 25 June 2012
11 of 17
HEF4541B
NXP Semiconductors
Programmable timer
13. Package outline
DIP14: plastic dual in-line package; 14 leads (300 mil)
SOT27-1
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
M
H
14
8
pin 1 index
E
1
7
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
Z
A
A
A
2
(1)
(1)
1
UNIT
mm
b
b
c
D
E
e
e
L
M
M
H
w
1
1
E
max.
min.
max.
max.
1.73
1.13
0.53
0.38
0.36
0.23
19.50
18.55
6.48
6.20
3.60
3.05
8.25
7.80
10.0
8.3
4.2
0.51
3.2
2.54
0.1
7.62
0.3
0.254
0.01
2.2
0.068
0.044
0.021
0.015
0.014
0.009
0.77
0.73
0.26
0.24
0.14
0.12
0.32
0.31
0.39
0.33
inches
0.17
0.02
0.13
0.087
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-13
SOT27-1
050G04
MO-001
SC-501-14
Fig 9. Package outline SOT27-1 (DIP14)
HEF4541B
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 25 June 2012
12 of 17
HEF4541B
NXP Semiconductors
Programmable timer
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
7
e
detail X
w
M
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.75
1.27
0.05
1.05
0.25
0.01
0.25
0.1
0.25
0.01
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.024
0.028
0.012
inches
0.041
0.01 0.004
0.069
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT108-1
076E06
MS-012
Fig 10. Package outline SOT108-1 (SO14)
HEF4541B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 25 June 2012
13 of 17
HEF4541B
NXP Semiconductors
Programmable timer
14. Abbreviations
Table 13. Abbreviations
Acronym
CMOS
DUT
Description
Complementary Metal Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
HBM
MM
Machine Model
TTL
Transistor-Transistor Logic
15. Revision history
Table 14. Revision history
Document ID
HEF4541B v.4
Modifications:
Release date
20120625
Data sheet status
Change notice
Supersedes
Product data sheet
-
HEF4541B_CNV v.3
• The format of this data sheet has been redesigned to comply with the new identity guidelines
of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Section 2 “Features and benefits” added.
HEF4541B_CNV v.3
HEF4541B_CNV v.2
19950101
Product specification
-
HEF4541B_CNV v.2
19950101
Product specification
-
-
HEF4541B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 25 June 2012
14 of 17
HEF4541B
NXP Semiconductors
Programmable timer
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use — NXP Semiconductors products are not designed,
16.2 Definitions
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
16.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
HEF4541B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 25 June 2012
15 of 17
HEF4541B
NXP Semiconductors
Programmable timer
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
HEF4541B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 25 June 2012
16 of 17
HEF4541B
NXP Semiconductors
Programmable timer
18. Contents
1
2
3
4
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
6
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Application information. . . . . . . . . . . . . . . . . . 10
RC oscillator timing component limitations. . . .10
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 14
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 14
7
8
9
10
11
12
13
14
15
16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 15
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
16.1
16.2
16.3
16.4
17
18
Contact information. . . . . . . . . . . . . . . . . . . . . 16
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2012.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 25 June 2012
Document identifier: HEF4541B
相关型号:
HEF4543BDF
IC 4000/14000/40000 SERIES, SEVEN SEGMENT DECODER/DRIVER, CONFIGURABLE OUTPUT, CDIP16, SOT-74, CERDIP-16, Decoder/Driver
NXP
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