HEF4724BN [NXP]
8-bit addressable latch; 8位可寻址锁存器
| 型号： | HEF4724BN |
| 厂家： | 
NXP |
| 描述： | 8-bit addressable latch |
| 文件： | 总7页 (文件大小：73K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4724B
MSI
8-bit addressable latch
January 1995
Product specification
File under Integrated Circuits, IC04
Philips Semiconductors
Product specification
HEF4724B
MSI
8-bit addressable latch
selected output (O0 to O7; determined by A0 to A2) follows
D. When E goes HIGH, the contents of the latch are
stored. When operating in the addressable latch mode
(E = CL = LOW), changing more than one bit of A0 to
A2 could impose a transient wrong address. Therefore,
this should only be done while in the memory mode
(E = HIGH, CL = LOW).
DESCRIPTION
The HEF4724B is an 8-bit addressable latch with three
address inputs (A0 to A2), a data input (D), an active LOW
enable input (E), an active HIGH clear input (CL), and eight
parallel latch outputs (O0 to O7).
When E and CL are HIGH, all outputs (O0 to O7) are LOW.
Eight-channel demultiplexing or active HIGH 1-of-8
decoding with output enable operation occurs when CL is
HIGH and E is LOW. When CL and E are LOW, the
Fig.2 Pinning diagram.
HEF4724BP(N):
HEF4724BD(F):
HEF4724BT(D):
16-lead DIL; plastic
(SOT38-1)
16-lead DIL; ceramic (cerdip)
(SOT74)
16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
PINNING
A0 to A2
address inputs
Fig.1 Functional diagram.
A
data input
E
enable input (active LOW)
clear input (active HIGH)
parallel latch outputs
CL
O0 to O7
FAMILY DATA, IDD LIMITS category MSI
See Family Specifications
January 1995
2
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Fig.3 Logic diagram.
Fig.4 Logic diagram (one latch).
Philips Semiconductors
Product specification
HEF4724B
MSI
8-bit addressable latch
MODE SELECTION
E
CL
MODE
L
H
L
L
L
addressable latch
memory
H
H
active HIGH 8-channel demultiplexer
clear
H
FUNCTION TABLE
CL
E
D
A0
A1
A2
O0
O1
O2
O3
O4
O5
O6
O7 MODE
H
H
H
H
H
H
H
H
H
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
X
X
L
X
L
X
L
L
D1
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
clear
D1
D1
D1
D1
D1
D1
D1
D1
X
H
L
L
L
D1
L
L
L
L
L
L
L
H
H
L
L
L
D1
L
L
L
L
L
L
demultiplexer;
unaddressed
latch is
H
L
L
L
L
D1
L
L
L
L
L
H
H
H
H
X
L
L
L
L
D1
L
L
L
L
cleared
H
L
L
L
L
L
L
D1
L
L
L
H
H
X
L
L
L
L
L
L
D1
L
L
H
X
L
L
L
L
L
L
L
D1
On-1 On-1 On-1 On-1 On-1 On-1 On-1 On-1 memory
L
D1
D1
D1
D1
D1
D1
D1
D1
D1
On-1 On-1 On-1 On-1 On-1 On-1 On-1
D1 On-1 On-1 On-1 On-1 On-1 On-1
L
H
L
L
L
On-1
addressable
latch;
unaddressed
latch holds
previous
state
L
H
H
L
L
On-1 On-1
On-1 On-1 On-1
On-1 On-1 On-1 On-1
On-1 On-1 On-1 On-1 On-1
D1
On-1 On-1 On-1 On-1 On-1
L
H
L
L
D1 On-1 On-1 On-1 On-1
L
H
H
H
H
D1
On-1 On-1 On-1
D1 On-1 On-1
L
H
L
L
L
H
H
On-1 On-1 On-1 On-1 On-1 On-1 D1 On-1
On-1 On-1 On-1 On-1 On-1 On-1 On-1 D1
L
H
Notes
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
X = state is immaterial
On-1 = state before the positive transition of E
D1 = either HIGH or LOW
January 1995
4
Philips Semiconductors
Product specification
HEF4724B
MSI
8-bit addressable latch
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; input transition times ≤ 20 ns
VDD
V
TYPICAL FORMULA FOR P (µW)
2
2
2
Dynamic power
5
10
15
700 fi + ∑ (foCL) × VDD
3700 fi + ∑ (foCL) × VDD
10 800 fi + ∑ (foCL) × VDD
where
dissipation per
package (P)
fi = input freq. (MHz)
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (foCL) = sum of outputs
V
DD = supply voltage (V)
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
TYPICAL EXTRAPOLATION
FORMULA
SYMBOL MIN. TYP. MAX.
Propagation delays
E → On
5
10
15
5
115
50
35
95
40
30
95
35
25
85
35
25
110
45
35
95
40
30
85
35
25
230
95
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
88 ns + (0,55 ns/pF) CL
39 ns + (0,23 ns/pF) CL
27 ns + (0,16 ns/pF) CL
68 ns + (0,55 ns/pF) CL
29 ns + (0,23 ns/pF) CL
22 ns + (0,16 ns/pF) CL
68 ns + (0,55 ns/pF) CL
24 ns + (0,23 ns/pF) CL
17 ns + (0,16 ns/pF) CL
58 ns + (0,55 ns/pF) CL
24 ns + (0,23 ns/pF) CL
17 ns + (0,16 ns/pF) CL
83 ns + (0,55 ns/pF) CL
34 ns + (0,23 ns/pF) CL
27 ns + (0,16 ns/pF) CL
68 ns + (0,55 ns/pF) CL
29 ns + (0,23 ns/pF) CL
22 ns + (0,16 ns/pF) CL
58 ns + (0,55 ns/pF) CL
24 ns + (0,23 ns/pF) CL
17 ns + (0,16 ns/pF) CL
HIGH to LOW
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
70
195
80
LOW to HIGH
10
15
5
55
D → On
190
75
HIGH to LOW
10
15
5
55
170
75
LOW to HIGH
10
15
5
55
An → On
225
95
HIGH to LOW
10
15
5
70
190
80
LOW to HIGH
10
15
5
55
CL → On
165
70
HIGH to LOW
10
15
50
January 1995
5
Philips Semiconductors
Product specification
HEF4724B
MSI
8-bit addressable latch
VDD
V
TYPICAL EXTRAPOLATION
FORMULA
SYMBOL MIN. TYP. MAX.
Set-up times
5
10
15
5
40
15
10
40
20
15
20
15
15
50
20
15
75
30
20
70
30
20
20
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
D → E
tsu
0
20
10
5
An → E
10
15
5
tsu
Hold times
0
D → E
10
15
5
thold
thold
tWEL
tWCLH
5
5
see also waveforms
Fig.5
25
10
5
An → E
10
15
5
Minimum E
35
15
10
35
15
10
pulse width; LOW
10
15
5
Minimum CL
pulse width; HIGH
10
15
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
TYPICAL EXTRAPOLATION
FORMULA
SYMBOL MIN. TYP. MAX.
Output transition
times
5
60
30
20
60
30
20
120 ns
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
HIGH to LOW
10
15
5
tTHL
60 ns
40 ns
120 ns
60 ns
40 ns
LOW to HIGH
10
15
tTLH
January 1995
6
Philips Semiconductors
Product specification
HEF4724B
MSI
8-bit addressable latch
(1) The address to enable set-up time is the time before the HIGH to LOW enable transition that the address must be stable so that the
correct latch is addressed and the other latches are not affected.
Fig.5 Waveforms showing minimum E and CL pulse widths, set-up times, hold times. Set-up and hold times are
shown as positive values but may be specified as negative values.
January 1995
7
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