HEF4751VT-T [NXP]

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型号：	HEF4751VT-T
厂家：	NXP
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INTEGRATED CIRCUITS

DATA SHEET

For a complete data sheet, please also download:

• The IC04 LOCMOS HE4000B Logic

Family Specifications HEF, HEC

• The IC04 LOCMOS HE4000B Logic

Package Outlines/Information HEF, HEC

HEF4751V

LSI

Universal divider

January 1995

Product speciﬁcation

File under Integrated Circuits, IC04

Philips Semiconductors

Product speciﬁcation

HEF4751V

LSI

Universal divider

To accommodate fixed or variable frequency offset, two

numbers are applied in parallel, one being subtracted from

the other to produce the internal programme.

DESCRIPTION

The HEF4751V is a universal divider (U.D.) intended for

use in high performance phase lock loop frequency

synthesizer systems. It consists of a chain of counters

operating in a programmable feedback mode.

Programmable feedback signals are generated for up to

three external (fast) ÷ 10/11 prescaler.

The decade selection address is generated by an internal

programme counter which may run continuously or on

demand. Two or more universal dividers can be cascaded,

each extra U.D. (in slave mode) adds two decades to the

system. The combination retains the full programmability

and features of a single U.D. The U.D. provides a fast

output signal FF at output OFF, which can have a phase

jitter of ± 1 system input period, to allow fast frequency

locking. The slow output signal FS at output OFS, which is

jitter-free, is used for fine phase control at a lower speed.

The system comprising one HEF4751V U.D. together with

prescalers is a fully programmable divider with a maximum

configuration of: 5 decimal stages, a programmable mode

M stage (1 ≤ M ≤ 16, non-decimal fraction channel

selection), and a mode H stage (H = 1 or 2, stage for half

channel offset).

Programming is performed in BCD code in a bit-parallel,

digit-serial format.

Fig.1 Pinning diagram.

HEF4751VP(N): 28-lead DIL; plastic (SOT117)

HEF4751VD(F): 28-lead DIL; ceramic (cerdip) (SOT135V)

HEF4751VT(D): 28-lead SO; plastic (SOT136A)

( ): Package Designator North America

SUPPLY VOLTAGE

RATING

RECOMMENDED OPERATING

−0,5 to + 18

4,5 to 12,5 V

FAMILY DATA, I_DDLIMITS category LSI

See Family Specifications

January 1995

Philips Semiconductors

Product speciﬁcation

HEF4751V

LSI

Universal divider

Fig.2 Block diagram.

January 1995

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1 ≤ M ≤ 16; 1 ≤ H ≤ 2; n₅> 0; f_i/f_OFS= {(n₅10⁴+ n₄10³+ n₃10²+ n₂10 + n₁) M + n₀} H + n_h.

Fig.3 The HEF4751V U.D. used in a system with 3 (fast) prescalers.

Philips Semiconductors

Product speciﬁcation

HEF4751V

LSI

Universal divider

Fig.4 Timing diagram showing programme data inputs.

Allocation of data input

Allocation of data input B3 to B0 during fetch period 6

INPUTS

A₃A₂A₁A₀B₃B₂B₁B₀SI

B₃

B₂

C0_bDIVISION RATIO

FETCH

PERIOD

n_0A

n_1A

n_2A

n_3A

n_4A

n_5A

n_0B

n_1B

n_2B

n_3B

n_4B

n_5B

b_in

10/11

B₁

B₀

¹⁄₂CHANNEL CONFIGURATION

H = 1

⁄

C0_b

control

channel

control

H = 2; n_h= 0

H = 2; n_h= 1

test state

Notes

1. H = HIGH state (the more positive voltage)

2. L = LOW state (the less positive voltage)

3. X = state is immaterial

January 1995

Philips Semiconductors

Product speciﬁcation

HEF4751V

LSI

Universal divider

is programmed in fetch period 6 via data A inputs in

PROGRAMME DATA INPUT (see also Figs 3 and 4)

negative logic (except all HIGH is understood as: M = 16).

The counter C0 is a side steppable 10/11 counter

composed of an internal part C0_band an external part C0_a.

C0_bis configured via B₃and B₂to a division ratio of 1 or 2

or 5 or 10/11; C0_amust have the complementary ratio

10/11 or 5/6 or 2/3 or 1 respectively. In the latter case

C0_bcomprises the whole C0 counter with internal

feedback, C0_ais then not required.

The programming process is timed and controlled by input

PC and PE. When the programme enable (PE) input is

HIGH; the positive edges of the programme clock (PC)

signal step through the internal programme counter in a

sequence of 8 states. Seven states define fetch periods,

each indicated by a LOW signal at one of the

corresponding data address outputs (OD₀to OD₆). These

data address signals may be used to address the external

programme source. The data fetched from the programme

source is applied to inputs A₀to A₃and B₀to B₃. When PC

is LOW in a fetch period an internal load pulse is

generated, the data is valid during this time and has to be

stable. When PE is LOW, the programming cyclus is

interrupted on the first positive edge of PC. On the next

negative edge at input PC fetch period 6 is entered. Data

may enter asynchronously in fetch period 6.

The half channel counter C4 is enabled with B₀= HIGH

and disabled with B₀= LOW. With C4 enabled, a half

channel offset can be programmed with input B₁= HIGH,

and no offset with B₁= LOW.

FEEDBACK TO PRESCALERS (see also Figs 5 and 6)

The counters C1, C0, C−1 and C−2 are side-steppable

counters, i.e. its division ratio may be increased by one, by

applying a pulse to a control terminal for the duration of

one division cycle. Counter C2 has 10 states, which are

accessible as timing signals for the rate selectors RS1 to

RS4. A rate selector, programmed with n (n₁to n₄in the

U.D.) generates n of 10 basic timing periods an active

signal. Since n ≤ 9, 1 of 10 periods is always non-active. In

this period RS1 transfers the output of rate selector RS0,

which is timed by counter C3 and programmed with n₀.

Similarly, RS0 transfers RSH output during one period of

C3. Rate selector RSH is timed by C4 and programmed

with n_h. In one of the two states of C4, if enabled, or

always, if C4 is disabled, RSH transfers the LOW active

signal at input RI to RS0. If RI is not used it must be

connected to HIGH. The feedback output signals of RS1,

RS2 and RS3 are externally available as active LOW

signals at outputs OFB₁, OFB₂and OFB₃.

Ten blocks in the U.D. need programme input signals (see

Fig.2). Four of these (C0_b, C3, C4 and RSH) are

concerned with the configuration of the U.D. and are

programmed in fetch period 6. The remaining blocks (RS0

to RS4 and C1) are programmed with number P,

consisting of six internal digits n₀to n₅.

P = (n₅10⁴+ n₄10³+ n₃10²+ n₂10 + n₁) M + n₀

These digits are formed by a substractor from two external

numbers A and B and a borrow-in (b_in).

P = A − B − b_inor if this result is negative;

P = A − B − b_in+ M 10⁵.

The numbers A and B, each consisting of six four bit digits

n_0Ato n_5Aand n_0Bto n_5B, are applied in fetch period 0 to 5

to the inputs A₀to A₃(data A) and B₀to B₃(data B) in

binary coded negative logic.

Output OFB₁is intended for the prescaler at the highest

frequency (if present), OFB₂for the next (if present) and

OFB₃for the lowest frequency prescaler (if present). A

prescaler needs a feedback signal, which is timed on one

of its own division cycles in a basic timing period. The

timing signal at OSY is LOW during the last U.D. input

period of a basic timing period and is suitable for timing of

the feedback for the last external prescaler. The

A = (n_5A10⁴+ n_4A10³+ n_3A10²+ n_2A10 + n_1A) M

+ n_0A.

B = (n_5B10⁴+ n_4B10³+ n_3B10²+ n_2B10 + n_1B) M

+ n_0B.

Borrow-in (b_in) is applied via input SI in fetch period 0

(SI = HIGH: borrow, SI = LOW: no borrow).

Counter C1 is automatically programmed with the most

significant non-zero digit (n_ms) from the internal digits n₅to

n₂of number P. The counter chain C − 2 to C1 (see Fig.3)

is fully programmable by the use of pulse rate feedback.

synchronization signal for a preceding prescaler is the

OR-function of the sync. input and sync. output of the

following prescaler (all sync. signals active LOW).

Rate feedback is generated by the rate selectors RS4 to

RS0 and RSH, which are programmed with digits n₄to

n₀and n_hrespectively. In fetch period 6 the fractional

counter C3, half channel counter C4 and C0_bare

programmed and configured via data B inputs. Counter C3

January 1995

Philips Semiconductors

Product speciﬁcation

HEF4751V

LSI

Universal divider

Fig.5 Block diagram showing feedback to prescalers.

Fig.6 Timing diagram showing signals occurring in Fig.5.

January 1995

Philips Semiconductors

Product speciﬁcation

HEF4751V

LSI

Universal divider

CASCADING OF U.D.s (see also Fig. 8)

OUTPUT (see also Fig.7)

A U.D. is programmed into the ‘slave’ mode by the

programme input data: n_2A= 11, n_2B= 10,

The normal output of the U.D. is the slow output OFS,

which consists of evenly spaced LOW pulses. This output

is intended for accurate phase comparison. If a better

frequency acquisition time is required, the fast output OFF

can be used. The output frequency on OFF is a factor

M H higher than the frequency on OFS. However, phase

jitter of maximum ± 1 system input period occurs at OFF,

since the division ratio of the counters preceding OFF are

varied by slow feedback pulse trains from rate selectors

following OFF.

n_3A= n_4A= n_3B= n_4B= n_5B= 0. A U.D. operating in the

slave mode performs the function of two extra

programmable stages C2’ and C3’ to a ‘master’ (not slave)

mode operating U.D. More slave U.D.s may be used,

every slave adding two lower significant digits to the

system.

Output OFB₃is converted to the borrow output of the

programme data subtractor, which is valid after fetch

period 5. Input SI is the borrow input (both in master and in

slave mode), which has to be valid in fetch period 0. Input

SI has to be connected to output OFB₃of a following slave,

if not present, to LOW. For proper transfer of the borrow

from a lower to a higher significant U.D. subtractor, the

U.D.s have to be programmed sequentially in order of

significance or synchronously if the programme is

repeated at least the number of U.D.s in the system.

Rate input RI and output OFS must be connected to rate

output OFB₁and the input IN of the next slave U.D. The

combination thus formed retains the full programmability

and features of one U.D.

Fig.7 Timing diagram showing output pulses.

January 1995

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Fig.8 Block diagram showing cascading of U.Ds.

Philips Semiconductors

Product speciﬁcation

HEF4751V

LSI

Universal divider

DC CHARACTERISTICS

V_SS= 0 V

T_amb(°C)

+ 25

V_DD

V_OH

V_OL

SYMBOL

−40

+ 85

MIN. MAX.

MIN.

MAX. MIN. MAX.

Output (sink)

current LOW

4,75

0,4

0,5

1,6

1,7

2,9

1,0

3,0

1,4

1,5

2,7

0,85

2,5

1,1

1,2

2,2

0,55

1,7

I_OL

Output (source)

current HIGH

4,6

2,5

9,5

−I_OH

AC CHARACTERISTICS

V_SS= 0 V; T_amb= 25 °C; input transition times ≤ 20 ns

V_DD

PARAMETER

SYMBOL

MIN.

TYP.

135

MAX.

UNIT

Propagation delay

IN → OSY

270 ns

t_PHL

C_L= 10 pF

90 ns

HIGH to LOW

Output transition

times

HIGH to LOW

60 ns

25 ns

90 ns

40 ns

t_THL

C_L= 50 pF

LOW to HIGH

t_TLH

f_max

Maximum input

frequency; IN

Maximum input

frequency; IN

Maximum input

frequency; PC

MHz

δ = 50%

MHz

C0_bratio > 1

δ = 50%

f_max

0,3

1,0

C0_bratio = 1

f_max

0,15

0,5

V_DD

TYPICAL FORMULA FOR P (µW)

Dynamic power

dissipation per

package (P)

where

1 200 f_i+ ∑ (f_oC_L) × V_DD

f_i= input freq. (MHz)

f_o= output freq. (MHz)

5 400 f_i+ ∑ (f_oC_L) × V_DD

C_L= load capacitance (pF)

∑ (f_oC_L) = sum of outputs

V_DD= supply voltage (V)

January 1995

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