HSTL16919DGG-T_技术文档

INTEGRATED CIRCUITS

HSTL16919

9-bit to 18-bit HSTL to LVTTL

memory address latch with

12 kohm pull-up resistor

Product data

2004 Apr 15

Supersedes data of 2001 Jul 19

Philips

Semiconductors

Philips Semiconductors

Product data

9-bit to 18-bit HSTL to LVTTL memory address latch

with 12 kohm pull-up resistor

HSTL16919

FEATURES

PIN CONFIGURATION

• Inputs meet JEDEC HSTL Std. JESD 8–6, and outputs meet

Level III specifications

48

47

46

V

2Q1

1Q1

1

2

3

CC

• 12 kΩ pull-up on D and LE inputs

V

CC

• ESD classification testing is done to JEDEC Standard JESD22.

GND

1Q2

Protection exceeds 2000 V to HBM per method A114.

45 2Q2

44 GND

43 1Q3

D1

D2

4

5

• Latch-up testing is done to JEDEC Standard JESD78, which

exceeds 100 mA.

V

6

7

8

9

CC

• Packaged in 48-pin plastic thin shrink small outline package

42

41

D3

D4

2Q3

(TSSOP48)

V

CC

40 1Q4

39

GND

DESCRIPTION

The HSTL16919 is a 9-bit to 18-bit D-type latch designed for

2Q4

38 GND

1LE 10

3.15 V to 3.45 V V operation. The D inputs accept HSTL levels

GND 11

CC

and the Q outputs provide LVTTL levels.

37

36

V

12

1Q5

2Q5

REF

The HSTL16919 is particularly suitable for driving an address bus to

two banks of memory. Each bank of nine outputs is controlled with

its own latch-enable (LE) input.

GND 13

2LE 14

GND 15

D5 16

35 GND

34 1Q6

33 2Q6

Each of the nine D inputs is tied to the inputs of two D-type latches

that provide true data (Q) at the outputs. While LE is LOW the Q

outputs of the corresponding nine latches follow the D inputs. When

LE is taken HIGH, the Q outputs are latched at the levels set up at

the D inputs.

32

31

30

D6 17

V

CC

D7 18

1Q7

2Q7

The HSTL16919 is characterized for operation from 0 °C to +70 °C.

V

19

CC

29 GND

28 1Q8

D8 20

D9 21

27

26

GND 22

2Q9 23

1Q9 24

2Q8

V

CC

25

V

CC

SW00768

ORDERING INFORMATION

T

amb

= 0 °C to +70 °C

Package

Name

Type number

Description

plastic thin shrink small outline package; 48 leads; body width 6.1 mm

Version

HSTL16919DGG

TSSOP48

SOT362-1

2

2004 Apr 15

Philips Semiconductors

Product data

9-bit to 18-bit HSTL to LVTTL memory address latch

with 12 kohm pull-up resistor

HSTL16919

PIN DESCRIPTION

LOGIC DIAGRAM (positive logic)

SYMBOL

FUNCTION

12

V

REF

CC

4, 5, 7, 8, 16, 17,

18, 20, 21

D[1:9]

1Q[1:9]

2Q[1:9]

Inputs

12 kΩ

2, 46, 43, 40, 37,

34, 31, 28, 24

10

4

1LE

D1

Outputs

12 kΩ

1, 45, 42, 39, 36,

33, 30, 27, 23

1D

C1

10

14

12

1LE

2LE

2

Latch enable

1Q1

12 kΩ

V

REF

Reference voltage

Supply voltage

14

2LE

6, 19, 25, 26, 32,

41, 47, 48

V

CC

1D

C1

1

3, 9, 11, 13, 15,

22, 29, 35, 38, 44

2Q1

GND

Ground

TO EIGHT OTHER CHANNELS

SW00906

FUNCTION TABLE

INPUTS

OUTPUT

LE

L

D

H

L

Q

H

L

1

H

X

Q

0

NOTE:

1. Output level before the indicated steady-state input conditions

were established.

3

2004 Apr 15

Philips Semiconductors

Product data

9-bit to 18-bit HSTL to LVTTL memory address latch

with 12 kohm pull-up resistor

HSTL16919

1

ABSOLUTE MAXIMUM RATINGS

Over operating free-air temperature range (unless otherwise noted).

SYMBOL

PARAMETER

Supply voltage range

CONDITIONS

RATING

–0.5 to +4.6

–0.5 to V +0.5

UNIT

V

CC

2

V

I

Input voltage range

V

CC

2

V

Output voltage range

Input clamp current

Output clamp current

–0.5 to V +0.5

V

O

CC

I

IK

V < 0 V

–50

±50

mA

°C/W

°C

I

3

I

V < 0 V or V > V

O O CC

OK

I

O

Continuous output current

V

O

= 0 V to V

CC

±50

Continuous current through each V or GND

±100

CC

4

θ

Package thermal impedance

89

JA

T

stg

Storage temperature range

–65 to +150

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the

device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to

absolute-maximum-rated conditions for extended periods may affect device reliability.

2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

3. This current flows only when the output is in the HIGH state and V > V

.

O

CC

4. The package thermal impedance is calculated in accordance with JESD 51.

1

RECOMMENDED OPERATING CONDITIONS

LIMITS

Nom

—

SYMBOL

PARAMETER

UNIT

Min

Max

3.45

0.9

V

CC

Supply voltage

Reference voltage

Input voltage

3.15

V

REF

0.68

0.75

—

V

I

0

1.5

V

AC HIGH-level input voltage

AC LOW-level input voltage

DC HIGH-level input voltage

DC LOW-level input voltage

HIGH-level output current

All inputs

V

+ 200 mV

—

V

IH

REF

V

—

V

– 200 mV

—

V

IL

REF

V

IH

+ 100 mV

—

V

REF

V

—

0

—

– 100 mV

–24

V

IL

REF

I

—

mA

°C

OH

I

OL

LOW-level output current

—

24

T

amb

Operating free-air temperature range

—

+70

NOTE:

1. All unused inputs of the device must be held at V or GND to ensure proper device operation.

CC

4

2004 Apr 15

Philips Semiconductors

Product data

9-bit to 18-bit HSTL to LVTTL memory address latch

with 12 kohm pull-up resistor

HSTL16919

ELECTRICAL CHARACTERISTICS

Over recommended operating free-air temperature range (unless otherwise noted).

LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

= 3.15 V; I = –18 mA

UNIT

Max

1

Min

—

Typ

V

IK

V

—

50

2

–1.2

—

V

CC

I

V

OH

HIGH-level output voltage

LOW-level output voltage

Control inputs

V

= 3.15 V; I = –24 mA

2.4

—

CC

OH

V

OL

V

= 3.15 V; I = 24 mA

0.5

–500

90

V

CC

OL

V

= 3.45 V; V = 0 V or 1.5 V

—

µA

mA

pF

CC

I

Data inputs

= 3.45 V; V = 0 V or 1.5 V

—

I

V

REF

V

= 3.45 V; V = 0.68 V or 0.9 V

REF

—

CC

I

Supply current

Control inputs

Data inputs

Outputs

V

= 3.45 V; V = 0 V or 1.5 V

—

100

—

CC

I

V

= 0 V or 3.3 V; V = 0 V or 3.3 V

—

CC

I

C

I

V

= 0 V or 3.3 V; V = 0 V or 3.3 V

—

2.5

4

—

I

C

V

CC

= 0 V; V = 0 V

—

O

NOTE:

1. All typical values are at V = 3.3 V; T

= 25 °C.

CC

amb

TIMING REQUIREMENTS

Over recommended operating free-air temperature range (unless otherwise noted).

V

= 3.3 V ± 0.15 V

CC

SYMBOL

PARAMETER

TEST CONDITIONS

UNIT

Min

3

Max

t

w

Pulse duration

Setup time

Hold time

LE LOW (Figure 1)

D before LE ↑ (Figure 2)

D after LE ↑ (Figure 2)

D after LE ↓

—

0

ns

t

su

2

t

h

1

t

ldr

Data race condition timeĂ

—

NOTE:

1. This is the maximum time after LE switches LOW that the data input can return to the latched state from the opposite state without producing

a glitch on the output.

SWITCHING CHARACTERISTICS

Over recommended operating free-air temperature range; V

= 0.75 V.

REF

V

CC

= 3.3 V ± 0.15 V

FROM

(INPUT)

TO

(OUTPUT)

SYMBOL

PARAMETER

UNIT

Min

1.9

Max

3.4

D

Q

ns

t

pd

Propagation delay (Figure 3)

LE

4.2

SIMULTANEOUS SWITCHING CHARACTERISTICS

Over recommended operating free-air temperature range; V

= 0.75 V

REF

V

CC

= 3.3 V ± 0.15 V

FROM

(INPUT)

TO

(OUTPUT)

SYMBOL

PARAMETER

UNIT

Min

1.9

Max

4.4

D

Q

ns

Propagation delay; all outputs switching

(Figure 3)

t

pd

LE

5.2

5

2004 Apr 15

Philips Semiconductors

Product data

9-bit to 18-bit HSTL to LVTTL memory address latch

with 12 kohm pull-up resistor

HSTL16919

VOLTAGE WAVEFORMS

LOAD CIRCUIT

FROM OUTPUT

UNDER TEST

t

w

1.25 V

0.25 V

C

= 80 pF

L

500 Ω

INPUT

V

REF

(see Note)

SW00770

SW00773

Figure 1. Pulse duration

NOTE: C includes probe and jig capacitance.

L

Figure 4. Load circuit

1.25 V

0.25 V

1.25 V

LE

V

REF

t

su

t

h

DATA INPUT

V

REF

0.25 V

SW00771

Figure 2. Setup and Hold times

1.25 V

0.25 V

INPUT

(Note 1)

V

REF

t

PHL

PLH

V

OH

OUTPUT

1.5 V

OL

SW00772

Figure 3. Propagation delay times

NOTES:

1. All input pulses are supplied by generators having the following

characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 1 ns, t ≤ 1 ns.

O

r

f

2. The outputs are measured one at a time with one transition per

measurement.

3. t

and t are the same as t .

PLH pd

PHL

6

2004 Apr 15

Philips Semiconductors

Product data

9-bit to 18-bit HSTL to LVTTL memory address latch

with 12 kohm pull-up resistor

HSTL16919

TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm

SOT362-1

7

2004 Apr 15

Philips Semiconductors

Product data

9-bit to 18-bit HSTL to LVTTL memory address latch

with 12 kohm pull-up resistor

HSTL16919

REVISION HISTORY

Rev

Date

Description

_2

20040415

Product data (9397 750 13143). Supersedes data of 2001 Jul 19 (9397 750 08587).

Modifications:

• Page 3: Logic diagram (positive logic) modified.

_1

20010719

Product data (9397 750 08587). ECN 853-2269 26745of 19 July 2001.

Data sheet status

Product

status

Definitions

[1]

Level

Data sheet status

[2] [3]

I

Objective data

Development

This data sheet contains data from the objective specification for product development.

Philips Semiconductors reserves the right to change the specification in any manner without notice.

II

Preliminary data

Qualification

Production

This data sheet contains data from the preliminary specification. Supplementary data will be published

at a later date. Philips Semiconductors reserves the right to change the specification without notice, in

order to improve the design and supply the best possible product.

III

Product data

This data sheet contains data from the product specification. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant

changes will be communicated via a Customer Product/Process Change Notification (CPCN).

[1] Please consult the most recently issued data sheet before initiating or completing a design.

[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL

http://www.semiconductors.philips.com.

[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see

the relevant data sheet or data handbook.

Limitingvaluesdefinition— Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting

values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given

in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no

representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be

expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree

to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described

or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated

viaaCustomerProduct/ProcessChangeNotification(CPCN).PhilipsSemiconductorsassumesnoresponsibilityorliabilityfortheuseofanyoftheseproducts,conveys

nolicenseortitleunderanypatent, copyright, ormaskworkrighttotheseproducts, andmakesnorepresentationsorwarrantiesthattheseproductsarefreefrompatent,

copyright, or mask work right infringement, unless otherwise specified.

Koninklijke Philips Electronics N.V. 2004

Contact information

For additional information please visit

http://www.semiconductors.philips.com.

Fax: +31 40 27 24825

Date of release: 04-04

9397 750 13143

For sales offices addresses send e-mail to:

sales.addresses@www.semiconductors.philips.com.

Document order number:

Philips

Semiconductors

8

2004 Apr 15


型号：	HSTL16919DGG-T
厂家：	NXP
描述：	IC 16919 SERIES, LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PDSO48, 6.10 MM, PLASTIC, MO-153, SOT-362-1, TSSOP-48, FF/Latch 光电二极管输出元件逻辑集成电路触发器
文件：	总8页 (文件大小：68K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HSTL16919DGG-T [NXP]

相关型号：

HSTS016L

HSTS016L-10A

HSTS21

HSTS21-50A

HSTTLDM-100

HSTTLDM-1000

HSTTLDM-175

HSTTLDM-200

HSTTLDM-25

HSTTLDM-40

HSTTLDM-45

HSTTLDM-450