I74F50729D [NXP]
Synchronizing dual D-type flip-flop with edge-triggered set and reset with metastable immune characteristics; 同步双D型触发器与边沿触发的集合和与亚稳免疫特性重置
| 型号： | I74F50729D |
| 厂家： | 
NXP |
| 描述： | Synchronizing dual D-type flip-flop with edge-triggered set and reset with metastable immune characteristics |
| 文件： | 总12页 (文件大小：97K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74F50729
Synchronizing dual D-type flip-flop with
edge-triggered set and reset with
metastable immune characteristics
Product specification
IC15 Data Handbook
1990 Sep 14
Philips
Semiconductors
Philips Semiconductors
Product specification
Synchronizing dual D-type flip-flop with edge-triggered
set and reset and metastable immune characteristics
74F50729
FEATURES
PIN CONFIGURATION
• Metastable immune characteristics
• Output skew less than 1.5ns
V
1
14
13
CC
RD0
• High source current (I = 15mA) ideal for clock driver
OH
2
3
4
5
6
7
D0
RD1
applications
12 D1
CP0
• See 74F5074 for synchronizing dual D–type flip–flop
11
10
9
CP1
SD1
Q1
SD0
Q0
• See 74F50109 for synchronizing dual J–K positive
edge–triggered flip–flop
Q0
• See 74F50728 for synchronizing cascaded dual D–type flip–flop
• Industrial temperature range available (–40°C to +85°C)
8
GND
Q1
SF00611
DESCRIPTION
The 74F50729 is a dual positive edge–triggered D–type featuring
individual data, clock, set and reset inputs; also true and
complementary outputs.
TYPICAL SUPPLY
CURRENT (TOTAL)
TYPE
TYPICAL f
MAX
74F50729
120 MHz
19mA
The 74F50729 is designed so that the outputs can never display a
metastable state due to setup and hold time violations. If setup time
and hold time are violated the propagation delays may be extended
beyond the specifications but the outputs will not glitch or display a
metastable state. Typical metastability parameters for the 74F50729
6
are: τ 135ps and τ 9.8 X 10 sec where τ represents a function
of the rate at which a latch in a metastable state resolves that
condition and T represents a function of the measurement of the
o
propensity of a latch to enter a metastable state.
Set (SDn) and reset (RDn) are asynchronous positive–edge
triggered inputs and operate independently of the clock (CPn) input.
Data must be stable just one setup time prior to the low–to–high
transition of the clock for guaranteed propagation delays.
Clock triggering occurs at a voltage level and is not directly related
to the transition time of the positive–going pulse. Following the hold
time interval, data at the Dn input may be changed without affecting
the levels of the output.
ORDERING INFORMATION
ORDER CODE
INDUSTRIAL RANGE
= 5V ±10%,
COMMERCIAL RANGE
DESCRIPTION
PKG DWG #
V
CC
= 5V ±10%,
V
CC
T
amb
= 0°C to +70°C
T
amb
= –40°C to +85°C
14–pin plastic DIP
14–pin plastic SO
N74F50729N
N74F50729D
I74F50729N
SOT27-1
I74F50729D
SOT108-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
74F (U.L.) HIGH/
LOW
LOAD VALUE HIGH/
LOW
PINS
DESCRIPTION
D0, D1
CP0, CP1
Data inputs
1.0/0.417
1.0/1.0
1.0/1.0
1.0/1.0
750/33
20µA/250µA
20µA/20µA
20µA/20µA
20µA/20µA
15mA/20mA
Clock inputs (active rising edge)
Set inputs (active rising edge)
Reset inputs (active rising edge)
Data outputs
SD0, SD1
RD0, RD1
Q0, Q1, Q0, Q1
NOTE: One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
2
1990 Sep 14
853-1390 00420
Philips Semiconductors
Product specification
Synchronizing dual D-type flip-flop with edge-triggered
set and reset and metastable immune characteristics
74F50729
LOGIC SYMBOL
IEC/IEEE SYMBOL
4
3
&
S
3
6
2
12
C1
1D
2
1
D0 D1
3
4
CP0
SD0
RD0
R
S
1
11
CP1
10
11
10
13
9
8
SD1
RD1
C2
Q0 Q0 Q1 Q1
12
13
2D
R
5
6
9
8
V
= Pin 14
CC
GND = Pin 7
SF00612
SF00613
manifestation of the event will be an increased clock–to–Q/Q
propagation delay. This propagation delay is, of course, a function of
the metastability characteristics of the part defined by τ and T
METASTABLE IMMUNE CHARACTERISTICS
Philips Semiconductors uses the term ‘metastable immune’ to
describe characteristics of some of the products in its family.
Specifically the 74F50XXX family presently consist of 4 products
which will not glitch or display metastable immune characteristics.
This term means that the outputs will not glitch or display an output
anomaly under any circumstances including setup and hold time
violations. This claim is easily verified on the 74F5074. By running
two independent signal generators (see Fig. 1) at nearly the same
frequency (in this case 10MHz clock and 10.02 MHz data) the
device–under–test can be often be driven into metastable state. If
the Q output is then used to trigger a digital scope set to infinite
persistence the Q output will build a waveform. An experiment was
run by continuously operating the devices in the region where
metastability will occur.
0.
The metastability characteristics of the 74F5074 and related part
types represent state–of–the–art TTL technology.
After determining the T and t of the flop, calculating the mean time
0
between failures (MTBF) is simple. Suppose a designer wants to
use the 74F50729 for synchronizing asynchronous data that is
arriving at 10MHz (as measured by a frequency counter), has a
clock frequency of 50MHz, and has decided that he would like to
sample the output of the 74F50729 10 nanoseconds after the clock
edge. He simply plugs his number into the equation below:
(t’/t)
MTBF = e / T f f
o C I
In this formula, f is the frequency of the clock, f is the average
C
I
When the device–under–test is a 74F74 (which was not designed
with metastable immune characteristics) the waveform will appear
as in Fig. 2.
input event frequency, and t’ is the time after the clock pulse that the
output is sampled (t’ < h, h being the normal propagation delay). In
this situation the f will be twice the data frequency of 20 MHz
I
because input events consist of both of low and high transitions.
Figure 2 shows clearly that the Q output can vary in time with
respect to the Q trigger point. This also implies that the Q or Q
output waveshapes may be distorted. This can be verified on an
analog scope with a charge plate CRT. Perhaps of even greater
interest are the dots running along the 3.5V volt line in the upper
right hand quadrant. These show that the Q output did not change
state even though the Q output glitched to at least 1.5 volt, the
trigger point of the scope.
15
2
Multiplying f by f gives an answer of 10 Hz . From Fig. 3. it is
I
C
10
clear that the MTBF is greater than 10 seconds. Using the above
formula the actual MTBF is 1.51 X 10 seconds or about 480 years.
10
TRIGGER
DIGITAL
SIGNAL GENERATOR
SIGNAL GENERATOR
D
Q
Q
SCOPE
When the device–under–test is a metastable immune part, such as
the 74F5074, the waveform will appear as in Fig. 3. The 74F5074 Q
output will appear as in Fig. 3. The 74F5074 Q output will not vary
with respect to the Q trigger point even when the a part is driven into
a metastable state. Any tendency towards internal metastability is
resolved by Philips Semiconductors patented circuitry. If a
CP
INPUT
SF00586
Figure 1. Test Setup
metastable event occurs within the flop the only outward
3
1990 Sep 14
Philips Semiconductors
Product specification
Synchronizing dual D-type flip-flop with edge-triggered
set and reset and metastable immune characteristics
74F50729
COMPARISON OF METASTABLE IMMUNE AND NON–IMMUNE CHARACTERISTICS
4
3
2
1
0
Time base = 2.00ns/div Trigger level = 1.5 Volts Trigger slope = positive
SF00587
Figure 2. 74F74 Q output triggered by Q output, setup and hold times violated
3
2
1
0
Time base = 2.00ns/div Trigger level = 1.5 Volts Trigger slope = positive
SF00588
Figure 3. 74F74 Q output triggered by Q output, setup and hold times violated
4
1990 Sep 14
Philips Semiconductors
Product specification
Synchronizing dual D-type flip-flop with edge-triggered
set and reset and metastable immune characteristics
74F50729
MEAN TIME BETWEEN FAILURES (MTBF) VERSUS t’
6
8
10
12
10
10
10
10
14
15
10
12
11
10
9
10
10
10
10
10
10
10
10 = f f
C I
10,000 years
100 years
MTBF in seconds
8
one year
7
6
one week
7
8
9
10
t’ in nanoseconds
SF00589
6
NOTE: V = 5V, T
= 25°C, τ =135ps, To = 9.8 X 10 sec
CC
amb
Figure 4.
TYPICAL VALUES FOR τ AND T AT VARIOUS V S AND TEMPERATURES
0
CC
T
amb
= 0°C
T
amb
= 25°C
T = 70°C
amb
V
CC
τ
T
0
τ
T
0
τ
T
0
9
6
5
5.5V
5.0V
4.5V
125ps
115ps
115ps
1.0 X 10 sec
138ps
135ps
132ps
5.4 X 10 sec
160ps
167ps
175ps
1.7 X 10 sec
10
6
4
1.3 X 10 sec
9.8 X 10 sec
3.9 X 10 sec
13
8
4
3.4 X 10 sec
5.1 X 10 sec
7.3 X 10 sec
FUNCTION TABLE
LOGIC DIAGRAM
INPUTS
OUTPUTS
OPERATING
4, 10
SD
SD RD CP
D
X
X
h
l
Q
H
Q
MODE
↑
↑
↑
↑
↑
↑
X
X
↑
L
H
Asynchronous set
5, 9
6, 8
1, 13
RD
↑
L
Asynchronous reset
Load ”1”
Q
Q
↑
H
L
↑
↑
L
H
Load ”0”
3, 11
CP
↑
↑
X
NC
NC
Hold
NOTES:
2, 12
D
1. H
2. h
=
=
High–voltage level
High–voltagelevel one setup time prior to low–to–high clock
V
= Pin 14
CC
transition
GND = Pin 7
SF00614
3. L
4. l
=
=
Low–voltage level
Low–voltage level one setup time prior to low–to–high clock
transition
5. NC= No change from the previous setup
6. X
7. ↑
8. ↑
=
=
=
Don’t care
Low–to–high clock transition
Not low–to–high clock transition
5
1990 Sep 14
Philips Semiconductors
Product specification
Synchronizing dual D-type flip-flop with edge-triggered
set and reset and metastable immune characteristics
74F50729
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free air temperature range.)
SYMBOL
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
UNIT
V
V
CC
V
IH
Supply voltage
Input voltage
Input current
V
I
IN
mA
V
I
Voltage applied to output in high output state
Current applied to output in low output state
Operating free air temperature range
–0.5 to V
V
OUT
CC
40
mA
°C
°C
°C
OUT
T
amb
Commercial range
Industrial range
0 to +70
–40 to +85
–65 to +150
T
stg
Storage temperature range
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
MIN
4.5
NOM
MAX
UNIT
V
V
Supply voltage
5.0
5.5
CC
IH
IL
V
V
High–level input voltage
Low–level input voltage
Input clamp current
2.0
V
0.8
–18
–12
–15
20
V
I
I
mA
mA
mA
mA
Ik
High–level output current
V
± 10%
± 5%
OH
CC
V
CC
I
OL
Low–level output current
T
amb
Operating free air temperature range
Commercial range
Industrial range
0
+70
°C
°C
–40
+85
6
1990 Sep 14
Philips Semiconductors
Product specification
Synchronizing dual D-type flip-flop with edge-triggered
set and reset and metastable immune characteristics
74F50729
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST
LIMITS
UNIT
1
2
CONDITIONS
MIN
2.5
TY.
MAX
V
OH
High-level output voltage
V
V
= MIN, V = MIN
I
= MAX
V
V
±10%V
±5%V
CC
IH
OH
CC
= MAX,
2.7
3.4
IL
CC
CC
I
=
OH
2.0
V
±5%V
–15mA
= MAX
OL
V
CC
= MIN, V =
IL
V
OL
Low-level output voltage
I
0.30
0.30
0.50
0.50
V
V
±10%V
±5%V
CC
MAX,
V
IH
= MIN
CC
V
Input clamp voltage
V
V
V
V
= MIN, I = I
IK
-0.73 -1.2
100
V
IK
CC
I
I
I
I
Input current at maximum input voltage
High–level input current
= MAX, V = 7.0V
µA
µA
µA
µA
mA
mA
I
CC
I
= MAX, V = 2.7V
20
IH
IL
CC
CC
I
Low–level input current
Dn
= MAX, V = 0.5V
-250
I
CPn, SDn, RDn
–20
3
I
I
Short–circuit output current
V
V
= MAX, V = 2.25V
-60
-150
OS
CC
O
4
Supply current (total)
= MAX
19
27
CC
CC
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type
and function table for operating mode.
2. All typical values are at V = 5V, T
3. Not more than one output should be shorted at a time. For testing I , the use of high-speed test apparatus and/or sample-and-hold
= 25°C.
CC
amb
OS
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I tests should be performed last.
OS
4. Measure I with the clock input grounded and all outputs open, then with Q and Q outputs high in turn.
CC
AC ELECTRICAL CHARACTERISTICS
LIMITS
T
= +25°C
T
= 0°C to
+70°C
= +5.0V ± 10%
T
amb
= –40°C to +85°C
V = +5.0V ± 10%
CC
amb
amb
V
SYMBOL
PARAMETER
TEST
V
= +5.0V
UNIT
CC
CC
CONDITION
C = 50pF,
L
C = 50pF,
L
C = 50pF,
L
R = 500Ω
L
R = 500Ω
L
R = 500Ω
L
MIN
TYP MAX
MIN
MAX
MIN
MAX
f
Maximum clock frequency
Waveform 1
Waveform 1
105
120
85
75
ns
ns
max
t
t
Propagation delay
CPn to Qn or Qn
2.0
2.0
3.9
3.9
6.0
6.0
1.5
2.0
6.5
6.5
1.5
2.0
7.0
6.5
PLH
PHL
t
t
Propagation delay
SDn RDn to Qn or Qn
2.0
3.0
4.0
5.0
6.5
7.5
1.5
2.0
7.5
8.0
1.5
2.0
7.5
8.0
PLH
PHL
Waveform 2
Waveform 4
ns
ns
1, 2
t
Output skew
1.5
1.5
1.5
ok(o)
NOTES:
1. | t
actual –t
actual | for any one output compared to any other output where N and M are either LH or HL.
PLH
PHL
2. Skew lines are valid only under same conditions (temperature, V , loading, etc.,).
CC
7
1990 Sep 14
Philips Semiconductors
Product specification
Synchronizing dual D-type flip-flop with edge-triggered
set and reset and metastable immune characteristics
74F50729
AC SETUP REQUIREMENTS
LIMITS
T
= +25°C
T
= 0°C to +70°C
= +5.0V ± 10%
T
= –40°C to +85°C
amb
amb
amb
V
SYMBOL
PARAMETER
TEST
V
= +5.0V
V
= +5.0V ± 10%
UNIT
CC
CC
CC
CONDITION
C = 50pF,
R = 500Ω
L
C = 50pF,
R = 500Ω
L
C = 50pF,
R = 500Ω
L
L
L
L
MIN
TYP MAX
MIN
MAX
MIN
MAX
t
t
(H)
(L)
Setup time, high or low
Dn to CPn
1.5
1.5
2.0
2.0
2.0
2.0
su
su
Waveform 1
Waveform 1
ns
ns
t (H)
Hold time, high or low
Dn to CPn
1.0
1.0
1.5
1.5
1.5
1.5
h
t (L)
h
t
t
(H)
(L)
CPn pulse width,
high or low
3.0
4.0
3.5
6.0
3.5
6.0
w
w
Waveform 2
Waveform 3
Waveform 3
ns
ns
ns
t
w
(L)
SDn, RDn pulse width, low
3.5
6.0
4.0
6.5
4.0
6.5
t
Recovery time
SDn, RDn to CPn
rec
t
Recovery time
SDn to RDn or RDn to SDn
rec
Waveform 3
6.0
1.0
1.0
ns
AC WAVEFORMS
For all waveforms, V = 1.5V.
M
The shaded areas indicate when the input is permitted to change for predictable output performance.
t
(L)
Dn
w
V
t
V
V
V
M
M
M
M
SDn
RDn
V
V
M
M
t
(H)
t (H)
h
(L)
t (L)
h
su
su
1/f
M
max
t
(L)
w
V
V
t
(L)
M
M
CPn
Qn
w
V
V
M
V
M
t
(H)
w
t
t
PHL
PLH
t
PHL
t
PLH
Qn
Qn
V
V
V
M
M
M
V
V
M
M
M
t
t
PLH
PHL
t
t
PHL
PLH
V
M
V
M
V
Qn
SF00050
SF00049
Waveform 2. Propagation delay for set and reset to output,
set and reset pulse width
Waveform 1. Propagation delay for data to output, data setup
time and hold times, and clock width, and
maximum clock frequency
V
Qn, Qn
M
t
sk(o)
SDn or RDn
V
M
t
Qn, Qn
rec
V
M
V
CPn
M
SF00590
Waveform 4. Output skew
SF00603
Waveform 3. Recovery time for set or reset to output
8
1990 Sep 14
Philips Semiconductors
Product specification
Synchronizing dual D-type flip-flop with edge-triggered
set and reset and metastable immune characteristics
74F50729
TEST CIRCUIT AND WAVEFORMS
t
w
AMP (V)
90%
V
CC
90%
NEGATIVE
V
V
M
M
PULSE
10%
10%
V
V
OUT
IN
0V
PULSE
GENERATOR
D.U.T.
t
t )
t
t )
THL ( f
TLH ( r
R
C
R
L
t
t )
T
L
t
t )
TLH ( r
THL ( f
AMP (V)
90%
M
90%
POSITIVE
PULSE
V
V
M
10%
10%
0V
Test Circuit for Totem-Pole Outputs
DEFINITIONS:
t
w
Input Pulse Definition
INPUT PULSE REQUIREMENTS
R
L
C
L
R
T
=
=
=
Load resistor;
see AC ELECTRICAL CHARACTERISTICS for value.
Load capacitance includes jig and probe capacitance;
see AC ELECTRICAL CHARACTERISTICS for value.
Termination resistance should be equal to Z
pulse generators.
family
V
rep. rate
t
t
t
amplitude
3.0V
M
w
TLH
THL
of
OUT
2.5ns 2.5ns
74F
1.5V
1MHz
500ns
SF00006
9
1990 Sep 14
Philips Semiconductors
Product specification
Synchronizing dual D-type flip-flop with edge-triggered
set and reset and metastable immune characteristics
74F50729
DIP14: plastic dual in-line package; 14 leads (300 mil)
SOT27-1
10
1990 Sep 14
Philips Semiconductors
Product specification
Synchronizing dual D-type flip-flop with edge-triggered
set and reset and metastable immune characteristics
74F50729
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
11
1990 Sep 14
Philips Semiconductors
Product specification
Synchronizing dual D-type flip-flop with edge-triggered
set and reset and metastable immune characteristics
74F50729
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Date of release: 10-98
9397-750-05216
Document order number:
Philips
Semiconductors
相关型号：
I74F50729N
Synchronizing dual D-type flip-flop with edge-triggered set and reset with metastable immune characteristics
NXP
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