IP4064CX8LF [NXP]
Integrated SIM card passive filter array with ESD protection to IEC61000-4-2, level 4; 集成的SIM卡无源滤波器阵列ESD保护IEC61000-4-2 4级
| 型号： | IP4064CX8LF |
| 厂家： | 
NXP |
| 描述： | Integrated SIM card passive filter array with ESD protection to IEC61000-4-2, level 4 |
| 文件： | 总13页 (文件大小：85K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IP4064CX8/LF; IP4364CX8/LF
Integrated SIM card passive filter array with ESD protection to
IEC61000-4-2, level 4
Rev. 01 — 12 November 2007
Product data sheet
1. Product profile
1.1 General description
The IP4064CX8/LF and IP4364CX8/LF are 3-channel RC low-pass filter arrays which are
designed to provide filtering of undesired RF signals in the 800 MHz to 3000 MHz
frequency band. In addition, the IP4064CX8/LF and IP4364CX8/LF incorporate diodes to
provide protection to downstream components against Electrostatic Discharge (ESD)
voltages as high as ±15 kV contact and > ±15 kV air discharge, far exceeding
IEC61000-4-2, level 4. The IP4064CX8/LF and IP4364CX8/LF are fabricated using
monolithic silicon technology and integrate three resistors and seven high-level
ESD-protection diodes in a single wafer level chip-scale package. These features make
the IP4064CX8/LF and IP4364CX8/LF ideal for use in applications requiring component
miniaturization, such as mobile phone handsets, cordless telephones and personal digital
devices.
1.2 Features
I Pb-free and RoHS compliant
I 3-channel SIM card interface integrated RC-filter array
I 100 Ω/100 Ω/47 Ω series channel resistors integrated
I Downstream ESD protection up to ±15 kV (contact) exceeding IEC61000-4-2, level 4
I Wafer level chip-scale package with 0.4 mm (IP4364CX8/LF) and 0.5 mm
(IP4064CX8/LF) pitch
1.3 Applications
I SIM interfaces in e.g. cellular and PCS mobile handsets
IP4064CX8/LF; IP4364CX8/LF
NXP Semiconductors
Integrated SIM card passive filter array with ESD protection
2. Pinning information
2.1 Pinning
bump A1
index area
bump A1
index area
IP4064CX8/LF
IP4364CX8/LF
1
2
3
1
2
3
A
B
A
B
C
C
001aag227
001aag228
Transparent top view
Transparent top view
Fig 1. Pin configuration IP4064CX8/LF
Fig 2. Pin configuration IP4364CX8/LF
2.2 Pin description
Table 1.
Pin description
Pin
A2
A3
B1
B2
B3
C1
C2
C3
Description
external pin 1
internal pin 1
external pin 2
ground
internal pin 2
external pin 3
supply ESD protection
internal pin 3
3. Ordering information
Table 2.
Ordering information
Type number
Package
Name
Description
Version
IP4064CX8/LF
IP4364CX8/LF
WLCSP8
WLCSP8
wafer level chip-size package; 8 bumps; 1.41 × 1.41 × 0.7 mm
wafer level chip-size package; 8 bumps; 1.16 × 1.16 × 0.66 mm
IP4064CX8/LF
IP4364CX8/LF
IP4064CX8LF_IP4364CX8LF_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 12 November 2007
2 of 13
IP4064CX8/LF; IP4364CX8/LF
NXP Semiconductors
Integrated SIM card passive filter array with ESD protection
4. Functional diagram
C2
R1
A3
B3
C3
A2
B1
C1
100 Ω
R2
47 Ω
R3
100 Ω
IEC61000-4-2
level 1
IEC61000-4-2
level 4
protection pins
protection pins
B2
001aag217
Fig 3. Schematic diagram IP4064CX8/LF and IP4364CX8/LF
5. Limiting values
Table 3.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VI
Parameter
Conditions
Min
Max Unit
input voltage
−0.5 +5.5
V
VESD
electrostatic discharge
pins A2, B1, C1, C2 to B2
contact discharge
air discharge
[1]
[1]
−15
−15
+15
+15
kV
kV
IEC 61000-4-2, Level 4,
pins A2, B1, C1, C2 to B2
contact discharge
air discharge
−8
+8
kV
kV
−15
+15
IEC 61000-4-2, Level 1, all
other pins to B2
contact discharge and air
discharge
−2
+2
kV
Pch
channel power dissipation
continuous power;
-
60
mW
T
amb = 70 °C
Ptot
Tstg
total power dissipation
storage temperature
Tamb = 70 °C
-
180
mW
−55
-
+150 °C
Treflow(peak) peak reflow temperature
Tamb ambient temperature
10 s maximum
260
+85
°C
°C
−30
[1] Device is tested with 1000 pulses of ±15 kV contact discharges each, according the IEC61000-4-2 model
and so exceeds the specified level 4 (8 kV contact discharge) by far.
IP4064CX8LF_IP4364CX8LF_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 12 November 2007
3 of 13
IP4064CX8/LF; IP4364CX8/LF
NXP Semiconductors
Integrated SIM card passive filter array with ESD protection
6. Characteristics
Table 4.
Characteristics
Tamb = 25 °C unless otherwise specified.
Symbol Parameter Conditions
Rs(ch) channel series resistance R1, R3
Min
Typ
Max Unit
75
100
125
58.8
20
Ω
R2
35.2 47
Ω
Cch
channel capacitance
including diode
capacitance; VI = 0 V;
f = 1 MHz
-
-
pF
VBR
ILR
breakdown voltage
Itest = 1 mA
VI = 3 V
6
-
-
-
10
50
V
reverse leakage current
nA
IP4064CX8LF_IP4364CX8LF_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 12 November 2007
4 of 13
IP4064CX8/LF; IP4364CX8/LF
NXP Semiconductors
Integrated SIM card passive filter array with ESD protection
7. Application information
7.1 Insertion loss
The IP4064CX8/LF and IP4364CX8/LF is mainly designed as an EMI/RFI filter for SIM
card interfaces. The insertion loss in a 50 Ω system for all three channels of the
IP4364CX8/LF is shown in Figure 5 as an example. The insertion loss of IP4064CX8/LF is
identical. The insertion loss of the three channels was measured with a test PCB utilizing
laser drilled micro-via holes that connect the PCB ground plane to the ground pins.
IN
OUT
DUT
50 Ω
50 Ω
TEST BOARD
V
gen
001aag218
Fig 4. Frequency response set-up
001aag219
0
s
21
(dB)
(1)
−10
−20
−30
−40
(2)
(3)
−1
2
3
4
10
1
10
10
10
10
f (MHz)
(1) Pin B1 to B3.
(2) Pin A2 to A3.
(3) Pin C1 to C3.
Fig 5. Typical IP4064CX8/LF and IP4364CX8/LF frequency response curves
IP4064CX8LF_IP4364CX8LF_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 12 November 2007
5 of 13
IP4064CX8/LF; IP4364CX8/LF
NXP Semiconductors
Integrated SIM card passive filter array with ESD protection
7.2 Crosstalk
The set-up for crosstalk measurements in a 50 Ω system from one channel to another is
shown in Figure 6. Four typical examples of crosstalk measurement results are depicted
in Figure 7. Channels not shown there behave similar. Unused channels are terminated
with 50 Ω to ground.
IN_1
IN_2
OUT_2
OUT_1
DUT
50 Ω
50 Ω
TEST BOARD
50 Ω
50 Ω
V
gen
001aag220
Fig 6. Crosstalk measurement configuration
001aag221
0
s
21
(dB)
−20
(1)
(2)
(3)
(4)
−40
−60
−80
−100
2
3
4
1
10
10
10
10
f (MHz)
(1) Pin C1 to B3.
(2) Pin B1 to C3.
(3) Pin B1 to A3.
(4) Pin A2 to C3.
Fig 7. Typical IP4064CX8/LF and IP4364CX8/LF crosstalk behavior
IP4064CX8LF_IP4364CX8LF_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 12 November 2007
6 of 13
IP4064CX8/LF; IP4364CX8/LF
NXP Semiconductors
Integrated SIM card passive filter array with ESD protection
8. Package outline
WLCSP8: wafer level chip-size package; 8 bumps; 1.41 x 1.41 x 0.7 mm
IP4064CX8/LF
D
B
A
bump A1
index area
A
2
E
A
A
1
detail X
e
1
C
b
y
e
M
v
C A
B
C
e
e
2
B
A
1
2
3
X
0
0.25
scale
0.5 mm
DIMENSIONS (mm are the original dimensions)
A
UNIT
A
1
A
2
b
D
E
e
e
e
2
v
y
1
max
0.26 0.44 0.37 1.46 1.46
0.22 0.38 1.36 1.36
mm
0.7
0.5
1
1
0.005 0.02
0.27
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
07-05-09
07-05-25
IP4064CX8/LF
Fig 8. Package outline IP4064CX8/LF (WLCSP8)
IP4064CX8LF_IP4364CX8LF_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 12 November 2007
7 of 13
IP4064CX8/LF; IP4364CX8/LF
NXP Semiconductors
Integrated SIM card passive filter array with ESD protection
WLCSP8: wafer level chip-size package; 8 bumps; 1.16 x 1.16 x 0.66 mm
IP4364CX8/LF
D
B
A
bump A1
index area
A
2
E
A
A
1
detail X
e
1
C
b
y
e
M
v
C A
B
C
e
e
2
B
A
1
2
3
X
0
0.25
scale
0.5 mm
DIMENSIONS (mm are the original dimensions)
A
UNIT
A
1
A
2
b
D
E
e
e
e
2
v
y
1
max
0.22 0.44 0.31 1.21 1.21
0.18 0.38 1.11 1.11
mm
0.66
0.4
0.8
0.8 0.005 0.02
0.21
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
JEITA
07-05-09
07-05-25
IP4364CX8/LF
Fig 9. Package outline IP4364CX8/LF (WLCSP8)
IP4064CX8LF_IP4364CX8LF_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 12 November 2007
8 of 13
IP4064CX8/LF; IP4364CX8/LF
NXP Semiconductors
Integrated SIM card passive filter array with ESD protection
9. Soldering
9.1 Introduction to soldering WLCSP packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering WLCSP (Wafer Level Chip-Size Packages) can be found in application note
AN10439 “Wafer Level Chip Scale Package” and in application note AN10365 “Surface
mount reflow soldering description”.
Wave soldering is not suitable for this package.
All NXP WLCSP packages are lead-free.
9.2 Board mounting
Board mounting of a WLCSP requires several steps:
1. Solder paste printing on the PCB
2. Component placement with a pick and place machine
3. The reflow soldering itself
9.3 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 10) than a PbSn process, thus
reducing the process window
• Solder paste printing issues, such as smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature), and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic) while being low enough that the packages and/or boards are not
damaged. The peak temperature of the package depends on package thickness and
volume and is classified in accordance with Table 5
Table 5.
Lead-free process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
260
350 to 2000
260
> 2000
260
< 1.6
1.6 to 2.5
> 2.5
260
250
245
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 10.
IP4064CX8LF_IP4364CX8LF_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 12 November 2007
9 of 13
IP4064CX8/LF; IP4364CX8/LF
NXP Semiconductors
Integrated SIM card passive filter array with ESD protection
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 10. Temperature profiles for large and small components
For further information on temperature profiles, refer to application note AN10365
“Surface mount reflow soldering description”.
9.3.1 Stand off
The stand off between the substrate and the chip is determined by:
• The amount of printed solder on the substrate
• The size of the solder land on the substrate
• The bump height on the chip
The higher the stand off, the better the stresses are released due to TEC (Thermal
Expansion Coefficient) differences between substrate and chip.
9.3.2 Quality of solder joint
A flip-chip joint is considered to be a good joint when the entire solder land has been
wetted by the solder from the bump. The surface of the joint should be smooth and the
shape symmetrical. The soldered joints on a chip should be uniform. Voids in the bumps
after reflow can occur during the reflow process in bumps with high ratio of bump diameter
to bump height, i.e. low bumps with large diameter. No failures have been found to be
related to these voids. Solder joint inspection after reflow can be done with X-ray to
monitor defects such as bridging, open circuits and voids.
9.3.3 Rework
In general, rework is not recommended. By rework we mean the process of removing the
chip from the substrate and replacing it with a new chip. If a chip is removed from the
substrate, most solder balls of the chip will be damaged. In that case it is recommended
not to re-use the chip again.
IP4064CX8LF_IP4364CX8LF_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 12 November 2007
10 of 13
IP4064CX8/LF; IP4364CX8/LF
NXP Semiconductors
Integrated SIM card passive filter array with ESD protection
Device removal can be done when the substrate is heated until it is certain that all solder
joints are molten. The chip can then be carefully removed from the substrate without
damaging the tracks and solder lands on the substrate. Removing the device must be
done using plastic tweezers, because metal tweezers can damage the silicon. The
surface of the substrate should be carefully cleaned and all solder and flux residues
and/or underfill removed. When a new chip is placed on the substrate, use the flux
process instead of solder on the solder lands. Apply flux on the bumps at the chip side as
well as on the solder pads on the substrate. Place and align the new chip while viewing
with a microscope. To reflow the solder, use the solder profile shown in application note
AN10365 “Surface mount reflow soldering description”.
9.3.4 Cleaning
Cleaning can be done after reflow soldering.
10. Abbreviations
Table 6.
Abbreviations
Description
Acronym
DUT
Device Under Test
EMI
ElectroMagnetic Interference
ElectroStatic Discharge
ESD
PCB
PCS
RFI
Printed-Circuit Board
Personal Communication System
Radio Frequency Interference
Restriction Of the use of certain Hazardous Substances directive
Subscriber Identity Module
RoHS
SIM
11. Revision history
Table 7.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
IP4064CX8LF_IP4364CX8LF_1 20071112
Product data sheet
-
-
IP4064CX8LF_IP4364CX8LF_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 12 November 2007
11 of 13
IP4064CX8/LF; IP4364CX8/LF
NXP Semiconductors
Integrated SIM card passive filter array with ESD protection
12. Legal information
12.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
12.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
12.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
12.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
13. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: salesaddresses@nxp.com
IP4064CX8LF_IP4364CX8LF_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 12 November 2007
12 of 13
IP4064CX8/LF; IP4364CX8/LF
NXP Semiconductors
Integrated SIM card passive filter array with ESD protection
14. Contents
1
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1
1.2
1.3
2
2.1
2.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2
3
4
5
6
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 4
7
7.1
7.2
Application information. . . . . . . . . . . . . . . . . . . 5
Insertion loss . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Crosstalk. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
8
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 7
9
9.1
9.2
9.3
9.3.1
9.3.2
9.3.3
9.3.4
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Introduction to soldering WLCSP packages . . . 9
Board mounting . . . . . . . . . . . . . . . . . . . . . . . . 9
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . . 9
Stand off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Quality of solder joint . . . . . . . . . . . . . . . . . . . 10
Rework . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Cleaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
10
11
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 11
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 11
12
Legal information. . . . . . . . . . . . . . . . . . . . . . . 12
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 12
12.1
12.2
12.3
12.4
13
14
Contact information. . . . . . . . . . . . . . . . . . . . . 12
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 12 November 2007
Document identifier: IP4064CX8LF_IP4364CX8LF_1
相关型号：
IP4085CX4/LF,135
IP4085CX4; IP4385CX4; IP4386CX4; IP4387CX4 - Integrated high-performance ESD protection diodes CSP 4-Pin
NXP
IP4085CX4/LF/P,135
IP4085CX4; IP4385CX4; IP4386CX4; IP4387CX4 - Integrated high-performance ESD protection diodes CSP 4-Pin
NXP
©2020 ICPDF网 联系我们和版权申明