IP4786CZ32S,118 [NXP]
IP4786CZ32S - DVI and HDMI interface ESD and overcurrent protection, DDC/CEC buffering, hot plug detect and backdrive protection QFN 32-Pin;
| 型号： | IP4786CZ32S,118 |
| 厂家： | 
NXP |
| 描述： | IP4786CZ32S - DVI and HDMI interface ESD and overcurrent protection, DDC/CEC buffering, hot plug detect and backdrive protection QFN 32-Pin 商用集成电路 |
| 文件： | 总34页 (文件大小：1678K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IP4786CZ32S
DVI and HDMI interface ESD and overcurrent protection,
DDC/CEC buffering, hot plug detect and backdrive protection
HXQFN32
Rev. 2 — 11 July 2013
Product data sheet
1. General description
The IP4786CZ32S is designed to protect High-Definition Multimedia Interface (HDMI)
transmitter host interfaces. It includes HDMI 5 V overcurrent / overvoltage protection,
Display Data Channel (DDC) buffering and decoupling, Hot Plug Detect (HPD), backdrive
protection, Consumer Electronic Control (CEC) buffering and decoupling, and 8 kV
contact ElectroStatic Discharge (ESD) protection for all I/Os in accordance with the
IEC 61000-4-2, level 4 standard.
The IP4786CZ32S incorporates Transmission Line Clamping (TLC) technology on the
high-speed Transition-Minimized Differential Signaling (TMDS) lines to simplify routing
and help reduce impedance discontinuities. All TMDS lines are protected by an
impedance-matched diode configuration that minimizes impedance discontinuities caused
by typical shunt diodes.
The enhanced 60 mA overcurrent / overvoltage linear regulator guarantees
HDMI-compliant 5 V output voltage levels with up to 6.5 V inputs.
The DDC lines use a new buffering concept which decouples the internal capacitive load
from the external capacitive load for use with standard Complementary Metal Oxide
Semiconductor (CMOS) or Low Voltage Transistor-Transistor Logic (LVTTL) I/O cells
down to 1.8 V. This buffering also redrives the DDC and CEC signals, allowing the use of
longer or cheaper HDMI cables with a higher capacitance. The internal hot plug detect
module simplifies the application of the HDMI transmitter to control the hot plug signal.
All lines provide appropriate integrated pull-ups and pull-downs for HDMI compliance and
backdrive protection to guarantee that HDMI interface signals are not pulled down if the
system is powered down or enters Standby mode. Only a single external capacitor is
required for operation.
2. Features and benefits
HDMI High-Speed, 340 MHz, deep color and HDMI Ethernet and Audio return
Channel (HEAC) compatible
Impedance matched 100 differential transmission line ESD protection for
TMDS lines (10 ). No Printed-Circuit Board (PCB) pre-compensation required
Simplified flow-through routing utilizing less overall PCB space
DDC capacitive decoupling between system side and HDMI connector side and
buffering to drive cable with high capacitive load (> 700 pF/25 m)
All external I/O lines with ESD protection of at least 8 kV in accordance with the
IEC 61000-4-2, level 4 standard
Hot plug detect module
IP4786CZ32S
NXP Semiconductors
DVI and HDMI interface ESD and overcurrent protection
CEC buffering and isolation, with integrated backdrive-protected 26 k pull-up
Robust ESD protection without degradation after repeated ESD strikes
Highest integration in a small footprint, PCB level, optimized RF routing,
32-pin HXQFN leadless package
3. Applications
The IP4786CZ32S can be used for a wide range of HDMI source devices, consumer
and computing electronics:
Tablet and notebook PCs
Portable Media Players
Digital Still Cameras (DSC)
High-Definition (HD) and Standard-Definition (SD) Blu-ray and DVD players
Set-top boxes (STB)
PC graphic cards
Game consoles
HDMI picture performance quality enhancer modules
Digital Visual Interface (DVI)
4. Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
Version
IP4786CZ32S
HXQFN32 plastic thermal enhanced extremely thin quad flat
SOT1318-1
package; no leads; 32 terminals; body 4 4 0.5 mm
IP4786CZ32S
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 11 July 2013
2 of 34
IP4786CZ32S
NXP Semiconductors
DVI and HDMI interface ESD and overcurrent protection
5. Functional diagram
TMDS_D2+_SYS
TMDS_D2+_CON
ESD
TMDS_D2–_SYS
TMDS_D1+_SYS
TMDS_D1–_SYS
TMDS_D0+_SYS
TMDS_D0–_SYS
TMDS_CK+_SYS
TMDS_CK–_SYS
TMDS_D2–_CON
TMDS_D1+_CON
TMDS_D1–_CON
TMDS_D0+_CON
TMDS_D0–_CON
TMDS_CK+_CON
8 kV
TMDS_CK–_CON
V
CC(5V0)
3.3 V VOLTAGE
REGULATOR
ESD
V
ESD
CC(SYS)
CEC driver
10 kΩ
26 kΩ
CEC_SYS
CEC_CON
2 kV
ESD
8 kV
ESD
V
V
HDMI_5V0_CON
1.85 kΩ
CC(SYS)
DDC driver
3.65 kΩ
DDC_CLK_SYS
DDC_CLK_CON
2 kV
ESD
8 kV
ESD
CC(SYS)
3.65 kΩ
HDMI_5V0_CON
1.85 kΩ
DDC driver
DDC_DAT_SYS
DDC_DAT_CON
2 kV
ESD
8 kV
ESD
Hot plug
HOTPLUG_DET_SYS
HOTPLUG_DET_CON
100 kΩ
100 kΩ
2 kV
ESD
8 kV
ESD
V
HDMI_5V0_CON
ESD_BYPASS
CC(5V0)
2 kV
8 kV
ESD
CURRENT LIMITER
8 kV
clamp
V
V
CC(5V0)
CC(SYS)
ESD
enable
enCEC
ESD
2 kV
enLim
enRef
CEC_STBY
100 kΩ
POWER
MANAGEMENT UNIT
V
CC(SYS)
2 kV
ESD
V
V
CC(5V0)
CC(SYS)
n
ibias 1..n
vref 1..m
m
UTILITY_CON
100 kΩ
CURRENT-/VOLTAGE-
REFERENCES
8 kV
001aan369
Fig 1. Functional diagram
IP4786CZ32S
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 11 July 2013
3 of 34
IP4786CZ32S
NXP Semiconductors
DVI and HDMI interface ESD and overcurrent protection
6. Pinning information
6.1 Pinning
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Fig 2. Pin configuration IP4786CZ32S
6.2 Pin description
Table 2.
Pin description
Pin
1
Name
Description
TMDS_D2+_SYS
TMDS_D2_SYS
TMDS_D1+_SYS
TMDS_D1_SYS
TMDS_D0+_SYS
TMDS_D0_SYS
TMDS_CK+_SYS
TMDS_CK_SYS
DDC_CLK_SYS
DDC_DAT_SYS
VCC(5V0)
TMDS to ASIC inside system
TMDS to ASIC inside system
TMDS to ASIC inside system
TMDS to ASIC inside system
TMDS to ASIC inside system
TMDS to ASIC inside system
TMDS to ASIC inside system
TMDS to ASIC inside system
DDC clock system side
2
3
4
5
6
7
8
9
10
11
12
13
DDC data system side
5 V supply input
HOTPLUG_DET_CON
HDMI_5V0_CON
hot plug detect connector side
5 V overcurrent out to connector
IP4786CZ32S
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 11 July 2013
4 of 34
IP4786CZ32S
NXP Semiconductors
DVI and HDMI interface ESD and overcurrent protection
Table 2.
Pin description …continued
Pin
14
Name
Description
DDC_DAT_CON
DDC_CLK_CON
UTILITY_CON
TMDS_CK_CON
TMDS_CK+_CON
TMDS_D0_CON
TMDS_D0+_CON
TMDS_D1_CON
TMDS_D1+_CON
TMDS_D2_CON
TMDS_D2+_CON
CEC_CON
DDC data connector side
15
DDC clock connector side
16
utility line ESD protection
17
TMDS ESD protection to connector
TMDS ESD protection to connector
TMDS ESD protection to connector
TMDS ESD protection to connector
TMDS ESD protection to connector
TMDS ESD protection to connector
TMDS ESD protection to connector
TMDS ESD protection to connector
CEC signal connector side
18
19
20
21
22
23
24
25
26
ESD_BYPASS
VCC(SYS)
ESD bias voltage
27
supply voltage for level shifting
CEC Standby mode control (LOW for lowest power, CEC-only mode)
CEC I/O signal system side
not connected
28
CEC_STBY
29
CEC_SYS
30
n.c.
31
n.c.
not connected
32
HOTPLUG_DET_SYS
GND
hot plug detect system side
ground
ground pad
7. Limiting values
Table 3.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
Max
Unit
V
VCC(5V0) supply voltage (5.0 V)
GND 0.5 6.5
GND 0.5 5.5
VI
input voltage
I/O pins
V
[1]
[2]
VESD
electrostatic discharge
voltage
IEC 61000-4-2, level 4 (contact)
IEC 61000-4-2, level 1 (contact)
-
-
-
8
2
50
kV
kV
mW
Ptot
total power dissipation
DDC operating at 100 kHz; CEC operating at
1 kHz; 50 % duty cycle; CEC_STBY = HIGH;
no current at HDMI_5V0_CON
DDC and CEC bus in idle mode;
CEC_STBY = HIGH;
no current at HDMI_5V0_CON
-
-
3.0
1.0
mW
mW
DDC and CEC bus in idle mode;
CEC_STBY = LOW
Tamb
Tstg
ambient temperature
storage temperature
25
55
+85
C
C
+125
[1] Connector-side pins (typically denoted with “_CON” suffix) to ground.
[2] System-side pins: CEC_SYS, DDC_DAT_SYS, DDC_CLK_SYS, HOTPLUG_DET_SYS, CEC_STBY, VCC(SYS) and VCC(5V0)
.
IP4786CZ32S
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 11 July 2013
5 of 34
IP4786CZ32S
NXP Semiconductors
DVI and HDMI interface ESD and overcurrent protection
8. Static characteristics
Table 4.
Supplies
Tamb = 25 C to +85 C unless otherwise specified.
Symbol Parameter
Conditions
Min
4.5
Typ
5.0
3.3
Max
6.5
Unit
V
[1]
VCC(5V0) supply voltage (5.0 V)
VCC(SYS) system supply voltage
1.62
5.5
V
[1] The IP4786CZ32S contains a 5 V voltage regulator function for higher input voltages.
Any input voltage of 4.925 V < VCC(5V0) < 6.50 V provides HDMI-compliant output levels of 4.8 V to 5.3 V
on HDMI_5V0_CON.
Table 5.
TMDS protection circuit
Tamb = 25 C to +85 C unless otherwise specified.
Symbol
TMDS channel
Zi(dif) differential input
Parameter
Conditions
Min Typ Max Unit
TDR measured;
tr = 200 ps
90
-
100 110
impedance
[1][2]
Ceff
effective capacitance
equivalent shunt
0.6
-
pF
capacitance for TDR
minimum; tr = 200 ps
Protection diode
VBRzd Zener diode breakdown
I = 1.0 mA
6.0
-
9.0
V
voltage
rdyn
dynamic resistance
surge; I = 1.0 A;
IEC 61000-4-5/9
positive transient
negative transient
TLP
-
-
1.0
1.0
-
-
[3]
positive transient
negative transient
VCC(5V0) < Vch(TMDS)
VI = 3.0 V
-
-
-
-
-
-
1.0
1.0
-
-
[4][5]
Ibck
ILR
VF
back current
0.1 1.0 A
reverse leakage current
forward voltage
1.0
0.7
8.0
-
-
-
A
V
VCL(ch)trt(pos) positive transient channel
clamping voltage
100 ns TLP;
50 pulser at 50 ns
V
[1] This parameter is guaranteed by design.
[2] Capacitive dip at HDMI Time Domain Reflectometer (TDR) measurement conditions.
[3] ANSI-ESD SP5.5.1-2004, ESD sensitivity testing Transmission Line Pulse (TLP) component level
method 50 TDR.
[4] Signal pins:
TMDS_D0+_CON, TMDS_D0_CON, TMDS_D1+_CON, TMDS_D1_CON, TMDS_D2+_CON,
TMDS_D2_CON, TMDS_CK+_CON, TMDS_CK_CON,
TMDS_D0+_SYS, TMDS_D0_SYS, TMDS_D1+_SYS, TMDS_D1_SYS, TMDS_D2+_SYS,
TMDS_D2_SYS, TMDS_CK+_SYS and TMDS_CK_SYS.
[5] Backdrive current from TMDS_x_SYS and TMDS_x_CON pins to local VCC(5V0) bias rail at power-down.
Device does not block backdrive current leakage through the device to/from ASIC I/O pins connected
to TMDS_x_SYS pins.
IP4786CZ32S
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 11 July 2013
6 of 34
IP4786CZ32S
NXP Semiconductors
DVI and HDMI interface ESD and overcurrent protection
Table 6.
HDMI_5V0_CON
Tamb = 25 C to +85 C unless otherwise specified.
Symbol Parameter
rdyn dynamic resistance
Conditions
TLP
Min Typ Max Unit
[1]
positive transient
negative transient
-
-
-
1.0
1.0
8
-
-
-
V
VCL
clamping voltage
100 ns TLP;
50 pulser at 50 ns
IO(max)
Ibck
IO(sc)
Vdo
maximum output current V(HDMI_5V0_CON) = 4.8 V
back current VCC(5V0) < V(HDMI_5V0_CON)
short-circuit output current V(HDMI_5V0_CON) = 0 V
55
-
-
-
-
mA
10
A
-
125 175 mA
[2]
[2]
dropout voltage
4.5 V < VCC(5V0) < 4.925 V;
DDC = LOW
IO = 10 mA
IO = 55 mA
-
-
70
-
-
mV
125 mV
VO(LDO)
LDO output voltage
IO 55 mA;
4.8 5.05 5.3
V
4.925 V < VCC(5V0) < 6.5 V;
DDC = LOW
[1] ANSI-ESD SP5.5.1-2004, ESD sensitivity testing TLP component level method 50 TDR.
[2] The IP4786CZ32S contains a 5 V voltage regulator function for higher input voltages.
Any input voltage of 4.925 V < VCC(5V0) < 6.50 V provides HDMI-compliant output levels of 4.8 V to 5.3 V
on HDMI_5V0_CON.
Table 7.
UTILITY_CON
Tamb = 25 C to +85 C unless otherwise specified.
Symbol Parameter
Conditions
Min Typ Max Unit
Supplies: pins VCC(5V0) and VCC(SYS)
[1]
rdyn
dynamic resistance
TLP
positive transient
negative transient
-
-
-
1.0
1.0
8.0
-
-
-
V
VCL
Ci
clamping voltage
input capacitance
100 ns TLP;
50 pulser at 50 ns
VCC(5V0) = 0 V;
-
8.0 10
pF
VCC(SYS) = 0 V; Vbias = 2.5 V;
AC input = 3.5 V(p-p)
f = 100 kHz
;
Rpd
pull-down resistance
60
100 140 k
[1] ANSI-ESD SP5.5.1-2004, ESD sensitivity testing TLP component level method 50 TDR.
IP4786CZ32S
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 11 July 2013
7 of 34
IP4786CZ32S
NXP Semiconductors
DVI and HDMI interface ESD and overcurrent protection
Table 8.
Static characteristics
Tamb = 25 C to +85 C unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
DDC buffer on connector side[1]
VIH
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
0.5
V(HDMI_5V0_CON)
-
6.5
V
VIL
0.5
-
0.3
V(HDMI_5V0_CON)
V
[2]
VOH
VOL
V(HDMI_5V0_CON)
0.02
-
V(HDMI_5V0_CON)
+ 0.02
V
LOW-level output voltage internal pull-up and
external sink
-
100
200
mV
VIK
CIO
input clamping voltage
II = 18 mA
-
-
-
1.0
V
[2][3]
input/output capacitance VCC(5V0) = 5.0 V;
VCC(SYS) = 3.3 V;
8.0
10
pF
CEC_STBY = HIGH
Rpu
pull-up resistance
1.6
1.8
2.0
k
DDC buffer on system side[1][4]
VIH HIGH-level input voltage VCC(SYS) = 1.8 V
450
-
-
mV
mV
mV
mV
mV
mV
mV
mV
V
VCC(SYS) = 2.5 V
VCC(SYS) = 3.3 V
VCC(SYS) = 5.0 V
VCC(SYS) = 1.8 V
VCC(SYS) = 2.5 V
VCC(SYS) = 3.3 V
VCC(SYS) = 5.0 V
620
-
-
760
-
-
800
-
-
VIL
LOW-level input voltage
HIGH-level output voltage
-
-
330
-
-
380
-
-
400
-
-
420
[2]
[5]
[5]
[5]
[5]
VOH
VOL
VCC(SYS) 0.02
-
VCC(SYS) + 0.02
LOW-level output voltage VCC(SYS) = 1.8 V
VCC(SYS) = 2.5 V
-
-
-
-
-
-
490
640
685
720
-
500
690
790
820
1.0
8.0
mV
mV
mV
mV
V
VCC(SYS) = 3.3 V
VCC(SYS) = 5.0 V
VIK
CIO
input clamping voltage
II = 18 mA
[2]
input/output capacitance VCC(5V0) = 0 V;
VCC(SYS) = 0 V;
6.0
pF
Vbias = 2.5 V;
AC input = 3.5 V(p-p)
;
f = 100 kHz
Rpu
pull-up resistance
3.2
3.65
4.1
k
IP4786CZ32S
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 11 July 2013
8 of 34
IP4786CZ32S
NXP Semiconductors
DVI and HDMI interface ESD and overcurrent protection
Table 8.
Static characteristics …continued
Tamb = 25 C to +85 C unless otherwise specified.
Symbol Parameter
CEC_CON[1]
Conditions
Min
Typ
Max
Unit
VIH
VIL
HIGH-level input voltage
2.0
-
-
V
LOW-level input voltage
HIGH-level output voltage
-
-
0.80
3.63
200
10
V
VOH
VOL
CIO
2.88
3.3
100
8.0
V
LOW-level output voltage IOL = 1.5 mA
-
-
mV
pF
[2]
input/output capacitance VCC(5V0) = 0 V;
VCC(SYS) = 0 V;
Vbias = 1.65 V;
AC input = 2.5 V(p-p)
;
f = 100 kHz
Rpu
pull-up resistance
23.4
26.0
28.6
k
CEC_SYS[1][4]
VIH
HIGH-level input voltage VCC(SYS) = 1.8 V
VCC(SYS) = 2.5 V
450
-
-
mV
mV
mV
mV
mV
mV
mV
mV
V
620
-
-
VCC(SYS) = 3.3 V
760
-
-
VCC(SYS) = 5.0 V
800
-
-
VIL
LOW-level input voltage
VCC(SYS) = 1.8 V
VCC(SYS) = 2.5 V
VCC(SYS) = 3.3 V
VCC(SYS) = 5.0 V
-
-
330
-
-
380
-
-
400
-
-
420
[2]
[5]
[5]
[5]
[5]
[2]
VOH
VOL
HIGH-level output voltage
VCC(SYS) 0.02
-
VCC(SYS) + 0.02
LOW-level output voltage VCC(SYS) = 1.8 V
VCC(SYS) = 2.5 V
-
-
-
-
-
490
640
675
710
6.0
500
690
770
800
7.0
mV
mV
mV
mV
pF
VCC(SYS) = 3.3 V
VCC(SYS) = 5.0 V
CIO
input/output capacitance VCC(5V0) = 0 V;
VCC(SYS) = 0 V;
Vbias = 1.65 V;
AC input = 2.5 V(p-p)
;
f = 100 kHz
Rpu
pull-up resistance
8.5
10
11.5
k
HOTPLUG_DET_CON[1]
VIH
VIL
Rpd
Ci
HIGH-level input voltage
2.0
-
-
-
V
LOW-level input voltage
pull-down resistance
input capacitance
-
0.8
140
10
V
60
-
100
8.0
k
pF
[2]
VCC(5V0) = 0 V;
VCC(SYS) = 0 V;
Vbias = 2.5 V;
AC input = 3.5 V(p-p)
;
f = 100 kHz
IP4786CZ32S
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 11 July 2013
9 of 34
IP4786CZ32S
NXP Semiconductors
DVI and HDMI interface ESD and overcurrent protection
Table 8.
Static characteristics …continued
Tamb = 25 C to +85 C unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
HOTPLUG_DET_SYS[1]
VOH
VOL
Rpd
HIGH-level output voltage IOL = 1 mA
LOW-level output voltage IOL = 1 mA
pull-down resistance
0.7 VCC(SYS)
-
-
V
-
200
100
300
140
mV
k
60
[1] The device is active if the input voltage at pin CEC_STBY is above the HIGH level.
[2] This parameter is guaranteed by design.
[3] Capacitive load measured at power-on.
[4] No external pull-up resistor attached.
[5] Typical value at Tamb = +25 C.
Table 9.
CEC_STBY power management circuit
VCC(SYS) = 1.62 V to 5.5 V; VCC(5V0) = 4.5 V to 6.5 V; GND = 0 V; Tamb = 25 C to +85 C unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Board side: input pin CEC_STBY[1]
[2]
[3]
VIH
VIL
Rpd
Ci
HIGH-level input voltage
LOW-level input voltage
pull-down resistance
input capacitance
HIGH = active
1.2
0.5
60
-
-
6.5
0.8
140
7
V
LOW = standby
-
V
100
6
k
pF
VI = 3 V or 0 V
[1] The CEC_STBY pin should be connected permanently to VCC(5V0) or VCC(SYS) if no enable control is needed.
[2] DDC buffers, HPD buffer, and HDMI_5V0_CON out enabled; CEC buffer enabled.
[3] DDC buffers, HPD buffer, and HDMI_5V0_CON out disabled; CEC buffer enabled.
IP4786CZ32S
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IP4786CZ32S
NXP Semiconductors
DVI and HDMI interface ESD and overcurrent protection
9. Dynamic characteristics
Table 10. Dynamic characteristics
VCC(5V0) = 5.0 V; VCC(SYS) = 1.8 V; GND = 0 V; Tamb = 25 C to +85 C unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max Unit
DDC_DAT_SYS, DDC_CLK_SYS, DDC_DAT_CON, DDC_CLK_CON[1]
tPLH
tPHL
tPLH
tPHL
tTLH
tTHL
tTLH
tTHL
LOW to HIGH propagation delay
HIGH to LOW propagation delay
LOW to HIGH propagation delay
HIGH to LOW propagation delay
LOW to HIGH transition time
HIGH to LOW transition time
LOW to HIGH transition time
HIGH to LOW transition time
system side to connector side Figure 15
system side to connector side Figure 15
connector side to system side Figure 16
connector side to system side Figure 16
connector side Figure 17
-
-
-
-
-
-
-
-
80
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
60
120
80
150
100
250
80
connector side Figure 17
system side Figure 18
system side Figure 18
[1] All dynamic measurements are done with a 75 pF load. Rise times are determined by internal pull-up resistors.
DDDꢀꢁꢁꢃꢃꢃꢄ
ꢄꢅꢃ
=
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70'6B&.
70'6B'ꢅ
70'6B'ꢄ
70'6B'ꢃ
ꢄꢄꢃ
ꢄꢃꢃ
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ꢊꢃ
ꢃ
ꢃꢉꢄ
ꢃꢉꢅ
ꢃꢉꢏ
ꢃꢉꢎ
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ꢃꢉꢌ
WLPHꢀꢆQVꢈ
tr = 200 ps; no filter; VCC(5V0) = 5 V
100 differential (CH1 + CH2)
Fig 3. Differential TDR plot
IP4786CZ32S
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IP4786CZ32S
NXP Semiconductors
DVI and HDMI interface ESD and overcurrent protection
018aaa086
3
Sdd21;
Scc21
(dB)
(1)
–3
(2)
–9
–15
6
7
8
9
10
10
10
10
10
10
f (Hz)
(1) Sdd21
(2) Scc21
Normalized to 100 ; differential pairs at signal pins.
Fig 4. Mixed-mode differential and common-mode insertion loss; typical values
018aaa087
3
Sdd21
(dB)
(1)
–3
(2)
–9
–15
6
7
8
9
10
10
10
10
10
10
f (Hz)
(1) Sdd21; Near End Crosstalk (NEXT)
(2) Sdd21; Far End Crosstalk (FEXT)
normalized to 100 ; differential pairs CH1/CH2 versus CH3/CH4
Fig 5. Mixed-mode differential and common-mode NEXT / FEXT; typical values
IP4786CZ32S
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IP4786CZ32S
NXP Semiconductors
DVI and HDMI interface ESD and overcurrent protection
DDDꢀꢁꢁꢃꢃꢅꢄ
227 MHz pixel clock
Horizontal scale: 90 ps/div
Vertical scale: 200 mV/div
Offset: 42.6 mV
Fig 6. Eye diagram using IP4786CZ32S (1080p, 12 bit)
DDDꢀꢁꢁꢃꢃꢅꢆ
297 MHz pixel clock
Horizontal scale: 67.5 ps/div
Vertical scale: 200 mV/div
Offset: 42.6 mV
Fig 7. Eye diagram using IP4786CZ32S (1080p, 16 bit)
IP4786CZ32S
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IP4786CZ32S
NXP Semiconductors
DVI and HDMI interface ESD and overcurrent protection
018aaa090
0.4
C
line
(pF)
0.2
0.0
–0.2
–0.4
–1.0
1.0
3.0
5.0
7.0
V
(V)
bias
Deviation from typical capacitance normalized at Vbias = 2.5 V
Fig 8. Line capacitance as a function of bias voltage; typical values
018aaa091
018aaa092
4.00
CL
2.5
V
V
CL
(V)
(V)
3.75
3.50
3.25
3.00
2.0
1.5
1.0
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
0.4
0.6
0.8
1.0
1.2
I (A)
I (A)
IEC 61000-4-5; tp = 8/20 s; positive pulse
IEC 61000-4-5; tp = 8/20 s; negative pulse
Fig 9. Dynamic resistance with positive clamping
Fig 10. Dynamic resistance with negative clamping
IP4786CZ32S
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Product data sheet
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IP4786CZ32S
NXP Semiconductors
DVI and HDMI interface ESD and overcurrent protection
018aaa093
018aaa094
14
I
0
I
(A)
(A)
12
–2
–4
–6
10
8
6
–8
4
–10
–12
–14
2
0
6
10
14
18
22
–12
–8
–4
0
V
(V)
V
(V)
CL
CL
tp = 100 ns; TLP; signal pins; typical values
tp = 100 ns; TLP; signal pins; typical values
Fig 11. Dynamic resistance with positive clamping
Fig 12. Dynamic resistance with negative clamping
018aaa095
018aaa096
6.5
6.0
V
I
V
O
(V)
(V)
(2)
(1)
(4)
6.0
(5)
4.0
5.5
5.0
4.5
(1)
(3)
2.0
0.0
(4)
(2)
(3)
5.0
5.5
6.0
6.5
0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14
(A)
V
(V)
I
O
CC(5V0)
(1) 5.3 V; maximum values; HDMI CTS TID 7-11
(2) 4.8 V; minimum values; HDMI CTS TID 7-11
(3) I = 0 mA
(1) VCC(5V0) = 4.5 V
(2) VCC(5V0) = 5.0 V
(3) VCC(5V0) = 5.5 V
(4) I = 55 mA
(4) VCC(5V0) = 6.5 V
(5) VCC(5V0) supply input; 4.925 V to 6.5 V
Fig 13. Overvoltage limiter function (HDMI_5V0_CON)
Fig 14. Overcurrent limiter function (HDMI_5V0_CON)
IP4786CZ32S
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IP4786CZ32S
NXP Semiconductors
DVI and HDMI interface ESD and overcurrent protection
10. AC waveforms
10.1 DDC propagation delay
V
DDC system side
CC(SYS)
0.5 V
CC(SYS)
0.28 V
CC(SYS)
V
OL
DDC connector side
V
(HDMI_5V0_CON)
0.5 V
0.5 V
(HDMI_5V0_CON)
(HDMI_5V0_CON)
V
OL
t
t
PLH
PHL
018aaa097
Fig 15. Propagation delay DDC, DDC system side to DDC connector side
DDC connector side
V
(HDMI_5V0_CON)
0.5 V
0.5 V
(HDMI_5V0_CON)
(HDMI_5V0_CON)
V
OL
V
DDC system side
CC(SYS)
0.5 V
0.5 V
CC(SYS)
CC(SYS)
V
OL
t
t
PLH
PHL
018aaa098
Fig 16. Propagation delay DDC, DDC connector side to DDC system side
IP4786CZ32S
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IP4786CZ32S
NXP Semiconductors
DVI and HDMI interface ESD and overcurrent protection
10.2 DDC transition time
DDC system side
V
V
CC(SYS)
V
V
OL
(HDMI_5V0_CON)
DDC connector side
80 % V
20 % V
(HDMI_5V0_CON)
(HDMI_5V0_CON)
OL
t
t
PLH
PHL
018aaa099
Fig 17. Transition time DDC connector side
DDC connector side
V
V
(HDMI_5V0_CON)
V
V
OL
DDC system side
CC(SYS)
80 % V
CC(SYS)
CC(SYS)
20 % V
OL
t
t
PLH
PHL
018aaa100
Fig 18. Transition time DDC system side
IP4786CZ32S
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IP4786CZ32S
NXP Semiconductors
DVI and HDMI interface ESD and overcurrent protection
11. Application information
11.1 TMDS ESD
To protect the TMDS lines and also to comply with the impedance requirements of the
HDMI specification, the IP4786CZ32S provides ESD protection with matched
TLC ESD structures. Typical Dual Rail Clamp (DRC) or rail-to-rail shunt structures are
common for low-capacitance ESD protection (Figure 19; left side) where the dominant
factor for the TMDS line impedance dip is determined by the capacitive load to ground.
Parasitic lead inductances of the packaging in this case work against the ESD clamping
performance by including the I/t reactance of the inductance into the path of the ESD
shunt.
The IP4786CZ32S utilizes these inherent inductances in series with the transmission line
in order to present an effective capacitive load of roughly only 0.7 pF. This TLC structure
minimizes the capacitive dip, for ideal signal integrity (Figure 19; right side) without
complicated PCB pre-compensation. As a beneficial side effect, this enhances the
ESD performance of the device as well, since the reactance of the series inductance
attenuates the fast initial peak of the ESD pulse, for a lower residual pulse delivered to the
Application Specific Integrated Circuit (ASIC).
018aaa102
018aaa101
a. Classic parallel ESD shunt protection
b. Improved series shunt TLC clamping
Fig 19. TLC ESD protection of TMDS lines
IP4786CZ32S
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IP4786CZ32S
NXP Semiconductors
DVI and HDMI interface ESD and overcurrent protection
11.2 Operating and standby modes
The operating mode of IP4786CZ32S depends on the availability of the VCC(5V0) and
CC(SYS) supply voltages and on the state of the CEC_STBY input signal. Without
V
availability of both supplies, IP4786CZ32S is in Standby mode. As soon as VCC(5V0) and
VCC(SYS) are within the range specified in Section 8, the part is in an operating mode that
can be controlled via the CEC_STBY input signal. In case CEC_STBY is LOW, only the
CEC buffer is active and enabled to receive or send CEC commands. All other outputs are
in a high-ohmic state. A HIGH input signal enables all parts of IP4786CZ32S and puts the
device into full operating mode.
Table 11. IP4786CZ32S operating modes
VCC(SYS)
< 1.1 V
1.1 V
VCC(5V0)
< 4.5 V
4.5 V
CEC_STBY[1] Mode
Description
X
L
Standby mode
all outputs high-ohmic
CEC Standby mode CEC circuit active;
all other outputs high-ohmic
H
full operating mode all functional blocks active
[1] X = Don’t care (either LOW or HIGH level); L = LOW-level input; H = HIGH-level input
If no CEC Standby mode is required, or if no special Power-down modes are desired, the
CEC_STBY pin can be pulled HIGH to VCC(5V0) or VCC(SYS) for continuous HDMI and CEC
operation as soon as the supplies are available.
Strapping the CEC_STBY = VCC(SYS) = VDD of the ASIC guarantees that all interface
signals ending with the suffix “_SYS” on the system side are disabled when VCC(SYS) goes
LOW. This configuration protects the ASIC I/O signals from exceeding its local VDD. In this
mode, even if VCC(5V0) is powered, HDMI_5V0_CON goes active and hot plug events can
be detected only when the ASIC power supply rail is on.
Strapping CEC_STBY = VCC(5V0) is the most basic configuration where the buffers are
enabled whenever the local VCC(5V0) and VCC(SYS) supplies reach minimum operating
levels.
IP4786CZ32S
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IP4786CZ32S
NXP Semiconductors
DVI and HDMI interface ESD and overcurrent protection
11.3 DDC circuit
The DDC bus circuit integrates all required pull-ups, and provides full capacitive
decoupling between the HDMI connector and the DDC bus lines on the PCB. The
capacitive decoupling ensures that the maximum capacitive load is well within the 50 pF
maximum of the HDMI specification. No external pull-ups or pull-downs are required.
The bidirectional buffers support high-capacitive load on the HDMI cable-side. Various
non-compliant but prevalent low-cost cables have been observed with a capacitive load of
up to 6 nF on the DDC lines, far exceeding the 700 pF HDMI limit. The IP4786CZ32S can
easily decouple this from the weaker ASIC I/O buffers, and drive the rogue cable
successfully.
V
CC(SYS)
V
ESD_BYPASS HDMI_5V0_CON
1.85 kΩ
CC(SYS)
ESD_BYPASS HDMI_5V0_CON
1.85 kΩ
3.65 kΩ
3.65 kΩ
DDC_DAT_SYS
DDC_DAT_CON
DDC_CLK_SYS
DDC_CLK_CON
018aaa103
018aaa104
a. DDC clock
Fig 20. DDC circuit
b. DDC data
5
(1)
(2)
4
3
V
2
1
0
time
018aaa105
(1) Valid I2C signaling example on the cable (connector side) from 5 V (HIGH) to approximately 1 V (LOW).
(2) Valid logic-level signaling example to the ASIC (system side) from 1.8 V (HIGH) to approximately 0.5 V (LOW).
Fig 21. DDC level shifting waveform example
IP4786CZ32S
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Product data sheet
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IP4786CZ32S
NXP Semiconductors
DVI and HDMI interface ESD and overcurrent protection
11.4 Logic low I2C voltage shifter
The DDC buffers provide an additional feature commonly required for high-integration
HDMI ASICs. In order to be compatible with the 5 V I2C standard used for DDC
communication, I/O buffer cells of many HDMI modern transmitter chips require level
shifting. As FET-based level shifting just limits the HIGH level of the signal, the LOW level
remains unchanged. As a result, the LOW-level voltages on the DDC bus often exceed
the 0.3 VDD LOW-level input voltage (VIL) limit of low-voltage I/O buffers.
To enable proper operation that is independent of the system side I/O voltage, the DDC
buffers inside IP4786CZ32S shift both the HIGH and the LOW levels by the required
amount. This ensures that LOW levels on the system side DDC bus match the LOW-level
input voltage requirements down to I/O voltages of 1.8 V.
Besides the DDC buffers, this feature is also included in the CEC buffer, allowing standard
I/O buffer cells to be used in HDMI ASICs and microcontrollers.
018aaa106
0.9
(1)
V
;V ;
OL IH
IL
(V)
V
(2)
(3)
0.7
0.5
0.3
1.6
2.6
3.6
4.6
5.6
V
(V)
CC(SYS)
(1) VOL(max) driven to system (ASIC) side when I2C logic LOW (less than 0.3 HDMI_5V0_CON)
(2) VIH(min) threshold on system (ASIC) side to drive I2C logic HIGH
(3)
V
IL(max) threshold on system (ASIC) side to drive I2C logic LOW
Fig 22. Logic voltage thresholds as a function of supply voltage on system side
IP4786CZ32S
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IP4786CZ32S
NXP Semiconductors
DVI and HDMI interface ESD and overcurrent protection
11.5 Hot plug detect circuit and HEAC support
The IP4786CZ32S includes a hot plug detect circuit that simplifies the hot plug
application. The circuit generates a standard logic level from the hot plug signal.
The hot plug detect circuit is pulling down the signal to avoid any floating signal.
The comparator guarantees a save detection of the 2 V hot plug signal without any
glitches or oscillation at the hot plug output.
The IP4786CZ32S also provides an additional ESD pin to protect the reserved / HEAC pin
along with hot plug detect to 8 kV IEC 61000-4-2, level 4.
V
CC(5V0)
ESD_BYPASS
HOTPLUG_DET_CON
HOTPLUG_DET_SYS
100 kΩ
100 kΩ
018aaa107
Fig 23. Hot plug detect circuit
11.6 CEC
The logical multidrop topology of the CEC bus can include complex physical stubs,
loading cables, and interconnects that may deteriorate signal quality.
The IP4786CZ32S includes a full bidirectional buffer to drive the CEC bus and isolate
the CEC microcontroller or ASIC General-Purpose Input/Output (GPIO).
The CEC buffer derives power from an on-board 3.3 V regulator from the VCC(5V0) domain
(see Figure 24). This allows extensive system power management configurations and
guarantees an HDMI-compliant V(CEC_CON) on the connector, as well as the
backdrive-protected 125 A nominal CEC pull-up which does not degrade the bus when
powered down.
By placing the CEC microcontroller and VCC(5V0) input on a 5 V rail as shown in Figure 27,
the CEC microcontroller can communicate over CEC for power commands, and then
enable the HDMI port via the CEC_STBY pin, as well as the rest of the system as needed.
The CEC buffer is always active as soon as both supply voltages are present. For details
on the operating and Standby modes of IP4786CZ32S, see Section 11.2.
IP4786CZ32S
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IP4786CZ32S
NXP Semiconductors
DVI and HDMI interface ESD and overcurrent protection
V
V
CC(SYS)
CC(5V0)
3V3
ESD_BYPASS
10 kΩ
26 kΩ
CEC_CON
CEC_SYS
018aaa108
Fig 24. CEC module
11.7 Backdrive protection
The HDMI connector contains various signals which can partly supply current into an
HDMI device that is powered down.
Typically, the DDC lines and the CEC signals can force significant current back into the
powered-down rails as shown in Figure 25, causing power-on reset problems with the
system, and possible damage. The IP4786CZ32S prevents this backdrive condition
whenever the I/O voltage is greater than the local supply.
supply off
5 V
HDMI source
HDMI sink
backdrive current
2
HDMI ASIC
I C-bus ASIC
018aaa109
Fig 25. Generalized backdrive protection
IP4786CZ32S
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Product data sheet
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IP4786CZ32S
NXP Semiconductors
DVI and HDMI interface ESD and overcurrent protection
11.8 55 mA overcurrent / overvoltage LDO function
To isolate faults from the source power supply while still meeting HDMI output
specifications, IP4786CZ32S integrates a complete linear output overcurrent protection.
The Low DropOut (LDO) design provides a low-cost solution requiring just a single output
capacitor (1 F or higher, Equivalent Series Resistance (ESR) < 1 ), eliminating start-up
and ripple concerns (see Figure 26).
A typical 100 mV dropout voltage Vdo overcurrent-only solution would require a
5.1 V 3 % input supply to guarantee 4.8 V to 5.3 V over 0 mA to 55 mA at the HDMI
connector. The overcurrent / overvoltage feature of the IP4786CZ32S allows the use of
wider tolerance input supplies up to 6.5 V while still meeting the 4.8 V-to-5.3 V output limit
required by HDMI. This means, for example, a cost-reduced 5.2 V 5 % or even
a 5.5 V 10 % supply can be used with the IP4786CZ32S.
As with all the I/O pins, this block is ESD-protected and also provides backdrive protection
when a rogue HDMI sink powers the HDMI cable unexpectedly.
ESD_BYPASS
V
CC(5V0)
HDMI_5V0_CON
DDC/HPD
buffers
CEC
3V3
regulator
60 mA
overcurrent
control
CEC
buffer
018aaa110
Fig 26. 5 V LDO with overcurrent / overvoltage protection
IP4786CZ32S
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IP4786CZ32S
NXP Semiconductors
DVI and HDMI interface ESD and overcurrent protection
11.9 Schematic view of application
Only a single external component (CO = 1 F) is required to protect and interface the
ASIC to a complete and compliant HDMI port. The 100 nF ESD bypass capacitor is
optional.
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Fig 27. Schematic view of IP4786CZ32S application
IP4786CZ32S
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Product data sheet
Rev. 2 — 11 July 2013
25 of 34
IP4786CZ32S
NXP Semiconductors
DVI and HDMI interface ESD and overcurrent protection
11.10 Typical application
The IP4786CZ32S is designed to simplify routing to the HDMI connector, and ease the
incorporation of high-level ESD protection into delicately balanced high-speed
TMDS lines. These lines rely on tightly controlled microstrip or stripline transmission lines
with minimal impedance discontinuities, which can deteriorate return loss, increase
deterministic jitter and generally erode overall link signal integrity.
Normally when designing the PCB with standard shunt ESD clamps, careful consideration
must be given to manual pre-compensation of the additional load of the added
ESD component. With the IP4786CZ32S TLCs, the ESD suppressor is designed to
maintain the characteristic impedance of the PCB microstrip or stripline, and therefore the
designer needs only be concerned with the standard-controlled impedance of the
unloaded PCB lines. This simplifies the task of the PCB designer, and minimizes the
tuning cycles, which are sometimes required when pre-compensation misses the mark.
A basic application diagram for the ESD protection of an HDMI interface is shown in
Figure 28 for a type-C HDMI connector.
The optimized HXQFN32 pinning simplifies the PCB design to keep the ESD protection
close to the connector where it can minimize the coupling of the ESD pulse onto other
lines in the system during a strike.
Due to the integrated pull-up and pull-down resistors, only two external capacitors are
required to implement a fully compliant HDMI port.
ꢄꢃꢀPP
DDDꢀꢁꢁꢂꢃꢁꢅ
Fig 28. Application of the IP4786CZ32S showing optimized HDMI type-C connector routing
IP4786CZ32S
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Product data sheet
Rev. 2 — 11 July 2013
26 of 34
IP4786CZ32S
NXP Semiconductors
DVI and HDMI interface ESD and overcurrent protection
12. Package outline
HXQFN32: plastic thermal enhanced extremely thin quad flat package; no leads;
32 terminals; body 4 x 4 x 0.5 mm
SOT1318-1
D
B
A
E
A
terminal 1
index area
c
A
1
detail X
e
1
C
1/2 e
v
w
C
C
A
B
y
y
e
b
C
1
L
9
16
e
8
1
17
e
E
h
2
1/2 e
24
terminal 1
index area
32
25
X
D
h
0
5 mm
v
scale
e
Dimensions (mm are the original dimensions)
(1)
Unit
A
A
1
b
c
D
D
h
E
E
h
e
e
L
w
y
y
1
1
2
max 0.50 0.05 0.30
4.1 2.95 4.1 2.95
0.4
mm nom
min
0.02 0.21 0.127 4.0 2.80 4.0 2.80 0.4 2.8 2.8 0.3 0.1 0.05 0.05 0.1
0.00 0.18
3.9 2.65 3.9 2.65
0.2
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
sot1318-1_po
References
Outline
version
European
projection
Issue date
IEC
- - -
JEDEC
- - -
JEITA
- - -
11-11-16
11-11-27
SOT1318-1
Fig 29. Package outline SOT1318-1 (HXQFN32)
IP4786CZ32S
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Product data sheet
Rev. 2 — 11 July 2013
27 of 34
IP4786CZ32S
NXP Semiconductors
DVI and HDMI interface ESD and overcurrent protection
13. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
13.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
13.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering
13.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
IP4786CZ32S
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 11 July 2013
28 of 34
IP4786CZ32S
NXP Semiconductors
DVI and HDMI interface ESD and overcurrent protection
13.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 30) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 12 and 13
Table 12. SnPb eutectic process (from J-STD-020D)
Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350
235
350
220
< 2.5
2.5
220
220
Table 13. Lead-free process (from J-STD-020D)
Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350
260
350 to 2000
> 2000
260
< 1.6
260
250
245
1.6 to 2.5
> 2.5
260
245
250
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 30.
IP4786CZ32S
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Product data sheet
Rev. 2 — 11 July 2013
29 of 34
IP4786CZ32S
NXP Semiconductors
DVI and HDMI interface ESD and overcurrent protection
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 30. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
14. Glossary
HDMI sink — Device which receives HDMI signals for example, a TV set.
HDMI source — Device which transmits HDMI signal for example, DVD player.
IP4786CZ32S
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Product data sheet
Rev. 2 — 11 July 2013
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NXP Semiconductors
DVI and HDMI interface ESD and overcurrent protection
15. Revision history
Table 14. Revision history
Document ID
IP4786CZ32S v.2
Modifications:
Release date
20130711
Data sheet status
Change notice
Supersedes
Product data sheet
-
IP4786CZ32S v.1
• Section 2 “Features and benefits”: updated
• Section 3 “Applications”: updated
• Figure 6 and Figure 7: corrected
• Section 11.2 “Operating and standby modes”: added
• Section 11.4 “Logic low I2C voltage shifter”: updated
• Section 11.6 “CEC”: updated
IP4786CZ32S v.1
20120727
Preliminary data sheet
-
-
IP4786CZ32S
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Product data sheet
Rev. 2 — 11 July 2013
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IP4786CZ32S
NXP Semiconductors
DVI and HDMI interface ESD and overcurrent protection
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use — NXP Semiconductors products are not designed,
16.2 Definitions
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
16.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
IP4786CZ32S
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Product data sheet
Rev. 2 — 11 July 2013
32 of 34
IP4786CZ32S
NXP Semiconductors
DVI and HDMI interface ESD and overcurrent protection
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
16.4 Licenses
Purchase of NXP ICs with HDMI technology
non-automotive qualified products in automotive equipment or applications.
Use of an NXP IC with HDMI technology in equipment that complies with
the HDMI standard requires a license from HDMI Licensing LLC, 1060 E.
Arques Avenue Suite 100, Sunnyvale CA 94085, USA, e-mail:
admin@hdmi.org.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
16.5 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
IP4786CZ32S
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 11 July 2013
33 of 34
IP4786CZ32S
NXP Semiconductors
DVI and HDMI interface ESD and overcurrent protection
18. Contents
1
2
3
4
5
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
7
8
9
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . 11
10
10.1
10.2
AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . 16
DDC propagation delay . . . . . . . . . . . . . . . . . 16
DDC transition time . . . . . . . . . . . . . . . . . . . . 17
11
Application information. . . . . . . . . . . . . . . . . . 18
TMDS ESD. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Operating and standby modes . . . . . . . . . . . . 19
DDC circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Logic low I2C voltage shifter . . . . . . . . . . . . . . 21
Hot plug detect circuit and HEAC support . . . 22
CEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Backdrive protection. . . . . . . . . . . . . . . . . . . . 23
55 mA overcurrent / overvoltage LDO function 24
Schematic view of application . . . . . . . . . . . . 25
Typical application . . . . . . . . . . . . . . . . . . . . . 26
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
11.9
11.10
12
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 27
13
Soldering of SMD packages . . . . . . . . . . . . . . 28
Introduction to soldering . . . . . . . . . . . . . . . . . 28
Wave and reflow soldering . . . . . . . . . . . . . . . 28
Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 28
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 29
13.1
13.2
13.3
13.4
14
15
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 31
16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 32
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 32
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 33
16.1
16.2
16.3
16.4
16.5
17
18
Contact information. . . . . . . . . . . . . . . . . . . . . 33
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2013.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 11 July 2013
Document identifier: IP4786CZ32S
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