IP4855CX25 [NXP]
SD 3.0-compliant memory card integrated voltage level translator with EMI filter and ESD protection; SD 3.0的存储器卡积分的电压电平与EMI滤波器和ESD保护翻译
| 型号： | IP4855CX25 |
| 厂家： | 
NXP |
| 描述： | SD 3.0-compliant memory card integrated voltage level translator with EMI filter and ESD protection |
| 文件： | 总29页 (文件大小：245K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IP4855CX25
SD 3.0-compliant memory card integrated voltage level
translator with EMI filter and ESD protection
Rev. 1 — 13 September 2012
Product data sheet
1. General description
The device is an SD 3.0-compliant 6-bit bidirectional dual voltage level translator. It is
designed to interface between a memory card operating at 1.8 V or 2.9 V signal levels and
a host with a fixed nominal supply voltage of 1.2 V to 3.3 V. The device supports SD 3.0
SDR50, DDR50, SDR25, SDR12 and SD 2.0 High-Speed (50 MHz) and Default-Speed
(25 MHz) modes. The device has an integrated switchable voltage regulator to supply the
card-side I/Os, built-in EMI filters and robust ESD protections (IEC 61000-4-2, level 4).
2. Features and benefits
Supports up to 100 MHz clock rate
Feedback channel for clock synchronization
SD 3.0 specification-compliant voltage translation to support SDR50, DDR50, SDR25,
SDR12, High-Speed and Default-Speed modes
Low dropout voltage regulator to supply the card-side I/Os
Low power consumption by push-pull output stage with break-before-make
architecture
Integrated pull-up and pull-down resistors: no external resistors required
Integrated EMI filters suppress higher harmonics of digital I/Os
Integrated 8 kV ESD protection according to IEC 61000-4-2, level 4 on card side
Level shifting buffers keep ESD stress away from the host (zero-clamping concept)
Pb-free, RoHS compliant and free of halogen and antimony (Dark Green compliant)
25-ball WLCSP; pitch 0.4 mm
3. Applications
SD, MMC or microSD memory card interfaces in portable electronic applications
supporting different interface voltage modes of the SD 3.0 specification, such as mobile
and smart phone, digital camera and card reader in (laptop) computer.
4. Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
Version
IP4855CX25/P
WLCSP25 wafer level chip-size package; 25 bumps (5 5) IP4855CX25
[1] Size 2.04 2.04 0.5 mm
IP4855CX25
NXP Semiconductors
SD 3.0-compliant memory card integrated dual voltage level translator
5. Block diagram
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Fig 1. Application diagram
IP4855CX25
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 13 September 2012
2 of 29
IP4855CX25
NXP Semiconductors
SD 3.0-compliant memory card integrated dual voltage level translator
6. Functional diagram
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Fig 2. Functional diagram
IP4855CX25
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 13 September 2012
3 of 29
IP4855CX25
NXP Semiconductors
SD 3.0-compliant memory card integrated dual voltage level translator
7. Pinning information
7.1 Pinning
bump A1
index area
1
2
3
4
5
A
B
C
D
E
008aaa193
transparent top view,
solder balls facing down
Fig 3. Pin configuration WLCSP25
Table 2. Pin allocation table
Pin Symbol
A1 DATA2_H
B1 DATA3_H
C1 CLK_IN
D1 DATA0_H
E1 DATA1_H
Pin Symbol
A2 DIR_CMD
B2 SEL
Pin Symbol
A3 DIR_0
B3 VCCA
C3 GND
Pin Symbol
A4 VSUPPLY
B4 VLDO
Pin Symbol
A5 DATA2_SD
B5 DATA3_SD
C5 CLK_SD
C2 ENABLE
D2 CMD_H
E2 CLK_FB
C4 VSD_REF
D4 CMD_SD
E4 WP
D3 CD
D5 DATA0_SD
E5 DATA1_SD
E3 DIR_1_3
7.2 Pin description
Table 3.
Symbol [1]
DATA2_H
DIR_CMD
DIR_0
Pin description
Pin
A1
A2
A3
A4
A5
B1
B2
B3
B4
B5
Type [2] Description
I/O
I
data 2 input or output on host side
direction control input for command
direction control input for data 0
I
VSUPPLY
DATA2_SD
DATA3_H
SEL
S
supply voltage (from battery or regulator)
I/O
I/O
I
data 2 input or output on memory card side
data 3 input or output on host side
card side I/O voltage level select
supply voltage from host side
VCCA
S
VLDO
O
I/O
internal supply decoupling
DATA3_SD
data 3 input or output on memory card side
IP4855CX25
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 13 September 2012
4 of 29
IP4855CX25
NXP Semiconductors
SD 3.0-compliant memory card integrated dual voltage level translator
Table 3.
Pin description …continued
Symbol [1]
CLK_IN
ENABLE
GND
Pin
C1
C2
C3
C4
C5
D1
D2
D3
D4
D5
E1
E2
E3
E4
E5
Type [2] Description
I
clock signal input on host side
I
device enable input
S
supply ground
VSD_REF
CLK_SD
DATA0_H
CMD_H
CD
I
reference voltage for the internal voltage regulator
clock signal output on memory card side
data 0 input or output on host side
command input or output on host side
card detect switch biasing output
O
I/O
I/O
O
CMD_SD
DATA0_SD
DATA1_H
CLK_FB
DIR_1_3
WP
I/O
I/O
I/O
O
command input or output on memory card side
data 0 input or output on memory card side
data 1 input or output on host side
clock feedback output on host side
direction control input for data 1, data 2, data 3
write protect switch biasing output
data 1 input or output on memory card side
I
O
DATA1_SD
I/O
[1] The pin names relate particularly to SD memory cards, but also apply to microSD and MMC memory cards.
[2] I = input, O = output, I/O = input and output, S = power supply
8. Functional description
8.1 Level translator
The bidirectional level translator shifts the data between the I/O supply levels of the host
and the memory card. Dedicated direction control signals determine if a command and
data signals are transferred from the memory card to the host (card read mode) or from
the host to the memory card (card write mode). The voltage translator has to support
several clock and data transfer rates at the signaling levels specified in the SD 3.0
standard specification.
Table 4.
Supported modes
Bus speed mode
Default-Speed
High-Speed
SDR12
Signal level (V)
Clock rate (MHz)
Data rate (MB/s)
3.3
3.3
1.8
1.8
1.8
1.8
25
50
25
50
100
50
12.5
25
12.5
25
SDR25
SDR50
50
DDR50
50
IP4855CX25
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 13 September 2012
5 of 29
IP4855CX25
NXP Semiconductors
SD 3.0-compliant memory card integrated dual voltage level translator
8.2 Enable and direction control
The pin ENABLE enables/disables the Low DropOut (LDO) and is used to put the
host-side, card-side I/O drivers into high-ohmic 3-state mode.
Table 5.
Control
Pin
I/O function control signal truth table
Host-side
Memory card-side
Level[1]
Pin
Function
Pin
Function
Pin ENABLE = HIGH and VCCA 1.62 V
DIR_CMD
DIR_0
H
L
CMD_H
input
CMD_SD
CMD_SD
DATA0_SD
DATA0_SD
output
input
CMD_H
output
input
H
L
DATA0_H
DATA0_H
output
input
output
input
DIR_1_3
H
DATA1_H
DATA2_H
DATA3_H
DATA1_SD
DATA2_SD
DATA3_SD
output
L
DATA1_H
DATA2_H
DATA3_H
output
DATA1_SD
DATA2_SD
DATA3_SD
input
-
-
-
-
CLK_IN
CLK_FB
input
CLK_SD
-
output
-
output
Pin ENABLE = LOW or VCCA 0.8 V
DIR_CMD
DIR_0
X
X
X
CMD_H
high-ohmic
high-ohmic
high-ohmic
CMD_SD
high-ohmic
high-ohmic
high-ohmic
DATA0_H
DATA0_SD
DIR_1_3
DATA1_H
DATA2_H
DATA3_H
DATA1_SD
DATA2_SD
DATA3_SD
-
-
-
-
CLK_IN
CLK_IN
input
CLK_SD
-
high-ohmic
-
high-ohmic
[1] H = HIGH; L = LOW and X = irrelevant.
8.3 Integrated voltage regulator
The low dropout voltage regulator delivers supply voltage for the voltage translators and
the card-side input/output stages. It has to support 1.8 V and 3 V signaling modes as
stipulated in the SD 3.0 specification. The switching time between the two output voltage
modes is compliant with SD 3.0 specification. Depending on the signaling level at pin
SEL, the regulator delivers 1.8 V (SEL = HIGH) or 2.9 V (SEL = LOW, VSD_REF < 1 V). For
card supply voltage, see Section 8.4.
Table 6.
Input
SEL[1]
H
SD card side voltage level control signal truth table
Output
VSD_REF
VLDO
Pin[2]
Function
irrelevant 1.8 V
DATA0_SD to DATA3_SD, CLK_SD
DATA0_SD to DATA3_SD, CLK_SD
DATA0_SD to DATA3_SD, CLK_SD
low supply voltage level (1.8 Vtyp)
L
< 1 V
2.9 V
high supply voltage level (2.9 Vtyp)
> 1.5 V
VSD_REF
supply voltage level based on VSD_REF
[1] H = HIGH and L = LOW.
[2] Host-side pins are not influenced by SEL.
IP4855CX25
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 13 September 2012
6 of 29
IP4855CX25
NXP Semiconductors
SD 3.0-compliant memory card integrated dual voltage level translator
8.4 Memory card voltage tracking (reference select)
The device can track the memory card supply via pin VSD_REF. This allows achieving
optimum interoperability by perfectly matching input/output levels between voltage
translator and memory card in the 3 V signaling mode. Therefore, the voltage regulator
aims to follow the reference voltage provided at input VSD_REF directly . If tracking of the
memory card supply is not desired, connect pin VSD_REF to ground so the voltage
regulator refers to an integrated voltage reference. For 1.8 V (SEL = HIGH) signaling, the
voltage regulator is referred to the internal reference which is independent of the voltage
at VSD_REF.
8.5 Feedback clock channel
The clock is transmitted from the host to the memory card side. The voltage translator and
the Printed-Circuit Board (PCB) tracks introduce some amount of delay. It reduces timing
margin for data read back from memory card, especially at higher data rates. Therefore, a
feedback path is provided to compensate the delay. The reasoning behind this approach
is the fact that the clock is always delivered by the host, while the data in the timing critical
read mode comes from the card.
8.6 EMI filter
All input/output driver stages are equipped with EMI filters to reduce interferences towards
sensitive mobile communication.
8.7 ESD protection
The device has robust ESD protections on all memory card pins as well as on the VSD_REF
and VSUPPLY pins. The architecture prevents any stress for the host: the voltage translator
discharges any stress to supply ground.
Pins Write Protect (WP) and Card Detection (CD) might be pulled down by the memory
card which has to be detected by the host. Both signals must be HIGH if no card is
inserted. Therefore the pins are equipped with International Electrotechnical
Commission (IEC) system-level ESD protections and pull-up resistors connected to the
host supply VCCA
.
IP4855CX25
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 13 September 2012
7 of 29
IP4855CX25
NXP Semiconductors
SD 3.0-compliant memory card integrated dual voltage level translator
9. Limiting values
Table 7.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
Max
Unit
VCC
supply voltage
4 ms transient
on pin VSUPPLY
0.5
0.5
0.5
-
+6.0
+4.6
+4.6
1000
+150
+85
V
on pin VCCA
V
VI
input voltage
4 ms transient at I/O pins
Tamb = 40 C to +85 C
V
Ptot
total power dissipation
storage temperature
ambient temperature
mW
C
C
V
Tstg
Tamb
VESD
55
40
[1]
electrostatic discharge
voltage
IEC 61000-4-2, level 4, all memory card-side pins,
VSUPPLY, VSD_REF, WP and CD to ground
8000 +8000
Human Body Model (HBM)
2000 +2000
V
JEDEC JESD22-A114F; all pins
Machine Model (MM) JEDEC JESD22-A115;
all pins
200
100
+200
+100
V
Ilu(IO)
input/output latch-up current JESD 78B: 0.5 VCC < VI < 1.5 VCC; Tj < 125 C
mA
[1] All system level tests are performed with the application-specific capacitors connected to the supply pins VSUPPLY, VLDO and VCCA
.
10. Recommended operating conditions
Table 8.
Operating conditions
Symbol Parameter
Conditions
Min
2.5
1.1
0.3
0.3
-
Typ
Max
Unit
V
[1]
[2]
VCC
supply voltage
input voltage
on pin VSUPPLY
-
5.5
on pin VCCA
-
3.6
V
VI
host side
-
VCCA + 0.3
VO(reg) + 0.3
-
V
memory card side
recommended capacitor at pin VLDO
-
V
Cext
ESR
Cext
external
capacitance
1.0
F
equivalent series at pin VLDO
resistance
0
-
50
mW
external
recommended capacitor at pin VSUPPLY
recommended capacitor at pin VCCA
-
-
0.1
0.1
-
-
F
F
capacitance
[1] By minimum value the device is still fully functional, but the voltage on pin VLDO might drop below the recommended memory card
supply voltage.
[2] The voltage must not exceed 3.6 V.
IP4855CX25
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 13 September 2012
8 of 29
IP4855CX25
NXP Semiconductors
SD 3.0-compliant memory card integrated dual voltage level translator
Table 9.
Integrated resistors
Tamb = 25 C; unless otherwise specified.
Symbol Parameter Conditions
pull-down resistance R7; tolerance 30 %
Min
329
70
Typ
470
100
350
350
Max Unit
Rpd
611
130
500
500
k
R30; tolerance 30 %
R38; tolerance 30 %
200
200
k
k
R20, R21; tolerance 30 %
R10; tolerance 30 %
Rpu
pull-up resistance
series resistance
10.5 15
19.5 k
R11 to R13; tolerance 30 %
R14 and R15; tolerance 30 %
49
70
32
70
91
k
k
100
40
130
48
[1]
[1]
Rs
card side; R1 to R6;
tolerance 20 %
host side; R31 to R37;
26
33
40
tolerance 20 %
[1] Guaranteed by design and characterization.
11. Static characteristics
Table 10. Static characteristics
At recommended operating conditions; Tamb = 40 C to +85 C; voltages are referenced to GND (ground = 0 V);
Cext = 1 F at pin VLDO; unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ[1]
Max
Unit
Supply voltage regulator for card-side I/O pin: VLDO
VO(reg)
regulator output
voltage
SEL = LOW; VSD_REF < 1 V; VSUPPLY 2.9 V
2.75
2.9
3.0
V
V
SEL = LOW; VSD_REF > 1.5 V;
VSD_REF VSD_REF VSD_REF
VSUPPLY VSD_REF
0.15
+ 0.05
1.95
150
SEL = HIGH; VSUPPLY 2.5 V
1.7
-
1.8
-
V
Vdo(reg) regulator dropout
voltage
SEL = LOW; VSUPPLY 2.9 V; IO = 50 mA
mV
Host-side input signals: CMD_H and DATA0_H to DATA3_H, CLK_IN
VIH
VIL
ILI
HIGH-level input
voltage
0.625
VCCA
-
-
-
VCCA
0.3
+
V
LOW-level input
voltage
0.3
0.25
VCCA
V
input leakage current VCCA = 1.8 V; ENABLE = LOW
-
1.0
nA
Host-side control signals
SEL, ENABLE, DIR_0, DIR_1_3, DIR_CMD
VIH
HIGH-level input
voltage
0.625
VCCA
-
-
VCCA
0.3
+
V
V
VIL
LOW-level input
voltage
0.3
0.35
VCCA
VSD_REF
VIH
HIGH-level input
voltage
1.5
-
-
3.63
1.0
V
V
VIL
LOW-level input
voltage
0.3
IP4855CX25
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 13 September 2012
9 of 29
IP4855CX25
NXP Semiconductors
SD 3.0-compliant memory card integrated dual voltage level translator
Table 10. Static characteristics …continued
At recommended operating conditions; Tamb = 40 C to +85 C; voltages are referenced to GND (ground = 0 V);
Cext = 1 F at pin VLDO; unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ[1]
Max
Unit
Host-side output signals: CLK_FB, CMD_H and DATA0_H to DATA3_H
VOH
VOL
HIGH-level output
voltage
IO = 2 mA; VI = VIH (card side)
0.75
VCCA
-
V
V
LOW-level output
voltage
IO = 2 mA; VI = VIL (card side)
-
-
0.125
VCCA
Card-side input signals: CMD_SD and DATA0_SD to DATA3_SD
VIH
HIGH-level input
voltage
SEL = LOW (2.9 V interface)
SEL = HIGH (1.8 V interface)
SEL = LOW (2.9 V interface)
SEL = HIGH (1.8 V interface)
0.625
VO(reg)
-
-
-
-
VO(reg)
0.3
+
V
V
V
V
0.625
VO(reg)
VO(reg)
0.3
+
VIL
LOW-level input
voltage
0.3
0.3
0.25
VO(reg)
0.25
VO(reg)
Card-side output signal
CMD_SD and DATA0_SD to DATA3_SD, CLK_SD
VOH
HIGH-level output
voltage
IO = 4 mA; VI = VIH (host side); SEL = LOW
(2.9 V interface)
0.75
VO(reg)
-
-
-
-
-
VO(reg)
0.3
+
+
V
IO = 2 mA; VI = VIH (host side); SEL = HIGH
(1.8 V interface)
0.75
VO(reg)
VO(reg)
0.3
V
VOL
LOW-level output
voltage
IO = 4 mA; VI = VIL (host side); SEL = LOW
(2.9 V interface)
0.3
0.3
-
0.125
VO(reg)
V
IO = 2 mA; VI = VIL (host side); SEL = HIGH
(1.8 V interface)
0.125
VO(reg)
V
IO(sc)
short-circuit output
current
card-side pins connected to ground;
host-side input signals = HIGH;
VSD_REF = 3.6 V; VSUPPLY = 5.5 V;
VCCA = 3.6 V; SEL = LOW;
100
mA
DIR_1_3, DIR_CMD, DIR_0 = HIGH
Bus signal equivalent capacitance
[2]
Cch
channel capacitance VI = 0 V; fi = 1 MHz; VSUPPLY = 3.5 V;
V
CCA = 1.8 V
host side
card side
-
-
3.5
5
5
pF
pF
10
Current consumption
ICC(stat) static supply current
ENABLE = HIGH (active mode);
all inputs = HIGH; DIR = LOW
SEL = LOW (2.9 V interface)
SEL = HIGH (1.8 V interface)
ENABLE = LOW (inactive mode)
-
-
-
-
-
-
100
100
1
A
A
A
ICC(stb)
standby supply
current
[1] Typical values are measured at Tamb = 25 C.
[2] EMI filter line capacitance per data channel from I/O driver to pin; Cch is guaranteed by design.
IP4855CX25
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 13 September 2012
10 of 29
IP4855CX25
NXP Semiconductors
SD 3.0-compliant memory card integrated dual voltage level translator
12. Dynamic characteristics
12.1 Voltage regulator
Table 11. Voltage regulator
T
amb = 25 C; unless otherwise specified.
Symbol Parameter Conditions
Voltage regulator output pin: VLDO
Min
Typ
Max
Unit
tstartup(reg)
regulator start-up time VCCA = 1.8 V; VSUPPLY = 3.5 V;
-
-
-
-
-
-
100
1
s
ms
s
Cext = 1 F; see Figure 5
tf(o)
output fall time
output rise time
VO(reg) = 2.9 V to 1.8 V;
SEL = LOW to HIGH; see Figure 4
tr(o)
VO(reg) = 1.8 V to 2.9 V;
100
SEL = HIGH to LOW; see Figure 4
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V
I
50 %
ENABLE
GND
t
startup(reg)
V
O(reg)
97 %
regulator
output
0 V
001aah981
Measuring points: ENABLE signal at 0.5 VCCA and regulator output signal at 0.97 VO(reg)
.
Fig 5. Regulator start-up time
IP4855CX25
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 13 September 2012
11 of 29
IP4855CX25
NXP Semiconductors
SD 3.0-compliant memory card integrated dual voltage level translator
12.2 ESD characteristic of pin write protect and card detect
Table 12. ESD characteristic of write protect and card detect
At recommended operating conditions; Tamb = +25 C; voltages are referenced to
GND (ground = 0 V); unless otherwise specified
Symbol Parameter
Conditions
Min
Typ
Max Unit
ESD protection pins: WP and CD
VBR
rdyn
breakdown voltage
dynamic resistance
TLP; I = 1 mA
-
-
-
8
-
-
-
V
[1]
[1]
positive transient
negative transient
0.5
0.5
[1] TLP according to ANSI-ESD STM5.5.1/IEC 62615 Zo = 50 ; pulse width = 100 ns; rise time = 200 ps;
averaging window = 50 ns to 80 ns
13. Application information
The IP4855CX25 is optimized to connect SD 3.0 and SD 2.0 compatible memory cards to
1.8 V base band/host interfaces. While the internal I/O interface towards the memory card
is supplied by the IP4855CX25 integrated voltage regulator, any connected memory card
has to be supplied from an external source. Using for example DDR50 or SDR50 modes
requires a power supply with up to 400 mA DC current capabilities.
Place IP4855CX25 as close as possible to the card holder to minimize the influence of
trace length on the timing values. The trace length between IP4855CX25 and the card
has a much bigger influence on the timing than the identical length between the host
interface and the IP4855CX25.
IP4855CX25
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 13 September 2012
12 of 29
IP4855CX25
NXP Semiconductors
SD 3.0-compliant memory card integrated dual voltage level translator
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Fig 6. IP4855CX25 application diagram and output driver structure
One main task of the level translator is to shift the signal within the SD 3.0 specification.
Therefore, the following simulation results show the low impact of the device. Use the
clock feedback channel for a compensation of delay introduced by PCB traces and
IP4855CX25.
IP4855CX25
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 13 September 2012
13 of 29
IP4855CX25
NXP Semiconductors
SD 3.0-compliant memory card integrated dual voltage level translator
13.1 Simulation setup for transition time, propagation delay and
set-up/hold times
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a. Host-side to card-side simulation setup
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b. Card-side to host-side simulation setup
Fig 7. Timing simulation setup
2
2
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Fig 8. Output rise and fall times
IP4855CX25
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 13 September 2012
14 of 29
IP4855CX25
NXP Semiconductors
SD 3.0-compliant memory card integrated dual voltage level translator
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Fig 9. Set-up, hold and output delay timing
IP4855CX25
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 13 September 2012
15 of 29
IP4855CX25
NXP Semiconductors
SD 3.0-compliant memory card integrated dual voltage level translator
13.2 Interface voltage timing data
Table 13. Output rise and fall times card side
VSUPPLY = 4 V; unless otherwise specified; track impedance 35 , track length (to and from IP4855CX25) 15 mm;
Rsource = 50 ; see Figure 7 for set-up circuit and Figure 8 for timing diagram; VCCA = 1.8 V; transition time is the same as
output rise time and output fall time
Symbol Parameter
Conditions
Min.
Typ
Max
Unit
Memory card-side output pins: CLK_SD, CMD_SD and DATA0_SD to DATA3_SD; 2.9 V mode (SEL = LOW)
Reference points at 20 % and 70 %
tt
transition time
CL = 10 pF
nominal case; Tamb = +25 C; VLDO = 2.9 V
best case; Tamb = 40 C; VLDO = 3.6 V
worst case; Tamb = +85 C; VLDO = 2.7 V
CL = 20 pF
0.8
0.8
0.8
1.1
1.0
1.1
1.3
1.2
1.3
ns
ns
ns
[1]
nominal case; Tamb = +25 C; VLDO = 2.9 V
best case; Tamb = 40 C; VLDO = 3.6 V
worst case; Tamb = +85 C; VLDO = 2.7 V
1.4
1.3
1.4
1.6
1.6
1.6
1.9
1.8
1.9
ns
ns
ns
Reference points at 10 % and 90 % [2]
tt
transition time
CL = 10 pF
nominal case; Tamb = +25 C; VLDO = 2.9 V
best case; Tamb = 40 C; VLDO = 3.6 V
worst case; Tamb = +85 C; VLDO = 2.7 V
CL = 20 pF
1.9
1.9
2.0
2.1
2.0
2.2
2.4
2.2
2.4
ns
ns
ns
[1]
nominal case; Tamb = +25 C; VLDO = 2.9 V
best case; Tamb = 40 C; VLDO = 3.6 V
worst case; Tamb = +85 C; VLDO = 2.7 V
2.9
2.9
2.9
3.1
3.0
3.2
3.4
3.2
3.5
ns
ns
ns
Memory card-side output pins: CLK_SD, CMD_SD and DATA0_SD to DATA3_SD; 1.8 V mode (SEL = HIGH)
Reference points at 20 % and 70 %
tt
transition time
CL = 10 pF
nominal case; Tamb = +25 C; VLDO = 1.8 V
best case; Tamb = 40 C; VLDO = 1.95 V
worst case; Tamb = +85 C; VLDO = 1.7 V
CL = 20 pF
0.8
0.8
0.8
1.1
1.0
1.1
1.3
1.2
1.3
ns
ns
ns
[1]
tt
transition time
nominal case; Tamb = +25 C; VLDO = 1.8 V
best case; Tamb = 40 C; VLDO = 1.95 V
worst case; Tamb = +85 C; VLDO = 1.7 V
1.4
1.3
1.4
1.6
1.6
1.6
1.9
1.8
1.9
ns
ns
ns
Reference points at 10 % and 90 % [2]
tt
transition time
CL = 10 pF
nominal case; Tamb = +25 C; VLDO = 1.8 V
best case; Tamb = 40 C; VLDO = 1.95 V
worst case; Tamb = +85 C; VLDO = 1.7 V
1.9
1.9
2.0
2.1
2.0
2.2
2.4
2.2
2.4
ns
ns
ns
IP4855CX25
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 13 September 2012
16 of 29
IP4855CX25
NXP Semiconductors
SD 3.0-compliant memory card integrated dual voltage level translator
Table 13. Output rise and fall times card side …continued
VSUPPLY = 4 V; unless otherwise specified; track impedance 35 , track length (to and from IP4855CX25) 15 mm;
Rsource = 50 ; see Figure 7 for set-up circuit and Figure 8 for timing diagram; VCCA = 1.8 V; transition time is the same as
output rise time and output fall time
Symbol Parameter
tt transition time
Conditions
Min.
Typ
Max
Unit
[1]
CL = 20 pF
nominal case; Tamb = +25 C; VLDO = 1.8 V
best case; Tamb = 40 C; VLDO = 1.95 V
worst case; Tamb = +85 C; VLDO = 1.7 V
2.9
2.9
2.9
3.1
3.0
3.2
3.4
3.2
3.5
ns
ns
ns
[1] A capacitive load of CL = 20 pF is out of the range of allowed SD-card interface parasitic capacitance.
Table 14. Output rise and fall times host side
VSUPPLY = 4.0 V; SEL = LOW; VO(reg) = 2.9 V; unless otherwise specified; track impedance 35 , track length (to and from
IP4855CX25) 15 mm; Rsource = 50 ; see Figure 7 for set-up circuit and Figure 8 timing diagram;
transition time is the same as output rise time and output fall time
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Host-side output pins: CLK_FB, CMD_H and DATA0_H to DATA3_H (3.3 V host)
Reference points at 20 % and 70 %
tt
transition time
CL = 5 pF
nominal case; Tamb = +25 C; VCCA = 3.3 V
best case; Tamb = 40 C; VCCA = 3.6 V
worst case; Tamb = +85 C; VCCA = 2.7 V
0.5
0.5
0.5
0.6
0.6
0.6
0.7
0.7
0.7
ns
ns
ns
Reference points at 10 % and 90 % [1]
tt
transition time
CL = 5 pF
nominal case; Tamb = +25 C; VCCA = 3.3 V
best case; Tamb = 40 C; VCCA = 3.6 V
worst case; Tamb = +85 C; VCCA = 2.7 V
1.0
1.0
1.3
1.3
1.2
1.4
1.5
1.4
1.6
ns
ns
ns
Host-side output pins: CLK_FB, CMD_H and DATA0_H to DATA3_H (1.8 V host)
Reference points at 20 % and 70 %
tt
transition time
CL = 5 pF
nominal case; Tamb = +25 C; VCCA = 1.8 V
best case; Tamb = 40 C; VCCA = 1.9 V
worst case; Tamb = +85 C; VCCA = 1.62 V
0.5
0.5
0.5
0.6
0.6
0.6
0.7
0.7
0.7
ns
ns
ns
Reference points at 10 % and 90 % [1]
tt
transition time
CL = 5 pF
nominal case; Tamb = +25 C; VCCA = 1.8 V
best case; Tamb = 40 C; VCCA = 1.9 V
worst case; Tamb = +85 C; VCCA = 1.62 V
1.0
1.0
1.3
1.3
1.2
1.4
1.5
1.4
1.6
ns
ns
ns
[1] Reference points 90 % and 10 % are not required according to the SD 3.0 specification.
IP4855CX25
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 13 September 2012
17 of 29
IP4855CX25
NXP Semiconductors
SD 3.0-compliant memory card integrated dual voltage level translator
13.3 DDR50 mode timing details
The Default-Speed (DS) and High-Speed (HS) modes use 3.3 V signaling and offer a
maximum of 25 MB/s. Besides these modes, IP4855CX25 also supports the SDR12,
SDR25 and DDR50 modes using 1.8 V signaling and up to 50 MB/s.
Especially the DDR50 mode introduces a basic change in the timing behavior of the
SD card interface. The SDR12 and SDR50 modes are similar to the DS and HS modes.
Any delay on all relevant signal lines (as shown in the timing diagram in Figure 10) is
uncritical for SD card write operations as long as the skew between the different signals is
small enough.
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Fig 10. DDR50 write timing diagram
IP4855CX25
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 13 September 2012
18 of 29
IP4855CX25
NXP Semiconductors
SD 3.0-compliant memory card integrated dual voltage level translator
In contrast to the write cycle, the read cycle is more complex to analyze and depends on
the IP4855CX25 delay, the maximum delay added by the PCB and the additional setup
time of the SD card.
Table 15. DDR50 read mode: parameters for best case and worst case timings
Parameter
Best case timing (Figure 11) Worst case timing (Figure 12)
PCB output impedance Zo
Symmetrical trace length
tPD
65
25
15 mm per side
minimum
fast
100 mm per side
maximum
slow
Driver model
The same mechanism is triggered on each falling clock edge too, as the DDR50 mode
uses both edges of the clock signal for data transfer.
According to the SD 3.01 physical layer specification, the maximum delay between
CLK_IN (CLK_SD signal) at the SD card and data out from the SD card (DATA[3:0]_SD
out) is 7.0 ns. This value is specified for a load of CL 25 pF.
IP4855CX25
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 13 September 2012
19 of 29
IP4855CX25
NXP Semiconductors
SD 3.0-compliant memory card integrated dual voltage level translator
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PCB Zo = 65 , trace length = 15 mm, tPD = minimum, fast driver model
Fig 11. Detailed description of a DDR50 read cycle, best case timing
IP4855CX25
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Product data sheet
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NXP Semiconductors
SD 3.0-compliant memory card integrated dual voltage level translator
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PCB Zo = 25 , trace length = 100 mm, tPD = maximum, slow driver model
Fig 12. Detailed description of a DDR50 read cycle, worst case timing
IP4855CX25
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Product data sheet
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NXP Semiconductors
SD 3.0-compliant memory card integrated dual voltage level translator
14. Test information
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Definitions test circuit:
Rsource = source resistance of pulse generator.
Rterm = termination resistance should be equal to output impedance Zo of pulse generator.
CL = load capacitance including jig and probe capacitance.
RL = load resistance.
Fig 13. Load circuitry for measuring switching time
IP4855CX25
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Product data sheet
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IP4855CX25
NXP Semiconductors
SD 3.0-compliant memory card integrated dual voltage level translator
15. Package outline
WLCSP25: wafer level chip-size package; 25 bumps (5 x 5)
D
bump A1
index area
A
2
E
A
A
1
detail X
e
1
e
b
E
D
C
B
A
e
e
1
X
1
2
3
4
5
European
projection
wlcsp25_5x5_po
Fig 14. Package outline IP4855CX25 (WLCSP25)
Table 16. Dimensions of IP4855CX25 for Figure 14
Symbol
Min
0.44
0.18
0.25
0.21
1.99
1.99
-
Typ
0.47
0.20
0.27
0.26
2.04
2.04
0.4
Max
0.50
0.22
0.29
0.31
2.09
2.09
-
Unit
mm
mm
mm
mm
mm
mm
mm
A
A1
A2
b
D
E
e
IP4855CX25
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Product data sheet
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IP4855CX25
NXP Semiconductors
SD 3.0-compliant memory card integrated dual voltage level translator
16. Design and assembly recommendations
16.1 PCB design guidelines
For optimum performance, use a Non-Solder Mask PCB Design (NSMD), also known as a
copper-defined design, incorporating laser-drilled micro-vias connecting the ground pads
to a buried ground-plane layer. This results in the lowest possible ground inductance and
provides the best high frequency and ESD performance. For this case, refer to Table 17
for the recommended PCB design parameters.
Table 17. Recommended PCB design parameters
Parameter
Value or Specification [1]
PCB pad diameter
Micro-via diameter
Solder mask aperture diameter
Copper thickness
Copper finish
250 m
100 m (0.004 inch)
325 m
20 m to 40 m
AuNi or OSP
FR4
PCB material
[1] OSP: Organic Solderability Preservation
FR4: Flame Retard 4
16.2 PCB assembly guidelines for Pb-free soldering
Table 18. Assembly recommendations
Parameter
Value or Specification
Solder screen aperture diameter
Solder screen thickness
Solder paste: Pb-free
Solder/flux ratio
290 m
100 m (0.004 inch)
SnAg (3 % to 4 %) Cu (0.5 % to 0.9 %)
50/50
Solder reflow profile
see Figure 15
IP4855CX25
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Product data sheet
Rev. 1 — 13 September 2012
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IP4855CX25
NXP Semiconductors
SD 3.0-compliant memory card integrated dual voltage level translator
T
(°C)
reflow(peak)
250
T
230
217
cooling rate
pre-heat
t (s)
t
t
3
1
t
2
t
t
4
5
001aai161
The device can withstand at least three reflows of this profile.
Fig 15. Pb-free solder reflow profile
Table 19. Reflow soldering process characteristics
Symbol
Parameter
Conditions
Min
Typ
Max Unit
Treflow(peak) peak reflow temperature
230
60
-
-
-
-
-
-
-
-
-
260
180
30
C
s
t1
time 1
time 2
time 3
time 4
time 5
soak time
t2
time during T 250 C
time during T 230 C
time during T > 217 C
s
t3
10
30
-
50
s
t4
150
540
6
s
t5
s
dT/dt
rate of change of
temperature
cooling rate
pre-heat
-
C/s
C/s
2.5
4.0
17. Abbreviations
Table 20. Abbreviations
Acronym
DUT
Description
Device Under Test
EMI
ElectroMagnetic Interference
ElectroStatic Discharge
Flame Retard 4
ESD
FR4
MMC
NSMD
OSP
MultiMedia Card
Non-Solder Mask Design
Organic Solderability Preservation
Printed-Circuit Board
PCB
RoHS
SD
Restriction of Hazardous Substances
Secure Digital
WLCSP
Wafer-Level Chip-Scale Package
IP4855CX25
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Product data sheet
Rev. 1 — 13 September 2012
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IP4855CX25
NXP Semiconductors
SD 3.0-compliant memory card integrated dual voltage level translator
18. Revision history
Table 21. Revision history
Document ID
Release date
20120913
Data sheet status
Change notice
Supersedes
IP4855CX25 v.1
Product data sheet
-
-
IP4855CX25
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Product data sheet
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IP4855CX25
NXP Semiconductors
SD 3.0-compliant memory card integrated dual voltage level translator
19. Legal information
19.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use — NXP Semiconductors products are not designed,
19.2 Definitions
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
19.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
IP4855CX25
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 13 September 2012
27 of 29
IP4855CX25
NXP Semiconductors
SD 3.0-compliant memory card integrated dual voltage level translator
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
19.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
20. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
IP4855CX25
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Product data sheet
Rev. 1 — 13 September 2012
28 of 29
IP4855CX25
NXP Semiconductors
SD 3.0-compliant memory card integrated dual voltage level translator
21. Contents
1
2
3
4
5
6
General description. . . . . . . . . . . . . . . . . . . . . . 1
21
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
7
7.1
7.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
8
Functional description . . . . . . . . . . . . . . . . . . . 5
Level translator. . . . . . . . . . . . . . . . . . . . . . . . . 5
Enable and direction control. . . . . . . . . . . . . . . 6
Integrated voltage regulator . . . . . . . . . . . . . . . 6
Memory card voltage tracking
8.1
8.2
8.3
8.4
(reference select) . . . . . . . . . . . . . . . . . . . . . . . 7
Feedback clock channel. . . . . . . . . . . . . . . . . . 7
EMI filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . 7
8.5
8.6
8.7
9
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8
Recommended operating conditions. . . . . . . . 8
Static characteristics. . . . . . . . . . . . . . . . . . . . . 9
10
11
12
12.1
12.2
Dynamic characteristics . . . . . . . . . . . . . . . . . 11
Voltage regulator. . . . . . . . . . . . . . . . . . . . . . . 11
ESD characteristic of pin write protect and card
detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
13
13.1
Application information. . . . . . . . . . . . . . . . . . 12
Simulation setup for transition time, propagation
delay and set-up/hold times . . . . . . . . . . . . . . 14
Interface voltage timing data. . . . . . . . . . . . . . 16
DDR50 mode timing details . . . . . . . . . . . . . . 18
13.2
13.3
14
15
Test information. . . . . . . . . . . . . . . . . . . . . . . . 22
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 23
16
16.1
16.2
Design and assembly recommendations . . . 24
PCB design guidelines . . . . . . . . . . . . . . . . . . 24
PCB assembly guidelines for Pb-free
soldering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
17
18
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 25
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 26
19
Legal information. . . . . . . . . . . . . . . . . . . . . . . 27
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 27
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 28
19.1
19.2
19.3
19.4
20
Contact information. . . . . . . . . . . . . . . . . . . . . 28
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2012.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 13 September 2012
Document identifier: IP4855CX25
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