IRFZ44NS/T3 [NXP]

TRANSISTOR 49 A, 55 V, 0.022 ohm, N-CHANNEL, Si, POWER, MOSFET, FET General Purpose Power;


型号：	IRFZ44NS/T3
厂家：	NXP
描述：	TRANSISTOR 49 A, 55 V, 0.022 ohm, N-CHANNEL, Si, POWER, MOSFET, FET General Purpose Power 开关脉冲晶体管
文件：	总8页 (文件大小：57K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Philips Semiconductors

Product specification

N-channel enhancement mode

TrenchMOS^TMtransistor

IRFZ44NS

GENERAL DESCRIPTION

QUICK REFERENCE DATA

N-channel enhancement mode

standard level field-effect power

transistor in a surface mounting

plastic envelope using ’trench’

technology. The device features very

low on-state resistance and has

integral zener diodes giving ESD

protection up to 2kV. It is intended for

useinswitchedmodepowersupplies

and general purpose switching

applications.

SYMBOL

PARAMETER

MAX.

UNIT

V_DS

I_D

P_tot

T_j

Drain-source voltage

Drain current (DC)

Total power dissipation

Junction temperature

Drain-source on-state

110

175

˚C

mΩ

R_DS(ON)

resistance

V_GS= 10 V

PINNING - SOT404 (D²PAK)

PIN CONFIGURATION

SYMBOL

DESCRIPTION

gate

drain

source

mb drain

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

V_DS

V_DGR

±V_GS

I_D

I_DM

Drain-source voltage

Drain-gate voltage

Gate-source voltage

Drain current (DC)

160

110

175

˚C

R_GS= 20 kΩ

T_mb= 25 ˚C

T_mb= 100 ˚C

T_mb= 25 ˚C

Drain current (DC)

Drain current (pulse peak value)

Total power dissipation

Storage & operating temperature

P_tot

T_stg, T_j

- 55

ESD LIMITING VALUE

SYMBOL PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

V_C

Electrostatic discharge capacitor

voltage, all pins

Human body model

(100 pF, 1.5 kΩ)

THERMAL RESISTANCES

SYMBOL PARAMETER

CONDITIONS

TYP.

MAX.

UNIT

R_{th j-mb}

Thermal resistance junction to

mounting base

1.4

K/W

R_{th j-a}

Thermal resistance junction to

ambient

Minimum footprint, FR4

board

K/W

February 1999

Rev 1.000

Philips Semiconductors

Product specification

N-channel enhancement mode

TrenchMOS^TMtransistor

IRFZ44NS

STATIC CHARACTERISTICS

T_j= 25˚C unless otherwise specified

SYMBOL PARAMETER

CONDITIONS

MIN. TYP. MAX. UNIT

V_(BR)DSS

V_GS(TO)

Drain-source breakdown

voltage

Gate threshold voltage

V_GS= 0 V; I_D= 0.25 mA;

2.0

1.0

T_j= -55˚C

V_DS= V_GS; I_D= 1 mA

3.0

0.05

0.04

4.0

4.4

500

T_j= 175˚C

T_j= -55˚C

I_DSS

I_GSS

Zero gate voltage drain current V_DS= 55 V; V_GS= 0 V;

Gate source leakage current V_GS= ±10 V; V_DS= 0 V

Gate source breakdown voltage I_G= ±1 mA;

Drain-source on-state

resistance

µA

mΩ

T_j= 175˚C

±V_(BR)GSS

R_DS(ON)

V_GS= 10 V; I_D= 25 A

T_j= 175˚C

DYNAMIC CHARACTERISTICS

T_mb= 25˚C unless otherwise specified

SYMBOL PARAMETER

CONDITIONS

MIN. TYP. MAX. UNIT

g_fs

Forward transconductance

V_DS= 25 V; I_D= 25 A

C_iss

C_oss

C_rss

Input capacitance

Output capacitance

Feedback capacitance

V_GS= 0 V; V_DS= 25 V; f = 1 MHz

1350 1800

330

155

400

215

Q_g

Q_gs

Q_gd

Total gate charge

Gate-cource charge

Gate-drain (miller) charge

V_DD= 44 V; I_D= 50 A; V_GS= 10 V

t_{d on}

t_r

t_{d off}

t_f

Turn-on delay time

Turn-on rise time

Turn-off delay time

Turn-off fall time

V_DD= 30 V; I_D= 25 A;

V_GS= 10 V; R_G= 10 Ω

Resistive load

L_d

L_s

Internal drain inductance

Internal source inductance

Measured from upper edge of drain

tab to centre of die

Measured from source lead

soldering point to source bond pad

2.5

7.5

REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS

T_j= 25˚C unless otherwise specified

SYMBOL PARAMETER

CONDITIONS

MIN. TYP. MAX. UNIT

I_DR

Continuous reverse drain

current

I_DRM

V_SD

Pulsed reverse drain current

Diode forward voltage

160

1.2

I_F= 25 A; V_GS= 0 V

I_F= 40 A; V_GS= 0 V

0.95

1.0

t_rr

Q_rr

Reverse recovery time

Reverse recovery charge

I_F= 40 A; -dI_F/dt = 100 A/µs;

V_GS= -10 V; V_R= 30 V

0.15

µC

February 1999

Rev 1.000

Philips Semiconductors

Product specification

N-channel enhancement mode

TrenchMOS^TMtransistor

IRFZ44NS

AVALANCHE LIMITING VALUE

SYMBOL PARAMETER

CONDITIONS

MIN. TYP. MAX. UNIT

W_DSS

Drain-source non-repetitive

unclamped inductive turn-off

energy

I_D= 45 A; V_DD≤ 25 V;

110

V_GS= 10 V; R_GS= 50 Ω; T_mb= 25 ˚C

Normalised Power Derating

1000

ID/A

PD%

120

110

100

tp =

RDS(ON) =VDS/ID

100

1 us

10us

100 us

1 ms

10ms

100ms

Tmb /

100 120 140 160 180

100

VDS/V

Fig.1. Normalised power dissipation.

PD% = 100 P_D/P_{D 25 ˚C}= f(T_mb)

Fig.3. Safe operating area. T_mb= 25 ˚C

I_D& I_DM= f(V_DS); I_DMsingle pulse; parameter t_p

Zth/(K/W)

Normalised Current Derating

ID%

120

110

100

0.5

0.2

0.1

0.05

D =

0.02

0.01

0.001

100 120 140 160 180

1E-06

0.0001

0.01

t/s

100

Tmb /

Fig.2. Normalised continuous drain current.

ID% = 100 I_D/I_{D 25 ˚C}= f(T_mb); conditions: V_GS≥ 10 V

Fig.4. Transient thermal impedance.

Z_{th j-mb}= f(t); parameter D = t_p/T

February 1999

Rev 1.000

Philips Semiconductors

Product specification

N-channel enhancement mode

TrenchMOS^TMtransistor

IRFZ44NS

100

gfs/S

VGS/V =

ID/A

8.0

7.5

7.0

6.5

8.5

6.0

5.5

5.0

4.5

4.0

100

VDS/V

ID/A

Fig.5. Typical output characteristics, T_j= 25 ˚C.

I_D= f(V_DS); parameter V_GS

Fig.8. Typical transconductance, T_j= 25 ˚C.

g_fs= f(I_D); conditions: V_DS= 25 V

RDS(ON)/mOhm

BUK959-60

Rds(on) normlised to 25degC

2.5

VGS/V =

6.5

1.5

0.5

-100

-50

Tmb / degC

100

150

200

ID/A

Fig.6. Typical on-state resistance, T_j= 25 ˚C.

R_DS(ON)= f(I_D); parameter V_GS

Fig.9. Normalised drain-source on-state resistance.

a = R_DS(ON)/R_{DS(ON)25 ˚C}= f(T_j); I_D= 25 A; V_GS= 10 V

100

ID/A

BUK759-60

VGS(TO) / V

max.

typ.

min.

Tj/C =

175

-100

-50

Tj / C

100

150

200

VGS/V

Fig.7. Typical transfer characteristics.

I_D= f(V_GS) ; conditions: V_DS= 25 V; parameter T_j

Fig.10. Gate threshold voltage.

V_GS(TO)= f(T_j); conditions: I_D= 1 mA; V_DS= V_GS

February 1999

Rev 1.000

Philips Semiconductors

Product specification

N-channel enhancement mode

TrenchMOS^TMtransistor

IRFZ44NS

100

IF/A

Sub-Threshold Conduction

1E-01

1E-02

1E-03

1E-04

1E-05

1E-06

typ

98%

Tj/C =

175

0.2

0.4

0.6

0.8

1.2

1.4

VSDS/V

Fig.11. Sub-threshold drain current.

I_D= f(V_GS); conditions: T_j= 25 ˚C; V_DS= V_GS

Fig.14. Typical reverse diode current.

I_F= f(V_SDS); conditions: V_GS= 0 V; parameter T_j

2.5

WDSS%

120

110

100

1.5

Ciss

ThouandspF

Coss

Crss

100

120

140

160

180

0.01

0.1

100

VDS/V

Tmb /

Fig.12. Typical capacitances, C_iss, C_oss, C_rss.

C = f(V_DS); conditions: V_GS= 0 V; f = 1 MHz

Fig.15. Normalised avalanche energy rating.

W_DSS% = f(T_mb); conditions: I_D= 49 A

VGS/V

VDD

VDS = 14V

VDS

VDS = 44V

VGS

-ID/100

T.U.T.

R 01

RGS

shunt

QG/nC

Fig.16. Avalanche energy test circuit.

W_DSS= 0.5 LI_D²BV_DSS/(BV_DSS− V_DD

Fig.13. Typical turn-on gate-charge characteristics.

V_GS= f(Q_G); conditions: I_D= 50 A; parameter V_DS

)

February 1999

Rev 1.000

Philips Semiconductors

Product specification

N-channel enhancement mode

TrenchMOS^TMtransistor

IRFZ44NS

VDD

VDS

VGS

T.U.T.

Fig.17. Switching test circuit.

February 1999

Rev 1.000

Philips Semiconductors

Product specification

N-channel enhancement mode

TrenchMOS^TMtransistor

IRFZ44NS

MECHANICAL DATA

Plastic single-ended package (Philips version of D2-PAK); 2 leads

SOT404

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

UNIT

4.5

4.1

1.40

1.27

0.85

0.60

0.64

0.46

9.65

8.65

1.6

1.2

10.3

9.7

2.9

2.1

15.4

14.8

2.60

2.20

2.54

REFERENCES

JEDEC

EUROPEAN

PROJECTION

OUTLINE

VERSION

ISSUE DATE

IEC

EIAJ

97-06-16

SOT404

Fig.18. SOT404 surface mounting package. Centre pin connected to mounting base.

Notes

1. This product is supplied in anti-static packaging. The gate-source input must be protected against static

discharge during transport or handling.

2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18.

3. Epoxy meets UL94 V0 at 1/8".

February 1999

Rev 1.000

Philips Semiconductors

Product specification

N-channel enhancement mode

TrenchMOS^TMtransistor

IRFZ44NS

MOUNTING INSTRUCTIONS

Dimensions in mm

11.5

9.0

17.5

2.0

3.8

5.08

Fig.19. SOT404 : soldering pattern for surface mounting.

DEFINITIONS

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and

operation of the device at these or at any other conditions above those given in the Characteristics sections of

this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Philips Electronics N.V. 1999

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the

The information presented in this document does not form part of any quotation or contract, it is believed to be

accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any

consequence of its use. Publication thereof does not convey nor imply any license under patent or other

industrial or intellectual property rights.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices or systems where malfunction of these

products can be reasonably expected to result in personal injury. Philips customers using or selling these products

for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting

from such improper use or sale.

February 1999

Rev 1.000

IRFZ44NS/T3 [NXP]

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