ISP1106W,118 [NXP]
IC LINE TRANSCEIVER, PBCC16, 3 X 3 X 0.65 MM, PLASTIC, MO-217, SOT-639-2, HBCC-16, Line Driver or Receiver;
| 型号： | ISP1106W,118 |
| 厂家： | 
NXP |
| 描述： | IC LINE TRANSCEIVER, PBCC16, 3 X 3 X 0.65 MM, PLASTIC, MO-217, SOT-639-2, HBCC-16, Line Driver or Receiver |
| 文件： | 总29页 (文件大小：189K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IMPORTANT NOTICE
Dear customer,
As from August 2nd 2008, the wireless operations of NXP have moved to a new company,
ST-NXP Wireless.
As a result, the following changes are applicable to the attached document.
●
●
Company name - Philips Semiconductors is replaced with ST-NXP Wireless.
Copyright - the copyright notice at the bottom of each page “© Koninklijke Philips
Electronics N.V. 200x. All rights reserved”, shall now read: “© ST-NXP Wireless 200x -
All rights reserved”.
●
●
Web site - http://www.semiconductors.philips.com is replaced with
http://www.stnwireless.com
Contact information - the list of sales offices previously obtained by sending an email
to sales.addresses@www.semiconductors.philips.com, is now found at
http://www.stnwireless.com under Contacts.
If you have any questions related to the document, please contact our nearest sales office.
Thank you for your cooperation and understanding.
ST-NXP Wireless
34ꢀ.80 7IRELESS
www.stnwireless.com
ISP1105/1106
Advanced Universal Serial Bus transceivers
Rev. 08 — 19 February 2004
Product data
1. General description
The ISP1105/1106 range of Universal Serial Bus (USB) transceivers are compliant
with the Universal Serial Bus Specification Rev. 2.0. They can transmit and receive
serial data at both full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s) data rates. The
ISP1105/1106 range can be used as a USB device transceiver or a USB host
transceiver.
They allow USB Application Specific ICs (ASICs) and Programmable Logic Devices
(PLDs) with power supply voltages from 1.65 V to 3.6 V to interface with the physical
layer of the Universal Serial Bus. They have an integrated 5 V-to-3.3 V voltage
regulator for direct powering via the USB supply VBUS
.
ISP1105 allows single-ended and differential input modes selectable by a MODE
input and it is available in HVQFN16 and HBCC16 packages. ISP1106 allows only
differential input mode and is available in both TSSOP16 and HBCC16 packages.
The ISP1105/1106 are ideal for portable electronics devices such as mobile phones,
digital still cameras, Personal Digital Assistants (PDA) and Information Appliances
(IA).
2. Features
■ Complies with Universal Serial Bus Specification Rev. 2.0
■ Can transmit and receive serial data at both full-speed (12 Mbit/s) and low-speed
(1.5 Mbit/s) data rates
■ Integrated bypassable 5 V-to-3.3 V voltage regulator for powering via USB VBUS
■ VBUS disconnection indication through VP and VM
■ Used as a USB device transceiver or a USB host transceiver
■ Stable RCV output during SE0 condition
■ Two single-ended receivers with hysteresis
■ Low-power operation
■ Supports an I/O voltage range from 1.65 V to 3.6 V
■ ±12 kV ESD protection at the D+, D−, VCC(5.0) and GND pins
■ Full industrial operating temperature range from −40 to +85 °C
■ Available in small HBCC16, HVQFN16 (only ISP1105) and TSSOP16 (only
ISP1106) packages; HBCC16 and HVQFN16 are lead-free and halogen-free
packages.
ISP1105/1106
Advanced USB transceivers
Philips Semiconductors
3. Applications
■ Portable electronic devices, such as:
◆ Mobile phone
◆ Digital still camera
◆ Personal Digital Assistant (PDA)
◆ Information Appliance (IA).
4. Ordering information
Table 1:
Ordering information
Type number Package
Name
Description
Version
ISP1105BS
HVQFN16
plastic thermal enhanced very thin quad flat package; no leads;
SOT758-1
16 terminals; body 3 × 3 × 0.85 mm
ISP1105W
HBCC16
plastic thermal enhanced bottom chip carrier; 16 terminals;
SOT639-2
body 3 × 3 × 0.65 mm
ISP1106DH
ISP1106W
TSSOP16
HBCC16
plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
SOT639-2
plastic thermal enhanced bottom chip carrier; 16 terminals;
body 3 × 3 × 0.65 mm
4.1 Ordering options
Table 2:
Product
ISP1105
ISP1106
Selection guide
Package
Description
HVQFN16 and HBCC16 supports both single-ended and differential input modes; see Table 5 and Table 6.
TSSOP16 and HBCC16 supports only the differential input mode; see Table 6.
9397 750 11231
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
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2 of 28
ISP1105/1106
Advanced USB transceivers
Philips Semiconductors
5. Block diagram
3.3 V
VOLTAGE
REGULATOR
V
V
CC(5.0)
CC(I/O)
V
reg(3.3)
V
pu(3.3)
SOFTCON
OE
(1)
1.5 kΩ
33 Ω (1%)
33 Ω (1%)
D+
SPEED
D−
(2)
VMO/FSE0
(2)
VPO/VO
(3)
MODE
LEVEL
SHIFTER
SUSPND
RCV
ISP1105
ISP1106
VP
VM
MBL301
GND
(1) Connect to D− for low-speed operation.
(2) Pin function depends on device type.
(3) Only for ISP1105.
Fig 1. Block diagram (combined ISP1105 and ISP1106).
9397 750 11231
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Product data
Rev. 08 — 19 February 2004
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ISP1105/1106
Advanced USB transceivers
Philips Semiconductors
6. Pinning information
6.1 Pinning
5
6
7
8
6
7
8
D−
SUSPND
5
9
9
D−
4
3
2
1
VM
VP
D+
VM
VP
4
3
2
10
11
12
10 D+
ISP1105W
ISP1105BS
VPO/VO
VMO/FSE0
RCV
VPO/VO
11
GND
(exposed diepad)
GND
(exposed diepad)
RCV
12 VMO/FSE0
OE
V
13
1
16
15
14
reg(3.3)
OE
14
15
13
16
004aaa314
Bottom view
MBL303
Bottom view
Fig 2. Pin configuration ISP1105BS (HVQFN).
Fig 3. Pin configuration ISP1105W (HBCC16).
V
V
V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CC(5.0)
reg(3.3)
pu(3.3)
6
7
8
D−
SUSPND
5
9
SOFTCON
OE
VMO
VPO
D+
D+
VM
VP
4
3
2
10
11
12
RCV
ISP1106DH
ISP1106W
VPO
VMO
VP
RCV
VM
D−
SUSPND
GND
SPEED
V
13
1
16
15
14
reg(3.3)
OE
V
CC(I/O)
Bottom view
MBL304
MBL302
Fig 4. Pin configuration ISP1106DH (TSSOP16).
Fig 5. Pin configuration ISP1106W (HBCC16).
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Product data
Rev. 08 — 19 February 2004
4 of 28
ISP1105/1106
Advanced USB transceivers
Philips Semiconductors
6.2 Pin description
Table 3:
Symbol[1]
Pin description
Pin
Type Description
ISP1105
ISP1106
BS
W
DH
W
OE
1
1
3
1
I
output enable input (CMOS level with respect to VCC(I/O), active LOW);
enables the transceiver to transmit data on the USB bus
input pad; push pull; CMOS
RCV
2
3
2
3
4
2
3
O
differential data receiver output (CMOS level with respect to VCC(I/O));
driven LOW when input SUSPND is HIGH; the output state of RCV is
preserved and stable during an SE0 condition
output pad; push pull; 4 mA output drive; CMOS
VP
5
6
O
O
single-ended D+ receiver output (CMOS level with respect to VCC(I/O)); for
external detection of single-ended zero (SE0), error conditions, speed of
connected device; driven HIGH when no supply voltage is connected to
VCC(5.0) and Vreg(3.3)
output pad; push pull; 4 mA output drive; CMOS
VM
4
4
4
single-ended D− receiver output (CMOS level with respect to VCC(I/O)); for
external detection of single-ended zero (SE0), error conditions, speed of
connected device; driven HIGH when no supply voltage is connected to
VCC(5.0) and Vreg(3.3)
output pad; push pull; 4 mA output drive; CMOS
SUSPND
MODE
5
6
5
6
7
-
5
-
I
I
suspend input (CMOS level with respect to VCC(I/O)); a HIGH level enables
low-power state while the USB bus is inactive and drives output RCV to a
LOW level
input pad; push pull; CMOS
mode input (CMOS level with respect to VCC(I/O)); a HIGH level enables the
differential input mode (VPO, VMO) whereas a LOW level enables a
single-ended input mode (VO, FSE0); see Table 5 and Table 6
input pad; push pull; CMOS
ground supply[2]
GND
die die
pad pad
8
9
6
7
-
-
VCC(I/O)
7
7
supply voltage for digital I/O pins (1.65 to 3.6 V). When VCC(I/O) is not
connected, the (D+, D−) pins are in three-state; this supply pin is totally
independent of VCC(5.0) and Vreg(3.3) and must never exceed the Vreg(3.3)
voltage
SPEED
8
8
10
8
I
speed selection input (CMOS level with respect to VCC(I/O)); adjusts the
slew rate of differential data outputs D+ and D− according to the
transmission speed
LOW — low-speed (1.5 Mbit/s)
HIGH — full-speed (12 Mbit/s)
input pad; push pull; CMOS
D−
D+
9
9
11
12
9
AI/O
negative USB data bus connection (analog, differential); for low-speed
mode connect to pin Vpu(3.3) via a 1.5 kΩ resistor
10
10
10 AI/O
positive USB data bus connection (analog, differential); for full-speed mode
connect to pin Vpu(3.3) via a 1.5 kΩ resistor
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Product data
Rev. 08 — 19 February 2004
5 of 28
ISP1105/1106
Advanced USB transceivers
Philips Semiconductors
Table 3:
Pin description…continued
Symbol[1]
Pin
Type Description
ISP1105
ISP1106
BS
11
-
W
11
-
DH
-
W
-
VPO/VO
VPO
I
I
-
driver data input (CMOS level with respect to VCC(I/O), Schmitt trigger); see
Table 5 and Table 6
13
-
11
-
input pad; push pull; CMOS
VO
-
-
VMO/FSE0
VMO
12
-
12
-
-
-
driver data input (CMOS level with respect to VCC(I/O), Schmitt trigger); see
Table 5 and Table 6
14
-
12
-
input pad; push pull; CMOS
FSE0
-
-
Vreg(3.3)
13
13
15
13
internal regulator option: regulated supply voltage output (3.0 to 3.6 V)
during 5 V operation; a decoupling capacitor of at least 0.1 µF is required
regulator bypass option: used as a supply voltage input for 3.3 V ±10%
operation
VCC(5.0)
14
15
14
15
16
1
14
15
-
-
internal regulator option: supply voltage input (4.0 to 5.5 V); can be
connected directly to USB supply VBUS
regulator bypass option: connect to Vreg(3.3)
Vpu(3.3)
pull-up supply voltage (3.3 V ±10%); connect an external 1.5 kΩ resistor on
D+ (full-speed) or D− (low-speed); pin function is controlled by input
SOFTCON
SOFTCON = LOW — Vpu(3.3) floating (high impedance); ensures zero
pull-up current
SOFTCON = HIGH — Vpu(3.3) = 3.3 V; internally connected to Vreg(3.3)
SOFTCON
16
16
2
16
I
software controlled USB connection input; a HIGH level applies 3.3 V to pin
Vpu(3.3), which is connected to an external 1.5 kΩ pull-up resistor; this
allows USB connect/disconnect signalling to be controlled by software
input pad; push pull; CMOS
[1] Symbol names with an overscore (e.g. NAME) indicate active LOW signals.
[2] ISP1105: ground terminal is connected to the exposed die pad (heatsink).
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Product data
Rev. 08 — 19 February 2004
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ISP1105/1106
Advanced USB transceivers
Philips Semiconductors
7. Functional description
7.1 Function selection
Table 4:
Function table
SUSPND OE
(D+, D−)
RCV
VP/VM
Function
L
L
driving and
receiving
active
active
normal driving
(differential receiver active)
L
H
L
receiving[1]
active
inactive[2] active
active
receiving
driving during ‘suspend’[3]
H
driving
(differential receiver inactive)
H
H
high-Z[1]
inactive[2] active
low-power state
[1] Signal levels on (D+, D−) are determined by other USB devices and external pull-up/down resistors.
[2] In ‘suspend’ mode (SUSPND = HIGH) the differential receiver is inactive and output RCV is always
LOW. Out-of-suspend (‘K’) signalling is detected via the single-ended receivers VP and VM.
[3] During suspend, the slew-rate control circuit of low-speed operation is disabled. The (D+, D−) lines
are still driven to their intended states, without slew-rate control. This is permitted because driving
during suspend is used to signal remote wake-up by driving a ‘K’ signal (one transition from idle to
‘K’ state) for a period of 1 to 15 ms.
7.2 Operating functions
Table 5:
Driving function (pin OE = L) using single-ended input data interface for
ISP1105 (pin MODE = L)
FSE0
VO
L
Data
L
differential logic 0
differential logic 1
SE0
L
H
L
H
H
H
SE0
Table 6:
Driving function (pin OE = L) using differential input data interface for
ISP1105 (pin MODE = H) and ISP1106
VMO
VPO
L
Data
L
SE0
L
H
differential logic 1
differential logic 0
illegal state
H
H
L
H
Table 7:
Receiving function (pin OE = H)
RCV
(D+, D−)
VP[1]
VM[1]
Differential logic 0
Differential logic 1
SE0
L
L
H
L
H
L
L
H
RCV*[2]
[1] VP = VM = H indicates the sharing mode (VCC(5.0) and Vreg(3.3) are disconnected).
[2] RCV* denotes the signal level on output RCV just before SE0 state occurs. This level is stable during
the SE0 period.
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Product data
Rev. 08 — 19 February 2004
7 of 28
ISP1105/1106
Advanced USB transceivers
Philips Semiconductors
7.3 Power supply configurations
The ISP1105/1106 can be used with different power supply configurations, which can
be changed dynamically. An overview is given in Table 9.
Normal mode — Both VCC(I/O) and VCC(5.0) or (VCC(5.0) and Vreg(3.3)) are connected.
For 5 V operation, VCC(5.0) is connected to a 5 V source (4.0 to 5.5 V). The internal
voltage regulator then produces 3.3 V for the USB connections. For 3.3 V operation,
both VCC(5.0) and Vreg(3.3) are connected to a 3.3 V source (3.0 to 3.6 V). VCC(I/O) is
independently connected to a voltage source (1.65 V to 3.6 V), depending on the
supply voltage of the external circuit.
Disable mode — VCC(I/O) is not connected, VCC(5.0) or (VCC(5.0) and Vreg(3.3)) are
connected. In this mode, the internal circuits of the ISP1105/1106 ensure that the
(D+, D−) pins are in three-state and the power consumption drops to the low-power
(suspended) state level. Some hysteresis is built into the detection of VCC(I/O) lost.
Sharing mode — VCC(I/O) is connected, (VCC(5.0) and Vreg(3.3)) are not connected. In
this mode, the (D+, D−) pins are made three-state and the ISP1105/1106 allows
external signals of up to 3.6 V to share the (D+, D−) lines. The internal circuits of the
ISP1105/1106 ensure that virtually no current (maximum 10 µA) is drawn via the (D+,
D−) lines. The power consumption through pin VCC(I/O) drops to the low-power
(suspended) state level. Both the VP and VM pins are driven HIGH to indicate this
mode. Pin RCV is made LOW. Some hysteresis is built into the detection of Vreg(3.3)
lost.
Table 8:
Pins
Pin states in disable or sharing mode
Disable mode state
Sharing mode state
VCC(5.0) / Vreg(3.3)
5 V input / 3.3 V output;
3.3 V input / 3.3 V input
not present
VCC(I/O)
Vpu(3.3)
(D+, D−)
(VP, VM)
RCV
not present
1.65 V to 3.6 V input
high impedance (off)
high impedance
H
high impedance (off)
high impedance
invalid[1]
invalid[1]
L
Inputs (VO/VPO, FSE0/VMO,
SPEED, MODE[2], SUSPND, OE,
SOFTCON)
high impedance
high impedance
[1] High impedance or driven LOW.
[2] ISP1105 only.
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Product data
Rev. 08 — 19 February 2004
8 of 28
ISP1105/1106
Advanced USB transceivers
Philips Semiconductors
Table 9:
Power supply configuration overview
VCC(5.0) or
Vreg(3.3)
VCC(I/O)
Configuration
Special characteristics
Connected
Connected
connected
normal mode
disable mode
-
not connected
(D+, D−) and Vpu(3.3) high
impedance; VP, VM, RCV:
invalid[1]
Not connected
connected
sharing mode
(D+, D−) and Vpu(3.3) high
impedance;
VP, VM driven HIGH;
RCV driven LOW
[1] High impedance or driven LOW.
7.4 Power supply input options
The ISP1105/1106 range has two power supply input options.
Internal regulator — VCC(5.0) is connected to 4.0 to 5.5 V. The internal regulator is
used to supply the internal circuitry with 3.3 V (nominal). The Vreg(3.3) pin becomes a
3.3 V output reference.
Regulator bypass — VCC(5.0) and Vreg(3.3) are connected to the same supply. The
internal regulator is bypassed and the internal circuitry is supplied directly from the
Vreg(3.3) power supply. The voltage range is 3.0 to 3.6 V to comply with the USB
specification.
The supply voltage range for each input option is specified in Table 10.
Table 10: Power supply input options
Input option
VCC(5.0)
Vreg(3.3)
VCC(I/O)
Internal regulator supply input for internal voltage reference
supply input for digital
I/O pins
regulator
output
(4.0 to 5.5 V)
(3.3 V, 300 µA)
(1.65 V to 3.6 V)
Regulator
bypass
connected to Vreg(3.3)
with maximum voltage (3.0 V to 3.6 V)
drop of 0.3 V
supply input
supply input for digital
I/O pins
(1.65 V to 3.6 V)
(2.7 to 3.6 V)
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Product data
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9 of 28
ISP1105/1106
Advanced USB transceivers
Philips Semiconductors
8. Electrostatic discharge (ESD)
8.1 ESD protection
The pins that are connected to the USB connector (D+, D−, VCC(5.0) and GND) have a
minimum of ±12 kV ESD protection. The ±12 kV measurement is limited by the test
equipment. Capacitors of 4.7 µF connected from Vreg(3.3) to GND and VCC(5.0) to GND
are required to achieve this ±12 kV ESD protection (see Figure 6).
ISP1105/1106 can withstand ±12 kV using the Human Body Model and ±5 kV using
the Contact Discharge Method as specified in IEC 61000-4-2.
R
R
C
D
1 MΩ
1500 Ω
charge current
limit resistor
discharge
resistance
DEVICE UNDER
TEST
V
A
CC(5.0)
V
reg(3.3)
HIGH VOLTAGE
DC SOURCE
B
C
S
storage
capacitor
4.7 µF
4.7 µF
100 pF
GND
004aaa145
Fig 6. Human Body ESD test model.
8.2 ESD test conditions
A detailed report on test set-up and results is available on request.
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Product data
Rev. 08 — 19 February 2004
10 of 28
ISP1105/1106
Advanced USB transceivers
Philips Semiconductors
9. Limiting values
Table 11: Absolute maximum ratings
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VCC(5.0)
VCC(I/O)
Vreg(3.3)
VI
Parameter
Conditions
Min
−0.5
−0.5
−0.5
−0.5
-
Max
+6.0
+4.6
+4.6
Unit
V
supply voltage
I/O supply voltage
regulated supply voltage
DC input voltage
V
V
VCC(I/O) + 0.5
V
Ilu
latch-up current
VI = −1.8 to 5.4 V
ILI < 1 µA
100
mA
[1][2]
Vesd
electrostatic discharge voltage
on pins D+, D−,
−12000
+12000
V
VCC(5.0) and GND
on other pins
−2000
−40
+2000
+125
V
Tstg
storage temperature
°C
[1] Testing equipment limits measurement to only ±12 kV. Capacitors needed on VCC(5.0) and Vreg(3.3); see Section 8.
[2] Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ resistor (Human Body Model).
10. Recommended operating conditions
Table 12: Recommended operating conditions
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VCC(5.0)
supply voltage (internal
regulator option)
5 V operation
4.0
5.0
5.5
V
Vreg(3.3)
supply voltage (regulator
bypass option)
3.3 V operation
3.0
3.3
3.6
V
VCC(I/O)
VI
I/O supply voltage
input voltage
1.65
0
-
-
-
3.6
V
V
V
VCC(I/O)
3.6
VI(AI/O)
input voltage on analog I/O
0
pins (D+/D−)
Tamb
operating ambient temperature
−40
-
+85
°C
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Product data
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ISP1105/1106
Advanced USB transceivers
Philips Semiconductors
11. Static characteristics
Table 13: Static characteristics: supply pins
VCC = 4.0 to 5.5 V or Vreg(3.3) = 3.0 to 3.6 V; VCC(I/O) = 1.65 to 3.6 V; VGND = 0 V; see Table 10 for valid voltage level
combinations; Tamb = −40 to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
[1][2]
[3]
Vreg(3.3)
regulated supply voltage
output
internal regulator option;
3.0
3.3
3.6
V
Iload ≤ 300 µA
ICC
operating supply current
full-speed transmitting and
receiving at 12 Mbit/s; CL = 50 pF
on D+/D−
-
4
8
mA
[3]
[4]
ICC(I/O)
ICC(idle)
operating I/O supply current full-speed transmitting and
receiving at 12 Mbit/s
-
-
1
-
2
mA
supply current during
full-speed idle and SE0
full-speed idle: VD+ > 2.7 V,
VD− < 0.3 V; SE0: VD+ < 0.3 V,
VD− < 0.3 V
500
µA
ICC(I/O)(static)
ICC(susp)
static I/O supply current
suspend supply current
full-speed idle, SE0 or suspend
SUSPND = HIGH
-
-
-
-
-
-
-
-
20
20
20
20
µA
µA
µA
µA
[4]
[4]
ICC(dis)
disable mode supply current VCC(I/O) not connected
ICC(I/O)(sharing) sharing mode I/O supply
current
VCC(5.0) or Vreg(3.3) not connected
IDx(sharing)
sharing mode load current
on pins D+ and D−
VCC(5.0) or Vreg(3.3) not connected;
SOFTCON = LOW; VDx = 3.6 V
-
-
10
µA
Vreg(3.3)th
regulated supply voltage
detection threshold
1.65 V ≤ VCC(I/O) ≤ Vreg(3.3)
2.7 V ≤ Vreg(3.3) ≤ 3.6 V
;
supply lost
-
-
0.8
V
V
V
[5]
supply present
VCC(I/O) = 1.8 V
2.4
-
-
-
-
Vreg(3.3)hys
VCC(I/O)th
regulated supply voltage
detection hysteresis
0.45
I/O supply voltage detection Vreg(3.3) = 2.7 to 3.6 V
threshold
supply lost
-
-
0.5
V
V
V
supply present
1.4
-
-
-
-
VCC(I/O)hys
I/O supply voltage detection Vreg(3.3) = 3.3 V
hysteresis
0.45
[1] Iload includes the pull-up resistor current via pin Vpu(3.3)
[2] In ‘suspend’ mode, the minimum voltage is 2.7 V.
.
[3] Maximum value is characterized only, not tested in production.
[4] Excluding any load current and Vpu(3.3)/Vsw source current to the 1.5 kΩ and 15 kΩ pull-up and pull-down resistors (200 µA typ.).
[5] When VCC(I/O) < 2.7 V, the minimum value for Vth(reg3.3)(present) is 2.0 V.
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Table 14: Static characteristics: digital pins
VCC(I/O) = 1.65 to 3.6 V; VGND = 0 V; Tamb = −40 to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VCC(I/O) = 1.65 to 3.6 V
Input levels
VIL
LOW-level input voltage
-
-
-
0.3VCC(I/O)
-
V
V
VIH
HIGH-level input voltage
LOW-level output voltage
HIGH-level output voltage
0.6VCC(I/O)
Output levels
VOL
IOL = 100 µA
IOL = 2 mA
-
-
-
-
-
-
0.15
V
V
V
V
0.4
VOH
IOH = 100 µA
IOH = 2 mA
V
CC(I/O) − 0.15
CC(I/O) − 0.4
-
-
V
Leakage current
ILI
input leakage current
−1
-
+1
µA
Example 1: VCC(I/O) = 1.8 V ± 0.15 V
Input levels
VIL
LOW-level input voltage
HIGH-level input voltage
-
-
-
0.5
-
V
V
VIH
1.2
Output levels
VOL
LOW-level output voltage
HIGH-level output voltage
IOL = 100 µA
IOL = 2 mA
-
-
-
-
-
0.15
V
V
V
V
-
0.4
VOH
IOH = 100 µA
IOH = 2 mA
1.5
1.25
-
-
Example 2: VCC(I/O) = 2.5 V ± 0.2 V
Input levels
VIL
LOW-level input voltage
HIGH-level input voltage
-
-
-
0.7
-
V
V
VIH
1.7
Output levels
VOL
LOW-level output voltage
HIGH-level output voltage
IOL = 100 µA
IOL = 2 mA
-
-
-
-
-
0.15
V
V
V
V
-
0.4
VOH
IOH = 100 µA
IOH = 2 mA
2.15
1.9
-
-
Example 3: VCC(I/O) = 3.3 V ± 0.3 V
Input levels
VIL
LOW-level input voltage
HIGH-level input voltage
-
-
-
0.9
-
V
V
VIH
2.15
Output levels
VOL
LOW-level output voltage
HIGH-level output voltage
IOL = 100 µA
IOL = 2 mA
-
-
-
-
-
0.15
V
V
V
V
-
0.4
VOH
IOH = 100 µA
IOH = 2 mA
2.85
2.6
-
-
Capacitance
CIN
input capacitance
pin to GND
-
-
10
pF
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Table 15: Static characteristics: analog I/O pins (D+, D−)
VCC = 4.0 to 5.5 V or Vreg(3.3) = 3.0 to 3.6 V; VGND = 0 V; Tamb = −40 to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Input levels
Differential receiver
VDI
differential input sensitivity
|VI(D+) − VI(D−)
|
0.2
0.8
-
-
-
V
V
VCM
differential common mode
voltage
includes VDI range
2.5
Single-ended receiver
VIL
LOW-level input voltage
-
-
-
-
0.8
-
V
V
V
VIH
HIGH-level input voltage
hysteresis voltage
2.0
0.4
Vhys
0.7
Output levels
VOL
VOH
LOW-level output voltage
HIGH-level output voltage
RL = 1.5 kΩ to +3.6 V
RL = 15 kΩ to GND
-
-
-
0.3
3.6
V
V
[1]
2.8
Leakage current
ILZ
OFF-state leakage current
−1
-
-
+1
20
µA
Capacitance
CIN
transceiver capacitance
pin to GND
-
pF
Resistance
ZDRV
[2]
driver output impedance
input impedance
steady-state drive
34
10
-
39
-
44
-
Ω
ZINP
MΩ
Ω
RSW
internal switch resistance at
pin Vpu(3.3)
-
10
Termination
[3][4]
VTERM
termination voltage for
3.0
-
3.6
V
upstream port pull-up (RPU
)
[1] VOH(min) = Vreg(3.3) − 0.2 V.
[2] Includes external resistors of 33 Ω ±1% on both D+ and D−.
[3] This voltage is available at pins Vreg(3.3) and Vpu(3.3)
[4] In ‘suspend’ mode the minimum voltage is 2.7 V.
.
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12. Dynamic characteristics
Table 16: Dynamic characteristics: analog I/O pins (D+, D−)[1]
VCC = 4.0 to 5.5 V or Vreg(3.3) = 3.0 to 3.6 V; VCC(I/O) = 1.65 to 3.6 V; VGND = 0 V; see Table 10 for valid voltage level
combinations; Tamb = −40 to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Driver characteristics
Full-speed mode
tFR
rise time
CL = 50 to 125 pF;
10% to 90% of |VOH − VOL|;
see Figure 7
4
4
-
-
20
20
ns
ns
tFF
fall time
CL = 50 to 125 pF;
90% to 10% of |VOH − VOL|;
see Figure 7
FRFM
VCRS
differential rise/fall time
excluding the first transition from
idle state
90
-
-
111.1
2.0
%
V
matching (tFR/tFF
)
[2]
output signal crossover
voltage
excluding the first transition from
idle state; see Figure 10
1.3
Low-speed mode
tLR rise time
CL = 50 to 600 pF;
10% to 90% of |VOH − VOL|;
see Figure 7
75
75
-
-
300
300
ns
ns
tLF
fall time
CL = 50 to 600 pF;
90% to 10% of |VOH − VOL|;
see Figure 7
LRFM
differential rise/fall time
excluding the first transition from
idle state
80
-
-
125
2.0
%
V
matching (tLR/tLF
)
[2]
VCRS
output signal crossover
voltage
excluding the first transition from
idle state; see Figure 10
1.3
Driver timing
Full-speed mode
tPLH(drv) driver propagation delay
LOW-to-HIGH; see Figure 10
HIGH-to-LOW; see Figure 10
-
-
-
-
18
18
ns
ns
(VO/VPO, FSE0/VMO to
D+,D−)
tPHL(drv)
driver propagation delay
(VO/VPO, FSE0/VMO to
D+,D−)
tPHZ
tPLZ
tPZH
tPZL
driver disable delay (OE to
D+,D−)
HIGH-to-OFF; see Figure 8
LOW-to-OFF; see Figure 8
OFF-to-HIGH; see Figure 8
OFF-to-LOW; see Figure 8
-
-
-
-
-
-
-
-
15
15
15
15
ns
ns
ns
ns
driver disable delay (OE to
D+,D−)
driver enable delay (OE to
D+,D−)
driver enable delay (OE to
D+,D−)
Low-speed mode
Not specified: low-speed delay timings are dominated by the slow rise/fall times tLR and tLF.
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Table 16: Dynamic characteristics: analog I/O pins (D+, D−)[1]…continued
VCC = 4.0 to 5.5 V or Vreg(3.3) = 3.0 to 3.6 V; VCC(I/O) = 1.65 to 3.6 V; VGND = 0 V; see Table 10 for valid voltage level
combinations; Tamb = −40 to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Receiver timings (full-speed and low-speed mode)
Differential receiver
tPLH(rcv)
propagation delay (D+,D− to LOW-to-HIGH; see Figure 9
RCV)
-
-
-
-
15
15
ns
ns
tPHL(rcv)
propagation delay (D+,D− to HIGH-to-LOW; see Figure 9
RCV)
Single-ended receiver
tPLH(se) propagation delay (D+,D− to LOW-to-HIGH; see Figure 9
-
-
-
-
18
18
ns
ns
VP, VM)
tPHL(se)
propagation delay (D+,D− to HIGH-to-LOW; see Figure 9
VP, VM)
[1] Test circuit: see Figure 13.
[2] Characterized only, not tested. Limits guaranteed by design.
1.8 V
0.9 V
logic input 0.9 V
0 V
t
, t
t
, t
FR LR
FF LF
t
t
t
t
PHZ
PLZ
PZH
PZL
V
OH
90 %
90 %
V
OH
V
−0.3 V
OH
differential
data lines
V
CRS
V
+0.3 V
10 %
10 %
OL
V
V
MGS966
OL
OL
MGS963
Fig 7. Rise and fall times.
Fig 8. Timing of OE to D+, D−.
2.0 V
1.8 V
differential
data lines
V
V
CRS
CRS
0.9 V
logic input 0.9 V
0 V
0.8 V
t
t
PLH(rcv)
PLH(se)
PHL(rcv)
t
t
PHL(drv)
t
t
PLH(drv)
PHL(se)
V
OH
V
OH
differential
data lines
0.9 V
0.9 V
logic output
V
V
CRS
CRS
V
V
OL
OL
MGS965
MGS964
Fig 9. Timing of D+, D− to RCV, VP, VM.
Fig 10. Timing of VO/VPO, FSE0/VMO to D+, D−.
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13. Test information
test point
33 Ω
500 Ω
D.U.T.
50 pF
V
MBL142
V = 0 V for tPZH, tPHZ
V = Vreg(/3.3) for tPZL, tPLZ
Fig 11. Load for enable and disable times.
test point
D.U.T.
25 pF
MGS968
Fig 12. Load for VM, VP and RCV.
V
pu(3.3)
(1)
test point
1.5 kΩ
D.U.T.
D+/D−
33 Ω
15 kΩ
C
L
MGS967
Load capacitance:
CL = 50 pF or 125 pF (full-speed mode, minimum or maximum timing)
CL = 50 pF or 600 pF (low-speed mode, minimum or maximum timing)
(1) Full-speed mode: connected to D+; low-speed mode: connected to D−.
Fig 13. Load for D+, D−.
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14. Package outline
HBCC16: plastic thermal enhanced bottom chip carrier; 16 terminals; body 3 x 3 x 0.65 mm
SOT639-2
b
v
M
M
C
C
A B
D
B
A
E
w
f
v
M
C
A
B
w
M
C
terminal 1
index area
b
1
b
3
v
M
M
C
C
A B
w
b
v
M
M
C
A B
2
w
C
detail X
e
1
C
D
h
e
y
y
C
1
5
9
e
e
4
E
e
h
2
1/2 e
4
1
13
16
A
X
1
1/2 e
3
A
2
e
3
A
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
A
A
b
E
e
e
w
b
b
b
D
D
E
e
e
3
e
f
v
y
y
1
UNIT
1
2
h
1
1
2
3
h
2
4
max.
0.10 0.7 0.33 0.33 0.38 0.38 3.1 1.45 3.1 1.45
0.05 0.6 0.27 0.27 0.32 0.32 2.9 1.35 2.9 1.35
0.23
0.17
mm
0.8
0.1 0.05 0.2
0.5
2.5
2.5 2.45 2.45
0.08
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
JEITA
01-11-13
03-03-12
SOT639-2
MO-217
Fig 14. HBCC16 package outline.
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Advanced USB transceivers
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HVQFN16: plastic thermal enhanced very thin quad flat package; no leads;
16 terminals; body 3 x 3 x 0.85 mm
SOT758-1
B
A
D
terminal 1
index area
A
E
A
1
c
detail X
e
C
1
1/2 e
y
y
v
M
C
A B
C
1
e
b
w
M
C
5
8
L
4
9
e
e
E
2
h
1/2 e
12
1
16
13
terminal 1
index area
D
h
X
0
2.5
scale
5 mm
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
b
c
E
e
e
e
2
D
D
E
L
y
1
v
w
y
1
h
1
h
max.
0.05 0.30
0.00 0.18
3.1 1.75
2.9 1.45
3.1
2.9
1.75
1.45
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
1.5
1.5
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-03-25
02-10-21
SOT758-1
- - -
MO-220
- - -
Fig 15. HVQFN16 package outline.
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TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.40
0.06
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT403-1
MO-153
Fig 16. TSSOP16 package outline.
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15. Packaging
The ISP1105/1106W (HBCC16 package) is delivered on a type A carrier tape, see
Figure 17. The tape dimensions are given in Table 17.
The reel diameter is 330 mm. The reel is made of polystyrene (PS) and is not
designed for use in a baking process.
The cumulative tolerance of 10 successive sprocket holes is ±0.02 mm. The camber
must not exceed 1 mm in 100 mm.
i
4
A0
K0
W
B0
P1
Type A
direction of feed
A0
K0
4
W
B0
elongated
sprocket hole
P1
direction of feed
MLC338
Type B
Fig 17. Carrier tape dimensions.
Table 17: Type A carrier tape dimensions for ISP1105/1106W
Dimension
Value
3.3
Unit
mm
mm
mm
mm
mm
A0
B0
K0
P1
W
3.3
1.1
8.0
12.0 ±0.3
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16. Soldering
16.1 Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account
of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit
Packages (document order number 9398 652 90011).
There is no soldering method that is ideal for all surface mount IC packages. Wave
soldering can still be used for certain surface mount ICs, but it is not suitable for fine
pitch SMDs. In these situations reflow soldering is recommended. In these situations
reflow soldering is recommended.
16.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and
binding agent) to be applied to the printed-circuit board by screen printing, stencilling
or pressure-syringe dispensing before package placement. Driven by legislation and
environmental forces the worldwide use of lead-free solder pastes is increasing.
Several methods exist for reflowing; for example, convection or convection/infrared
heating in a conveyor type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending on heating method.
Typical reflow peak temperatures range from 215 to 270 °C depending on solder
paste material. The top-surface temperature of the packages should preferably be
kept:
• below 225 °C (SnPb process) or below 245 °C (Pb-free process)
– for all BGA, HTSSON..T and SSOP..T packages
– for packages with a thickness ≥ 2.5 mm
– for packages with a thickness < 2.5 mm and a volume ≥ 350 mm3 so called
thick/large packages.
• below 240 °C (SnPb process) or below 260 °C (Pb-free process) for packages with
a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages.
Moisture sensitivity precautions, as indicated on packing, must be respected at all
times.
16.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices
(SMDs) or printed-circuit boards with a high component density, as solder bridging
and non-wetting can present major problems.
To overcome these problems the double-wave soldering method was specifically
developed.
If wave soldering is used the following conditions must be observed for optimal
results:
• Use a double-wave soldering method comprising a turbulent wave with high
upward pressure followed by a smooth laminar wave.
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• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be
parallel to the transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the
transport direction of the printed-circuit board.
The footprint must incorporate solder thieves at the downstream end.
• For packages with leads on four sides, the footprint must be placed at a 45° angle
to the transport direction of the printed-circuit board. The footprint must
incorporate solder thieves downstream and at the side corners.
During placement and before soldering, the package must be fixed with a droplet of
adhesive. The adhesive can be applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the adhesive is cured.
Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 °C or
265 °C, depending on solder material applied, SnPb or Pb-free respectively.
A mildly-activated flux will eliminate the need for removal of corrosive residues in
most applications.
16.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low
voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time
must be limited to 10 seconds at up to 300 °C.
When using a dedicated tool, all other leads can be soldered in one operation within
2 to 5 seconds between 270 and 320 °C.
16.5 Package related soldering information
Table 18: Suitability of surface mount IC packages for wave and reflow soldering
methods
Package[1]
Soldering method
Wave
Reflow[2]
BGA, HTSSON..T[3], LBGA, LFBGA, SQFP,
SSOP..T[3], TFBGA, USON, VFBGA
not suitable
suitable
DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, not suitable[4]
HSQFP, HSSON, HTQFP, HTSSOP, HVQFN,
HVSON, SMS
suitable
PLCC[5], SO, SOJ
suitable
suitable
LQFP, QFP, TQFP
not recommended[5][6]
not recommended[7]
not suitable
suitable
SSOP, TSSOP, VSO, VSSOP
CWQCCN..L[8], PMFP[9], WQCCN..L[8]
suitable
not suitable
[1] For more detailed information on the BGA packages refer to the (LF)BGA Application Note
(AN01026); order a copy from your Philips Semiconductors sales office.
[2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the
maximum temperature (with respect to time) and body size of the package, there is a risk that internal
or external package cracks may occur due to vaporization of the moisture in them (the so called
popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated
Circuit Packages; Section: Packing Methods.
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[3] These transparent plastic packages are extremely sensitive to reflow soldering conditions and must
on no account be processed through more than one soldering cycle or subjected to infrared reflow
soldering with peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow
oven. The package body peak temperature must be kept as low as possible.
[4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom
side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with
the heatsink on the top side, the solder might be deposited on the heatsink surface.
[5] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave
direction. The package footprint must incorporate solder thieves downstream and at the side corners.
[6] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it
is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
[7] Wave soldering is suitable for SSOP, TSSOP, VSO and VSOP packages with a pitch (e) equal to or
larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than
0.5 mm.
[8] Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered
pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex
foil by using a hot bar soldering process. The appropriate soldering profile can be provided on
request.
[9] Hot bar soldering or manual soldering is suitable for PMFP packages.
9397 750 11231
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 08 — 19 February 2004
24 of 28
ISP1105/1106
Advanced USB transceivers
Philips Semiconductors
17. Additional soldering information
17.1 (H)BCC packages: footprint
The surface material of the terminals on the resin protrusion consists of a 4-layer
metal structure (Au, Pd, Ni and Pd). The Au + Pd layer (0.1 µm min.) ensures
solderability, the Ni layer (5 µm min.) prevents diffusion, and the Pd layer on top
(0.5 µm min.) ensures effective wire bonding.
Terminal
PCB land
Solder resist mask
Stencil mask
All dimensions in mm
Solder land
Normal
0.05
0.05
b
1
b
1
Solder resist
Solder stencil
b
b
0.05
0.05
For exact dimensions
see package outline
drawing (SOT639-2)
Corner
0.05
0.05
b
b
2
2
b
b
2
2
0.05
0.3 (8×)
0.05
Cavity
0.05
Stencil print thickness:
0.1 to 0.12 mm
0.1
(4×)
E
E
h
h
004aaa123
D
D
h
h
0.05
Cavity: exposed die pad, either functioning as heatsink or as ground connection; only for HBCC packages.
Fig 18. (H)BCC footprint and solder resist mask dimensions.
17.2 (H)BCC packages: reflow soldering profile
The conditions for reflow soldering of (H)BCC packages are as follows:
• Preheating time: minimum 90 s at T = 145 to 155 °C
• Soldering time: minimum 90 s (BCC) or minimum 100 s (HBCC) at T > 183 °C
• Peak temperature:
– Ambient temperature: Tamb(max) = 260 °C
– Device surface temperature: Tcase(max) = 255 °C.
9397 750 11231
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 08 — 19 February 2004
25 of 28
ISP1105/1106
Advanced USB transceivers
Philips Semiconductors
18. Revision history
Table 19: Revision history
Rev Date
CPCN
-
Description
08 20040219
Product data (9397 750 11231); removed ISP1107 related information.
Modifications:
• Changed the data sheet title from ISP1105/1106/1107 to ISP1105/1106 and removed all
information pertaining to ISP1107
• Changed USB 1.1 reference to USB 2.0; also added data transfer rates
• Added HVQFN16 package details in Table 1, Section 6 and Section 14
• Figure 1: removed the first figure note
• Table 3: added pad details
• Table 11: updated
• Table 15: removed ZDRV2, and also table note 3
• Figure 8 and Figure 10: changed 1.65 V to 1.8 V.
Product data (9397 750 09529)
07 20020329
06 20011130
05 20010903
04 20010802
03 20010704
02 20010205
-
-
-
-
-
-
Product data; sixth version (9397 750 08872)
Product data; fifth version (9397 750 08681)
Preliminary data; fourth version (9397 750 08643)
Preliminary data; third version (9397 750 08515)
Objective specification; second version (9397 750 07879) ISP1107 stand-alone data
sheet only.
01 20000223
-
Objective specification; initial version (9397 750 06899) ISP1107 stand-alone data
sheet only.
9397 750 11231
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 08 — 19 February 2004
26 of 28
ISP1105/1106
Advanced USB transceivers
Philips Semiconductors
19. Data sheet status
Level Data sheet status[1]
Product status[2][3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1]
[2]
Please consult the most recently issued data sheet before initiating or completing a design.
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
20. Definitions
21. Disclaimers
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
Contact information
For additional information, please visit http://www.semiconductors.philips.com.
For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.
Fax: +31 40 27 24825
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
27 of 28
9397 750 11231
Product data
Rev. 08 — 19 February 2004
ISP1105/1106
Advanced USB transceivers
Philips Semiconductors
Contents
1
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
3
4
4.1
5
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
7
Functional description . . . . . . . . . . . . . . . . . . . 7
Function selection. . . . . . . . . . . . . . . . . . . . . . . 7
Operating functions. . . . . . . . . . . . . . . . . . . . . . 7
Power supply configurations. . . . . . . . . . . . . . . 8
Power supply input options. . . . . . . . . . . . . . . . 9
7.1
7.2
7.3
7.4
8
8.1
8.2
Electrostatic discharge (ESD). . . . . . . . . . . . . 10
ESD protection . . . . . . . . . . . . . . . . . . . . . . . . 10
ESD test conditions . . . . . . . . . . . . . . . . . . . . 10
9
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 11
Recommended operating conditions. . . . . . . 11
Static characteristics. . . . . . . . . . . . . . . . . . . . 12
Dynamic characteristics . . . . . . . . . . . . . . . . . 15
Test information. . . . . . . . . . . . . . . . . . . . . . . . 17
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 18
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
10
11
12
13
14
15
16
16.1
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Introduction to soldering surface mount
packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 22
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 22
Manual soldering . . . . . . . . . . . . . . . . . . . . . . 23
Package related soldering information . . . . . . 23
16.2
16.3
16.4
16.5
17
17.1
17.2
Additional soldering information . . . . . . . . . . 25
(H)BCC packages: footprint . . . . . . . . . . . . . . 25
(H)BCC packages: reflow soldering profile. . . 25
18
19
20
21
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 26
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 27
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
© Koninklijke Philips Electronics N.V. 2004.
Printed in The Netherlands
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner.
The information presented in this document does not form part of any quotation or
contract, is believed to be accurate and reliable and may be changed without notice. No
liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.
Date of release: 19 February 2004
Document order number: 9397 750 11231
相关型号：
ISP1107W-G
IC LINE TRANSCEIVER, PBCC16, 3 X 3 X 0.65 MM, PLASTIC, MO-217, SOT-639-2, HBCC-16, Line Driver or Receiver
NXP
ISP1107W-T
IC LINE TRANSCEIVER, PBCC16, 3 X 3 X 0.65 MM, PLASTIC, MO-217, SOT-639-2, HBCC-16, Line Driver or Receiver
NXP
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