ISP1130DL [NXP]

Universal Serial Bus compound hub with integrated keyboard controller; 集成键盘控制器通用串行总线复合集线器
ISP1130DL
型号: ISP1130DL
厂家: NXP    NXP
描述:

Universal Serial Bus compound hub with integrated keyboard controller
集成键盘控制器通用串行总线复合集线器

外围集成电路 光电二极管 控制器
文件: 总68页 (文件大小:1617K)
中文:  中文翻译
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ISP1130  
Universal Serial Bus compound hub with integrated keyboard  
controller  
Rev. 01 — 23 March 2000  
Objective specification  
1. General description  
The ISP1130 integrates a Universal Serial Bus (USB) hub with a keyboard controller  
into a single chip, which complies with Universal Serial Bus Specification Rev. 1.1 and  
the USB Device Class Definition for Human Interface Devices (HID). The hub has  
1 to 2 downstream ports and 1 to 3 non-removable embedded functions, one of  
which is dedicated to the keyboard operation. The hub controller is fully implemented  
in hardware, ensuring a fast response to host requests.  
The integrated 5 V to 3.3 V regulator allows direct connection to the USB power  
supply VBUS. The downstream ports are either bus-powered or hybrid-powered and  
can interface low-power USB devices such as a joystick or a mouse. ISP1130 uses  
SoftConnect™ technology to connect to the USB host upon detection of VBUS. The  
low power consumption in ‘suspend’ mode allows easy design of equipment that is  
compliant with the ACPI™, OnNow™ and USB power management requirements.  
The integrated keyboard controller is based on the 80C51 family and has 8 kbytes of  
mask ROM and 256 bytes of data RAM. The code memory is protected against  
reading by an external device. A built-in watchdog timer resets the device in case of a  
microcontroller hang-up. To reduce power consumption, the microcontroller can be  
put in sleep mode or power-down mode.  
c
c
A serial I2C-bus interface is provided for optional access to an external EEPROM.  
This allows the user to program the vendor ID, product ID or activate the built-in  
keyboard matrix.  
The ISP1130 has built-in overcurrent sense inputs, supporting individual and global  
overcurrent protection for downstream ports. All ports (including the hub) have  
GoodLink™ indicator outputs for easy visual monitoring of USB traffic. The ISP1130  
has a reduced frequency (6 MHz) crystal oscillator to minimize Electro Magnetic  
Interference (EMI). These features allow significant cost savings in system design  
and easy implementation of advanced USB functionality into PC peripherals.  
2. Features  
Compound USB hub device with integrated hub repeater, hub controller, Serial  
Interface Engine (SIE), data transceivers and 5 V to 3.3 V voltage regulator  
Complies with Universal Serial Bus Specification Rev. 1.1 and Device Class  
Definition for Human Interface Devices (HID)  
Complies with ACPI, OnNow and USB power management requirements  
 
ISP1130  
USB compound hub with keyboard controller  
Philips Semiconductors  
Supports bus-powered and hybrid-powered application  
1 to 2 downstream ports with automatic speed detection  
1 to 3 non-removable embedded functions, 1 dedicated for keyboard operation  
8 × 18 scan line matrix for HID compliant keyboard applications  
Integrated 80C51 microcontroller core with 8 kbytes mask ROM and 256 bytes  
data RAM  
On-chip watchdog timer for automatic fault recovery  
Internal power-on reset and low-voltage reset circuit  
Individual power switching for downstream ports  
Individual port overcurrent protection with built-in sense circuits  
6 MHz crystal oscillator with on-chip PLL for low EMI  
Reduced power consumption by putting microcontroller in sleep mode or  
power-down mode  
Visual USB traffic monitoring (GoodLink) for hub and downstream ports  
I2C-bus interface to read vendor ID, product ID and configuration bits from  
external EEPROM  
Operation over the extended USB bus voltage range (4.0 to 5.5 V)  
Operating temperature range 40 to +85 °C  
Available in 56-pin SDIP and SSOP packages.  
3. Ordering information  
Table 1: Ordering information  
Type number  
Package  
Name  
Description  
Version  
ISP1130DL  
ISP1130N  
SSOP56  
SDIP56  
plastic shrink small outline package; 56 leads; body width 7.5 mm  
plastic shrink dual in-line package; 56 leads (600 mil)  
SOT371-1  
SOT400-1  
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Objective specification  
Rev. 01 — 23 March 2000  
2 of 68  
 
ISP1130  
USB compound hub with keyboard controller  
Philips Semiconductors  
4. Block diagram  
GM8S1  
ha
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© Philips Electronics N.V. 2000. All rights reserved.  
Objective specification  
Rev. 01 — 23 March 2000  
3 of 68  
ISP1130  
USB compound hub with keyboard controller  
Philips Semiconductors  
5. Pinning information  
5.1 Pinning  
handbook, halfpage  
handbook, halfpage  
XTAL1  
XTAL2  
RESET  
1
2
56  
55  
XTAL1  
XTAL2  
RESET  
1
2
3
4
5
6
7
8
9
56  
55  
GND  
GND  
CAPSLOCK  
CAPSLOCK  
3
54 NUMLOCK  
54 NUMLOCK  
V
53  
V
53  
4
SCRLOCK  
SCRLOCK  
CC  
CC  
GND  
GND  
5
52  
52  
51  
INT  
INT  
V
PSEN  
6
V
pu(3.3)  
51  
50  
49  
PSEN  
ALE  
EA  
pu(3.3)  
UP_DM  
7
UP_DM  
UP_DP  
50 ALE  
UP_DP  
DN1_DM  
DN1_DP  
8
49  
48  
47  
46  
EA  
DN1_DM  
SYNCLK  
MEMSEL/UPGL  
GND  
9
48 SYNCLK  
47  
10  
DN1_DP 10  
DN2_DM 11  
MEMSEL/UPGL  
DN2_DM 11  
46  
45  
GND  
12  
13  
14  
12  
45 MY17/WR  
DN2_DP  
PSW1  
MY17/WR  
DN2_DP  
MY16/RD  
MY15  
44 MY16/RD  
MY15  
13  
44  
43  
42  
41  
PSW1  
14  
43  
PSW2  
PSW2  
ISP1130DL  
ISP1130N  
OC1/DPGL1 15  
16  
15  
16  
17  
18  
19  
20  
MY14  
42 MY14  
41 MY13  
OC1/DPGL1  
OC2/DPGL2  
GND  
MY13  
OC2/DPGL2  
GND 17  
40  
MY12  
40 MY12  
MX0  
MX1  
MX2  
MX0  
MY11  
MY10  
MY9  
MY8  
MY7  
MY6  
MY5  
MY4  
MY3  
V
18  
19  
20  
39 MY11  
38 MY10  
37 MY9  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
MX1  
MX2  
MX3/SCL 21  
MX4/SDA 22  
MX5 23  
MX3/SCL 21  
MX4/SDA 22  
MX5 23  
36  
35  
34  
33  
MY8  
MY7  
MY6  
MY5  
MX6 24  
MX6 24  
MX7 25  
MX7 25  
32 MY4  
MY0 26  
MY0 26  
MY3  
V
31  
30  
29  
MY1 27  
MY1 27  
reg(3.3)  
GND  
reg(3.3)  
MY2 28  
MY2 28  
GND  
MGS810  
MGS798  
Fig 2. Pin configuration SSOP56.  
Fig 3. Pin configuration SDIP56.  
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Objective specification  
Rev. 01 — 23 March 2000  
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ISP1130  
USB compound hub with keyboard controller  
Philips Semiconductors  
5.2 Pin description  
Table 2: Pin description (SSOP56 and SDIP56)  
Symbol[1]  
Pin  
1
Type  
Description  
XTAL1  
I
crystal oscillator input (6 MHz)  
crystal oscillator output (6 MHz)  
XTAL2  
2
O
I
RESET  
3
reset input (Schmitt trigger); a LOW level produces an  
asynchronous reset; connect to VCC for power-on reset  
(internal POR circuit)  
VCC  
4
5
6
-
-
-
supply voltage; connect to USB supply VBUS  
ground supply  
GND  
Vpu(3.3)  
regulated supply voltage (3.3 V ± 10%) from internal  
regulator; used to connect pull-up resistor on UP_DP line;  
pin function is controlled via the Device Status Register  
(see Table 36):  
Connect = 0 — Vpu(3.3) floating (high impedance)  
Connect = 1 — Vpu(3.3) = 3.3 V  
UP_DM  
UP_DP  
7
AI/O  
AI/O  
AI/O  
AI/O  
AI/O  
AI/O  
O
upstream port Dconnection (analog)  
upstream port D+ connection (analog)  
downstream port 1 Dconnection (analog)  
downstream port 1 D+ connection (analog)  
downstream port 2 Dconnection (analog)  
downstream port 2 D+ connection (analog)  
8
DN1_DM  
DN1_DP  
DN2_DM  
DN2_DP  
PSW1  
9
10  
11  
12  
13  
power switch control output for downstream port 1  
(open-drain)  
PSW2  
14  
15  
O
power switch control output for downstream port 2  
(open-drain)  
OC1/DPGL1  
AI/O  
pin function is controlled via the USBCON register (see  
Table 53):  
EnableOverCurrent = 0 — GoodLink LED indicator output  
for downstream port 1 (analog, open-drain); to connect an  
LED use a 330 series resistor  
EnableOverCurrent = 1 — overcurrent sense input for  
downstream port 1 (analog or digital); overcurrent sensing  
can be either analog (AnalogOCDisable = 0) or digital  
(AnalogOCDisable = 1)  
OC2/DPGL2  
16  
AI/O  
pin function is controlled via the USBCON register (see  
Table 53):  
EnableOverCurrent = 0 — GoodLink LED indicator output  
for downstream port 2 (analog, open-drain); to connect an  
LED use a 330 series resistor  
EnableOverCurrent = 1 — overcurrent sense input for  
downstream port 2 (analog or digital); overcurrent sensing  
can be either analog (AnalogOCDIsable = 0) or digital  
(AnalogOCDisable = 1)  
GND  
MX0  
MX1  
17  
18  
19  
-
I
I
ground supply  
keyboard matrix return line (5 V tolerant, open drain)[2]  
keyboard matrix return line (5 V tolerant, open drain)[2]  
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Objective specification  
Rev. 01 — 23 March 2000  
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ISP1130  
USB compound hub with keyboard controller  
Philips Semiconductors  
Table 2: Pin description (SSOP56 and SDIP56)…continued  
Symbol[1]  
Pin  
20  
Type  
I
Description  
MX2  
keyboard matrix return line (5 V tolerant, open drain)[2]  
MX3/SCL  
21  
I/O  
pin function is controlled via the I2C0CON register (see  
Table 76):  
ENS1 = 0 — keyboard matrix return line (5 V tolerant,  
open drain)[2]  
ENS1 = 1 — I2C-bus clock output (5 V tolerant, open  
drain)[2]  
MX4/SDA  
22  
I/O  
pin function is controlled via the I2C0CON register (see  
Table 76):  
ENS1 = 0 — keyboard matrix return line (5 V tolerant,  
open drain)[2]  
ENS1 = 1 — bidirectional I2C-bus data line (5 V tolerant,  
open drain)[2]  
MX5  
MX6  
MX7  
MY0  
MY1  
MY2  
GND  
Vreg(3.3)  
23  
24  
25  
26  
27  
28  
29  
30  
I
keyboard matrix return line(5 V tolerant, open drain)[2]  
keyboard matrix return line (5 V tolerant, open drain)[2]  
keyboard matrix return line (5 V tolerant, open drain)[2]  
bidirectional keyboard matrix scan line (5 V tolerant)[3]  
bidirectional keyboard matrix scan line (5 V tolerant)[3]  
bidirectional keyboard matrix scan line (5 V tolerant)[3]  
ground supply  
I
I
I/O  
I/O  
I/O  
-
-
regulated supply voltage (3.3 V ± 10%) from internal  
regulator; used to supply external devices  
MY3  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
bidirectional keyboard matrix scan line (5 V tolerant)[3]  
bidirectional keyboard matrix scan line (5 V tolerant)[3]  
bidirectional keyboard matrix scan line (5 V tolerant)[3]  
bidirectional keyboard matrix scan line (5 V tolerant)[3]  
bidirectional keyboard matrix scan line (5 V tolerant)[3]  
bidirectional keyboard matrix scan line (5 V tolerant)[3]  
bidirectional keyboard matrix scan line (5 V tolerant)[3]  
bidirectional keyboard matrix scan line (5 V tolerant)[3]  
bidirectional keyboard matrix scan line (5 V tolerant)[3]  
bidirectional keyboard matrix scan line (5 V tolerant)[3]  
bidirectional keyboard matrix scan line (5 V tolerant)[3]  
bidirectional keyboard matrix scan line (5 V tolerant)[3]  
bidirectional keyboard matrix scan line (5 V tolerant)[3]  
MY4  
MY5  
MY6  
MY7  
MY8  
MY9  
MY10  
MY11  
MY12  
MY13  
MY14  
MY15  
MY16/RD  
bidirectional keyboard matrix scan line (5 V tolerant)[3]  
used as read strobe when accessing external memory  
;
MY17/WR  
GND  
45  
46  
I/O  
-
bidirectional keyboard matrix scan line (5 V tolerant)[3]  
used as write strobe when accessing external memory  
;
ground supply  
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Objective specification  
Rev. 01 — 23 March 2000  
6 of 68  
ISP1130  
USB compound hub with keyboard controller  
Philips Semiconductors  
Table 2: Pin description (SSOP56 and SDIP56)…continued  
Symbol[1]  
Pin  
Type  
Description  
MEMSEL/  
UPGL  
47  
O
pin function is controlled via the USBCON register (see  
Table 53):  
GL-MEMSELSelection = 0 — upstream port GoodLink  
indicator output (open-drain)  
GL-MEMSELSelection = 1 — chip select output for  
external serial EEPROM (open-drain)  
SYNCLK  
EA  
48  
49  
O
I
embedded microcontroller clock output; used for emulation  
External Address enable input (internal pull-up); used to  
access external memory  
ALE  
50  
51  
O
O
Address Latch Enable output; used to demultiplex AD0  
during external memory access  
PSEN  
Program Store ENable output; selects external memory for  
program execution  
INT  
52  
53  
54  
55  
56  
I
external interrupt input (edge-triggered)  
control output for Scroll Lock LED (open-drain)  
control output for Num Lock LED (open-drain)  
control output for Caps Lock LED (open-drain)  
ground supply  
SCRLOCK  
NUMLOCK  
CAPSLOCK  
GND  
O
O
O
-
[1] Symbol names with an overscore (e.g. NAME) indicate active LOW signals.  
[2] MXn pins have an internal 8.2 kpull-up resistor.  
[3] MYn pins have an internal 82 kpull-down resistor (keyboard matrix enabled) or an internal 8.2 kΩ  
pull-up resistor (keyboard matrix disabled). This is controlled by bit DisableKBDMatrix in the USBCON  
register, see Table 53.  
6. Functional description  
The ISP1130 is a compound USB hub with an integrated keyboard controller. It has 2  
bus-powered downstream ports with 3 non-removable embedded functions, the first  
of which is dedicated to the keyboard function. The downstream ports can be used to  
connect low-speed or full-speed USB peripherals, such as a mouse, printer, another  
keyboard or another hub. The block diagram is shown in Figure 1.  
The embedded functions have no external hardware connections. They provide USB  
endpoints for equipment functions implemented by a microcontroller. Each endpoint  
has an associated FIFO buffer in the on-board RAM, which can be accessed by the  
integrated microcontroller via memory mapped registers using special commands  
(see Section 9).  
An optional serial I2C-bus interface (see Section 11) is provided for external  
EEPROM access, allowing the user to program the vendor ID, product ID or activate  
the built-in keyboard matrix.  
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Objective specification  
Rev. 01 — 23 March 2000  
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ISP1130  
USB compound hub with keyboard controller  
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6.1 80C51 microcontroller  
An integrated 80C51 microcontroller serves as a keyboard controller. It has 8 kbytes  
of mask ROM and 256 bytes of RAM. The I/O ports have been configured as an  
8 × 18 line scan matrix. Three LED control outputs are available for keyboard status  
indicators (Caps Lock, Num Lock and Scroll Lock). Interfacing to the USB hub is done  
via 3 registers (command, data, status), which are accessible via the external data  
memory address space (MOVX instruction).  
The keyboard firmware resides in the ROM and enumerates the embedded function  
as ‘HID compatible keyboard device’ during hub initialization.  
The microcontroller runs on a 12 MHz clock, derived from the PLL oscillator. A  
watchdog timer resets the microcontroller in case of a software hang-up.  
6.2 Analog transceivers  
The integrated transceivers interface directly to the USB cables through external  
termination resistors. They are capable of transmitting and receiving serial data at  
both ‘full-speed’ (12 Mbit/s) and ‘low-speed’ (1.5 Mbit/s) data rates. The slew rates  
are adjusted according to the speed of the device connected and lie within the range  
mentioned in the USB Specification Rev. 1.1.  
6.3 Philips Serial Interface Engine (SIE)  
The Philips SIE implements the full USB protocol layer. It is completely hardwired for  
speed and needs no firmware intervention. The functions of this block include:  
synchronization pattern recognition, parallel/serial conversion, bit (de-)stuffing, CRC  
checking/generation, Packet IDentifier (PID) verification/generation, address  
recognition, handshake evaluation/generation.  
6.4 Hub repeater  
The hub repeater is responsible for managing connectivity on a ‘per packet’ basis. It  
implements ‘packet signalling’ and ‘resume’ connectivity. Low-speed devices can be  
connected to downstream ports. If a low-speed device is detected the repeater will  
not propagate upstream packets to the corresponding port, unless they are preceded  
by a PREAMBLE PID.  
6.5 End-of-frame timers  
This block contains the specified EOF1 and EOF2 timers which are used to detect  
‘loss-of-activity’ and ‘babble’ error conditions in the hub repeater. The timers also  
maintain the low-speed keep-alive strobe which is sent at the beginning of a frame.  
6.6 General and individual port controller  
The general and individual port controllers together provide status and control of  
individual downstream ports. Any port status change will be reported to the host via  
the hub status change (interrupt) endpoint.  
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ISP1130  
USB compound hub with keyboard controller  
Philips Semiconductors  
6.7 GoodLink  
Indication of a good USB connection is provided through GoodLink technology. An  
LED can be directly connected via an external 330 resistor. The ISP1130 supports  
GoodLink indication for the hub (upstream port) via output MEMSEL/UPGL and for  
the two downstream ports via OCn/DPGLn, controlled via bits GL-MEMSELSelection  
and EnableOverCurrent in the USBCON register (see Table 53).  
During enumeration the LED blinks on momentarily. After successful configuration of  
the ISP1130, the LED is permanently on. The hub GoodLink indicator blinks off for  
approximately 128 ms when the hub receives a packet addressed to it. Downstream  
GoodLink indicators blink upon an acknowledgment from the associated port. In  
‘suspend’ mode the LED is off.  
This feature provides a user-friendly indication of the status of the hub, the connected  
downstream devices and the USB traffic. It is a useful diagnostics tool to isolate faulty  
USB equipment and helps to reduce field support and hotline costs.  
6.8 SoftConnect  
The connection to the USB is accomplished by bringing D+ (for full-speed USB  
devices) HIGH through a 1.5 kpull-up resistor. In the ISP1130, the 1.5 kpull-up  
resistor is integrated on-chip and by default is disconnected from the +3.3 V supply.  
The integrated microcontroller controls the connection of the internal resistor on D+ to  
Vpu(3.3) via bit SoftConnect_N in the USBCON register (see Table 53). Bit Connect in  
the Device Status register switches on Vpu(3.3) (default is off) to an alternative external  
pull-up resistor. A functional schematic diagram is given in Figure 4.  
id
ISP1130  
V
pu(3.3)  
Connect  
(Device Status  
Register)  
3.3 V  
supply  
1.5 k  
(internal  
pull-up)  
1.5 kΩ  
(external  
pull-up)  
SoftConnect_N  
(Configuration  
Register)  
UP_DP  
MGL920  
Fig 4. SoftConnect control logic.  
This mechanism allows the microcontroller to complete its initialization sequence  
before deciding to establish connection to the USB. Re-initialization of the USB  
connection can also be performed without disconnecting the cable.  
It should be noted that the tolerance of the internal resistors is higher (30%) than is  
specified by the USB specification (5%). However, the overall VSE voltage  
specification for the connection can still be met with good margin (see Table 92). The  
decision to use this feature lies with the USB equipment designer.  
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Rev. 01 — 23 March 2000  
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ISP1130  
USB compound hub with keyboard controller  
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6.9 Bit clock recovery  
The bit clock recovery circuit recovers the clock from the incoming USB data stream  
using a 4× oversampling principle. It is able to track jitter and frequency drift as  
specified by the USB Specification Rev. 1.1.  
6.10 Voltage regulator  
A 5 to 3.3 V DC-DC regulator is integrated on-chip to supply the analog transceiver  
and internal logic. This can also be used to supply the terminal 1.5 kpull-up resistor  
on the D+ line of the upstream connection.  
6.11 PLL clock multiplier  
A 6 to 48 MHz clock multiplier Phase-Locked Loop (PLL) is integrated on-chip. This  
allows for the use of low-cost 6 MHz crystals. The low crystal frequency also  
minimizes Electro-Magnetic Interference (EMI). The PLL requires no external  
components.  
6.12 Overcurrent detection  
An overcurrent detection circuit for downstream ports has been integrated on-chip. It  
is self-reporting, resets automatically, has a low trip time and requires no external  
components. The ISP1130 supports individual overcurrent detection.  
6.13 Power-on reset  
The ISP1130 has an internal power-on reset circuit, which generates a reset pulse  
when the supply voltage is switched on and when the supply voltage drops below a  
predetermined threshold value (see Table 89).  
6.14 I2C-bus interface  
A serial I2C-bus interface (single master or slave, bit rate up to 400 kHz) is provided  
to read vendor ID, product ID and other configuration data from an external EEPROM  
(e.g., Philips PCF8582 or equivalent). For more information, see Section 11.  
The I2C-bus interface timing is programmable and complies with the standard mode  
and the Fast mode of operation as described in The I2C-bus and how to use it, order  
number 9398 393 40011.  
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Objective specification  
Rev. 01 — 23 March 2000  
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ISP1130  
USB compound hub with keyboard controller  
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7. Endpoint descriptions  
Each USB device is logically composed of several independent endpoints. An  
endpoint acts as a terminus of a communication flow between the host and the  
device. At design time each endpoint is assigned a unique number (endpoint  
identifier, see Table 3). The combination of the device address (given by the host  
during enumeration), the endpoint number and the transfer direction allows each  
endpoint to be uniquely referenced.  
7.1 Endpoint configuration  
The ISP1130 hub has 1 to 2 downstream ports and 1 to 3 embedded functions. The  
upstream and downstream ports are fully handled by hardware and require no  
firmware intervention. Downstream port 2 can be disabled by connecting both D+ and  
Dto VCC  
.
The number of embedded functions can be configured from 1 to 3 via the USBCONA  
register. These embedded functions give access to the keyboard controller and other  
optional software functions. The functions are assigned as follows:  
Embedded function 1: standard keyboard  
Embedded function 2:  
multimedia functions (e.g. volume control)  
ACPI system control  
application launch keys  
Embedded function 3: user-defined functions.  
Each embedded function has two endpoint types: endpoint 0 (control) and endpoint 1  
(generic: bulk and/or interrupt). The embedded function endpoints can handle a  
maximum of 8 bytes per transfer.  
Table 3: Endpoint allocation  
Function  
Ports  
Endpoint Transfer  
identifier type  
Endpoint Direction[1] Max. packet  
index  
size (bytes)  
[2]  
0
control  
-
OUT  
IN  
64  
64  
1
0: upstream  
[2]  
1, 2[4]  
downstream  
:
Hub  
-
[2]  
1
0
interrupt  
control  
-
IN  
Embedded 3 (or 2[5]  
Function 1  
)
0
1
2
3
4
5
6
7
OUT  
IN  
8
8
1
0
1
generic[3]  
control  
OUT  
IN  
8
8
Embedded 4 (or 3[5]  
Function 2  
)
OUT  
IN  
8
8
generic[3]  
OUT  
IN  
8
8
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ISP1130  
USB compound hub with keyboard controller  
Philips Semiconductors  
Table 3: Endpoint allocation…continued  
Function  
Ports  
Endpoint Transfer  
identifier type  
Endpoint Direction[1] Max. packet  
index  
size (bytes)  
Embedded 5 (or 4[5]  
Function 3  
)
0
control  
8
OUT  
IN  
8
8
8
8
9
1
generic[3] 10  
11  
OUT  
IN  
[1] IN: input for the USB host; OUT: output from the USB host.  
[2] Hub endpoints are not indexed.  
[3] Generic endpoint can be used as bulk or interrupt endpoint.  
[4] Port 2 can be disabled by connecting both D+ and Dto VCC  
.
[5] The port number is reduced by 1 when downstream port 2 is disabled.  
7.2 Hub endpoint 0 (control)  
All USB devices and functions must implement a default control endpoint (ID = 0).  
This endpoint is used by the host to configure the device and to perform generic USB  
status and control access.  
The ISP1130 hub supports the following USB descriptor information through its  
control endpoint 0, which can handle transfers of 64 bytes maximum:  
Device descriptor  
Configuration descriptor  
Interface descriptor  
Endpoint descriptor  
Hub descriptor  
String descriptor.  
7.3 Hub endpoint 1 (interrupt)  
Endpoint 1 is used by the ISP1130 hub to provide port status change information to  
the host. This endpoint can be accessed only after the hub has been configured by  
the host (by sending the Set Configuration command).  
Endpoint 1 is an interrupt endpoint: the host polls it once every 255 ms by sending an  
IN token. If the hub has detected no change in the port status it returns a NAK (Not  
AcKnowledge) response to this request, otherwise it sends the Status Change byte  
(see Table 4).  
Table 4: Status Change byte: bit allocation  
Bit  
0
Symbol  
Hub SC  
Description  
a logic 1 indicates a status change on the hub’s upstream port  
a logic 1 indicates a status change on downstream port 1  
1
Port 1 SC  
Port 2 SC  
2
a logic 1 indicates a status change on downstream port 2 or on  
embedded function 1 (downstream port 2 disabled)  
3
Port 3 SC  
a logic 1 indicates a status change on embedded function 1 or on  
embedded function 2 (downstream port 2 disabled)  
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Table 4: Status Change byte: bit allocation…continued  
Bit  
Symbol  
Description  
4
Port 4 SC  
a logic 1 indicates a status change on embedded function 2 or on  
embedded function 3 (downstream port 2 disabled)  
5
Port 5 SC  
a logic 1 indicates a status change on embedded function 3; not used  
if downstream port 2 is disabled  
6
7
reserved  
reserved  
not used  
not used  
8. Host requests  
The ISP1130 handles all standard USB requests from the host via control endpoint 0.  
The control endpoint can handle a maximum of 64 bytes per transfer.  
Remark: Please note that the USB data transmission order is Least Significant Bit  
(LSB) first. In the following tables multi-byte variables are displayed least significant  
byte first.  
8.1 Standard requests  
Table 5 shows the supported standard USB requests. Some requests are explicitly  
unsupported. All other requests will be responded with a STALL packet.  
Table 5: Standard USB requests  
Request name  
bmRequestType bRequest  
wValue  
byte 2, 3  
(Hex)  
wIndex  
byte 4, 5  
(Hex)  
wLength  
byte 6, 7  
(Hex)  
Data  
byte 0 [7:0]  
(Bin)  
byte 1  
(Hex)  
Address  
Set Address  
Configuration  
Get Configuration  
X000 0000  
1000 0000  
05  
08  
address[1]  
00, 00  
00, 00  
00, 00  
00, 00  
01, 00  
none  
configuration  
value = 01H  
Set Configuration (0)  
Set Configuration (1)  
Descriptor  
X000 0000  
X000 0000  
09  
09  
00, 00  
01, 00  
00, 00  
00, 00  
00, 00  
00, 00  
none  
none  
Get Configuration  
Descriptor  
1000 0000  
06  
00, 02  
00, 00  
length[2]  
configuration,  
interface and  
endpoint  
descriptors  
Get Device Descriptor  
1000 0000  
06  
06  
06  
06  
00, 01  
00, 03  
01, 03  
02, 03  
00, 00  
00, 00  
09, 04  
09, 04  
length[2]  
length[2]  
length[2]  
length[2]  
device  
descriptor  
Get String Descriptor (0) 1000 0000  
Get String Descriptor (1) 1000 0000  
Get String Descriptor (2) 1000 0000  
language ID  
string  
manufacturer  
string  
product string  
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Table 5: Standard USB requests…continued  
Request name  
bmRequestType bRequest  
wValue  
byte 2, 3  
(Hex)  
wIndex  
byte 4, 5  
(Hex)  
wLength  
byte 6, 7  
(Hex)  
Data  
byte 0 [7:0]  
(Bin)  
byte 1  
(Hex)  
Feature  
Clear Device Feature  
(REMOTE_WAKEUP)  
X000 0000  
X000 0010  
X000 0000  
X000 0010  
01  
01  
03  
03  
01, 00  
00, 00  
01, 00  
00, 00  
00, 00  
81, 00  
00, 00  
81, 00  
00, 00  
00, 00  
00, 00  
00, 00  
none  
none  
none  
none  
Clear Endpoint (1)  
Feature (HALT/STALL)  
Set Device Feature  
(REMOTE_WAKEUP)  
Set Endpoint (1)  
Feature (HALT/STALL)  
Status  
Get Device Status  
Get Interface Status  
Get Endpoint (0) Status  
1000 0000  
1000 0001  
1000 0010  
00  
00  
00  
00, 00  
00, 00  
00, 00  
00, 00  
00, 00  
02, 00  
02, 00  
device status  
zero  
00/80[3], 00 02, 00  
endpoint 0  
status  
Get Endpoint (1) Status  
1000 0010  
0000 0000  
00  
07  
00, 00  
81, 00  
02, 00  
endpoint 1  
status  
Unsupported  
Set Descriptor  
XX, XX  
XX, XX  
XX, XX  
descriptor;  
STALL  
Get Interface  
Set Interface  
Synch Frame  
1000 0001  
X000 0001  
1000 0010  
0A  
0B  
0C  
00, 00  
XX, XX  
00, 00  
XX, XX  
XX, XX  
XX, XX  
01, 00  
00, 00  
02, 00  
STALL  
STALL  
STALL  
[1] Device address: 0 to 127.  
[2] Returned value in bytes.  
[3] MSB specifies endpoint direction: 0 = OUT, 1 = IN. The ISP1130 accepts either value.  
8.2 Hub specific requests  
In Table 6 the supported hub specific requests are listed, as well as some  
unsupported requests. Table 7 provides the feature selectors for setting or clearing  
port features.  
Table 6: Hub specific requests  
Request name  
bmRequestType bRequest  
wValue  
byte 2, 3  
(Hex)  
wIndex  
byte 4, 5  
(Hex)  
wLength  
byte 6, 7  
(Hex)  
Data  
byte 0 [7:0]  
(Bin)  
byte 1  
(Hex)  
Descriptor  
Get Hub Descriptor  
Feature  
1010 0000  
06  
00, 00/29[1] 00, 00  
length[2], 00 hub descriptor  
Clear Hub Feature  
(C_LOCAL_POWER)  
X010 0000  
X010 0011  
X010 0011  
01  
01  
03  
00, 00  
00, 00  
00, 00  
00, 00  
00, 00  
none  
none  
none  
Clear Port Feature  
(feature selectors)  
feature[3], 00 port [4], 00  
feature[3], 00 port [4], 00  
Set Port Feature  
(feature selectors)  
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Table 6: Hub specific requests…continued  
Request name  
bmRequestType bRequest  
wValue  
byte 2, 3  
(Hex)  
wIndex  
byte 4, 5  
(Hex)  
wLength  
byte 6, 7  
(Hex)  
Data  
byte 0 [7:0]  
(Bin)  
byte 1  
(Hex)  
Status  
Get Hub Status  
1010 0000  
1010 0011  
00  
00  
00, 00  
00, 00  
00, 00  
04, 00  
04, 00  
hub status and  
status change  
field  
Get Port Status  
Unsupported  
Get Bus Status  
port[4], 00  
port status  
1010 0011  
X010 0000  
02  
01  
00, 00  
01, 00  
port [4], 00  
00, 00  
01, 00  
00, 00  
STALL  
STALL  
Clear Hub Feature  
(C_OVER_CURRENT)  
Set Hub Descriptor  
X010 0000  
X010 0000  
07  
03  
XX, XX  
00, 00  
00, 00  
00, 00  
3E, 00  
00, 00  
STALL  
STALL  
Set Hub Feature  
(C_LOCAL_POWER)  
Set Hub Feature  
X010 0000  
03  
01, 00  
00, 00  
00, 00  
STALL  
(C_OVER_CURRENT)  
[1] USB Specification Rev. 1.0 uses 00H, USB Specification Rev. 1.1 specifies 29H.  
[2] Returned value in bytes.  
[3] Feature selector value, see Table 7.  
[4] Downstream port identifier: 1 to 5 (1, 2: downstream ports, 3 to 5: embedded functions 1 to 3). If downstream port 2 is disabled, the port  
identifiers are 1 to 4 (1: downstream port, 2 to 4: embedded functions 1 to 3).  
Table 7: Port feature selectors  
Feature selector name  
PORT_CONNECTION  
PORT_ENABLE  
Value (Hex) Set feature  
Clear feature  
not used  
00  
01  
02  
03  
04  
not used  
not used  
disables a port  
resumes a port  
not used  
PORT_SUSPEND  
PORT_OVERCURRENT  
PORT_RESET  
suspends a port  
not used  
resets and enables  
a port  
not used  
PORT_POWER  
08  
09  
10  
powers on a port  
not used  
powers off a port  
not used  
PORT_LOW_SPEED  
C_PORT_CONNECTION  
not used  
clears port connection  
change bit  
C_PORT_ENABLE  
11  
12  
not used  
not used  
not used  
not used  
clears port enable  
change bit  
C_PORT_SUSPEND  
clears port suspend  
change bit  
C_PORT_OVERCURRENT 13  
clears port overcurrent  
change bit  
C_PORT_RESET  
14  
clears port reset  
change bit  
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8.3 Descriptors  
The ISP1130 hub controller supports the following standard USB descriptors:  
Device  
Configuration  
Interface  
Endpoint  
Hub  
String.  
Table 8: Device descriptor  
Values in square brackets are optional.  
Offset  
(bytes)  
Field name  
Size  
Value  
Comments  
(bytes) (Hex)  
0
1
2
4
5
6
7
8
bLength  
1
1
2
1
1
1
1
2
12  
descriptor length = 18 bytes  
type = DEVICE  
USB Specification Rev. 1.1  
HUB_CLASSCODE  
-
bDescriptorType  
bcdUSB  
01  
10, 01  
09  
bDeviceClass  
bDeviceSubClass  
bDeviceProtocol  
bMaxPacketSize0  
idVendor  
00  
00  
-
40  
packet size = 64 bytes  
VID  
vendor ID; programmable via the Set  
VID/PID command (see Table 43)  
10  
12  
14  
idProduct  
2
2
1
PID  
product ID; programmable via the Set  
VID/PID command (see Table 43)  
bcdDevice  
iManufacturer  
00,  
XX[1]  
device release 1.0 (XX = 01H); silicon  
revision increments this value  
00  
no manufacturer string (default)  
manufacturer string enabled[2]  
no product string (default)  
product string enabled[2]  
no serial number string  
[01]  
00  
15  
iProduct  
1
[02]  
00  
16  
17  
iSerialNumber  
1
1
bNumConfigurations  
01  
one configuration  
[1] XX represents the hardware setting DEVREV, which indicates the 8-bit device release number. This  
value is incremented upon silicon revision.  
[2] Controlled via bit StringDescriptorEnable in the Set Mode command (see Table 25).  
Table 9: Configuration descriptor  
Values in square brackets are optional.  
Offset  
(bytes)  
Field name  
Size  
Value  
Comments  
(bytes) (Hex)  
0
1
2
bLength  
1
1
2
09  
descriptor length = 9 bytes  
type = CONFIGURATION  
bDescriptorType  
wTotalLength  
02  
19, 00  
total length of configuration, interface  
and endpoint descriptors (25 bytes)  
4
bNumInterfaces  
1
01  
one interface  
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Table 9: Configuration descriptor…continued  
Values in square brackets are optional.  
Offset  
(bytes)  
Field name  
Size  
Value  
Comments  
(bytes) (Hex)  
5
6
7
bConfigurationValue  
iConfiguration  
1
1
1
01  
00  
A0  
configuration value = 1  
no configuration string  
bmAttributes  
bus-powered with remote wake-up  
(default)  
[E0]  
32  
hybrid-powered with remote wake-up;  
configured via bit 7 in the USBCON  
register (see Table 53)  
8
MaxPower[1]  
1
100 mA  
[1] Value in units of 2 mA.  
Table 10: Interface descriptor  
Offset  
(bytes)  
Field name  
Size  
Value  
Comments  
(bytes) (Hex)  
0
1
2
3
4
5
6
7
8
bLength  
1
1
1
1
1
1
1
1
1
09  
04  
00  
00  
01  
09  
00  
00  
00  
descriptor length = 9 bytes  
type = INTERFACE  
-
bDescriptorType  
bInterfaceNumber  
bAlternateSetting  
bNumEndpoints  
bInterfaceClass  
bInterfaceSubClass  
bInterfaceProtocol  
bInterface  
no alternate setting  
status change (interrupt) endpoint  
HUB_CLASSCODE  
-
no class-specific protocol  
no interface string  
Table 11: Endpoint descriptor  
Offset  
(bytes)  
Field name  
Size  
Value  
Comments  
(bytes) (Hex)  
0
1
2
3
4
6
bLength  
1
1
1
1
2
1
07  
descriptor length = 7 bytes  
type = ENDPOINT  
bDescriptorType  
bEndpointAddress  
bmAttributes  
wMaxPacketSize  
bInterval  
05  
81  
endpoint 1, direction: IN  
interrupt endpoint  
03  
01, 00  
FF  
packet size = 1 byte  
polling interval (255 ms)  
Table 12: Hub descriptor  
Offset  
(bytes)  
Field name  
Size  
Value  
Comments  
(bytes) (Hex)  
0
1
2
bDescLength  
bDescriptorType  
bNbrPorts  
1
1
1
09  
descriptor length = 9 bytes  
type = HUB  
29  
03 [2]  
number of downstream ports (1 or 2;  
default = 2) + number of embedded  
functions (1 to 3; default = 1)  
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Table 12: Hub descriptor…continued  
Offset  
(bytes)  
Field name  
Size  
Value  
Comments  
(bytes) (Hex)  
3
wHubCharacteristics  
2
0D, 00  
15, 00  
individual power switching,  
individual overcurrent protection  
individual power switching,  
no overcurrent protection  
5
6
bPwrOn2PwrGood[1]  
bHubContrCurrent  
1
1
32  
64  
100 ms  
maximum hub controller current  
(100 mA)  
7
8
DeviceRemovable  
PortPwrCtrlMask  
1
1
08[3]  
FF  
downstream ports removable;  
embedded functions non-removable  
must be all ones for compatibility with  
USB Specification Rev. 1.0  
[1] Value in units of 2 ms.  
[2] Depending on the number of embedded functions configured, the value ranges from 03H to 05H or  
from 02H to 04H (downstream port 2 disabled).  
Remark: Downstream port 2 can be disabled by connecting both D+ and Dto VCC. Embedded  
functions are configured via the USBCONA register (see Table 55).  
[3] Default value (08H): ports 1 and 2 removable, port 3 non-removable. The value can be 08H, 18H or  
38H depending on the configured number of embedded functions (1, 2 or 3). When downstream  
port 2 is disabled, the possible values are 4CH, 0CH or 1CH (1, 2 or 3 embedded functions).  
Table 13: String descriptors  
String descriptors are optional and therefore disabled by default; they can be enabled via the  
Set Mode command (see Table 25).  
Offset  
(bytes)  
Field name  
Size  
Value  
Comments  
(bytes) (Hex)  
String descriptor (0): language ID string  
0
1
2
bLength  
1
1
2
04  
descriptor length = 4 bytes  
type = STRING  
bDescriptorType  
bString  
03  
09, 04  
LANGID code zero  
String descriptor (1): manufacturer string  
0
1
2
bLength  
1
2E  
descriptor length = 46 bytes  
type = STRING  
bDescriptorType  
bString  
1
03  
UC[1]  
44  
“Philips Semiconductors”  
String descriptor (2): product string  
0
1
2
bLength  
1
10  
descriptor length = 16 bytes  
type = STRING  
“ISP113X[2]; X = 0H for the ISP1130  
bDescriptorType  
bString  
1
03  
UC[1]  
14  
[1] Unicode encoded string.  
[2] X represents the hardware setting DEVNAME (4 bits), which specifies the final digit (X) in the device  
name string “ISP113X”. The Unicode representation of this digit is “0000.0000.0011.DEVNAME”.  
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8.4 Hub responses  
This section describes the hub responses to requests from the USB host.  
8.4.1 Get device status  
The hub returns 2 bytes, see Table 14.  
Table 14: Get device status response  
Bit #  
Function  
Value  
Description  
0
self-powered  
0
1
0
1
0
bus-powered  
hybrid-powered  
no remote wake-up  
remote wake-up enabled  
-
1
remote wake-up  
reserved  
2 to 15  
8.4.2 Get configuration  
The hub returns 1 byte, see Table 15.  
Table 15: Get configuration response  
Bit #  
Function  
Value  
Description  
device not configured  
device configured  
-
0
configuration value  
0
1
0
1 to 7  
reserved  
8.4.3 Get interface status  
The hub returns 2 bytes, see Table 16.  
Table 16: Get interface status response  
Bit #  
Function  
Value  
Description  
0 to 15  
reserved  
0
-
8.4.4 Get hub status  
The hub returns 4 bytes, see Table 17.  
Table 17: Get hub status response  
Bit #  
Function  
Value  
Description  
0
1
local power source  
overcurrent indicator  
0
0
1
0
0
local power supply good  
no overcurrent condition  
hub overcurrent condition detected  
-
2 to 15  
16  
reserved  
local power status change  
no change in local power status  
no change in overcurrent condition  
overcurrent condition changed  
-
17  
overcurrent indicator change 0  
1
18 to 31 reserved  
0
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8.4.5 Get port status  
The hub returns 4 bytes. The first 2 bytes contain the port status bits (wPortStatus,  
see Table 18). The last 2 bytes hold the port status change bits (wPortChange, see  
Table 19).  
Table 18: Get port status response (wPortStatus)  
Bit #  
Function  
Value  
Description  
0
current connect status  
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
no device present  
device present on this port  
port disabled  
1
2
3
4
port enabled/disabled  
suspend  
port enabled  
port not suspended  
port suspended  
no overcurrent condition  
overcurrent condition detected  
reset not asserted  
reset asserted  
overcurrent indicator  
reset  
5 to 7  
8
reserved  
-
port power  
port powered off  
port power on  
9
low-speed device attached  
full-speed device attached  
low-speed device attached  
-
10 to 15 reserved  
Table 19: Get port status response (wPortChange)  
Bit #  
Function  
Value  
Description  
0
connect status change  
0
1
0
1
0
1
no change in current connect status  
current connect status changed  
no port error  
1
port enabled/disabled  
change  
port disabled by a port error  
no change in suspend status  
resume complete  
2
suspend change  
3
overcurrent indicator change 0  
1
no change in overcurrent status  
overcurrent indicator changed  
no change in reset status  
reset complete  
4
reset change  
0
1
0
5 to 15  
reserved  
-
8.4.6 Get configuration descriptor  
The hub returns 25 bytes containing the configuration descriptor (9 bytes, see  
Table 9), the interface descriptor (9 bytes, see Table 10) and the endpoint descriptor  
(7 bytes, see Table 11).  
8.4.7 Get device descriptor  
The hub returns 18 bytes containing the device descriptor, see Table 8.  
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8.4.8 Get hub descriptor  
The hub returns 9 bytes containing the hub descriptor, see Table 12.  
8.4.9 Get string descriptor (0)  
The hub returns 4 bytes containing the language ID, see Table 13.  
8.4.10 Get string descriptor (1)  
The hub returns 46 bytes containing the manufacturer name, see Table 13.  
8.4.11 Get string descriptor (2)  
The hub returns 16 bytes containing the product name, see Table 13.  
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9. Commands  
There are three basic types of commands: Initialization, Data and General  
commands. Respectively, these are used to initialize the hub and the embedded  
functions; for data flow between the hub, embedded functions and the host; for  
controlling individual downstream ports; and general hub operation.  
The embedded microcontroller has access to the hub functions via 3 dedicated  
control registers (Command, Data, Status), which are mapped to the external data  
memory address space of the 80C51. See Section 10.4 “Hub control registers”.  
A summary of the available commands is given in Table 20. Some commands have  
the same command code (e.g., Read Buffer and Write Buffer). In these cases, the  
direction of the transaction (read or write) indicates which command is executed.  
To execute a command, the specified code must be written to the Command register.  
Any following transaction data can then be read or written via the Data register.  
Table 20: Command summary  
Name  
Destination  
Code (Hex)  
Transaction  
Initialization commands  
Set Address/Enable  
embedded function 1  
embedded function 2  
embedded function 3  
device  
D0  
D1  
D2  
D8  
F3  
write 1 byte  
write 1 byte  
write 1 byte  
write 1 byte  
write 2 bytes  
Set Endpoint Enable  
Set Mode  
device  
Data flow commands  
Read Interrupt Register device  
F4  
00  
01  
read 2 bytes  
Select Endpoint  
function 1 control OUT  
function 1 control IN  
read 1 byte (optional)  
read 1 byte (optional)  
read 1 byte (optional)  
read 1 byte (optional)  
read 1 byte (optional)  
read 1 byte (optional)  
read 1 byte (optional)  
read 1 byte (optional)  
read 1 byte (optional)  
read 1 byte (optional)  
read 1 byte (optional)  
read 1 byte (optional)  
read n bytes  
function 1 endpoint OUT 02  
function 1 endpoint IN  
function 2 control OUT  
function 2 control IN  
03  
04  
05  
function 2 endpoint OUT 06  
function 2 endpoint IN  
function 3 control OUT  
function 3 control IN  
07  
08  
09  
function 3 endpoint OUT 0A  
function 3 endpoint IN  
selected endpoint  
selected endpoint  
0B  
F0  
F0  
Read Buffer  
Write Buffer  
write n bytes  
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Table 20: Command summary…continued  
Name  
Destination  
Code (Hex)  
Transaction  
read 1 byte  
read 1 byte  
read 1 byte  
read 1 byte  
read 1 byte  
read 1 byte  
read 1 byte  
read 1 byte  
read 1 byte  
read 1 byte  
read 1 byte  
read 1 byte  
write 1 byte  
write 1 byte  
write 1 byte  
write 1 byte  
write 1 byte  
write 1 byte  
write 1 byte  
write 1 byte  
write 1 byte  
write 1 byte  
write 1 byte  
write 1 byte  
read 1 byte  
none  
Select Endpoint/  
Clear Interrupt  
function 1 control OUT  
function 1 control IN  
40  
41  
function 1 endpoint OUT 42  
function 1 endpoint IN  
function 2 control OUT  
function 2 control IN  
43  
44  
45  
function 2 endpoint OUT 46  
function 2 endpoint IN  
function 3 control OUT  
function 3 control IN  
47  
48  
49  
function 3 endpoint OUT 4A  
function 3 endpoint IN  
function 1 control OUT  
function 1 control IN  
4B  
40  
41  
Set Endpoint Status  
function 1 endpoint OUT 42  
function 1 endpoint IN  
function 2 control OUT  
function 2 control IN  
43  
44  
45  
function 2 endpoint OUT 46  
function 2 endpoint IN  
function 3 control OUT  
function 3 control IN  
47  
48  
49  
function 3 endpoint OUT 4A  
function 3 endpoint IN  
selected endpoint  
selected endpoint  
4B  
F2  
FA  
Clear Buffer  
Validate Buffer  
General commands  
Read Device Status  
Set Device Status  
device  
device  
device  
FE  
FE  
F5  
read 1 byte  
write 1 byte  
Read Current Frame  
Number  
read 1 or 2 bytes  
Read Embedded Port  
Status  
embedded function 1  
embedded function 2  
embedded function 3  
embedded function 1  
embedded function 2  
embedded function 3  
device  
E0  
E1  
E2  
E0  
E1  
E2  
FB  
FD  
FF  
read 1 byte  
read 1 byte  
read 1 byte  
write 1 byte  
write 1 byte  
write 1 byte  
write 4 bytes  
read 2 bytes  
read 1 byte  
Write Embedded Port  
Status  
Set VID/PID  
Read Chip ID  
Get Last Error  
device  
device  
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9.1 Initialization commands  
Initialization commands are used during the enumeration process of the USB  
network. These commands are used to enable the hub and embedded function  
endpoints. They are also used to set the USB assigned address.  
9.1.1 Set Address/Enable command  
Sets the USB assigned address and enables the embedded function. This also  
enables the associated control endpoint. Embedded functions each must have a  
unique USB address.  
Code (Hex) — D0 to D2 (embedded functions 1 to 3)  
Transaction — write 1 byte.  
Table 21: Set Address/Enable command: bit allocation  
Bit  
7
6
5
4
3
2
1
0
Symbol  
Reset  
Access  
DevEnable  
DevAddress  
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
Table 22: Set Address/Enable command: bit description  
Bit  
7
Symbol  
Description  
A logic 1 enables the embedded function  
USB assigned address of the embedded function  
DevEnable  
DevAddress  
6 to 0  
9.1.2 Set Endpoint Enable command  
Enables the specified endpoints of the hub and/or the embedded functions. The  
corresponding function must first be enabled via the Set Address/Enable command.  
Code (Hex) — D8  
Transaction — write 1 byte.  
Table 23: Set Endpoint Enable command: bit allocation  
Bit  
7
6
5
4
3
2
1
0
Func3  
GenEndp  
Enable  
Func2  
GenEndp  
Enable  
Func1  
GenEndp  
Enable  
Symbol  
-
-
-
-
-
Reset  
X
X
X
X
X
0
0
0
Access  
W
W
W
W
W
W
W
W
Table 24: Set Endpoint Enable command: bit description  
Bit  
Symbol  
Description  
7 to 3  
-
reserved  
2
1
0
Func3GenEndpEnable  
Func2GenEndpEnable  
Func1GenEndpEnable  
A logic 1 enables the generic endpoint of embedded function 3  
A logic 1 enables the generic endpoint of embedded function 2  
A logic 1 enables the generic endpoint of embedded function 1  
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9.1.3 Set Mode command  
Selects the operating mode and (de)activates features. The command is followed by  
one data write, containing the Configuration byte.  
Code (Hex) — F3  
Transaction — write 1 byte (Configuration).  
Table 25: Set Mode command, Configuration byte: bit allocation  
Bit  
7
6
5
4
3
2
1
0
String  
Descriptor  
Enable  
Remote  
WakeUp  
Enable  
Always  
PLL  
Clock  
Use  
IntDn  
Resistor  
Clock  
Restart  
Interrupt  
OnNAK  
Symbol  
-
-
Reset  
X
0
0
0
0
0
0
1
Access  
W
W
W
W
W
W
W
W
Table 26: Set Mode command, Configuration byte: bit description  
Bit  
7
Symbol  
Description  
-
reserved  
6
ClockRestart  
A logic 1 will cause a clock restart for 2 ms upon a bus transition, when the device  
is in ‘suspend’ mode. This allows the device to wake up without resume signaling.  
5
StringDescriptorEnable  
A logic 1 enables the string descriptor. The default string will be sent to the host  
upon request.  
4
3
RemoteWakeUpEnable  
AlwaysPLLClock  
A logic 1 enables remote wake-up by key press (embedded function 1).  
A logic 1 indicates that the internal clocks and PLL are always running, even in  
‘suspend’ mode. A logic 0 stops the internal clock, crystal oscillator and PLL.  
2
1
0
UseIntDnResistor  
A logic 1 causes the downstream pull-down resistors to be connected.  
reserved; must always be logic 0  
-
InterruptOnNAK  
A logic 1 will generate an interrupt upon sending a NAK. A logic 0 will only report  
successful transactions.  
9.2 Data flow commands  
Data flow commands are used to manage the data transmission between the USB  
endpoints and the embedded microcontroller. Much of the data flow is initiated via an  
interrupt to the microcontroller. The data flow commands are used to access the  
endpoints and determine whether the endpoint FIFOs contain valid data.  
Remark: The IN buffer of an endpoint contains input data for the host, the OUT buffer  
receives output data from the host.  
9.2.1 Read Interrupt Register command  
Shows the source(s) of an interrupt to the microcontroller. After writing the command,  
two bytes are read which hold the interrupt register contents. Byte 1 contains the  
least significant bits (7 to 0), byte 2 the most significant bits (15 to 8).  
Code (Hex) — F4  
Transaction — read 2 bytes.  
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Remark: All hub endpoints are handled internally by the ISP1130 hardware without  
the need of microcontroller intervention.  
Table 27: Interrupt Register: bit configuration  
Bit  
15  
14  
13  
12  
11  
10  
9
8
Device  
Port5  
Port4  
Port3  
Func3  
Endp1  
In  
Func3  
Endp1  
Out  
Func3  
ContlIn  
Endp  
Func3  
ContlOut  
Endp  
Symbol  
StatusReg StatusReg StatusReg StatusReg  
Change  
Change  
Change  
Change  
Reset  
Access  
Bit  
0
R
7
0
R
6
0
R
5
0
R
4
0
R
3
0
R
2
0
R
1
0
R
0
Func2  
Endp1  
In  
Func2  
Endp1  
Out  
Func2  
ContlIn  
Endp  
Func2  
ContlOut  
Endp  
Func1  
Endp1  
In  
Func1  
Endp1  
Out  
Func1  
ContlIn  
Endp  
Func1  
ContlOut  
Endp  
Symbol  
Reset  
0
0
0
0
0
0
0
0
Access  
R
R
R
R
R
R
R
R
Table 28: Interrupt Register: bit description  
Bit  
Symbol  
Description  
Byte 2  
15  
DeviceStatusRegChange  
Port5StatusRegChange  
Port4StatusRegChange  
Port3StatusRegChange  
Func3Endp1In  
Status register change on hub device  
14  
Status register change on embedded function 3  
Status register change on embedded function 2  
Status register change on embedded function 1  
Endpoint 1 IN of embedded function 3  
13  
12  
11  
10  
Func3Endp1Out  
Endpoint 1 OUT of embedded function 3  
Control endpoint IN of embedded function 3  
Control endpoint OUT of embedded function 3  
9
Func3ContlInEndp  
8
Func3ContlOutEndp  
Byte 1  
7
6
5
4
3
2
1
0
Func2Endp1In  
Endpoint 1 IN of embedded function 2  
Func2Endp1Out  
Func2ContlInEndp  
Func2ContlOutEndp  
Func1Endp1In  
Endpoint 1 OUT of embedded function 2  
Control endpoint IN of embedded function 2  
Control endpoint OUT of embedded function 2  
Endpoint 1 IN of embedded function 1  
Func1Endp1Out  
Func1ContlInEndp  
Func1ContlOutEndp  
Endpoint 1 OUT of embedded function 1  
Control endpoint IN of embedded function 1  
Control endpoint OUT of embedded function 1  
The interrupt register bits are cleared as follows:  
Reading the Device Status register resets the DeviceStatusRegChange bit  
Reading the Embedded Port Status register of a port resets the associated  
PortStatusRegChange bit  
The Select Endpoint/Clear Interrupt command clears the endpoint interrupt bits of  
the selected endpoint.  
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9.2.2 Select Endpoint command  
Selects an endpoint and initializes an internal pointer to the start of the associated  
RAM buffer. Optionally, this command can be followed by a data read, which returns  
the status of the endpoint buffer (see Table 29).  
Code (Hex) — 00 to 0B (endpoint index 0 to 11)  
Transaction — read 1 byte (optional).  
Table 29: Endpoint Buffer Status byte: bit allocation  
Bit  
7
6
5
4
3
2
1
0
Full  
Empty  
Status  
Sent  
NAK  
Packet  
Overwritten  
Setup  
Packet  
Stall  
Status  
Symbol  
-
-
-
Reset  
X
R
X
R
X
R
0
0
0
0
0
Access  
R
R
R
R
R
Table 30: Endpoint Buffer Status byte: bit description  
Bit  
7 to 5  
4
Symbol  
Description  
-
reserved  
SentNAK[1]  
A logic 1 indicates that the device has sent a NAK. This bit is reset when the  
device returns an acknowledge (ACK) after receiving an OUT packet, or when it  
gets an ACK after sending an IN packet.  
3
2
PacketOverwritten  
SetupPacket[2]  
A logic 1 indicates that the previous packet was overwritten by a Setup packet.  
This bit is reset by a Select Endpoint/Clear Interrupt command on this endpoint.  
A logic 1 indicates that the last successfully received packet had a SETUP token.  
This bit is reset by a Select Endpoint/Clear Interrupt command on this endpoint.  
1
0
StallStatus  
A logic 1 indicates that the endpoint is in stalled state.  
FullEmptyStatus  
A logic 1 indicates that the buffer is full, a logic 0 indicates that it is empty.  
[1] This bit is only defined for control endpoints; it is active only when the InterruptOnNAK feature has been enabled via the Set Mode  
command (see Table 25).  
[2] This bit will be logic 0 for IN buffers (host packets are received via the OUT buffer).  
9.2.3 Read Buffer command  
Returns the data buffer contents of the selected endpoint. Following the command, a  
maximum of (N + 2) bytes can be read, N representing the size of the endpoint buffer  
(see Table 3). After each byte the internal buffer pointer is automatically incremented  
by 1. To reset the buffer pointer to the start of the buffer, use the Select Endpoint  
command.  
Code (Hex) — F0  
Transaction — read multiple bytes (max. N + 2, N = buffer size).  
Reading a buffer may be interrupted by any other command (except for Select  
Endpoint). The data in the buffer are organized as shown in Table 31.  
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Table 31: Endpoint buffer organization  
Byte #  
Bit 7  
0/1 [1]  
X
Bit 6  
0/1[2]  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 7  
0
X
X
X
X
X
X
1
N (number of data bytes in the buffer)  
2
data byte 0  
...  
...  
N + 2  
data byte N 1  
[1] A logic 1 indicates that the packet was successfully received via the USB bus.  
[2] A logic 1 indicates that the packet in the buffer has a SETUP token.  
9.2.4 Write Buffer command  
Fills the data buffer of the selected endpoint. Following the command, a maximum of  
(N + 2) bytes may be written, N representing the size of the endpoint buffer (see  
Table 3). After each byte the internal buffer pointer is automatically incremented by 1.  
To reset the buffer pointer to the start of the buffer, use the Select Endpoint  
command.  
Code (Hex) — F0  
Transaction — write multiple bytes (max. N + 2, N = buffer size).  
Writing a buffer may be interrupted by any other command (except for Select  
Endpoint). The data must be organized in the same way as shown in Table 31. Upon  
writing, the value of byte 0 must be zero.  
Remark: There is no protection against writing or reading past a buffer’s boundary,  
against writing into an OUT buffer or reading from an IN buffer. Any of these actions  
could cause an incorrect operation. Data residing in an OUT buffer are only  
meaningful after a successful transaction.  
9.2.5 Select Endpoint/Clear Interrupt  
Selects the endpoint and clears the associated interrupt. In case of a Control  
endpoint, it also clears the SetupPacket and PacketOverwritten status bits. A data  
read following the command returns the endpoint buffer status (see Table 29 and  
Table 30).  
Code (Hex) — 40 to 4B (endpoint index 0 to 11)  
Transaction — read 1 byte.  
9.2.6 Clear Buffer command  
Unlocks the buffer of the selected endpoint, allowing the reception of new packets. An  
optional data read may follow the command, returning the packet status (see  
Table 32).  
Code (Hex) — F2  
Transaction — read 1 byte (optional).  
When a packet has been received successfully, an internal Buffer Full flag is set. Any  
subsequent packets will be refused by returning a NAK. After reading all data, the  
microcontroller must free the buffer using the Clear Buffer command.  
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Table 32: Packet Status byte: bit allocation  
Bit  
7
6
5
4
3
2
1
0
Symbol  
-
-
-
-
-
-
-
Packet  
Overwritten  
Reset  
X
R
X
R
X
R
X
R
X
R
X
R
X
R
0
Access  
R
Table 33: Packet Status byte: bit description  
Bit  
7 to 1  
0
Symbol  
Description  
-
reserved  
PacketOverwritten  
A logic 1 indicates that the previous packet was overwritten by a Setup Packet. In  
that case the buffer is not cleared.  
9.2.7 Validate Buffer command  
Indicates the presence of valid data for transmission to the USB host.  
Code (Hex) — FA  
Transaction — none.  
After writing data into an endpoint’s IN buffer, the microcontroller must set the Buffer  
Full flag by means of the Validate Buffer command. This indicates that the data in the  
buffer are valid and can be sent to the host when the next IN token is received.  
Remark: A control IN buffer cannot be validated when the Packet Overwritten bit of  
the corresponding OUT buffer is set.  
9.2.8 Set Endpoint Status command  
Stalls or unstalls the indicated endpoint.  
Code (Hex) — 40 to 4B (endpoint index 0 to 11)  
Transaction — write 1 byte.  
A stalled control endpoint is automatically unstalled when it receives a SETUP token,  
regardless of the content of the packet. If the endpoint should stay in its stalled state,  
the microcontroller can re-stall it with the Set Endpoint Status command.  
When a stalled endpoint is unstalled (either by the Set Endpoint Status command or  
by receiving a SETUP token), it is also re-initialized. This flushes the buffer: in and if it  
is an OUT buffer it waits for a DATA 0 PID, if it is an IN buffer it writes a DATA 0 PID.  
Remark: A Set Endpoint Status command with a STALLED bit of logic 0 will always  
initialize the endpoint, even when it was not stalled.  
Table 34: Set Endpoint Status command: bit allocation  
Bit  
7
6
5
4
3
2
1
0
Symbol  
Conditional  
Stall  
Rate  
Feedback  
Mode  
Disable  
-
-
-
-
Stalled  
Reset  
0
0
0
X
X
X
X
0
Access  
W
W
W
W
W
W
W
W
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Table 35: Set Endpoint Status command: bit description  
Bit  
Symbol  
Description  
7
ConditionalStall  
A logic 1 stalls both endpoints of a Control endpoint (Endpoint identifier = 0),  
unless the Setup Packet bit is set. In that case the entire command is ignored.  
6
5
RateFeedbackMode  
Disable  
A logic 1 switches an interrupt endpoint to ‘rate feedback mode’, a logic 0 enables  
‘toggle’ mode.  
A logic 1 disables the selected endpoint, a logic 0 enables it again. A bus reset  
(re-)enables all endpoints.  
4 to 1  
0
-
reserved  
Stalled  
A logic 1 stalls the selected endpoint. A logic 0 unstalls the endpoint and  
(re-)initializes it, whether it was stalled or not.  
[1] A ConditionalStall does not work if the PacketOverwritten status bit is set.  
9.3 General commands  
9.3.1 Read Device Status  
Returns the Device Status register contents, see Table 36 and Table 37. When the  
SuspendChange, ConnectChange or BusReset bit is logic 1, the corresponding bit in  
the Interrupt register is set and a microcontroller interrupt is generated.  
Code (Hex) — FE  
Transaction — read 1 byte.  
9.3.2 Set Device Status  
Changes the Device Status register. The contents of read-only bits are ignored.  
Code (Hex) — FE  
Transaction — write 1 byte.  
Table 36: Device Status register: bit allocation  
Bit  
7
6
5
4
3
2
1
0
Symbol  
-
-
-
Bus  
Reset  
Suspend  
Change  
Suspend  
Connect  
Change  
Connect  
Reset  
X
X
X
X
R
X
R
X
X
R
0
Access  
W
W
W
R/W  
R/W  
Table 37: Device Status register: bit description  
Bit  
7 to 5  
4
Symbol  
-
Description  
reserved  
BusReset  
A logic 1 signals that the device received a bus reset. Upon a bus reset the device  
will automatically enter its default state (unconfigured and responding to  
address 0). This bit is cleared when it is read.  
3
SuspendChange  
A logic 1 signals that the value of the Suspend bit has changed. The Suspend bit  
changes when the device enters ‘suspend’ mode or when it receives a ‘resume’  
signal on its upstream port. This bit is cleared when it is read.  
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Table 37: Device Status register: bit description…continued  
Bit  
Symbol  
Description  
2
Suspend  
Upon reading this bit indicates the current ‘suspend’ status: A logic 1 indicates  
that no activity occurred on the upstream port for more than 3 ms. Any activity on  
the upstream port will reset this bit to logic 0.  
Writing a logic 0 into this bit will generate a remote wake-up, if the device is  
suspended (Suspend = 1). Otherwise, writing a logic 0 has no effect.  
Remark: Writing a logic 1 never has any effect.  
1
0
ConnectChange  
Connect  
A logic 1 signals that the value of the Connect bit has changed. This bit is cleared  
when it is read.  
Writing a logic 1 causes the device to connect its pull-up resistor to the upstream  
port, a logic 0 disconnects the pull-up resistor. Upon reading this bit indicates the  
current ‘connect’ status.  
9.3.3 Read Current Frame Number  
Reports the frame number (11 bits) of the last successfully received Start Of Frame  
(SOF). It is followed by one or two data reads containing the frame number. Byte 1  
contains the least significant bits of the frame number (bits 7 to 0), byte 2 holds the  
most significant bits (bits 10 to 8) padded with zeroes (see Table 38).  
Code (Hex) — F5  
Transaction — read 1 or 2 bytes.  
Table 38: Frame number: bit allocation  
Bit  
15  
-
14  
-
13  
-
12  
-
11  
-
10  
9
8
Symbol  
Reset  
Access  
Bit  
frame[10:8]  
0
0
0
0
0
0
R
2
0
R
1
0
R
0
R
7
R
6
R
5
R
4
R
3
Symbol  
Reset  
Access  
frame[7:0]  
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
9.3.4 Read Embedded Port Status  
Returns the Embedded Port Status register contents, see Table 39 and Table 40.  
When the SuspendChange or BusReset bit is logic 1, the corresponding bit in the  
Interrupt register is set (see Table 27 and Table 28) and a microcontroller interrupt is  
generated. This command resets the SuspendChange, ConnectChange and  
BusReset bits.  
Code (Hex) — E0 to E2 (embedded function 1 to 3)  
Transaction — read 1 byte.  
9.3.5 Write Embedded Port Status  
Changes the Embedded Port Status register. Contents of read-only bits are ignored.  
Code (Hex) — E0 to E2 (embedded function 1 to 3)  
Transaction — write 1 byte.  
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Table 39: Embedded Port Status register: bit allocation  
Bit  
7
6
5
4
3
2
1
0
Symbol  
-
-
-
Port  
Reset  
Suspend  
Change  
Suspend  
Connect  
Change  
Connect  
Reset  
X
X
X
0
0
0
0
0
Access  
W
W
W
R
R
R/W  
R
R/W  
Table 40: Embedded Port Status register: bit description  
Bit  
7 to 5  
4
Symbol  
-
Description  
reserved  
PortReset  
A logic 1 signals that a Set Port Feature (PORT_RESET) request was received by  
the embedded port. If this bit is logic 1, reading it will clear the bit, enable the  
embedded port and report the end of the reset to the host.  
3
2
SuspendChange  
Suspend  
A logic 1 signals that the value of the Suspend bit has changed. The Suspend bit  
changes when the device enters ‘suspend’ mode or when it receives a ‘resume’  
signal on its upstream port. This bit is cleared when it is read.  
Upon reading this bit indicates the current ‘suspend’ status: A logic 1 indicates  
that the embedded port is suspended.  
Writing a logic 0 into this bit will generate a remote wake-up, if the embedded port  
is suspended (Suspend = 1). Otherwise, writing a logic 0 has no effect.  
Remark: Writing a logic 1 never has any effect.  
1
0
ConnectChange  
Connect  
A logic 1 signals that the value of the Connect bit has changed. This bit is cleared  
when it is read.  
Writing a logic 1 causes the embedded port to be connected, a logic 0  
disconnects the embedded port. Upon reading this bit indicates the current  
‘connect’ status.  
9.3.6 Read Chip ID  
Reports the chip identification code (12 bits), comprising the device release number  
DEVREV (see Table 8 “Device descriptor”) and the last digit of the device name  
DEVNAME (see Table 13 “String descriptors”). Byte 1 contains the least significant  
bits of the chip identification code, byte 2 the most significant bits (see Table 41 and  
Table 42).  
Code (Hex) — FD  
Transaction — read 2 bytes.  
Table 41: Chip identification code: bit allocation  
Bit  
15  
-
14  
-
13  
-
12  
-
11  
10  
9
8
Symbol  
Reset  
Access  
Bit  
DEVNAME[3:0]  
0
0
0
0
0
R
3
0
R
2
0
R
1
1
R
0
R
7
R
6
R
5
R
4
Symbol  
Reset  
Access  
DEVREV[7:0]  
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
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Table 42: Chip identification code: bit description  
Bit  
Symbol  
Description  
15 to 12  
11 to 8  
-
reserved  
DEVNAME[3:0]  
DEVNAME specifies the final digit (X) in the device name string “ISP113X”.  
The Unicode representation of this digit is “0000.0000.0011.DEVNAME”.  
For ISP1130 the value of X is 0H.  
7 to 0  
DEVREV[7:0]  
DEVREV represents the 8-bit device release number (01H = release 1.0).  
This value is incremented upon silicon revision.  
9.3.7 Set VID/PID  
Modifies the vendor ID and the product ID codes, which are reported in the Device  
descriptor (see Table 8).  
Code (Hex) — FB  
Transaction — write 4 bytes.  
Table 43: Set VID/PID command: data byte allocation  
Byte  
Description  
0
1
2
3
vendor ID (lower byte)  
vendor ID (upper byte)  
product ID (lower byte)  
product ID (upper byte)  
9.3.8 Get Last Error  
Reports the 4-bit error code of the last generated error. The bit ‘ErrorOccurred’ is  
refreshed upon each new packet transfer.  
Code (Hex) — FF  
Transaction — read 1 byte.  
Table 44: Last error byte: bit allocation  
Bit  
7
6
5
4
3
2
1
0
Symbol  
-
-
-
Error  
ErrorCode[3:0]  
Occurred  
Reset  
X
R
X
R
X
R
0
0
0
0
0
Access  
R
R
R
R
R
Table 45: Register bits description  
Bit  
Symbol  
Description  
7 to 5  
4
-
reserved  
ErrorOccurred  
ErrorCode[3:0]  
A logic 1 indicates that the last packet generated an error.  
error code; for error interpretation see Table 46 “Transaction error codes”  
3 to 0  
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Table 46: Transaction error codes  
Error code  
(Binary)  
Description  
0000  
no error  
0001  
PID encoding error; bits 7 to 4 are not the inverse of bits 3 to 0  
PID unknown; encoding is valid, but PID does not exist  
0010  
0011  
unexpected packet; packet is not of the expected type (token, data, or  
acknowledge), or is a SETUP token to a non-control endpoint  
0100  
0101  
0110  
0111  
1000  
1001  
1010  
1011  
1100  
1101  
1110  
1111  
token CRC error  
data CRC error  
time-out error  
babble error  
unexpected end-of-packet  
sent or received NAK (Not AcKnowledge)  
sent Stall; a token was received, but the endpoint was stalled  
overflow; the received packet was larger than the available buffer space  
sent empty packet (ISO only)  
bit stuffing error  
sync error  
wrong (unexpected) toggle bit in DATA PID; data was ignored  
10. Keyboard controller  
10.1 Microcontroller core  
The integrated 80C51 microcontroller has 8 kbytes of mask ROM and 256 bytes of  
RAM. The I/O ports have been configured as an 8 × 18 line keyboard scan matrix.  
Interfacing to the USB hub is done via 3 registers (Command, Data, Status), which  
are accessible via the external data memory address space (MOVX instruction).  
The keyboard firmware resides in the ROM and enumerates the embedded function  
as ‘HID compatible keyboard device’ during hub initialization.  
The microcontroller runs on a 12 MHz clock (fMCU_CLOCK), derived from the PLL  
oscillator. A watchdog timer resets the microcontroller in case of a software hang-up.  
10.2 Memory map  
10.2.1 Data memory  
The internal data memory of ISP1130 is divided into two physically separate areas:  
256 bytes RAM and 128 bytes of Special Function Registers (SFRs). Addressing is  
done as follows (see Figure 5):  
RAM (00H to 7FH): direct and indirect addressing; for indirect addressing registers  
R0 and R1 of the selected register bank are used as address pointers  
RAM (80H to FFH): indirect addressing, using registers R0 and R1 of the selected  
register bank as address pointers  
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SFRs (80H to FFH): direct addressing  
4 register banks (00H to 1FH): direct addressing; only 1 register bank may be  
enabled at any time  
Bit-addressable locations (20H to 2FH): direct addressing; these 16 bytes can  
be used as 128 bit-addressable locations.  
w
FFH  
SFRs  
INDIRECT  
ADDRESSING  
DIRECT  
ADDRESSING  
ONLY  
80H  
7FH  
DIRECT &  
INDIRECT  
ADDRESSING  
20H  
00H  
4 BANKS OF R0 to R7  
MGS799  
Data Memory Space  
Fig 5. Data memory organization.  
10.2.2 Program memory  
The ISP1130 has 8 kbytes of masked ROM for storing the 80C51 operating software.  
In order to protect the ROM against illegal copying, execution of a MOVC instruction  
from external code memory has been blocked. Instead of reading the program  
memory, it accesses the on-chip data memory.  
handbook, halfpage  
1FFFH  
8 kbytes  
ON-CHIP  
USER ROM  
0000H  
MGS800  
Fig 6. Program memory organization.  
10.3 Special function registers (SFRs)  
The SFRs of the 80C51 can only be directly addressed. The memory map is given in  
Table 47.  
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Table 47: SFR memory map  
Address  
range  
(Hex)  
Offset  
0
1
2
3
4
5
6
7
F8 to FF  
F0 to F7  
E8 to EF  
E0 to E7  
D8 to DF  
D0 to D7  
C8 to CF  
C0 to C7  
B8 to BF  
B0 to B7  
A8 to AF  
A0 to A7  
98 to 9F  
90 to 97  
88 to 8F  
80 to 87  
WDTKEY  
WDT  
B
ACC  
I2C0CON  
PSW  
I2C0STA  
I2C0DAT  
I2C0ADR  
USBCON USBCONA  
IP  
P3  
IE  
P2  
P1  
TCON  
P0  
TMOD  
SP  
TL0  
TL1  
TH0  
TH1  
DPL  
DPH  
PCON  
10.3.1 Program Status Word register (PSW)  
The PSW register of the 80C51 is bit-addressable. The names and functions of the  
bits are shown in Table 48 and Table 49.  
Table 48: PSW register: bit allocation  
7
6
5
4
3
2
1
0
CY  
AC  
F0  
RS1  
RS0  
OV  
-
P
Table 49: PSW register: bit description  
Bit[1]  
Symbol  
CY  
Description  
PSW.7  
PSW.6  
carry flag; receives carry out from bit 7 of ALU operands  
AC  
auxiliary carry flag; receives carry out from bit 3 of addition  
operands  
PSW.5  
PSW.4  
PSW.3  
PSW.2  
PSW.1  
PSW.0  
F0  
RS1  
RS0  
OV  
-
flag 0; general purpose status flag  
register bank selector bit 1; see Table 50  
register bank selector bit 0; see Table 50  
overflow flag; set by arithmetic operations  
user-definable general purpose flag  
P
parity flag, indicating the number of ‘1’ bits in the accumulator  
(logic 0 = even, logic 1 = odd); refreshed by hardware upon each  
instruction cycle  
[1] All bits are individually addressable.  
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Table 50: Register bank selection  
RS1  
RS0  
Register bank  
Address range (Hex)  
00 to 07  
0
0
1
1
0
1
0
1
0
1
2
3
08 to 0F  
10 to 17  
18 to 1F  
10.3.2 Power Control register (PCON)  
Table 51: PCON register: bit allocation  
Bit  
7
-
6
-
5
-
4
3
2
1
PD  
0
0
IDL  
0
Symbol  
Reset  
Access  
WLE  
0
GF1  
0
GF0  
0
0
0
0
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Table 52: PCON register: bit description  
Bit  
7 to 5  
4
Symbol  
Description  
-
reserved  
WLE  
Watchdog Load Enable. Writing a logic 1 enables writing to the  
watchdog timer register and starts the watchdog timer for the first  
time. A logic 0 disables writing to the watchdog timer register.  
The watchdog timer can be stopped by writing 55H to the  
WDTKEY register (see Table 70) or by a hardware reset.  
3
2
1
GF1  
GF0  
PD  
General purpose flag set or reset by software.  
General purpose flag set or reset by software.  
Writing a logic 1 activates Power-down mode and switches off the  
clock. When the microcontroller wakes up from Power-down mode  
this bit is cleared to logic 0.  
0
IDL  
Writing a logic 1 activates Idle mode, switching off the normal clock  
and turning on the sleep clock. A reset or interrupt returns the  
microcontroller from Idle to normal mode and clears this bit to  
logic 0.  
10.3.3 USB Control register (USBCON)  
Table 53: USBCON register: bit allocation  
Bit  
7
6
5
4
3
2
1
0
Symbol  
Self  
Powered  
Enable  
SYNCLK  
Disable  
KBDMatrix  
GL-MEMSEL  
Selection  
Enable  
OverCurrent  
AnalogOC  
Disable  
Soft  
Connect_N  
Suspend  
Clock  
Reset  
0
1
1
1
1
1
1
0
Access  
W
W
W
W
W
W
W
W
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Table 54: USBCON register: bit description  
Bit  
Symbol  
Description  
7
Self  
Powered  
A logic 0 selects bus-powered operation. A logic 1 enables (hybrid)  
self-powered operation.  
6
5
4
Enable  
SYNCLK  
A logic 1 enables a 12 MHz clock signal on output SYNCLK, used  
during external emulation of the microcontroller. A logic 0 disables  
the clock signal on SYNCLK.  
Disable  
A logic 0 selects internal 82 kpull-down resistors on the MYn  
KBDMatrix lines (keyboard matrix enabled). A logic 1 selects internal 8.2 kΩ  
pull-up resistors on the MYn lines (keyboard matrix disabled).  
GL-  
MEMSEL  
Selection  
A logic 0 enables upstream GoodLink indication, using output  
MEMSEL/UPGL to drive the LED. A logic 1 configures pin  
MEMSEL/UPGL as a chip select output for accessing an external  
serial EEPROM via the I2C-bus interface.  
3
2
1
0
Enable  
Over  
Current  
A logic 1 configures pins OCn/DPGLn as overcurrent detection  
inputs. A logic 0 configures pins OCn/DPGLn as downstream port  
GoodLink indicator outputs.  
AnalogOC A logic 0 enables internal analog overcurrent sensing on pins  
Disable  
OCn/DPGLn (if enabled via bit EnableOverCurrent). A logic 1  
selects digital overcurrent sensing.  
Soft  
A logic 0 connects an internal 1.5 kpull-up resistor to the  
Connect_N upstream USB port (pin UP_DP). A logic 1 disables the pull-up  
resistor.  
Suspend  
Clock  
A logic 1 switches off the clock after 2 ms following a ‘suspend’  
interrupt. A logic 0 causes the clock to remain active during  
‘suspend’ state. A change from logic 0 to logic 1 in the ‘suspend’  
interrupt service routine switches off the clock after 1 ms.  
10.3.4 USB Control A register (USBCONA)  
Table 55: USBCONA register: bit allocation  
Bit  
7
6
5
4
3
2
1
0
Symbol  
Reset  
Access  
reserved  
PortCount1 PortCount0  
0
0
0
0
0
0
0
1
W
W
W
W
W
W
W
W
Table 56: USBCONA register: bit description  
Bit  
Symbol  
Description  
7 to 2  
1, 0  
-
reserved  
PortCount[1:0] number of enabled embedded functions:  
00 — undefined  
01 — 1 embedded function (default)  
10 — 2 embedded functions  
11 — 3 embedded functions  
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10.4 Hub control registers  
The hub control registers (Command and Data) are mapped to the external data  
memory space of the 80C51 as shown in Table 57. To access these registers use a  
MOVX instruction.  
Table 57: Hub control registers: address mapping  
Register  
Command  
Data  
Access  
write  
Address (Hex)  
FFFE  
read/write  
FFFF  
10.5 Interrupt structure  
The ISP1130 implements a 6-source interrupt structure with 2 priority levels. The  
interrupt vector addresses and polling sequence is given in Table 58. The interrupt  
priority levels are set via the Interrupt Polarity (IP) register (see Table 61) and the  
interrupts can be enabled or disabled via the Interrupt Enable (IE) register (see  
Table 59).  
Table 58: Interrupt vectors and polling sequence  
Source  
EX0  
ET0  
EX1  
ET1  
I2C  
Description  
Vector address  
0003H  
external 0 interrupt (USB)  
timer 0 interrupt  
000BH  
external 1 interrupt (keyboard)  
0013H  
timer 1 interrupt  
I2C-bus interrupt  
001BH  
0023H  
IN2  
external 2 interrupt (input INT)  
002BH  
External interrupt 0 (EX0) is generated by the USB core when an activity occurs for  
any of the three embedded functions. Interrupt EX0 is level-triggered and sets bit IE0  
in the TCON register. IE0 is cleared by hardware when the service routine is entered.  
External interrupt 1 (EX1) is generated by a key press in the matrix. Interrupt EX1 is  
level-triggered and sets bit IE1 in the TCON register. IE1 is cleared by hardware  
when the service routine is entered. When the device is in ‘suspend’ state (the  
microcontroller clock is disabled), interrupt EX1 is registered and an internal Remote  
Wakeup is generated to restart the PLL and the clocks. When the device resumes its  
function and the clock to microcontroller core has been restored, the firmware  
branches to the interrupt service routine for EX1.  
External interrupt 2 (IN2) is generated by input pin INT, which is edge-triggered  
(HIGH-to-LOW transition).  
Timer 0 and Timer 1 interrupts are generated by a timer register overflow (except for  
Timer 0 in Mode 3), signalled by bits TF0 and TF1 in the TCON register. The bit that  
generated the interrupt is cleared by hardware, when the service routine is entered.  
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Table 59: IE register: bit allocation  
Bit  
7
EA  
0
6
-
5
IN2  
0
4
I2C  
0
3
2
1
0
Symbol  
Reset  
Access  
ET1  
0
EX1  
0
ET0  
0
EX0  
0
0
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Table 60: IE register: bit description  
Bit[1]  
Symbol  
Description  
IE.7  
EA  
enable all interrupts; a logic 0 disables all interrupts, a logic 1  
allows all interrupt sources to be individually enabled or disabled  
IE.6  
IE.5  
IE.4  
IE.3  
IE.2  
IE.1  
IE.0  
-
reserved  
IN2  
I2C  
ET1  
EX1  
ET0  
EX0  
A logic 1 enables external interrupt 2 (input INT)  
A logic 1 enables I2C interrupt  
A logic 1 enables Timer 1 overflow interrupt  
A logic 1 enables external interrupt 1 (keyboard)  
A logic 1 enables Timer 0 overflow interrupt  
A logic 1 enables external interrupt 0 (USB)  
[1] All bits are individually addressable.  
Table 61: IP register: bit allocation  
Bit  
7
-
6
-
5
IN2  
0
4
I2C  
0
3
2
1
0
Symbol  
Reset  
Access  
ET1  
0
EX1  
0
ET0  
0
EX0  
0
X
X
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Table 62: IP register: bit description  
Bit[1]  
IP.7  
IP.6  
IP.5  
IP.5  
IP.3  
IP.2  
IP.1  
IP.0  
Symbol  
-
Description[2]  
reserved  
-
reserved  
IN2  
I2C  
ET1  
EX1  
ET0  
EX0  
priority of external interrupt 2 (input INT)  
priority of I2C interrupt  
priority of Timer 1 interrupt  
priority of external interrupt 1 (keyboard)  
priority of Timer 0 interrupt  
priority of external 0 (USB) interrupt  
[1] All bits are individually addressable.  
[2] A logic 0 indicates a LOW priority, a logic 1 indicates a HIGH priority.  
10.6 Timers/counters  
The ISP1130 contains two 16-bit timer/counters (Timer 0 and Timer 1), which are  
used for generating interrupt requests. Each timer has a control bit C/T in the Timer  
Control register (TCON, see Table 67), which selects the timer or counter function. In  
the ISP1130 this bit must always be 0 for timer operation.  
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Both timers can be programmed independently to operate in 4 different modes via the  
Timer Mode register (TMOD, see Table 63). When Timer 0 is in mode 3, Timer 1 can  
be programmed to modes 0, 1 or 2 but it cannot set an interrupt request flag or  
generate an interrupt.  
Table 63: TMOD register: bit allocation  
Timer 1: bits 7 to 4; Timer 0: bits 3 to 0  
7
6
5
4
3
2
1
0
GATE  
C/T  
M1  
M0  
GATE  
C/T  
M1  
M0  
Table 64: TMOD register: bit description  
Bit  
7
Symbol  
GATE  
C/T  
Description  
Timer 1 counter gate control; must always be 0  
Timer 1 counter/timer select; must always be 0  
Timer 1 mode selector bit 1; see Table 63  
Timer 1 mode selector bit 0; see Table 63  
Timer 0 counter gate control; must always be 0  
Timer 0 counter/timer select; must always be 0  
Timer 0 mode selector bit 1; see Table 63  
Timer 0 mode selector bit 0; see Table 63  
6
5
M1  
4
M0  
3
GATE  
C/T  
2
1
M1  
0
M0  
Table 65: Timer mode selection  
M1, M0  
00  
Mode  
Description  
0
1
2
3
13-bit timer  
01  
16-bit timer  
10  
8-bit auto-reload timer  
11  
Timer 0: TL0 is an 8-bit timer controlled by Timer 0 control bits;  
TH0 is an 8-bit timer controlled by Timer 1 control bits  
Timer 1: stopped  
Each timer consists of two 8-bit registers in the SFR memory space: TLn and THn  
(see Table 66). The timer registers are incremented every machine cycle of the  
80C51 core. Since one machine cycle consists of 6 clock periods, the timer counts at  
a rate of 16 × fMCU_CLOCK. This corresponds with 2 MHz for the default microcontroller  
clock frequency of 12 MHz.  
Table 66: Timer register addresses  
Register  
TL0  
SFR address  
8AH  
Description  
Timer 0: lower byte  
Timer 0: upper byte  
Timer 1: lower byte  
Timer 1: upper byte  
TH0  
8CH  
TL1  
8BH  
TH1  
8DH  
The timers are started and stopped under software control via the SFR TCON (see  
Table 67). Each timer sets its interrupt request flag when the timer register overflows  
from all 1’s to all 0’s (normal timer) or to the reload value (auto-reload timer). When a  
timer interrupt is generated, the corresponding interrupt request flag is cleared by the  
hardware upon entering the interrupt service routine.  
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Table 67: TCON register: bit allocation  
Bit  
7
TF1  
0
6
5
TF0  
0
4
3
IE1  
0
2
IT1  
0
1
IE0  
0
0
IT0  
0
Symbol  
Reset  
Access  
TR1  
0
TR0  
0
R
R/W  
R
R/W  
R
R/W  
R
R/W  
Table 68: TCON register: bit description  
Bit[1]  
Symbol  
Description  
TCON.7  
TF1  
Timer 1 overflow flag; set by hardware upon Timer 1 overflow;  
cleared by hardware upon entering the interrupt service routine  
TCON.6  
TCON.5  
TR1  
TF0  
Timer 1 run control bit; 0 = timer OFF, 1 = timer ON  
Timer 0 overflow flag; set by hardware upon Timer 0 overflow;  
cleared by hardware upon entering the interrupt service routine  
TCON.4  
TCON.3  
TR0  
IE1  
Timer 0 run control bit; 0 = timer OFF, 1 = timer ON  
external interrupt 1 flag; set by hardware when a keyboard  
interrupt is detected; cleared by hardware upon entering the  
interrupt service routine  
TCON.2  
TCON.1  
IT1  
IE0  
triggering mode for external interrupt 1, set by software;  
must always be logic 0 (= HIGH-to-LOW transition)  
external interrupt 0 flag; set by hardware when a USB core  
interrupt is detected; cleared by hardware upon entering the  
interrupt service routine  
TCON.0  
IT0  
triggering mode for external interrupt 0, set by software;  
must always be 0 (= HIGH-to-LOW transition)  
[1] All bits are individually addressable.  
10.7 Watchdog timer  
The Watchdog timer is a counter that resets the microcontroller upon overflow. This  
allows recovery from erroneous processor states (e.g. caused by electrical noise or  
RF-interference). To prevent the Watchdog timer from overflowing, the software must  
reload the counter within a predefined (programmable) time.  
The Watchdog timer is a 19-bit counter, consisting of an 11-bit prescaler and an 8-bit  
SFR (WDT). The counter is clocked in state 2 of every CPU cycle (= 6 clocks) and  
generates a reset when register WDT overflows. For a 12 MHz clock frequency, the  
interval between overflows can be programmed between 1.024 ms (WDT = FFH) and  
262.144 ms (WDT = 00H). After a reset the WDT register contains all zeroes.  
To enable loading of the Watchdog timer, bit WLE in the PCON register must be set to  
logic 1 (see Table 51). When this is done for the first time, it also starts the timer. The  
Watchdog timer can be disabled by writing 55H to the WDTKEY register, or by a  
hardware reset.  
Table 69: Watchdog timer registers: address mapping  
Register  
WDTKEY  
WDT  
Access  
write  
Address (Hex)  
FE  
FF  
write  
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Table 70: WDTKEY register: bit allocation  
Bit  
7
6
5
4
3
2
1
0
Symbol  
Reset  
Access  
WDK[7:0]  
0
1
0
1
0
1
0
1
W
W
W
W
W
W
W
W
Table 71: WDTKEY register: bit description  
Bit  
Symbol  
Description  
7 to 0  
WDK[7:0]  
Watchdog Key: a value of 55H disables the Watchdog timer and  
inhibits the setting of bit PD in the PCON register. Any other value  
than 55H will (re)enable the Watchdog timer.  
Table 72: WDT register: bit allocation  
Bit  
7
6
5
4
3
2
1
0
Symbol  
Reset  
Access  
WDL[7:0]  
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
Table 73: WDT register: bit description  
Bit  
Symbol  
Description  
7 to 0  
WDL[7:0]  
Watchdog Load value. The Watchdog timer interval is given by  
(256 WDL) in units of 1.024 ms (12 MHz clock frequency).  
[1] This register can only be written if bit WLE in the PCON register is set to logic 1.  
10.7.1 Watchdog timer software example  
The following example shows how the Watchdog timer operation might be handled in  
a user program.  
;at program start  
WDT  
PCON  
WDT_INT  
EQU  
EQU  
EQU  
0FFH  
087H  
156  
;address of watchdog timer SFR  
;address of power-control SFR  
;WDT internal 100 * prescaler overflow  
;call to subroutine which reloads the WDT  
LCALL  
WATCHDOG  
;watchdog subroutine  
WATCHDOG:  
ORL  
MOV  
RET  
PCON,#10H  
WDT,#WDT_INT  
;set WLE bit in PCON  
;load watchdog timer with interval  
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10.8 I/O description  
The following groups of I/O lines are available for interfacing a keyboard matrix to the  
ISP1130:  
MX0 to MX7 — return lines for keyboard matrix; inputs with internal 8.2 kpull-up  
resistors, 5 V tolerant. Inputs MX3 and MX4 are multiplexed with the SCL and SDA  
lines respectively. This allows the ISP1130 firmware to read configuration data from  
an external EEPROM via SDA and SCL, e.g. upon a hardware or a USB bus reset.  
MY0 to MY17 — scan lines for keyboard matrix; bidirectional lines with internal 82 kΩ  
pull-down resistors and 8.2 kpull-up resistors. The pull-down resistors are selected  
by setting bit DisableKBDMatrix in the USBCON register. In Idle mode these lines are  
inputs, which are OR-ed together to generate an interrupt when a key is pressed.  
CAPSLOCK / NUMLOCK / SCRLOCK — open drain outputs for driving Caps Lock,  
Num Lock and Scroll Lock indicator LEDs (max. 8 mA).  
Remark: When accessing external functions or devices via the ISP1130 bus lines, it  
is recommended to isolate the MYn lines by means of analog switches, controlled via  
output MEMSEL/UPGL. This prevents bus conflicts during keyboard scanning.  
10.9 I/O port mapping  
Table 74 provides the mapping of standard 80C51 input/output ports with respect to  
their use in ISP1130.  
Table 74: Mapping of I/O ports between ISP1130 and 80C51  
ISP1130 ports  
MY0 to MY7  
MY8 to MY15  
MY16  
80C51 ports  
P0.0 to P0.7  
P2.0 to P2.7  
P1.0  
Description  
keyboard scan lines  
keyboard scan lines  
keyboard scan lines  
keyboard scan lines  
MY17  
P1.1  
MEMSEL/UPGL  
P1.2  
chip select output for an external EEPROM;  
upstream port GoodLink indicator output  
CAPSLOCK  
NUMLOCK  
SCRLOCK  
n.c.  
P1.3  
control output for Caps Lock LED indicator  
control output for Num Lock LED indicator  
control output for Scroll Lock LED indicator  
not used  
P1.4  
P1.5  
P1.6  
n.c.  
P1.7  
not used  
MX0 to MX7  
P3.0 to P3.7  
keyboard return lines  
10.10 Keyboard matrix implementation  
The ISP1130 can support a maximum key matrix size of 18 × 8, totalling 144 keys. A  
typical implementation of the keyboard matrix is shown in Figure 7.  
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w
Keyboard matrix  
MY0  
MY1  
V
CC  
MY2  
MY3  
MY4  
DisableKBDMatrix  
(USBCON register)  
MY5  
MY6  
8.2 kΩ  
MYn  
82 kΩ  
MY7  
MY8  
MY9  
MY10  
MY11  
MY12  
MY13  
MY14  
MY15  
MY16  
MY17  
internal circuit  
ISP1130  
MX0  
MX1  
MX2  
MX3  
MX4  
MX5  
MX6  
MX7  
V
CC  
8.2 kΩ  
MXn  
internal circuit  
MGS801  
Fig 7. Typical keyboard matrix implementation.  
The keyboard scanning algorithm is as follows:  
1. When no key press is detected within a predefined time interval, the  
microcontroller switches the MYn scan lines to ‘input’ and enters Idle mode.  
2. Pressing any key will result in the HIGH level of an MXn line to be transferred to  
an MYn input. Such a HIGH level (4.45 V typ.) exceeds VIH and generates an  
interrupt, since all MYn lines are OR-ed together.  
3. Upon a keyboard interrupt the microcontroller exits Idle mode and resumes  
standard keyboard matrix scanning to determine which key was pressed.  
This algorithm helps to reduce EMI and power consumption.  
10.11 Suspend and resume  
10.11.1 Suspend  
When there is no activity on the USB bus for more than 3 ms, the device generates  
an interrupt to the microcontroller to enter ‘suspend’ state.  
The microcontroller can respond to a ‘suspend’ interrupt in three ways, depending on  
the value of bit SuspendClock in the USBCON register when servicing the interrupt:  
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SuspendClock = 0: The operating clocks of the USB core and the microcontroller  
remain on during ‘suspend’ state. The device’s power consumption is not reduced  
and therefore this state does not guarantee ‘suspend’ current requirements.  
SuspendClock = 1: The internal clocks are automatically switched off after 2 ms.  
This allows the microcontroller adequate time to process the ‘suspend’ interrupt  
and enter Power-down mode. Power consumption is reduced to its minimum to  
meet the ‘suspend’ current requirements of USB Specification Rev. 1.1.  
SuspendClock is changed from 0 to 1: The clocks are switched off after 1 ms.  
This option can be used if the microcontroller requires more time than 2 ms to  
prepare for ‘suspend’ mode.  
Remark: After a resume operation, the microcontroller has to clear bit SuspendClock  
to logic 0 to enable further suspend operations.  
10.11.2 Resume  
The ISP1130 can resume operation from ‘suspend’ state in three ways, depending on  
whether the operating clocks are active or not:  
Operating clock on: Clearing the Suspend bit of the Device Status Register to  
logic 0 will generate a remote wake-up signal.  
Operating clock off: The following events will generate a remote wake-up signal:  
Key press (activity on the MYn lines)  
USB bus activity.  
Upon a remote wake-up signal, the USB core first enables the PLL and the clocks.  
When the clocks have stabilized, an interrupt wakes up the microcontroller from  
Power-down mode. The microcontroller resumes program execution from where it  
left off. A ‘resume’ signal is then generated on the upstream port.  
11. I2C-bus interface  
A simple I2C-bus interface is provided in the ISP1130 to read configuration data from  
an external EEPROM upon a (power-on) reset or a bus reset from the USB host. The  
interface hardware supports both single master and slave operation at bus speeds up  
to 400 kHz.  
For this application the user must configure the I2C-bus interface as single master via  
software. After reading the EEPROM configuration data, the I2C-bus driver software  
module and the EEPROM must be disabled, since the SCL and SDA lines are  
multiplexed with keyboard matrix scan lines (MX3 and MX4 respectively). Output  
MEMSEL/UPGL is available for (de)selecting the EEPROM.  
The I2C-bus interface is intended for bidirectional communication between ICs via two  
serial bus wires, SDA (data) and SCL (clock). Both lines are driven by open-drain  
circuits and must be connected to the positive supply voltage via pull-up resistors. In  
the ISP1130 8.2 kpull-up resistors are integrated on pins MX3/SCL and MX4/SDA.  
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11.1 Protocol  
The I2C-bus protocol defines the following conditions:  
Bus free: both SDA and SCL are HIGH  
START: a HIGH-to-LOW transition on SDA, while SCL is HIGH  
STOP: a LOW-to-HIGH transition on SDA, while SCL is HIGH  
Data valid: after a START condition, data on SDA are stable during the HIGH  
period of SCL; data on SDA may only change while SCL is LOW.  
Each device on the I2C-bus has a unique slave address, which the master uses to  
select a device for access.  
The master starts a data transfer using a START condition and ends it by generating  
a STOP condition. Transfers can only be initiated when the bus is free. The receiver  
must acknowledge each byte by means of a LOW level on SDA during the ninth clock  
pulse on SCL.  
For detailed information please consult The I2C-bus and how to use it., order number  
9398 393 40011.  
11.2 Hardware connections  
Via the I2C-bus interface the ISP1130 can be connected to an external EEPROM  
(PCF8582 or equivalent). The hardware connections are shown in Figure 8.  
The SCL and SDA pins are multiplexed with pins MX3 and MX4 respectively. Pin  
MEMSEL/UPGL can be used as a chip select output to select external devices, such  
as smart card readers, UARTs, etc.  
V
V
DD  
id
DD  
R
R
P
P
SCL  
SDA  
MX3/SCL  
MX4/SDA  
A0  
A1  
A2  
2
I C-bus  
PCF8582  
ISP1130  
USB HUB  
EEPROM  
or  
equivalent  
MGS808  
Fig 8. EEPROM connection diagram.  
The slave address which ISP1130 uses to access the EEPROM is 1010000B. Page  
mode addressing is not supported, so pins A0, A1 and A2 of the EEPROM must be  
connected to GND (logic 0).  
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11.3 Data transfer  
The I2C-bus interface can be used to read configuration data from an external  
EEPROM, e.g. upon a hardware or USB bus reset. The EEPROM must be enabled  
and disabled using output pin MEMSEL/UPGL. To select the I2C-bus function of pins  
MX3/SCL and MX4/SDA, bit ENS1 in the I2C0CON register must be set to logic 1.  
The number and the organization of the data bytes read from the EEPROM can be  
determined by the firmware designer.  
The I2C-bus interface is accessed via a number of SFRs, shown in Table 75.  
Table 75: I2C register addresses  
Register  
I2C0CON  
I2C0STA  
I2C0DAT  
I2C0ADR  
SFR address Description  
D8H  
D9H  
DAH  
DBH  
I2C-bus control register  
I2C-bus status register  
I2C-bus data register  
I2C-bus address register  
Table 76: I2C0CON register: bit allocation  
Bit  
7
6
ENS1  
0
5
4
3
SI  
2
AA  
0
1
0
Symbol  
Reset  
Access  
CR2  
0
STA  
0
STO  
0
CR1  
0
CR0  
0
0
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Table 77: I2C0CON register: bit description  
Bit[1]  
Symbol  
CR2  
Description  
I2C0CON.7  
I2C0CON.6  
selects I2C-bus bit frequency in Master mode, see Table 78  
ENS1  
Enable Serial I/O. A logic 1 enables the I2C-bus interface  
and sets pins MX3/SCL and MX4/SDA to logic 1. A logic 0  
disables the I2C-bus interface and clears bit STO to logic 0,  
allowing MX3/SCL and MX4/SDA to be used as open drain  
I/O pins.  
I2C0CON.5  
I2C0CON.4  
STA  
START flag. In Slave mode a logic 1 generates a START  
condition as soon as the bus is free. In Master mode a  
logic 1 generates a repeated START condition.  
STO  
STOP flag. In maSter mode a logic 1 generates a STOP  
condition. This bit is cleared by hardware if a STOP  
condition is detected on the bus. In Slave mode a logic 1 can  
be used to recover from an error: it causes SDA and SCL to  
be released and the device to be unaddressed.  
I2C0CON.3  
SI  
Serial Interrupt flag. A logic 1 signals a valid status change  
(see Table 83), causing the SCL LOW period to be stretched  
and the transfer to be suspended. This bit must be cleared  
by software when servicing the interrupt.  
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Table 77: I2C0CON register: bit description…continued  
Bit[1]  
Symbol  
Description  
I2C0CON.2  
AA  
Assert Acknowledge. A logic 1 indicates that an ACK (low  
level on SDA during acknowledge pulse on SCL) is returned  
for one of the following conditions:  
own slave address received  
General Call address received, if bit GC = 1 (I2C0CON)  
data byte received when in master receive mode  
data byte received when addressed in slave receiver  
mode.  
I2C0CON.1  
I2C0CON.0  
CR1  
CR0  
selects I2C-bus bit frequency in Master mode, see Table 78  
selects I2C-bus bit frequency in Master mode, see Table 78  
[1] All bits are individually addressable.  
Table 78: I2C-bus bit frequency (Master mode)  
CR2  
0
CR1  
0
CR0  
0
I2C-bus bit frequency (12 MHz oscillator)  
200 kHz  
7.5 kHz  
300 kHz  
400 kHz  
50 kHz  
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
3.75 kHz  
75 kHz  
1
1
0
1
1
1
100 kHz  
Table 79: I2C0DAT register: bit allocation  
Bit  
7
6
5
4
3
2
1
0
Symbol  
Reset  
Access  
SD[7:0]  
0
0
0
0
0
0
0
0
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Table 80: I2C0DAT register: bit description  
Bit  
Symbol  
Description  
7 to 0  
SD[7:0][1]  
DATA byte (just received or to be transmitted); a logic 0 value  
corresponds with a LOW level on SDA, a logic 1 with a HIGH  
level  
[1] Bits are transmitted or received MSB (SD7) first.  
Table 81: I2C0STA register: bit allocation  
Bit  
7
6
5
4
3
2
-
1
-
0
-
Symbol  
Reset  
Access  
SC[4:0]  
1
1
1
1
1
0
R
0
R
0
R
R
R
R
R
R
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Table 82: I2C0STA register: bit description  
Bit  
Symbol  
SC[4:0]  
-
Description  
7 to 3  
2 to 0  
status code, see Table 83  
reserved, always zero  
Table 83: I2C-bus status codes  
Status byte SC[4:0]  
Master transmit mode  
Description (see Table 84)  
08H  
10H  
18H  
20H  
28H  
30H  
38H  
00001  
00010  
00011  
00100  
00101  
00110  
00111  
START condition has been transmitted  
repeated START condition has been transmitted  
SLA and W have been transmitted, ACK was received  
SLA and W have been transmitted, ACK was received  
DATA byte has been transmitted, ACK was received  
DATA byte has been transmitted, ACK was received  
arbitration was lost in SLA, R/W or DATA byte  
Master receive mode  
08H  
10H  
38H  
40H  
48H  
50H  
58H  
00001  
00010  
00111  
01000  
01001  
01010  
01011  
START condition has been transmitted  
repeated START condition has been transmitted  
arbitration was lost while returning ACK  
SLA and R have been transmitted, ACK was received  
SLA and R have been transmitted, ACK was received  
DATA byte has been received, ACK was returned  
DATA byte has been received, ACK was returned  
Slave receive mode  
60H  
68H  
01100  
01101  
own SLA and W have been received, ACK was returned  
arbitration was lost in SLA, R/W as master; own SLA and W  
have been received, ACK was returned  
70H  
78H  
01110  
01111  
General Call has been received, ACK was returned  
arbitration was lost in SLA, R/W as master; General Call has  
been received  
80H  
88H  
90H  
98H  
A0H  
10000  
10001  
10010  
10011  
10100  
previously addressed with own SLA; DATA byte has been  
received, ACK was returned  
previously addressed with own SLA; DATA byte has been  
received, ACK was returned  
previously addressed with General Call; DATA byte has been  
received, ACK was returned  
previously addressed with General Call; DATA byte has been  
received, ACK was returned  
STOP or repeated START condition has been received, while  
still addressed as slave receiver or transmitter  
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Table 83: I2C-bus status codes…continued  
Status byte SC[4:0]  
Slave transmit mode  
Description (see Table 84)  
A8  
B0  
10101  
10110  
own SLA and R have been received, ACK was returned  
arbitration was lost in SLA, R/W as master; own SLA and R  
have been received, ACK was returned  
B8  
C0  
C8  
10111  
11000  
11001  
DATA byte has been transmitted, ACK was received  
DATA byte has been transmitted, ACK was received  
last DATA byte has been transmitted (AA = 0 in I2C0CON),  
ACK was received  
Miscellaneous  
00H  
00000  
bus error in master or addressed slave mode, caused by  
erroneous START or STOP condition  
F8H  
11111  
no relevant status information is available; bit SI in the  
I2C0CON register is cleared to logic 0  
Table 84: Symbols used in I2C-bus  
Symbol  
SLA  
R
Description  
slave address (7 bits)  
read bit (logic 1)  
W
write bit (logic 0)  
ACK  
ACK  
DATA  
acknowledgment (logic 0)  
no acknowledgment (logic 1)  
data byte to or from I2C-bus  
Table 85: I2C0ADR register: bit allocation  
Bit  
7
6
5
4
SA[6:0]  
0
3
2
1
0
GC  
0
Symbol  
Reset  
Access  
0
0
0
0
0
0
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Table 86: I2C0ADR register: bit description  
Bit  
Symbol  
Description  
7 to 1  
SA[6:0]  
own slave address of the microcontroller; only used in Slave  
mode, ignored in Master mode  
0
GC  
A logic 1 causes the device to respond to a General Call  
address (00H). A logic 0 lets the device ignore address 00H.  
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12. Hub power modes  
USB hubs can either be self-powered or bus-powered.  
Self-powered — Self-powered hubs have a 5 V local power supply on board which  
provide power to the hub and the downstream ports. The USB Specification Rev. 1.1  
requires that these hubs limit the current to 500 mA per downstream port and report  
overcurrent conditions to the host. The hub may optionally draw 100 mA from the  
USB supply (VBUS) to power the interface functions (hybrid-powered).  
Bus-powered — Bus-powered hubs obtain all power from the host or an upstream  
self-powered hub. The maximum current is 100 mA per downstream port. Current  
limiting and reporting of overcurrent conditions are both optional.  
The ISP1130 has bus-powered downstream ports and supports individual power  
switching via pins PSWn.  
12.1 Voltage drop requirements  
12.1.1 Bus-powered hubs  
Bus-powered hubs are guaranteed to receive a supply voltage of 4.5 V at the  
upstream port connector and must provide a minimum of 4.4 V to the downstream  
port connectors. The voltage drop of 100 mV across bus-powered hubs includes:  
Hub PCB (power and ground traces, ferrite beads)  
Power switch (FET on-resistance)  
Overcurrent sense device.  
The PCB resistance may cause a drop of 25 mV, which leaves 75 mV for the power  
switch and overcurrent sense device. The voltage drop components are shown in  
Figure 9.  
For bus-powered hubs overcurrent protection is optional. It may be implemented for  
all downstream ports on a global or individual basis. The ISP1130 has individual  
overcurrent protection for its downstream ports.  
voltage drop  
75 mV  
voltage drop  
25 mV  
4.50 V(min)  
4.40 V(min)  
V
V
BUS  
BUS  
hub board  
resistance  
D+  
D+  
(1)  
upstream  
port  
connector  
downstream  
port  
connector  
low-ohmic  
PMOS switch  
D−  
D−  
ISP1122  
power  
switch  
GND  
GND  
SHIELD  
SHIELD  
MGR783  
(1) Includes PCB traces, ferrite beads, etc.  
Fig 9. Typical voltage drop components in bus-powered mode (no overcurrent detection).  
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13. Overcurrent detection  
The ISP1130 has an analog overcurrent detection circuit for monitoring downstream  
port lines. This circuit automatically reports an overcurrent condition to the host and  
turns off the power to the faulty port. The host must reset the condition flag.  
Pins OC1/DPGL1 and OC2/DPGL2 can be used for individual port overcurrent  
detection or GoodLink indication. The pin functionality is selected via bit  
EnableOverCurrent in the USBCON register, see Table 53.  
13.1 Overcurrent circuit description  
The integrated overcurrent detection circuit of ISP1130 senses the voltage drop  
across the power switch or an extra low-ohmic sense resistor. When the port draws  
too much current, the voltage drop across the power switch exceeds the trip voltage  
threshold (Vtrip). The overcurrent circuit detects this and switches off the power  
switch control signal after a delay of 15 ms (ttrip). This delay acts as a ‘debounce’  
period to minimize false tripping, especially during the inrush current produced by ‘hot  
plugging’ of a USB device.  
13.2 Power switch selection  
From the voltage drop analysis given in Figure 9, the power switch has a voltage drop  
budget of 75 mV. For individual self-powered mode, the current drawn per port can be  
up to 500 mA. Thus the power switch should have maximum on-resistance of  
150 m.  
If the voltage drop due to the hub board resistance can be minimized, the power  
switch can have more voltage drop budget and therefore a higher on-resistance.  
Power switches with a typical on-resistance of around 100 mfit into this application.  
The ISP1130 overcurrent detection circuit has been designed with a nominal trip  
voltage (Vtrip) of 85 mV. This gives a typical trip current of approximately 850 mA for  
a power switch with an on-resistance of 100 m1.  
13.3 Tuning the overcurrent trip voltage  
The ISP1130 trip voltage can optionally be adjusted through external components to  
set the desired trip current. This is done by inserting tuning series resistors at pins  
OCn/DPGLn (see Figure 10). Rtd tunes down the trip voltage Vtrip according to  
Equation 1.  
Vtrip = Vtrip(intrinsic) IOC Rtd  
with IOC(nom) = 0.5 µA.  
(1)  
1. The following PMOS power switches have been tested to work well with the ISP1130: Philips PHP109, Vishay Siliconix Si2301DS,  
Fairchild FDN338P.  
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Rev. 01 — 23 March 2000  
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handbook, halfpage  
handbook, halfpage  
low-ohmic  
low-ohmic  
PMOS switch  
PMOS switch  
V
V
BUS  
CC  
I
I
OC  
OC  
R
R
td  
td  
V
OCn/DPGLn  
V
OCn/DPGLn  
CC  
CC  
ISP1130  
ISP1130  
MBL161  
MBL160  
IOC(nom) = 0.5 µA  
IOC(nom) = 0.5 µA  
a. Hybrid-powered mode.  
b. Bus-powered mode.  
Fig 10. Tuning the overcurrent trip voltage.  
13.4 Reference circuit  
A typical example of individual port power switching and individual overcurrent  
detection is given in Figure 11. The RC circuit (10 kand 1 µF) around the PMOS  
switch provides for soft turn-on. Series resistors between pins OCn/DPGLn and the  
supply voltage may be used to tune down the overcurrent trip voltage (see Figure 10).  
downstream  
ports  
low-ohmic  
PMOS switch  
ferrite bead  
+4.85 V(min)  
5 V  
POWER SUPPLY  
± 3%  
V
+
BUS  
D+  
+4.75 V  
(min)  
1
120  
0.1 µF  
10 kΩ  
µF  
D−  
1
GND  
SHIELD  
low-ohmic  
PMOS switch  
ferrite bead  
330 kΩ  
(2×)  
V
BUS  
+4.75 V  
(min)  
2
120  
µF  
D+  
0.1 µF  
10 kΩ  
D−  
2
GND  
SHIELD  
+4.85 V(min)  
V
CC  
PSW1  
PSW2  
GND  
ISP1130  
OC1/DPGL1  
OC2/DPGL2  
MBL162  
Power switches 1 and 2 are low-ohmic PMOS devices as specified in Section 13.2.  
Fig 11. Hybrid-powered hub; individual port power switching; individual overcurrent detection.  
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14. Limiting values  
Table 87: Absolute maximum ratings  
In accordance with the Absolute Maximum Rating System (IEC 60134).  
Symbol  
VCC  
Parameter  
Conditions  
Min  
0.5  
0.5  
-
Max  
+6.0  
-
Unit  
V
supply voltage  
VI  
input voltage  
V
Ilatchup  
Vesd  
Tstg  
latchup current  
VI < 0 or VI > VCC  
200  
mA  
V
[1] [2]  
electrostatic discharge voltage  
storage temperature  
total power dissipation  
ILI < 15 µA  
-
±4000[3]  
+150  
<tbf>  
60  
-
°C  
mW  
Ptot  
[1] Equivalent to discharging a 100 pF capacitor via a 1.5 kresistor (Human Body Model).  
[2] Values are given for device only; in-circuit Vesd(max) = ±8000 V.  
[3] For open-drain pins Vesd(max) = ±2000 V.  
Table 88: Recommended operating conditions  
Symbol  
VCC  
Parameter  
Conditions  
Min  
Max  
5.5  
5.5  
3.6  
Unit  
supply voltage  
input voltage  
4.0  
0
V
V
V
VI  
VI(AI/O)  
input voltage on analog I/O pins  
0
(D+/D)  
VO(od)  
Tamb  
open-drain output pull-up voltage  
operating ambient temperature  
0
5.5  
V
40  
+85  
°C  
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15. Static characteristics  
Table 89: Static characteristics; supply pins  
VCC = 4.0 to 5.5 V; VGND = 0 V; Tamb = 40 to +85 °C; unless otherwise specified.  
Symbol  
Vreg(3.3)  
Vth(por)  
Parameter  
Conditions  
Min  
3.0[1]  
Typ  
3.3  
Max  
3.6  
Unit  
V
regulated supply voltage  
power-on reset threshold  
voltage  
<tbf>  
2.03  
<tbf>  
V
ICC  
operating supply current  
suspend supply current  
-
-
<tbf>  
-
-
mA  
ICC(susp  
)
1.5 kpull-up on upstream  
port D+ (pin DP0)  
<tbf>  
µA  
no pull-up on upstream port  
-
-
<tbf>  
µA  
D+ (pin DP0)  
[1] In ‘suspend’ mode the minimum voltage is 2.7 V.  
Table 90: Static characteristics: digital pins  
VCC = 4.0 to 5.5 V; VGND = 0 V; Tamb = 40 to +85 °C; unless otherwise specified.  
Symbol  
Input levels  
VIL  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
LOW-level input voltage  
HIGH-level input voltage  
-
-
-
-
0.8  
-
V
V
V
VIH  
driven  
2.0  
2.7  
floating  
3.6  
Schmitt trigger inputs  
Vth(LH) positive-going threshold  
1.4  
0.9  
0.4  
-
-
-
1.9  
1.5  
0.7  
V
V
V
voltage  
Vth(HL)  
negative-going threshold  
voltage  
Vhys  
hysteresis voltage  
Output levels  
VOL  
LOW-level output voltage  
(open-drain outputs)  
IOL = rated drive  
IOL = 20 µA  
-
-
-
-
-
0.4  
0.1  
-
V
V
V
V
-
VOH  
HIGH-level output voltage  
(open-drain outputs)  
IOH = rated drive  
IOH = 20 µA  
2.4  
V
CC 0.1  
-
Leakage current  
ILI  
input leakage current  
-
-
-
±1  
±1  
µA  
µA  
Open-drain outputs  
IOZ  
OFF-state output current  
-
Table 91: Static characteristics: overcurrent sense pins  
VCC = 4.0 to 5.5 V; VGND = 0 V; Tamb = 40 to +85 °C; unless otherwise specified.  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
Vtrip  
overcurrent detection  
V = VCC VOCn  
<tbf>  
85  
<tbf>  
mV  
trip voltage on pins OCn  
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Table 92: Static characteristics: analog I/O pins (D+, D)[1]  
VCC = 4.0 to 5.5 V; VGND = 0 V; Tamb = 40 to +85 °C; unless otherwise specified.  
Symbol  
Input levels  
VDI  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
differential input sensitivity  
|VI(D+) VI(D)  
|
0.2  
0.8  
-
-
-
V
V
VCM  
differential common mode  
voltage  
includes VDI range  
2.5  
VIL  
LOW-level input voltage  
HIGH-level input voltage  
-
-
-
0.8  
-
V
V
VIH  
2.0  
Output levels  
VOL  
VOH  
LOW-level output voltage  
HIGH-level output voltage  
RL = 1.5 kto +3.6V  
RL = 15 kto GND  
-
-
-
0.3  
3.6  
V
V
2.8  
Leakage current  
ILZ  
OFF-state leakage current  
-
-
-
-
±10  
µA  
Capacitance  
CIN  
transceiver capacitance  
pin to GND  
20  
pF  
Resistance  
[2]  
ZDRV  
driver output impedance  
input impedance  
steady-state drive  
28  
10  
-
-
44  
-
ZINP  
MΩ  
Termination  
[3]  
VTERM  
termination voltage for  
3.0[4]  
-
3.6  
V
upstream port pull-up (RPU  
)
[1] D+ is the USB positive data pin (UP_DP, DNn_DP); Dis the USB negative data pin (UP_DM, DNn_DM).  
[2] Includes external resistors of 18 Ω ±1% on both D+ and D.  
[3] This voltage is available at pin Vreg(3.3)  
.
[4] In ‘suspend’ mode the minimum voltage is 2.7 V.  
16. Dynamic characteristics  
To be determined.  
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17. Application information  
V
V
CC  
CC  
V
CC  
R14  
XTAL1  
XTAL2  
RESET  
GND  
4.7 k  
56  
1
2
XTAL1  
D3  
D2  
D1  
R3  
CAPSLOCK  
NUMLOCK  
SCRLOCK  
INT  
Scroll  
Lock  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
470 Ω  
R4  
3
6 MHz  
22 pF  
C1  
C2  
22 pF  
V
Num  
Lock  
CC  
4
V
CC  
GND  
470 Ω  
R5  
J1  
5
V
L7  
L1  
L2  
pu(3.3)  
UP_DM  
UP_DP  
PSEN  
Caps  
Lock  
6
1
2
R8 22 Ω  
UP_1  
ALE  
470 Ω  
7
EA  
UP_2  
8
3
4
5
DN1_DM  
R9 22 Ω  
SYNCLK  
9
C3  
47 pF  
C4  
47 pF  
MEMSEL/UPGL  
GND  
DN1_DP  
DN2_DM  
DN2_DP  
PSW1  
10  
11  
12  
13  
14  
upstream  
port  
MY17/WR  
MY16/RD  
MY15  
MY14  
MY13  
MY12  
MY11  
MY10  
MY9  
V
CC1  
PSW1  
PSW2  
J2  
PSW2  
L8  
L3  
L4  
U1  
1
2
OC1/DPGL1  
OC2/DPGL2  
GND  
V
15 ISP1130  
R10 22 Ω  
R11 22 Ω  
CC1  
DN_1  
DN_2  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
V
CC2  
3
4
5
MX0  
C5  
47 pF  
C6  
47 pF  
MX1  
downstream  
port 1  
MX2  
MX3/SCL  
MX4/SDA  
MX5  
MY8  
V
CC2  
MY7  
J3  
MY6  
L9  
1
2
MY5  
R12 22 Ω  
R13 22 Ω  
MX6  
L5  
L6  
DN_3  
DN_4  
MY4  
MX7  
3
4
5
MY3  
MY0  
V
C7  
47 pF  
C8  
47 pF  
MY1  
reg(3.3)  
GND  
MY2  
downstream  
port 2  
V
CC  
Q1  
PHP125  
R6  
GND  
A
V
CC1  
1
2
3
4
8
7
6
5
UP_1  
100 kΩ  
C9  
0.1 µF  
MGS809  
C
GND  
B
C11  
4.7 µF  
U2  
SN75240  
R1  
GND  
D
PSW1  
PSW2  
UP_2  
47 kΩ  
GND  
V
CC  
Q2  
PHP125  
GND  
C
A
R7  
1
2
3
4
8
7
6
5
DN_1  
DN_2  
V
CC2  
GND  
B
100 kΩ  
DN_3  
DN_4  
U3  
SN75240  
C10  
0.1 µF  
GND  
D
C12  
4.7 µF  
R2  
GND  
47 kΩ  
Fig 12. Typical application circuit.  
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18. Test information  
The dynamic characteristics of the analog I/O ports (D+ and D) as listed in  
Section 16, were determined using the circuit shown in Figure 13.  
V
handbook, halfpage  
D.U.T.  
CC  
test point  
1.5 kΩ  
S1  
18 Ω  
C
15 kΩ  
test  
S1  
L
D/LS closed  
D+/LS open  
D/FS open  
closed  
D+/FS  
MGS802  
Load capacitance:  
CL = 50 pF (full-speed mode)  
CL = 200 pF or 600 pF (low-speed mode, minimum or maximum timing).  
Speed selection:  
full-speed mode (FS): 1.5 kpull-up resistor on D+  
low-speed mode (LS): 1.5 kpull-up resistor on D.  
Fig 13. Load impedance for D+ and Dpins.  
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19. Package outline  
SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm  
SOT371-1  
D
E
A
X
c
y
H
v
M
A
E
Z
29  
56  
Q
A
2
A
A
(A )  
3
1
θ
pin 1 index  
L
p
L
28  
1
detail X  
w M  
b
p
e
0
5
10 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
(1)  
(1)  
(1)  
UNIT  
A
A
A
b
c
D
E
e
H
E
L
L
Q
v
w
y
Z
θ
p
p
1
2
3
max.  
8o  
0o  
0.4  
0.2  
2.35  
2.20  
0.3  
0.2  
0.22 18.55  
0.13 18.30  
7.6  
7.4  
10.4  
10.1  
1.0  
0.6  
1.2  
1.0  
0.85  
0.40  
mm  
2.8  
0.25  
0.635  
1.4  
0.25  
0.18  
0.1  
Note  
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
EIAJ  
95-02-04  
99-12-27  
SOT371-1  
MO-118  
Fig 14. SSOP56 package outline.  
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SDIP56: plastic shrink dual in-line package; 56 leads (600 mil)  
SOT400-1  
D
M
E
A
2
A
L
A
1
c
e
(e )  
1
w M  
Z
b
1
M
H
b
56  
29  
pin 1 index  
E
1
28  
0
5
10 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
(1)  
A
max.  
A
A
2
max.  
(1)  
(1)  
Z
1
w
UNIT  
b
b
c
D
E
e
e
L
M
M
H
1
1
E
min.  
max.  
1.3  
0.8  
0.53  
0.40  
0.32  
0.23  
52.4  
51.6  
14.0  
13.6  
3.2  
2.8  
15.80  
15.24  
17.15  
15.90  
mm  
0.51  
4.0  
5.08  
1.778  
15.24  
0.18  
2.3  
Note  
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
EIAJ  
95-12-06  
SOT400-1  
Fig 15. SDIP56 package outline.  
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20. Soldering  
20.1 Introduction  
This text gives a very brief insight to a complex technology. A more in-depth account  
of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit  
Packages (document order number 9398 652 90011).  
There is no soldering method that is ideal for all IC packages. Wave soldering is often  
preferred when through-hole and surface mount components are mixed on one  
printed-circuit board. However, wave soldering is not always suitable for surface  
mount ICs, or for printed-circuit boards with high population densities. In these  
situations reflow soldering is often used.  
20.2 Surface mount packages  
20.2.1 Reflow soldering  
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and  
binding agent) to be applied to the printed-circuit board by screen printing, stencilling  
or pressure-syringe dispensing before package placement.  
Several methods exist for reflowing; for example, infrared/convection heating in a  
conveyor type oven. Throughput times (preheating, soldering and cooling) vary  
between 100 and 200 seconds depending on heating method.  
Typical reflow peak temperatures range from 215 to 250 °C. The top-surface  
temperature of the packages should preferable be kept below 230 °C.  
20.2.2 Wave soldering  
Conventional single wave soldering is not recommended for surface mount devices  
(SMDs) or printed-circuit boards with a high component density, as solder bridging  
and non-wetting can present major problems.  
To overcome these problems the double-wave soldering method was specifically  
developed.  
If wave soldering is used the following conditions must be observed for optimal  
results:  
Use a double-wave soldering method comprising a turbulent wave with high  
upward pressure followed by a smooth laminar wave.  
For packages with leads on two sides and a pitch (e):  
larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be  
parallel to the transport direction of the printed-circuit board;  
smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the  
transport direction of the printed-circuit board.  
The footprint must incorporate solder thieves at the downstream end.  
For packages with leads on four sides, the footprint must be placed at a 45° angle  
to the transport direction of the printed-circuit board. The footprint must  
incorporate solder thieves downstream and at the side corners.  
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During placement and before soldering, the package must be fixed with a droplet of  
adhesive. The adhesive can be applied by screen printing, pin transfer or syringe  
dispensing. The package can be soldered after the adhesive is cured.  
Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the  
need for removal of corrosive residues in most applications.  
20.2.3 Manual soldering  
Fix the component by first soldering two diagonally-opposite end leads. Use a low  
voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time  
must be limited to 10 seconds at up to 300 °C.  
When using a dedicated tool, all other leads can be soldered in one operation within  
2 to 5 seconds between 270 and 320 °C.  
20.3 Through-hole mount packages  
20.3.1 Soldering by dipping or by solder wave  
The maximum permissible temperature of the solder is 260 °C; solder at this  
temperature must not be in contact with the joints for more than 5 seconds. The total  
contact time of successive solder waves must not exceed 5 seconds.  
The device may be mounted up to the seating plane, but the temperature of the  
plastic body must not exceed the specified maximum storage temperature (Tstg(max)).  
If the printed-circuit board has been pre-heated, forced cooling may be necessary  
immediately after soldering to keep the temperature within the permissible limit.  
20.3.2 Manual soldering  
Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the  
seating plane or not more than 2 mm above it. If the temperature of the soldering iron  
bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit  
temperature is between 300 and 400 °C, contact may be up to 5 seconds.  
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20.4 Package related soldering information  
Table 93: Suitability of IC packages for wave, reflow and dipping soldering methods  
Mounting  
Package  
Soldering method  
Wave  
Reflow[1] Dipping  
Through-hole  
mount  
DBS, DIP, HDIP, SDIP, SIL suitable[2]  
suitable  
Surface mount  
BGA, LFBGA, SQFP,  
TFBGA  
not suitable  
suitable  
suitable  
HBCC, HLQFP, HSQFP,  
HSOP, HTQFP, HTSSOP,  
SMS  
not suitable[3]  
PLCC[4], SO, SOJ  
LQFP, QFP, TQFP  
SSOP, TSSOP, VSO  
suitable  
suitable  
not recommended[4] [5] suitable  
not recommended[6]  
suitable  
[1] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the  
maximum temperature (with respect to time) and body size of the package, there is a risk that internal  
or external package cracks may occur due to vaporization of the moisture in them (the so called  
popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated  
Circuit Packages; Section: Packing Methods.  
[2] For SDIP packages, the longitudinal axis must be parallel to the transport direction of the  
printed-circuit board.  
[3] These packages are not suitable for wave soldering as a solder joint between the printed-circuit board  
and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top  
version).  
[4] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave  
direction. The package footprint must incorporate solder thieves downstream and at the side corners.  
[5] Wave soldering is only suitable for LQFP, QFP and TQFP packages with a pitch (e) equal to or larger  
than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.  
[6] Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than  
0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.  
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21. Revision history  
Table 94: Revision history  
Rev Date  
CPCN  
Description  
Objective specification; initial version.  
01 20000323  
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USB compound hub with keyboard controller  
Philips Semiconductors  
22. Data sheet status  
Datasheet status  
Product status Definition[1]  
Objective specification  
Development  
This data sheet contains the design target or goal specifications for product development. Specification may  
change in any manner without notice.  
Preliminary specification Qualification  
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips  
Semiconductors reserves the right to make changes at any time without notice in order to improve design and  
supply the best possible product.  
Product specification  
Production  
This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any  
time without notice in order to improve design and supply the best possible product.  
[1]  
Please consult the most recently issued data sheet before initiating or completing a design.  
customers using or selling these products for use in such applications do so  
at their own risk and agree to fully indemnify Philips Semiconductors for any  
damages resulting from such application.  
23. Definitions  
Short-form specification The data in  
extracted from a full data sheet with the same type number and title. For  
detailed information see the relevant data sheet or data handbook.  
a short-form specification is  
Right to make changes — Philips Semiconductors reserves the right to  
make changes, without notice, in the products, including circuits, standard  
cells, and/or software, described or contained herein in order to improve  
design and/or performance. Philips Semiconductors assumes no  
responsibility or liability for the use of any of these products, conveys no  
licence or title under any patent, copyright, or mask work right to these  
products, and makes no representations or warranties that these products  
are free from patent, copyright, or mask work right infringement, unless  
otherwise specified.  
Limiting values definition Limiting values given are in accordance with  
the Absolute Maximum Rating System (IEC 60134). Stress above one or  
more of the limiting values may cause permanent damage to the device.  
These are stress ratings only and operation of the device at these or at any  
other conditions above those given in the Characteristics sections of the  
specification is not implied. Exposure to limiting values for extended periods  
may affect device reliability.  
Application information Applications that are described herein for any  
of these products are for illustrative purposes only. Philips Semiconductors  
make no representation or warranty that such applications will be suitable for  
the specified use without further testing or modification.  
25. Licenses  
Purchase of Philips I2C components  
Purchase of Philips I2C components conveys a license  
under the Philips’ I2C patent to use the components in the  
I2C system provided the system conforms to the I2C  
specification defined by Philips. This specification can be  
ordered using the code 9398 393 40011.  
24. Disclaimers  
Life support — These products are not designed for use in life support  
appliances, devices, or systems where malfunction of these products can  
reasonably be expected to result in personal injury. Philips Semiconductors  
26. Trademarks  
ACPI — is an open industry specification for PC power management,  
co-developed by Intel Corp., Microsoft Corp. and Toshiba  
SMBus — is a bus specification for PC power management, developed by  
Intel Corp. based on the I2C-bus from Royal Philips Electronics  
GoodLink — is a trademark of Royal Philips Electronics  
OnNow — is a trademark of Microsoft Corp.  
SoftConnect — is a trademark of Royal Philips Electronics  
9397 750 06895  
© Philips Electronics N.V. 2000 All rights reserved.  
Objective specification  
Rev. 01 — 23 March 2000  
66 of 68  
 
 
 
 
 
ISP1130  
USB compound hub with keyboard controller  
Philips Semiconductors  
Philips Semiconductors - a worldwide company  
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Middle East: see Italy  
For all other countries apply to: Philips Semiconductors,  
International Marketing & Sales Communications,  
Building BE, P.O. Box 218, 5600 MD EINDHOVEN,  
The Netherlands, Fax. +31 40 272 4825  
Internet: http://www.semiconductors.philips.com  
(SCA69)  
9397 750 06895  
© Philips Electronics N.V. 2000. All rights reserved.  
Objective specification  
Rev. 01 — 23 March 2000  
67 of 68  
ISP1130  
USB compound hub with keyboard controller  
Philips Semiconductors  
Contents  
1
2
3
4
General description . . . . . . . . . . . . . . . . . . . . . . 1  
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Ordering information. . . . . . . . . . . . . . . . . . . . . 2  
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
11  
I2C-bus interface. . . . . . . . . . . . . . . . . . . . . . . . 46  
Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47  
Hardware connections . . . . . . . . . . . . . . . . . . 47  
Data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . 48  
11.1  
11.2  
11.3  
12  
12.1  
Hub power modes . . . . . . . . . . . . . . . . . . . . . . 52  
Voltage drop requirements . . . . . . . . . . . . . . . 52  
5
5.1  
5.2  
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4  
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5  
13  
Overcurrent detection . . . . . . . . . . . . . . . . . . . 53  
Overcurrent circuit description . . . . . . . . . . . . 53  
Power switch selection . . . . . . . . . . . . . . . . . . 53  
Tuning the overcurrent trip voltage . . . . . . . . . 53  
Reference circuit. . . . . . . . . . . . . . . . . . . . . . . 54  
13.1  
13.2  
13.3  
13.4  
6
Functional description . . . . . . . . . . . . . . . . . . . 7  
80C51 microcontroller. . . . . . . . . . . . . . . . . . . . 8  
Analog transceivers . . . . . . . . . . . . . . . . . . . . . 8  
Philips Serial Interface Engine (SIE). . . . . . . . . 8  
Hub repeater. . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
End-of-frame timers . . . . . . . . . . . . . . . . . . . . . 8  
General and individual port controller. . . . . . . . 8  
GoodLink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
SoftConnect . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
Bit clock recovery . . . . . . . . . . . . . . . . . . . . . . 10  
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . 10  
PLL clock multiplier. . . . . . . . . . . . . . . . . . . . . 10  
Overcurrent detection . . . . . . . . . . . . . . . . . . . 10  
Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 10  
I2C-bus interface. . . . . . . . . . . . . . . . . . . . . . . 10  
6.1  
6.2  
6.3  
6.4  
6.5  
6.6  
6.7  
6.8  
6.9  
6.10  
6.11  
6.12  
6.13  
6.14  
14  
15  
16  
17  
18  
19  
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 55  
Static characteristics. . . . . . . . . . . . . . . . . . . . 56  
Dynamic characteristics . . . . . . . . . . . . . . . . . 57  
Application information. . . . . . . . . . . . . . . . . . 58  
Test information. . . . . . . . . . . . . . . . . . . . . . . . 59  
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 60  
20  
Soldering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62  
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 62  
Surface mount packages . . . . . . . . . . . . . . . . 62  
Through-hole mount packages . . . . . . . . . . . . 63  
Package related soldering information . . . . . . 64  
20.1  
20.2  
20.3  
20.4  
7
Endpoint descriptions. . . . . . . . . . . . . . . . . . . 11  
Endpoint configuration . . . . . . . . . . . . . . . . . . 11  
Hub endpoint 0 (control) . . . . . . . . . . . . . . . . . 12  
Hub endpoint 1 (interrupt). . . . . . . . . . . . . . . . 12  
21  
22  
23  
24  
25  
26  
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 65  
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 66  
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66  
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 66  
Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66  
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 66  
7.1  
7.2  
7.3  
8
Host requests. . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Standard requests . . . . . . . . . . . . . . . . . . . . . 13  
Hub specific requests . . . . . . . . . . . . . . . . . . . 14  
Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Hub responses . . . . . . . . . . . . . . . . . . . . . . . . 19  
8.1  
8.2  
8.3  
8.4  
9
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
Initialization commands . . . . . . . . . . . . . . . . . 24  
Data flow commands . . . . . . . . . . . . . . . . . . . 25  
General commands . . . . . . . . . . . . . . . . . . . . 30  
9.1  
9.2  
9.3  
10  
Keyboard controller. . . . . . . . . . . . . . . . . . . . . 34  
Microcontroller core . . . . . . . . . . . . . . . . . . . . 34  
Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 34  
Special function registers (SFRs) . . . . . . . . . . 35  
Hub control registers. . . . . . . . . . . . . . . . . . . . 39  
Interrupt structure . . . . . . . . . . . . . . . . . . . . . . 39  
Timers/counters . . . . . . . . . . . . . . . . . . . . . . . 40  
Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 42  
I/O description. . . . . . . . . . . . . . . . . . . . . . . . . 44  
I/O port mapping. . . . . . . . . . . . . . . . . . . . . . . 44  
Keyboard matrix implementation . . . . . . . . . . 44  
Suspend and resume . . . . . . . . . . . . . . . . . . . 45  
10.1  
10.2  
10.3  
10.4  
10.5  
10.6  
10.7  
10.8  
10.9  
10.10  
10.11  
© Philips Electronics N.V. 2000.  
Printed in The Netherlands  
All rights are reserved. Reproduction in whole or in part is prohibited without the prior  
written consent of the copyright owner.  
The information presented in this document does not form part of any quotation or  
contract, is believed to be accurate and reliable and may be changed without notice. No  
liability will be accepted by the publisher for any consequence of its use. Publication  
thereof does not convey nor imply any license under patent- or other industrial or  
intellectual property rights.  
Date of release: 23 March 2000  
Document order number: 9397 750 06895  

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