ISP1160BM_技术文档

ISP1160

Embedded Universal Serial Bus Host Controller

Rev. 04 — 04 July 2003

Product data

1. General description

The ISP1160 is an embedded Universal Serial Bus (USB) Host Controller (HC) that

complies with Universal Serial Bus Speciﬁcation Rev. 2.0, supporting data transfer at

full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s). The ISP1160 provides two

downstream ports. Each downstream port has an overcurrent (OC) detection input

pin and power supply switching control output pin. The downstream ports for the HC

can be connected with any USB compliant USB devices and USB hubs that have

USB upstream ports.

The ISP1160 is well suited for embedded systems and portable devices that require a

USB host. The ISP1160 brings high ﬂexibility to the systems that have it built-in. For

example, a system that has the ISP1160 built-in allows it to be connected to a device

that has a USB upstream port, such as a USB printer, USB camera, USB keyboard,

USB mouse, among others.

2. Features

■ Complies with Universal Serial Bus Speciﬁcation Rev. 2.0

■ Supports data transfer at full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s)

■ Adapted from Open Host Controller Interface Speciﬁcation for USB Release 1.0a

■ Selectable one or two downstream ports for HC

■ High-speed parallel interface to most of the generic microprocessors and

Reduced Instruction Set Computer (RISC) processors such as:

◆ Hitachi^®SuperH™ SH-3 and SH-4

◆ MIPS-based™ RISC

◆ ARM7™, ARM9™, and StrongARM^®

■ Maximum 15 Mbyte/s data transfer rate between the microprocessor and the HC

■ Supports single-cycle and burst mode DMA operations

■ Built-in FIFO buffer RAM for the HC (4 kbytes)

■ Endpoints with double buffering to increase throughput and ease real-time data

transfer for isochronous (ISO) transactions

■ 6 MHz crystal oscillator with integrated PLL for low EMI

■ Built-in software selectable internal 15 kΩ pull-down resistors for HC downstream

ports

■ Dedicated pins for suspend sensing output and wake-up control input for ﬂexible

applications

■ Operation at either +5 V or +3.3 V power supply voltage

■ Operating temperature range from −40 °C to +85 °C

■ Available in two LQFP64 packages (SOT314-2 and SOT414-1).

ISP1160

Embedded USB Host Controller

Philips Semiconductors

3. Applications

■ Personal Digital Assistant (PDA)

■ Digital camera

■ Third-generation (3-G) phone

■ Set-Top Box (STB)

■ Information Appliance (IA)

■ Photo printer

■ MP3 jukebox

■ Game console.

4. Ordering information

Table 1:

Ordering information

Type number

Package

Name

Description

Version

ISP1160BD

LQFP64 plastic low proﬁle quad ﬂat package; 64 leads;

SOT314-2

body 10 × 10 × 1.4 mm

ISP1160BD/01^[1]

ISP1160BM

LQFP64 plastic low proﬁle quad ﬂat package; 64 leads;

SOT414-1

body 7 × 7 × 1.4 mm

ISP1160BM/01^[2]

[1] Improvement in performance as compared to ISP1160BD.

[2] Improvement in performance as compared to ISP1160BM.

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ISP1160

Embedded USB Host Controller

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6. Pinning information

6.1 Pinning

DGND

D2

1

2

3

4

5

6

7

8

9

48 n.c.

H_PSW2_N

47

D3

46 H_PSW1_N

45 DGND

D4

D5

44 XTAL2

D6

43

42

XTAL1

ISP1160BD

ISP1160BM

ISP1160BD/01

ISP1160BM/01

D7

H_SUSPEND

DGND

D8

41 n.c.

40

39

38

H_WAKEUP

TEST_LOW

n.c.

D9 10

D10 11

D11 12

37 TEST_LOW

D12

D13

n.c.

13

14

15

16

36

35

34

33

DGND

EOT

DGND

D14

NDP_SEL

004aaa060

Fig 2. Pin conﬁguration LQFP64.

6.2 Pin description

Table 2:

Symbol^[1]

Pin description for LQFP64

1

Type

-

Description

DGND

D2

digital ground

2

I/O

bit 2 of bidirectional data; slew-rate controlled; TTL input;

three-state output

D3

D4

3

4

I/O

bit 3 of bidirectional data; slew-rate controlled; TTL input;

three-state output

bit 4 of bidirectional data; slew-rate controlled; TTL input;

three-state output

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Embedded USB Host Controller

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Table 2:

Pin description for LQFP64…continued

Symbol^[1]

Type

Description

D5

5

I/O

bit 5 of bidirectional data; slew-rate controlled; TTL input;

three-state output

D6

D7

6

7

I/O

bit 6 of bidirectional data; slew-rate controlled; TTL input;

three-state output

bit 7 of bidirectional data; slew-rate controlled; TTL input;

three-state output

DGND

D8

8

9

-

digital ground

I/O

bit 8 of bidirectional data; slew-rate controlled; TTL input;

three-state output

D9

10

11

12

13

14

I/O

bit 9 of bidirectional data; slew-rate controlled; TTL input;

three-state output

D10

D11

D12

D13

bit 10 of bidirectional data; slew-rate controlled; TTL input;

three-state output

bit 11 of bidirectional data; slew-rate controlled; TTL input;

three-state output

bit 12 of bidirectional data; slew-rate controlled; TTL input;

three-state output

bit 13 of bidirectional data; slew-rate controlled; TTL input;

three-state output

DGND

D14

15

16

-

digital ground

I/O

bit 14 of bidirectional data; slew-rate controlled; TTL input;

three-state output

D15

17

I/O

bit 15 of bidirectional data; slew-rate controlled; TTL input;

three-state output

DGND

V_HOLD1

18

19

-

digital ground

voltage holding pin 1; internally connected to the V_REG(3V3)

and V_HOLD2pins. When V_CCis connected to 5 V, this pin

will output 3.3 V, hence do not connect it to 5 V. When V_CC

is connected to 3.3 V, this pin can either be connected to

3.3 V or left unconnected. In all cases, decouple this pin to

DGND.

n.c.

20

21

22

23

24

-

I

-

no connection; leave this pin open

chip select input

CS_N

RD_N

WR_N

V_HOLD2

read strobe input

write strobe input

voltage holding pin 2; internally connected to the V_REG(3V3)

and V_HOLD1pins. When V_CCis connected to 5 V, this pin

will output 3.3 V, hence do not connect it to 5 V. When V_CC

is connected to 3.3 V, this pin can either be connected to

3.3 V or left unconnected. In all cases, decouple this pin to

DGND.

DREQ

n.c.

25

26

O

-

HC DMA request output (programmable polarity); signals

to the DMA controller that the ISP1160 wants to start a

DMA transfer; see Section 10.4.1

no connection; leave this pin open

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Embedded USB Host Controller

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Table 2:

Pin description for LQFP64…continued

Symbol^[1]

Type

Description

DACK_N

27

I

HC DMA acknowledge input; when not in use, this pin must

be connected to V_CCvia an external 10 kΩ resistor

TEST_HIGH

INT

28

29

-

this pin must be connected to V_CCvia an external 10 kΩ

resistor

O

HC interrupt output; programmable level, edge triggered

and polarity; see Section 10.4.1

n.c.

30

31

32

-

no connection; leave this pin open

n.c.

O

I

RESET_N

reset input (Schmitt trigger); a LOW level produces an

asynchronous reset (internal pull-up resistor)

NDP_SEL

33

I

indicates to the HC software the Number of Downstream

Ports (NDP) present:

0 — select 1 downstream port

1 — select 2 downstream ports

only changes the value of the NDP ﬁeld in the

HcRhDescriptorA register; both ports will always be

enabled; see Section 10.3.1

(internal pull-up resistor)

EOT

34

I

DMA master device to inform the ISP1160 of end of DMA

transfer; active level is programmable; when not in use, this

pin must be connected to V_CCvia an external 10 kΩ

resistor; see Section 10.4.1

DGND

35

36

37

-

digital ground

n.c.

no connection; leave this pin open

TEST_LOW

this pin must be connected to DGND via an external 10 kΩ

resistor

n.c.

38

39

40

-

I

no connection; leave this pin open

TEST_LOW

H_WAKEUP

this pin must be connected to DGND via a 1 MΩ resistor

HC wake-up input; generates a remote wake-up from the

suspend state (active HIGH); when not in use, this pin must

be connected to DGND via an external 10 kΩ resistor

(internal pull-down resistor)

n.c.

41

-

no connection; leave this pin open

H_SUSPEND 42

O

I

HC suspend state indicator output; active HIGH

XTAL1

43

crystal input; connected directly to a 6 MHz crystal; when

this pin is connected to an external clock source,

pin XTAL2 must be left open

XTAL2

44

O

crystal output; connected directly to a 6 MHz crystal; when

pin XTAL1 is connected to an external clock source, this

pin must be left open

DGND

45

46

-

digital ground

H_PSW1_N

O

power switching control output for downstream port 1;

open-drain output

H_PSW2_N

47

O

power switching control output for downstream port 2;

open-drain output

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Table 2:

Pin description for LQFP64…continued

Symbol^[1]

48

49

50

51

52

Type

-

Description

n.c.

no connection; leave this pin open

n.c.

-

no connection; leave this pin open

H_DM1

H_DP1

H_DM2

AI/O

USB D− data line for HC downstream port 1

USB D+ data line for HC downstream port 1

USB D− data line for HC downstream port 2; when not in

use, this pin must be left open

H_DP2

53

AI/O

USB D+ data line for HC downstream port 2; when not in

use, this pin must be left open

H_OC1_N

H_OC2_N

V_CC

54

55

56

I

-

overcurrent sensing input for HC downstream port 1

overcurrent sensing input for HC downstream port 2

digital power supply input (3.0 V to 3.6 V or

4.75 V to 5.25 V). This pin supplies the internal 3.3 V

regulator input. When connected to 5 V, the internal

regulator will output 3.3 V to pins V_REG(3V3), V_HOLD1and

V_HOLD2. When connected to 3.3 V, it will bypass the internal

regulator.

AGND

57

58

-

analog ground

V_REG(3V3)

internal 3.3 V regulator output; when pin V_CCis connected

to 5 V, this pin outputs 3.3 V. When pin V_CCis connected to

3.3 V, connect this pin to 3.3 V.

A0

59

60

I

address input; selects command (A0 = 1) or data (A0 = 0)

LOW_PW

if low-current consumption (range of µs) is needed during

suspend, connect this pin to address A1; otherwise,

connect to DGND

n.c.

61

62

63

-

no connection; leave this pin open

digital ground

DGND

D0

-

I/O

bit 0 of bidirectional data; slew-rate controlled; TTL input;

three-state output

D1

64

I/O

bit 1 of bidirectional data; slew-rate controlled; TTL input;

three-state output

[1] Symbol names ending with underscore N (for example, NAME_N) represent active LOW signals.

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Embedded USB Host Controller

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7. Functional description

7.1 PLL clock multiplier

A 6 MHz to 48 MHz clock multiplier Phase-Locked Loop (PLL) is integrated on-chip.

This allows for the use of a low-cost 6 MHz crystal, which also minimizes EMI. No

external components are required for the operation of the PLL.

7.2 Bit clock recovery

The bit clock recovery circuit recovers the clock from the incoming USB data stream

by using a 4 times oversampling principle. It is able to track jitter and frequency drift

as speciﬁed in Universal Serial Bus Speciﬁcation Rev. 2.0.

7.3 Analog transceivers

Two sets of transceivers are embedded in the chip for downstream ports with USB

connector type A. The integrated transceivers are compliant with the Universal Serial

Bus Speciﬁcation Rev. 2.0. These transceivers interface directly with the USB

connectors and cables through external termination resistors.

7.4 Philips Serial Interface Engine (SIE)

The Philips SIE implements the full USB protocol layer. It is completely hardwired for

speed and needs no ﬁrmware intervention. The functions of this block include:

synchronization pattern recognition, parallel to serial conversion, bit (de)stufﬁng,

CRC checking and generation, Packet IDentiﬁer (PID) veriﬁcation and generation,

address recognition, and handshake evaluation and generation.

8. Microprocessor bus interface

8.1 Programmed I/O (PIO) addressing mode

A generic PIO interface is deﬁned for speed and ease-of-use. It also allows direct

interfacing to most microcontrollers. To a microcontroller, the ISP1160 appears as a

memory device with a 16-bit data bus and uses the A0 address line to access internal

control registers and FIFO buffer RAM. Therefore, the ISP1160 occupies only two

I/O ports or two memory locations of a microprocessor. External microprocessors can

read from or write to the ISP1160’s internal control registers and FIFO buffer RAM

through the Programmed I/O (PIO) operating mode. Figure 3 shows the

Programmed I/O interface between a microprocessor and the ISP1160.

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Embedded USB Host Controller

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µP bus I/F

[

]

[

]

D 15:0

RD_N

WR_N

CS_N

A1

RD_N

WR_N

CS_N

A0

MICRO-

PROCESSOR

ISP1160

INT

IRQ1

004aaa061

Fig 3. Programmed I/O interface between a microprocessor and the ISP1160.

8.2 DMA mode

The ISP1160 also provides the DMA mode for external microprocessors to access its

internal FIFO buffer RAM. Data can be transferred by the DMA operation between a

microprocessor’s system memory and the ISP1160’s internal FIFO buffer RAM.

Remark: The DMA operation must be controlled by the external microprocessor

system’s DMA controller (Master).

Figure 4 shows the DMA interface between a microprocessor system and the

ISP1160. The ISP1160 provides a DMA channel controlled by DREQ for DACK_N

signals for the DMA transfer between a microprocessor’s system memory and the

ISP1160 HC’s internal FIFO buffer RAM.

The EOT signal is an external end-of-transfer signal used to terminate the DMA

transfer. Some microprocessors may not have this signal. In this case, the ISP1160

provides an internal EOT signal to terminate the DMA transfer as well. Setting the

HcDMAConﬁguration register (21H to read, A1H to write) enables the ISP1160’s HC

internal DMA counter for the DMA transfer. When the DMA counter reaches the value

set in the HcTransferCounter register (22H to read, A2H to write), an internal EOT

signal will be generated to terminate the DMA transfer.

µP bus I/F

[

]

[

]

D 15:0

RD_N

WR_N

RD_N

WR_N

MICRO-

PROCESSOR

ISP1160

DACK1_N

DREQ1

DACK_N

DREQ

EOT

004aaa062

Fig 4. DMA interface between a microprocessor and the ISP1160.

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8.3 Control registers access by PIO mode

8.3.1 I/O port addressing

Table 3 shows the ISP1160’s I/O port addressing. Complete decoding of the I/O port

address should include the chip select signal CS_N and the address line A0.

However, the direction of access of I/O ports is controlled by the RD_N and

WR_N signals. When RD_N is LOW, the microprocessor reads data from the

ISP1160’s data port. When WR_N is LOW, the microprocessor writes a command to

the command port, or writes data to the data port.

Table 3:

Port

I/O port addressing

CS_N

A0

Access Data bus width Description

(bits)

0

1

0

1

R/W

W

16

HC data port

16

HC command port

Figure 5 illustrates how an external microprocessor accesses the ISP1160’s internal

control registers.

CMD/DATA

SWITCH

1

command port

data port

Host bus I/F

Commands

0

Command register

.

A0

004aaa075

Control registers

When A0 = 0, microprocessor accesses the data port.

When A0 = 1, microprocessor accesses the command port.

Fig 5. Access to internal control registers.

8.3.2 Register access phases

The ISP1160’s register structure is a command-data register pair structure. A

complete register access cycle comprises a command phase followed by a data

phase. The command (also known as the index of a register) points the ISP1160 to

the next register to be accessed. A command is 8 bits long. On a microprocessor’s

16-bit data bus, a command occupies the lower byte, with the upper byte ﬁlled with

zeros.

Figure 6 shows a complete 16-bit register access cycle for the ISP1160. The

microprocessor writes a command code to the command port, and then reads from or

writes the data word to the data port. Take the example of a microprocessor

attempting to read the ISP1160’s ID, which is saved in the HC’s HcChipID register

(index 27H, read only). The 16-bit register access cycle is therefore:

1. The microprocessor writes the command code of 27H (0027H in 16-bit width) to

the HC command port

2. The microprocessor reads the data word of the chip’s ID from the HC data port.

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16-bit register access cycle

write command

(16 bits)

read/write data

(16 bits)

t

MGT937

Fig 6. 16-bit register access cycle.

Most of the ISP1160’s internal control registers are 16-bit wide. Some of the internal

control registers, however, are 32-bit wide. Figure 7 shows how the ISP1160’s 32-bit

internal control register is accessed. The complete cycle of accessing a 32-bit

register consists of a command phase followed by two data phases. In the two data

phases, the microprocessor ﬁrst reads or writes the lower 16-bit data, followed by the

upper 16-bit data.

32-bit register access cycle

write command

(16 bits)

read/write data

(lower 16 bits)

read/write data

(upper 16 bits)

t

MGT938

Fig 7. 32-bit register access cycle.

To further describe the complete access cycles of the internal control registers, the

status of some pins of the microprocessor bus interface are shown in Figure 8.

Signals

Valid status

0

1

0

CS_N

A0

RD_N = 1,

WR_N = 0

RD_N = 0 (read) or

WR_N = 0 (write)

RD_N = 0 (read) or

WR_N = 0 (write)

RD_N,

WR_N

Register data

(lower word)

Register data

(upper word)

data bus

Command code

004aaa370

Fig 8. Accessing HC control registers.

8.4 FIFO buffer RAM access by PIO mode

Since the ISP1160’s internal memory is structured as a FIFO buffer RAM, the FIFO

buffer RAM is mapped to dedicated register ﬁelds. Therefore, accessing the internal

FIFO buffer RAM is similar to accessing the internal control registers in multiple data

phases.

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FIFO buffer RAM access cycle (transfer counter = 2N)

write command

(16 bits)

read/write data

#1 (16 bits)

read/write data

#2 (16 bits)

read/write data

#N (16 bits)

t

MGT941

Fig 9. Internal FIFO buffer RAM access cycle.

Figure 9 shows a complete access cycle of the HC internal FIFO buffer RAM. For a

write cycle, the microprocessor ﬁrst writes the FIFO buffer RAM’s command code to

the command port, and then writes the data words one by one to the data port until

half of the transfer’s byte count is reached. The HcTransferCounter register (22H to

read, A2H to write) is used to specify the byte count of a FIFO buffer RAM’s read

cycle or write cycle. Every access cycle must be in the same access direction. The

read cycle procedure is similar to the write cycle.

8.5 FIFO buffer RAM access by DMA mode

The DMA interface between a microprocessor and the ISP1160 is shown in Figure 4.

When doing a DMA transfer, at the beginning of every burst the ISP1160 outputs a

DMA request to the microprocessor via pin DREQ. After receiving this signal, the

microprocessor will reply with a DMA acknowledge to the ISP1160 via pin DACK_N,

and at the same time, execute the DMA transfer through the data bus. In the DMA

mode, the microprocessor must issue a read or write signal to the ISP1160’s

pins RD_N or WR_N. The ISP1160 will repeat the DMA cycles until it receives an

EOT signal to terminate the DMA transfer.

The ISP1160 supports both external and internal EOT signals. The external EOT

signal is received as input on pin EOT, and generally comes from the external

microprocessor. The internal EOT signal is generated inside the ISP1160.

To select either EOT method, set the appropriate DMA conﬁguration register (see

Section 10.4.2). For example, setting DMACounterSelect (bit 2) of the

HcDMAConﬁguration register (21H to read, A1H to write) to logic 1 will enable the

DMA counter for DMA transfer. When the DMA counter reaches the value of the

HcTransferCounter register, the internal EOT signal will be generated to terminate the

DMA transfer.

The ISP1160 supports either single-cycle DMA operation or burst mode DMA

operation; see Figure 10 and Figure 11.

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DREQ

DACK_N

RD_N or

WR_N

[

]

D 15:0

data #1

data #2

data #N

EOT

004aaa368

N = 1/2 byte count of transfer data.

Fig 10. DMA transfer in single-cycle mode.

DREQ

DACK_N

RD_N or

WR_N

[

]

D 15:0

data #1

data #K

data #(K+1)

data #2K

data #(N−K+1)

data #N

EOT

004aaa369

N = 1/2 byte count of transfer data, K = number of cycles/burst.

Fig 11. DMA transfer in burst mode.

In Figure 10 and Figure 11, the DMA transfer is conﬁgured such that DREQ is active

HIGH and DACK_N is active LOW.

8.6 Interrupts

The ISP1160 has an interrupt request pin INT.

8.6.1 Pin conﬁguration

The interrupt output signals have four conﬁguration modes:

Mode 0

Mode 1

Mode 2

Mode 3

Mode 0 level trigger, active LOW

Mode 1 level trigger, active HIGH

Mode 2 edge trigger, active LOW

Mode 3 edge trigger, active HIGH.

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Figure 12 shows these four interrupt conﬁguration modes. They are programmable

through the HcHardware Conﬁguration register (see Section 10.4.1), which is also

used to disable or enable the signals.

clear or disable INT

INT active

INT

Mode 0 level triggered, active LOW

clear or disable INT

INT active

Mode 1 level triggered, active HIGH

INT active

INT

166 ns

Mode 2 edge triggered, active LOW

INT active

MGT944

166 ns

Mode 3 edge triggered, active HIGH

Fig 12. Interrupt pin operating modes.

8.6.2 Interrupt output pin (INT)

To program the four conﬁguration modes of the HC’s interrupt output signal (INT), set

InterruptPinTrigger and InterruptOutputPolarity (bits 1 and 2) of the

HcHardwareConﬁguration register (20H to read, A0H to write). InterruptPinEnable

(bit 0) is used as the master enable setting for pin INT.

INT has many associated interrupt events as shown as in Figure 13.

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HcµPInterrupt

register

HcµPInterruptEnable

register

HcInterruptEnable

register

MIE

RHSC

FNO

UE

OR

RD

SF

SO

group 2

RHSC

FNO

UE

OR

HcHardwareConfiguration

register

RD

LE

INT

InterruptPinEnable

LATCH

SF

004aaa102

SO

HcInterruptStatus

register

Fig 13. HC interrupt logic.

There are two groups of interrupts represented by group 1 and group 2 in Figure 13.

A pair of registers control each group.

Group 2 contains six possible interrupt events (recorded in the HcInterruptStatus

register). On occurrence of any of these events, the corresponding bit would be set to

logic 1; and if the corresponding bit in the HcInterruptEnable register is also logic 1,

the 6-input OR gate would output a logic 1. This output is AND-ed with the value of

MIE (bit 31 of HcInterruptEnable). Logic 1 at the AND gate will cause the OPR bit in

the HcµPInterrupt register to be set to logic 1.

Group 1 contains six possible interrupt events, one of which is the output of group 2

interrupt sources. The HcµPInterrupt and HcµPInterruptEnable registers work in the

same way as the HcInterruptStatus and HcInterruptEnable registers in the interrupt

group 2. The output from the 6-input OR gate is connected to a latch, which is

controlled by InterruptPinEnable (bit 0 of the HcHardwareConﬁguration register).

In the event in which the software wishes to temporarily disable the interrupt output of

the ISP1160 Host Controller, the following procedure should be followed:

1. Make sure that the InterruptPinEnable bit in the HcHardwareConﬁguration

register is set to logic 1.

2. Clear all bits in the HcµPInterrupt register.

3. Set the InterruptPinEnable bit to logic 0.

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To re-enable the interrupt generation:

1. Set all bits in the HcµPInterrupt register.

2. Set the InterruptPinEnable bit to logic 1.

Remark: The InterruptPinEnable bit in the HcHardwareConﬁguration register latches

the interrupt output. When this bit is set to logic 0, the interrupt output will remain

unchanged, regardless of any operations on the interrupt control registers.

If INT1 is asserted, and the Host Controller Driver (HCD) wishes to temporarily mask

off the INT signal without clearing the HcµPInterrupt register, the following procedure

should be followed:

1. Make sure that the InterruptPinEnable bit is set to logic 1.

2. Clear all bits in the HcµPInterruptEnable register.

3. Set the InterruptPinEnable bit to logic 0.

To re-enable the interrupt generation:

1. Set all bits in the HcµPInterruptEnable register according to the HCD

requirements.

2. Set the InterruptPinEnable bit to logic 1.

9. Host Controller (HC)

9.1 HC’s four USB states

The ISP1160’s USB HC has four USB states—USBOperational, USBReset,

USBSuspend and USBResume—that deﬁne the HC’s USB signalling and bus states

responsibilities. The signals are visible to the Host Controller Driver (HCD) via the

ISP1160 USB HC’s control registers.

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USBOperational

USBReset write

USBOperational write

USBReset write

USBOperational write

USBResume

USBReset

USBSuspend write

hardware or software

reset

USBResume write

or

remote wake-up

USBReset write

MGT947

USBSuspend

Fig 14. The ISP1160 HC’s USB states.

The USB states are reﬂected in the HostControllerFunctionalState ﬁeld of the

HcControl register (01H to read, 81H to write), which is located at bits 7 and 6 of the

register.

The HCD can perform only the USB state transitions shown in Figure 14.

Remark: The Software Reset in Figure 14 is not caused by the HcSoftwareReset

command. It is caused by the HostControllerReset ﬁeld of the HcCommandStatus

register (02H to read, 82H to write).

9.2 Generating USB trafﬁc

USB trafﬁc can be generated only when the ISP1160 USB HC is in the

USBOperational state. Therefore, the HCD must set the

HostControllerFunctionalState ﬁeld of the HcControl register before generating USB

trafﬁc.

A simplistic ﬂow diagram showing when and how to generate USB trafﬁc is shown in

Figure 15. For greater accuracy, refer to the Universal Serial Bus Speciﬁcation

Rev. 2.0 for the USB protocol and the ISP1160 USB HC’s register usage.

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Reset

Exit

no

HC state =

USBOperational

yes

Need

USB traffic?

Prepare PTD data in

µP system RAM

Transfer PTD data into

HC FIFO buffer RAM

Initialize

HC

HC informs HCD of

USB traffic results

HC performs USB transactions

via USB bus I/F

HC interprets

PTD data

Entry

MGT948

Fig 15. ISP1160 HC USB transaction loop.

Description of Figure 15:

1. Reset

This includes hardware reset by pin RESET_N and software reset by the

HcSoftwareReset command (A9H). The reset function will clear all the HC’s

internal control registers to their reset status. After reset, the HCD must initialize

the ISP1160 USB HC by setting some registers.

2. Initialize HC

It includes:

a. Setting the physical size for the HC’s internal FIFO buffer RAM by setting the

HcITLBufferLength register (2AH to read, AAH to write) and the

HcATLBufferLength register (2BH to read, ABH to write).

b. Setting the HcHardwareConﬁguration register according to requirements.

c. Clearing interrupt events, if required.

d. Enabling interrupt events, if required.

e. Setting the HcFmInterval register (0DH to read, 8DH to write).

f. Setting the HC’s Root Hub registers.

g. Setting the HcControl register to move the HC into the USBOperational state.

See also Section 9.5.

3. Entry

The normal entry point. The microprocessor returns to this point when there are

HC requests.

4. Need USB trafﬁc

USB devices need the HC to generate USB trafﬁc when they have USB trafﬁc

requests such as:

a. Connecting to or disconnecting from downstream ports

b. Issuing the Resume signal to the HC.

To generate USB trafﬁc, the HCD must enter the USB transaction loop.

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5. Prepare PTD data in µP system RAM

The communication between the HCD and the ISP1160 HC is in the form of

Philips Transfer Descriptor (PTD) data. The PTD data provides USB trafﬁc

information about the commands, status and USB data packets.

The physical storage media of PTD data for the HCD is the microprocessor’s

system RAM. For the ISP1160’s HC, the storage media is the internal FIFO buffer

RAM.

The HCD prepares PTD data in the microprocessor’s system RAM for transfer to

the ISP1160’s HC internal FIFO buffer RAM.

6. Transfer PTD data into HC’s FIFO buffer RAM

When PTD data is ready in the microprocessor’s system RAM, the HCD must

transfer the PTD data from the microprocessor’s system RAM into the ISP1160’s

internal FIFO buffer RAM.

7. HC interprets PTD data

The HC determines what USB transactions are required based on the PTD data

that has been transferred into the internal FIFO buffer RAM.

8. HC performs USB transactions via USB bus interface

The HC performs the USB transactions with the speciﬁed USB device endpoint

through the USB bus interface.

9. HC informs HCD of the USB trafﬁc results

The USB transaction status and the feedback from the speciﬁed USB device

endpoint will be put back into the ISP1160’s HC internal FIFO buffer RAM in PTD

data format. The HCD can read back the PTD data from the internal FIFO buffer

RAM.

9.3 PTD data structure

The Philips Transfer Descriptor (PTD) data structure provides communication

between the HCD and the ISP1160’s USB HC. The PTD data contains information

required by the USB trafﬁc. PTD data consists of a PTD followed by its payload data,

as shown in Figure 16.

FIFO buffer RAM

top

PTD

PTD data #1

payload data

PTD

PTD data #2

payload data

PTD

PTD data #N

payload data

bottom

MGT949

Fig 16. PTD data in FIFO buffer RAM.

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The PTD data structure is used by the HC to deﬁne a buffer of data that will be moved

to or from an endpoint in the USB device. This data buffer is set up for the current

frame (1 ms frame) by the HCD. The payload data for every transfer in the frame must

have a PTD as the header to describe the characteristic of the transfer. The PTD data

is DWORD (double-word or 4-byte) aligned.

9.3.1 PTD data header deﬁnition

The PTD forms the header of the PTD data. It tells the HC the transfer type, where

the payload data should go, and the actual size of the payload data. A PTD is an

8-byte data structure that is very important for HCD programming.

Table 4:

Bit

Philips Transfer Descriptor (PTD): bit allocation

7

6

5

4

3

2

1

0

Byte 0

Byte 1

Byte 2

Byte 3

Byte 4

Byte 5

Byte 6

Byte 7

ActualBytes[7:0]

Active

CompletionCode[3:0]

EndpointNumber[3:0]

Toggle

Speed

ActualBytes[9:8]

MaxPacketSize[9:8]

TotalBytes[9:8]

MaxPacketSize[7:0]

Last

TotalBytes[7:0]

reserved

B5_5

reserved

DirectionPID[1:0]

Format

FunctionAddress[6:0]

reserved

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Table 5:

Philips Transfer Descriptor (PTD): bit description

Symbol

Access

R/W

Description

Contains the number of bytes that were transferred for this PTD.

ActualBytes[9:0]

CompletionCode[3:0]

R/W

0000 NoError

General TD or isochronous data packet processing

completed with no detected errors.

0001 CRC

Last data packet from endpoint contained a CRC error.

0010 BitStufﬁng

Last data packet from endpoint contained a bit stufﬁng

violation.

0011 DataToggleMismatch

0100 Stall

Last packet from endpoint had data toggle PID that did

not match the expected value.

TD was moved to the Done queue because the

endpoint returned a STALL PID.

0101 DeviceNotResponding Device did not respond to token (IN) or did not provide a

handshake (OUT).

0110 PIDCheckFailure

0111 UnexpectedPID

1000 DataOverrun

Check bits on PID from endpoint failed on data PID (IN)

or handshake (OUT).

Received PID was not valid when encountered or PID

value is not deﬁned.

The amount of data returned by the endpoint exceeded

either the size of the maximum data packet allowed

from the endpoint (found in the MaximumPacketSize

ﬁeld of endpoint descriptor) or the remaining buffer size.

1001 DataUnderrun

The endpoint returned is less than MaximumPacketSize

and that amount was not sufﬁcient to ﬁll the speciﬁed

buffer.

1010 reserved

-

1011 reserved

1100 BufferOverrun

During an IN, the HC received data from an endpoint

faster than it could be written to system memory.

1101 BufferUnderrun

During an OUT, the HC could not retrieve data from the

system memory fast enough to keep up with the USB

data rate.

Active

R/W

Set to logic 1 by ﬁrmware to enable the execution of transactions by the HC. When the

transaction associated with this descriptor is completed, the HC sets this bit to logic 0,

indicating that a transaction for this element will not be executed when it is next

encountered in the schedule.

Toggle

R/W

R

Used to generate or compare the data PID value (DATA0 or DATA1). It is updated after

each successful transmission or reception of a data packet.

MaxPacketSize[9:0]

The maximum number of bytes that can be sent to or received from the endpoint in a

single data packet.

EndpointNumber[3:0]

R

USB address of the endpoint within the function.

Last PTD of a list (ITL or ATL). Logic 1 indicates that the PTD is the last PTD.

Speed of the endpoint:

Last

Speed

0 — full speed

1 — low speed

TotalBytes[9:0]

R

Speciﬁes the total number of bytes to be transferred with this data structure. For Bulk and

Control only, this can be greater than MaximumPacketSize.

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Table 5:

Philips Transfer Descriptor (PTD): bit description…continued

Symbol

Access

Description

DirectionPID[1:0]

R

00

01

10

11

SETUP

OUT

IN

reserved

B5_5

R/W

This bit is logic 0 at power-on reset. When this feature is not used, software used for the

ISP1160 is the same for the ISP1161 and the ISP1161A. When this bit is set to logic 1 in

this PTD for interrupt endpoint transfer, only one PTD USB transaction will be sent out in

1 ms.

Format

R

The format of this data structure. If this is a Control, Bulk or Interrupt endpoint, then

Format = 0. If this is an Isochronous endpoint, then Format = 1.

FunctionAddress[6:0]

This is the USB address of the function containing the endpoint that this PTD refers to.

9.4 HC’s internal FIFO buffer RAM structure

9.4.1 Partitions

According to the Universal Serial Bus Speciﬁcation Rev. 2.0, there are four types of

USB data transfers: Control, Bulk, Interrupt and Isochronous.

The HC’s internal FIFO buffer RAM has a physical size of 4 kbytes. This internal FIFO

buffer RAM is used for transferring data between the microprocessor and USB

peripheral devices. This on-chip buffer RAM can be partitioned into two areas:

Acknowledged Transfer List (ATL) buffer and Isochronous (ISO) Transfer List (ITL)

buffer. The ITL buffer is a Ping-Pong structured FIFO buffer RAM that is used to keep

the payload data and their PTD header for Isochronous transfers. The ATL buffer is a

non Ping-Pong structured FIFO buffer RAM that is used for the other three types of

transfers.

The ITL buffer can be further partitioned into ITL0 and ITL1 for the Ping-Pong

structure. The ITL0 and ITL1 buffers always have the same size. The microprocessor

can put ISO data into either the ITL0 buffer or the ITL1 buffer. When the

microprocessor accesses an ITL buffer, the HC can take over the other ITL buffer at

the same time. This architecture improves the ISO transfer performance.

The HCD can assign the logical size for the ATL buffer and ITL buffers at any time, but

normally at initialization after power-on reset. This is done by setting the

HcATLBufferLength register (2BH to read, ABH to write) and the HcITLBufferLength

register (2AH to read, AAH to write), respectively. The total length (ATL buffer + ITL

buffer) should not exceed the maximum RAM size of 4 kbytes. Figure 17 shows the

partitions of the internal FIFO buffer RAM. When assigning buffer RAM sizes, follow

this formula:

ATL buffer length + 2 × (ITL buffer size) ≤ 1000H (that is, 4 kbytes)

where: ITL buffer size = ITL0 buffer length = ITL1 buffer length

The following assignments are examples of legal uses of the internal FIFO buffer

RAM:

• ATL buffer length = 800H, ITL buffer length = 400H.

This is the maximum use of the internal FIFO buffer RAM.

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• ATL buffer length = 400H, ITL buffer length = 200H.

This is insufﬁcient use of the internal FIFO buffer RAM.

• ATL buffer length = 1000H, ITL buffer length = 0H.

This will use the internal FIFO buffer RAM for only ATL transfers.

FIFO buffer RAM

top

ITL0

ISO_A

ISO_B

ITL buffer

ATL buffer

ITL1

programmable

sizes

control/bulk/interrupt

data

ATL

not used

bottom

4 kbytes

MGT950

Fig 17. HC internal FIFO buffer RAM partitions.

The actual requirement for the buffer RAM needs to reach not the maximum size. You

can make your selection based on your application.

The following are some calculations of the ISO_A or ISO_B space for a frame of data:

• Maximum number of useful data sent during one USB frame is 1280 bytes (20 ISO

packets of 64 bytes). The total RAM size needed is:

20 × 8 + 1280 = 1440 bytes.

• Maximum number of packets for different endpoints sent during one USB frame is

150 (150 ISO packets of 1 byte). The total RAM size needed is:

150 × 8 + 150 × 1 = 1350 bytes.

• The Ping buffer RAM (ITL0) and the Pong buffer RAM (ITL1) have a maximum size

of 2 kbytes each. All data needed for one frame can be stored in the Ping or the

Pong buffer RAM.

When the embedded system wants to initiate a transfer to the USB bus, the data

needed for one frame is transferred to the ATL buffer or the ITL buffer. The

microprocessor detects the buffer status through interrupt routines. When the

HcBufferStatus register (2CH to read only) indicates that the buffer is empty, then the

microprocessor writes data into the buffer. When the HcBufferStatus register

indicates that the buffer is full, the data is ready on the buffer, and the microprocessor

needs to read data from the buffer.

For every 1 ms, there might be many events to generate interrupt requests to the

microprocessor for data transfer or status retrieval. However, each of the interrupt

types deﬁned in this speciﬁcation can be enabled or disabled by setting

HcµPInterruptEnable register bits accordingly.

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The data transfer can be done via the PIO mode or the DMA mode. The data transfer

rate can go up to 15 Mbyte/s. In the DMA operation, the single-cycle or multi-cycle

burst modes are supported. Multi-cycle burst modes of 1, 4 or 8 cycles per burst are

supported for the ISP1160.

9.4.2 Data organization

PTD data is used for every data transfer between a microprocessor and the USB bus,

and the PTD data resides in the buffer RAM. For an OUT or SETUP transfer, the

payload data is placed just after the PTD, after which the next PTD is placed. For an

IN transfer, RAM space is reserved for receiving a number of bytes that is equal to the

total bytes of the transfer. After this, the next PTD and its payload data are placed

(see Figure 18).

Remark: The PTD is deﬁned for both the ATL and ITL type data transfer. For ITL, the

PTD data is put into ITL buffer RAM, and the ISP1160 takes care of the Ping-Pong

action for the ITL buffer RAM access.

RAM buffer

top

000H

PTD of OUT transfer

payload data of OUT transfer

PTD of IN transfer

empty space for IN total data

PTD of OUT transfer

payload data of OUT transfer

bottom

7FFH

MGT952

Fig 18. Buffer RAM data organization.

The PTD data (PTD header and its payload data) is a structure of DWORD alignment.

This means that the memory address is organized in blocks of 4 bytes. Therefore, the

ﬁrst byte of every PTD and the ﬁrst byte of every payload data are located at an

address that is a multiple of 4. Figure 19 illustrates an example in which the ﬁrst

payload data is 14 bytes long, meaning that the last byte of the payload data is at the

location 15H. The next addresses (16H and 17H) are not multiples of 4. Therefore,

the ﬁrst byte of the next PTD will be located at the next multiple-of-four address (18H).

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RAM buffer

top

00H

08H

PTD

(8 bytes)

payload data

(14 bytes)

15H

18H

PTD

(8 bytes)

20H

payload data

MGT953

Fig 19. PTD data with DWORD alignment in buffer RAM.

9.4.3 Operation and C program example

Figure 20 shows the block diagram for internal FIFO buffer RAM operations in the

PIO mode. The ISP1160 provides one register as the access port for each buffer

RAM. For the ITL buffer RAM, the access port is the ITLBufferPort register (40H to

read, C0H to write). For the ATL buffer RAM, the access port is the ATLBufferPort

register (41H to read, C1H to write). The buffer RAM is an array of bytes (8 bits) while

the access port is a 16-bit register. Therefore, each read/write operation on the port

accesses two consecutive memory locations, incrementing the pointer of the internal

buffer RAM by two.

The lower byte of the access port register corresponds to the data byte at the even

location of the buffer RAM, and the upper byte corresponds to the next data byte at

the odd location of the buffer RAM. Regardless of the number of data bytes to be

transferred, the command code must be issued merely once, and it will be followed by

a number of accesses of the data port (see Section 8.4).

When the pointer of the buffer RAM reaches the value of the HcTransferCounter

register, an internal EOT signal will be generated to set bit 2, AllEOTInterrupt, of the

HcµPInterrupt register and update the HcBufferStatus register, to indicate that the

whole data transfer has been completed.

For ITL buffer RAM, every start of frame (SOF) signal (1 ms) will cause toggling

between ITL0 and ITL1 but this depends on the buffer status. If both ITL0BufferFull

and ITL1BufferFull of the HcBufferStatus register are already logic 1, meaning that

both ITL0 and ITL1 buffer RAMs are full, the toggling will not happen. In this case, the

microprocessor will always have access to ITL1.

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command port

data port

1

0

Host bus I/F

Control registers

Commands

Command register

A0

TransferCounter

22H/A2H

24H/A4H

EOT

2

1

0

µPInterrupt

=

internal EOT

2CH

40H/C0H

41H/C1H

BufferStatus

ITLBufferPort

ATLBufferPort

(16-bit width)

toggle

T

SOF

BufferStatus

Pointer

000H

001H

000H

001H

000H

001H

automatically

increments by 2

3FFH

7FFH

ITL0 buffer RAM

(8-bit width)

ITL1 buffer RAM

(8-bit width)

ATL buffer RAM

(8-bit width)

MGT951

Fig 20. PIO access to internal FIFO buffer RAM.

Following is an example of a C program that shows how to write data into the ATL

buffer RAM. The total number of data bytes to be transferred is 80 (decimal) that will

be set into the HcTransferCounter register as 50H. The data consists of four types of

PTD data:

1. The ﬁrst PTD header (IN) is 8 bytes, followed by 16 bytes of space reserved for

its payload data;

2. The second PTD header (IN) is also 8 bytes, followed by 8 bytes of space

reserved for its payload data;

3. The third PTD header (OUT) is 8 bytes, followed by 16 bytes of payload data with

values beginning from 0H to FH incrementing by 1;

4. The fourth PTD header (OUT) is also 8 bytes, followed by 8 bytes of payload data

with values beginning from 0H to EH incrementing by 2.

In all PTDs, we have assigned device address as 5 and endpoint 1. ActualBytes is

always zero (0). TotalBytes equals the number of payload data bytes transferred.

However, note that for bulk and control transfers, TotalBytes can be greater than

MaxPacketSize.

Table 6 shows the results after running this program.

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However, if communication with a peripheral USB device is desired, the device should

be connected to the downstream port and pass enumeration.

//The example program for writing ATL buffer RAM

#include <conio.h>

#include <stdio.h>

#include <dos.h>

//Define register commands

#define wHcTransferCounter 0x22

#define wHcuPInterrupt 0x24

#define wHcATLBufferLength 0x2b

#define wHcBufferStatus 0x2c

// Define I/O Port Address for HC

#define HcDataPort 0x290

#define HcCmdPort 0x292

//Declare external functions to be used

unsigned int HcRegRead(unsigned int wIndex);

void HcRegWrite(unsigned int wIndex,unsigned int wValue);

void main(void)

{

unsigned int i;

unsigned int wCount,wData;

// Prepare PTD data to be written into HC ATL buffer RAM:

unsigned int PTDData[0x28]=

{

0x0800,0x1010,0x0810,0x0005, //PTD header for IN token #1

//Reserved space for payload data of IN token #1

0x0000,0x0000,0x0000,0x0000, 0x0000,0x0000,0x0000,0x0000,

0x0800,0x1008,0x0808,0x0005, //PTD header for IN token #2

//Reserved space for payload data of IN token #2

0x0000,0x0000,0x0000,0x0000,

0x0800,0x1010,0x0410,0x0005, //PTD header for OUT token #1

0x0100,0x0302,0x0504,0x0706, //Payload data for OUT token #1

0x0908,0x0b0a,0x0d0c,0x0f0e,

0x0800,0x1808,0x0408,0x0005, //PTD header for OUT token #2

0x0200,0x0604,0x0a08,0x0e0c //Payload data for OUT token #2

};

HcRegWrite(wHcuPInterrupt,0x04); //Clear EOT interrupt bit

//HcRegWrite(wHcITLBufferLength,0x0);

HcRegWrite(wHcATLBufferLength,0x1000); //RAM full use for ATL

//Set the number of bytes to be transferred

HcRegWrite(wHcTransferCounter,0x50);

wCount = 0x28; //Get word count outport

(HcCmdPort,0x00c1); //Command for ATL buffer write

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//write 80 (0x50) bytes of data into ATL buffer RAM

for (i=0;i<wCount;i++)

{

outport(HcDataPort,PTDData[i]);

};

//Check EOT interrupt bit

wData = HcRegRead(wHcuPInterrupt);

printf("\n HC Interrupt Status = %xH.\n",wData);

//Check Buffer status register

wData = HcRegRead(wHcBufferStatus);

printf("\n HC Buffer Status = %xH.\n",wData);

}

//

// Read HC 16-bit registers

//

unsigned int HcRegRead(unsigned int wIndex)

{ unsigned int wValue;

outport(HcCmdPort,wIndex & 0x7f);

wValue = inport(HcDataPort);

return(wValue);

}

//

// Write HC 16-bit registers

//

void HcRegWrite(unsigned int wIndex,unsigned int wValue)

{

outport(HcCmdPort,wIndex | 0x80);

outport(HcDataPort,wValue);

}

Table 6:

Run results of the C program example

Observed items

HC not initialized and not in HC initialized and in

Comments

USBOperational state

HcµPInterrupt register

Bit 1 (ATLInt)

0

1

microprocessor must read ATL

transfer completed

Bit 2 (AllEOTInterrupt)

HcBufferStatus register

Bit 2 (ATLBufferFull)

Bit 5 (ATLBufferDone)

USB trafﬁc on USB Bus

1

0

1

transfer completed

PTD data processed by HC

OUT packets can be seen

no

yes

9.5 HC operational model

Upon power up, the HCD sets up all operational registers (32-bit). The

FSLargestDataPacket ﬁeld (bits 30 to 16) of the HcFmInterval register (0DH to read,

8DH to write) and the HcLSThreshold register (11H to read, 91H to write) determine

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the end of the frame for full-speed and low-speed packets. By programming these

ﬁelds, the effective USB bus usage can be changed. Furthermore, the size of the ITL

buffers (HcITLBufferLength, 2AH to read, AAH to write) is programmed.

If a USB frame contains both ISO and AT packets, two interrupts will be generated

per frame.

One interrupt is issued concurrently with the SOF. This interrupt (ITLInt is set in the

HcµPInterrupt register) triggers reading and writing of the ITL buffer by the

microprocessor, after which the interrupt is cleared by the microprocessor.

Next the programmable ATL Interrupt (bit ATLInt is set in the HcµPInterrupt register)

is issued, which triggers reading and writing of the ATL buffer by the microprocessor,

after which the interrupt is cleared by the microprocessor. If the microprocessor

cannot handle the ISO interrupt before the next ISO interrupt, disrupted ISO trafﬁc

can result.

To be able to send more than one packet to the same Control or Bulk endpoint in the

same frame, the Active bit and the TotalBytes ﬁeld are introduced (see Table 5).

Bit Active is cleared only if all data of the Philips Transfer Descriptor (PTD) have been

transferred or if a transaction at that endpoint contained a fatal error. If all PTDs of the

ATL are serviced once and the frame is not over yet, the HC starts looking for a PTD

with bit Active still set. If such a PTD is found and there is still enough time in this

frame, another transaction is started on the USB bus for this endpoint.

For ISO processing, the HCD also has to take care of the BufferStatus register

(2CH, read only) for the ITL buffer RAM operations. After the HCD writes ISO data

into ITL buffer RAM, the ITL0BufferFull or ITL1BufferFull bit (depending on whether it

is ITL0 or ITL1) will be set to logic 1.

After the HC processes the ISO data in the ITL buffer RAM, the corresponding

ITL0BufferDone or ITL1BufferDone bit will automatically be set to logic 1.

The HCD can clear the buffer status bits by a read of the ITL buffer RAM. This must

be done within the 1 ms frame from which ITL0BufferDone or ITL1BufferDone was

set. Failure to do so will cause the ISO processing to stop and a power-on reset or

software reset will have to be applied to the HC, a USB reset to the USB bus must

not be made.

For example, the HCD writes ISO_A data into the ITL0 buffer in the ﬁrst frame. This

will cause the HcBufferStatus register to show that the ITL0 buffer is full by setting

bit ITL0BufferFull to logic 1. At this stage, the HCD cannot write ISO data into the

ITL0 buffer RAM again.

In the second frame, the HC will process the ISO_A data in the ITL0 buffer. At the

same time, the HCD can write ISO_B data into the ITL1 buffer. When the next SOF

comes (the beginning of the third frame), both ITL1BufferFull and ITL0BufferDone are

automatically set to logic 1.

In the third frame, the HCD has to read at least two bytes (one word) of the ITL0

buffer to clear both the ITL0BufferFull and ITL0BufferDone bits. If both are not

cleared, when the next SOF comes (the beginning of the fourth frame) the

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ITL0BufferDone and ITL0BufferFull bits will be cleared automatically. This also

applies to the ITL1 buffer because ITL0 and ITL1 are Ping-Pong structured buffers. To

recover from this state, a power-on reset or software reset will have to be applied.

9.5.1 Time domain behavior

In example 1 (Figure 21), the CPU is fast enough to read back and download a

scenario before the next interrupt. Note that on the ISO interrupt of frame N:

• The ISO packet for frame N + 1 will be written

• The AT packet for frame N + 1 will be written.

AT

interrupt

traffic

on USB

SOF

(frame N)

(frame N + 1)

(frame N + 2)

(frame N + 3)

MGT954

ISO

interrupt

read ISO_A(N − 1) write ISO_A(N + 1)

read AT(N)

write AT(N + 1)

Fig 21. HC time domain behavior: example 1.

In example 2 (Figure 22), the microprocessor is still busy transferring the AT data

when the ISO interrupt of the next frame (N + 1) is raised. As a result, there will be no

AT trafﬁc in frame N + 1. The HC does not raise an AT interrupt in frame N + 1. The

AT part is simply postponed until frame N + 2. On the AT N + 2 interrupt, the transfer

mechanism is back to the normal operation. This simple mechanism ensures, among

other things, that Control transfers are not dropped systematically from the USB in

case of an overloaded microprocessor.

(frame N)

(frame N + 1)

(frame N + 2)

(frame N + 3)

MGT955

Fig 22. HC time domain behavior: example 2.

In example 3 (Figure 23), the ISO part is still being written while the Start of Frame

(SOF) of the next frame has occurred. This will result in undeﬁned behavior for the

ISO data on the USB bus in frame N + 1 (depending on whether the exact timing data

is corrupted or not). The HC should not raise an AT interrupt in frame N + 1.

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(frame N)

(frame N + 1)

(frame N + 2)

(frame N + 3)

MGT956

Fig 23. HC time domain behavior: example 3.

9.5.2 Control transaction limitations

The different phases of a Control transfer (SETUP, Data and Status) should never be

put in the same ATL.

9.6 Microprocessor loading

The maximum amount of data that can be transferred for an endpoint in one frame is

1023 bytes. The number of USB packets that are needed for this batch of data

depends on the maximum packet size that is speciﬁed.

The HCD has to schedule the transactions in a frame. On the other hand, the

microprocessor must have the ability to handle the interrupts coming from the HC

every 1 ms. It must also be able to do the scheduling for the next frame, reading the

frame information from and writing the next frame information to the buffer RAM in the

time between the end of the current frame and the start of the next frame.

9.7 Internal pull-down resistors for downstream ports

There are four internal 15 kΩ pull-down resistors built in the ISP1160 for the two

downstream ports: two resistors for each port. These resistors are software

selectable by programming bit 12 (2_DownstreamPort15Kresistorsel) of the

HcHardwareConﬁguration register (20H to read, A0H to write). When bit 12 is logic 0,

external 15 kΩ pull-down resistors are used. When bit 12 is logic 1, internal 15 kΩ

pull-down resistors are used. See Figure 24.

This feature is a cost-saving option. However, the power-on reset default value of

bit 12 is logic 0. If using the internal resistors, the HCD must check this bit status after

every reset, because a reset action (hardware or software) will clear this bit.

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V

BUS

USB

connector

ISP1160

22 Ω

D−

D+

bit 12

HcHardware

Configuration

47 pF

(2×)

external

15 kΩ

(2×)

internal

15 kΩ

(2×)

004aaa064

Using either internal or external 15 kΩ resistors.

Fig 24. Use of 15 kΩ pull-down resistors on downstream ports.

9.8 Overcurrent detection and power switching control

A downstream port provides 5 V power supply to V_BUS. The ISP1160 has built-in

hardware functions to monitor the downstream ports loading conditions and control

their power switching. These hardware functions are implemented by the internal

power switching control circuit and overcurrent detection circuit. H_PSW1_N and

H_PSW2_N are power switching control output pins (active LOW, open-drain) for

downstream ports 1 and 2, respectively. H_OC1_N and H_OC2_N are overcurrent

detection input pins for downstream ports 1 and 2, respectively.

Figure 25 shows the ISP1160 downstream port power management scheme.

regulator

HC CORE

HcHardware

V

CC

(+5 V or +3.3 V)

OC detect

Configuration

OC select

1

bit 10

≥

H_OCn_N

0

Reg

PSW

H_PSWn_N

C/L

ISP1160

004aaa065

’n’ represents the downstream port numbers (n = 1 or 2).

Fig 25. Downstream port power management scheme.

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9.8.1 Using an internal OC detection circuit

The internal OC detection circuit can be used only when V_CC(pin 56) is connected to

a 5 V power supply. The HCD must set AnalogOCEnable, bit 10 of the

HcHardwareConﬁguration register, to logic 1.

An application using the internal OC detection circuit and internal 15 kΩ pull-down

resistors is shown in Figure 26. In this example, the HCD must set both

AnalogOCEnable and DownstreamPort15Kresistorsel to logic 1. They are bit 10 and

bit 12 of the HcHardwareConﬁguration register, respectively.

When H_OCn_N detects an overcurrent status on a downstream port, H_PSWn_N

will output HIGH, a logic 1 to turn off the 5 V power supply to the downstream port

V_BUS. When there is no such detection, H_PSWn_N will output LOW, a logic 0 to turn

on the 5 V power supply to the downstream port V_BUS

.

In general applications, a P-channel MOSFET can be used as the power switch for

V_BUS. Connect the 5 V power supply to the drain of the P-channel MOSFET, V_BUSto

the source, and H_PSWn_N to the gate. Call the voltage drop across the drain and

source, the overcurrent detection voltage (V_OC). For the internal overcurrent detection

circuit, a voltage comparator has been designed-in, with a nominal voltage threshold

(∆V_trip) of 75 mV. When V_OCexceeds V_trip, H_PSWn_N will output a HIGH level,

logic 1 to turn off the P-channel MOSFET. If the P-channel MOSFET has a R_DSonof

150 mΩ, the overcurrent threshold will be 500 mA. The selection of a P-channel

MOSFET with a different R_DSonwill result in a different overcurrent threshold.

regulator

P-Channel

HC CORE

HcHardware

MOSFET

V

CC

+

5 V

OC detect

Configuration

OC select

bit 10

1

≥

+

V

=

5 V − V

BUS

OC

H_OCn_N

0

Reg

V

BUS

PSW

H_PSWn_N

C/L

USB

downstream

port

connector

22 Ω

H_DMn

ATX

SIE

22 Ω

H_DPn

bit 12

47 pF

(2×)

HcHardware

Configuration

15 kΩ

(2×)

ISP1160

004aaa066

’n’ represents the downstream port number (n = 1 or 2).

Fig 26. Using an internal OC detection circuit.

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9.8.2 Using an external OC detection circuit

When V_CC(pin 56) is connected to a 3.3 V instead of the 5 V power supply, the

internal OC detection circuit cannot be used. An external OC detection circuit must be

used instead. Regardless of the V_CCvalue, an external OC detection circuit can

always be used. To use an external OC detection circuit, AnalogOCEnable, bit 10 of

the HcHardwareConﬁguration register, should be logic 0. By default after reset, this

bit is already logic 0; therefore, the HCD does not need to clear this bit.

Figure 27 shows how to use an external OC detection circuit.

+

3.3 V or 5 V

regulator

HC CORE

HcHardware

V

CC

V

+

5 V

BUS

OC detect

Configuration

OC select

external

OC detect

bit 10

1

≥

V

i

H_OCn_N

o

0

Reg

OC

EN

PSW

H_PSWn_N

C/L

USB

downstream

port

connector

22 Ω

H_DMn

H_DPn

ATX

SIE

22 Ω

bit 12

47 pF

(2×)

HcHardware

Configuration

15 kΩ

(2×)

ISP1160

004aaa067

’n’ represents the downstream port number (n = 1 or 2).

Fig 27. Using an external OC detection circuit.

9.9 Suspend and wake-up

9.9.1 HC suspended state

The HC can be put into suspended state by setting the HcControl register (01H to

read, 81H to write). See Figure 14 for the HC’s ﬂow of USB state changes.

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XOSC_6MHz

HC_ClkOk

PLL_Lock

HC PLL

PLL_ClkOut

DIGITAL

CLOCK

SWITCH

XOSC

On

HC_Clk48MOut

HC_RawClk48M

On

HC

CORE

HC_EnableClock

HcHardware Configuration

bit 11 (SuspendClkNotStop)

On

HC_NeedClock

VOLTAGE

REGULATOR

H_WAKEUP (pin)

CS_N (pin)

004aaa375

Fig 28. ISP1160 suspend and resume clock scheme.

In the suspended state, the device will consume considerably less power by turning

off the internal 48 MHz clock, PLL and crystal, and setting the internal regulator to

power-down mode. The ISP1160 suspend and resume clock scheme is shown in

Figure 28.

Pin H_SUSPEND is the sensing output pin for the HC’s suspended state. When the

HC goes into the USBSuspend state, this pin will output a HIGH level (logic 1). This

pin is cleared to LOW (logic 0) level only when the HC is put into a USBReset state or

USBOperational state (refer to the HcControl register bits 7 to 6; 01H to read, 81H to

write). Bit 11, SuspendClkNotStop, of the HcHardwareConﬁguration register (20H to

read, A0H to write), deﬁnes if the HC internal clock is stopped or kept running when

the HC goes into the USBSuspend state. After the HC enters the USBSuspend state

for 1.3 ms, the internal clock will be stopped if bit SuspendClkNotStop is logic 0.

For details on power consumption, refer to Philips Application Note

AN10022 ISP1160x Low Power Consumption.

9.9.2 HC wake-up from suspended state

There are three methods to wake up the HC from the USBSuspend state: hardware

wake-up, software wake-up, and USB bus resume. They are described as follows.

Wake-up by pin H_WAKEUP: Pins H_SUSPEND and H_WAKEUP provide

hardware wake-up, a way of remote wake-up control for the HC without the need to

access the HC internal registers. H_WAKEUP is an external wake-up control input

pin for the HC. After the HC goes into the USBSuspend state, it can be woken up by

sending a HIGH level pulse to pin H_WAKEUP. This will turn on the HC’s internal

clock, and set bit 6, ClkReady, of the HcµPInterrupt register (24H to read, A4H to

write). Under the USBSuspend state, once pin H_WAKEUP goes HIGH, after 160 µs,

the internal clock will be up. If pin H_WAKEUP continues to be HIGH, then the

internal clock will be kept running, and the microprocessor can set the HC into

USBOperational state during this time. If H_WAKEUP goes LOW for more than

1.14 ms, the internal clock stops and the HC goes back into the USBSuspend state.

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Wake-up by pin CS_N (software wake-up): During the USBSuspend state, an

external microprocessor issues a chip select signal through pin CS_N to the

ISP1160. This method of access to the ISP1160 internal registers is a software

wake-up.

Wake-up by USB devices: For the USB bus resume, a USB device attached to the

root hub port issues a resume signal to the HC through the USB bus, switching the

HC from the USBSuspend state to the USBResume state. This will also set

bit ResumeDetected of the HcInterruptStatus register (03H to read, 83H to write).

No matter which method is used to wake up the HC from the USBSuspend state, the

corresponding interrupt bits must be enabled before the HC goes into the

USBSuspend state so that the microprocessor can receive the correct interrupt

request to wake up the HC.

10. HC registers

The HC contains a set of on-chip control registers. These registers can be read or

written by the Host Controller Driver (HCD). The Control and Status register sets,

Frame Counter register sets, and Root Hub register sets are grouped under the

category of HC Operational registers (32 bits). These operational registers are made

compatible to OpenHCI (Host Controller Interface) operational registers. This allows

the OpenHCI HCD to be easily ported to the ISP1160.

Reserved bits may be deﬁned in future releases of this speciﬁcation. To ensure

interoperability, the HCD must not assume that a reserved ﬁeld contains logic 0.

Furthermore, the HCD must always preserve the values of the reserved ﬁeld. When a

R/W register is modiﬁed, the HCD must ﬁrst read the register, modify the bits desired,

and then write the register with the reserved bits still containing the original value.

Alternatively, the HCD can maintain an in-memory copy of previously written values

that can be modiﬁed and then written to the HC register. When a ‘write to set’ or ‘clear

the register’ is performed, bits written to reserved ﬁelds must be logic 0.

As shown in Table 7, the addresses (the commands for reading registers) of these

32-bit operational registers are similar to the offsets deﬁned in the OHCI speciﬁcation

with the addresses being equal to offset divided by 4.

Table 7:

HC registers summary

Address (Hex) Register

Width Reference

Functionality

Read

00

Write

N/A

81

HcRevision

32

Section 10.1.1 on page 37

HC control and status registers

01

HcControl

Section 10.1.2 on page 38

Section 10.1.3 on page 39

Section 10.1.4 on page 40

Section 10.1.5 on page 42

Section 10.1.6 on page 43

Section 10.2.1 on page 44

Section 10.2.2 on page 45

Section 10.2.3 on page 46

Section 10.2.4 on page 47

02

82

HcCommandStatus

HcInterruptStatus

HcInterruptEnable

HcInterruptDisable

HcFmInterval

03

83

04

84

05

85

0D

0E

0F

11

8D

N/A

91

HC frame counter registers

HcFmRemaining

HcFmNumber

HcLSThreshold

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Table 7:

HC registers summary…continued

Address (Hex) Register

Width Reference

Functionality

Read

12

Write

92

HcRhDescriptorA

HcRhDescriptorB

HcRhStatus

32

16

Section 10.3.1 on page 48

HC Root Hub registers

13

93

Section 10.3.2 on page 50

Section 10.3.3 on page 51

Section 10.3.4 on page 53

Section 10.4.1 on page 57

Section 10.4.2 on page 58

Section 10.4.3 on page 59

Section 10.4.4 on page 59

Section 10.4.5 on page 61

Section 10.5.1 on page 62

Section 10.5.2 on page 63

Section 10.5.3 on page 63

Section 10.6.1 on page 64

Section 10.6.2 on page 64

Section 10.6.3 on page 65

Section 10.6.4 on page 65

Section 10.6.5 on page 66

Section 10.6.6 on page 66

Section 10.6.7 on page 67

14

94

15

95

HcRhPortStatus[1]

HcRhPortStatus[2]

HcHardwareConﬁguration

HcDMAConﬁguration

HcTransferCounter

HcµPInterrupt

16

96

20

A0

HC DMA and interrupt control

registers

21

A1

22

A2

24

A4

25

A5

HcµPInterruptEnable

HcChipID

27

N/A

A8

HC miscellaneous registers

28

HcScratch

N/A

2A

2B

2C

2D

2E

40

A9

HcSoftwareReset

HcITLBufferLength

HcATLBufferLength

HcBufferStatus

AA

AB

N/A

C0

C1

HC buffer RAM control registers

HcReadBackITL0Length

HcReadBackITL1Length

HcITLBufferPort

41

HcATLBufferPort

10.1 HC control and status registers

10.1.1 HcRevision register (R: 00H)

Code (Hex): 00 — read only

Table 8:

Bit

HcRevision register: bit allocation

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

23

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

0

R

0

R

0

R

0

R

0

R

0

R

0

R

9

0

R

8

15

14

13

12

11

10

Symbol

Reset

Access

0

R

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Bit

7

6

5

4

3

2

1

0

Symbol

Reset

Access

REV[7:0]

0

1

0

R

Table 9:

Bit

HcRevision register: bit description

Symbol

−

Description

31 to 8

7 to 0

reserved

REV[7:0]

Revision: This read-only ﬁeld contains the BCD representation of

the version of the HCI speciﬁcation that is implemented by this HC.

All HC implementations that are compliant with this speciﬁcation

will have a value of 10H.

10.1.2 HcControl register (R/W: 01H/81H)

The HcControl register deﬁnes the operating modes of the HC.

RemoteWakeupEnable (RWE) is modiﬁed only by the HCD.

Code (Hex): 01 — read

Code (Hex): 81 — write

Table 10: HcControl register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved

0

R/W

23

R/W

22

R/W

21

R/W

20

R/W

19

R/W

18

R/W

17

R/W

16

Symbol

Reset

Access

Bit

0

R/W

13

0

R/W

10

0

R/W

9

0

R/W

15

R/W

14

R/W

12

R/W

11

R/W

8

Symbol

Reset

Access

Bit

reserved

0

RWE

0

RWC

0

reserved

0

R/W

7

0

R/W

6

0

R/W

4

0

R/W

3

0

R/W

0

R/W

5

R/W

2

R/W

1

Symbol

Reset

Access

HCFS[1:0]

reserved

0

R/W

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Table 11: HcControl register: bit description

Bit

Symbol

-

Description

31 to 11

10

reserved

RWE

RemoteWakeupEnable: This bit is used by the HCD to enable or

disable the remote wake-up feature upon the detection of

upstream resume signaling. When this bit is set and the

ResumeDetected bit in HcInterruptStatus is set, a remote wake-up

is signaled to the host system. Setting this bit has no impact on the

generation of hardware interrupt.

9

RWC

RemoteWakeupConnected: This bit indicates whether the HC

supports remote wake-up signaling. If remote wake-up is

supported and used by the system, it is the responsibility of

system ﬁrmware to set this bit during POST. The HC clears the bit

upon a hardware reset but does not alter it upon a software reset.

Remote wake-up signaling of the host system is host-bus-speciﬁc

and is not described in this speciﬁcation.

8

-

reserved

7 to 6

HCFS

HostControllerFunctionalState for USB:

00B — USBReset

01B — USBResume

10B — USBOperational

11B — USBSuspend

A transition to USBOperational from another state causes

start-of-frame (SOF) generation to begin 1 ms later. The HCD may

determine whether the HC has begun sending SOFs by reading

the StartofFrame ﬁeld of HcInterruptStatus.

This ﬁeld can be changed by the HC only when in the

USBSuspend state. The HC can move from the USBSuspend

state to the USBResume state after detecting the resume signaling

from a downstream port.

The HC enters USBReset after a software reset and a hardware

reset. The latter also resets the Root Hub and asserts subsequent

reset signaling to downstream ports.

5 to 0

-

reserved

10.1.3 HcCommandStatus register (R/W: 02H/82H)

The HcCommandStatus register is used by the HC to receive commands issued by

the HCD, and it also reﬂects the HC’s current status. To the HCD, it appears to be a

‘write to set’ register. The HC must ensure that bits written as logic 1 become set in

the register while bits written as logic 0 remain unchanged in the register. The HCD

may issue multiple distinct commands to the HC without concern for corrupting

previously issued commands. The HCD has normal read access to all bits.

The SchedulingOverrunCount ﬁeld indicates the number of frames with which the HC

has detected the scheduling overrun error. This occurs when the Periodic list does

not complete before EOF. When a scheduling overrun error is detected, the HC

increments the counter and sets the SchedulingOverrun ﬁeld in the HcInterruptStatus

register.

Code (Hex): 02 — read

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Code (Hex): 82 — write

Table 12: HcCommandStatus register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

23

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

reserved

SOC[1:0]

0

R

0

R

0

R

0

R

0

R

0

R

0

R

9

0

R

8

15

14

13

12

11

10

Symbol

Reset

Access

Bit

reserved

0

R/W

7

0

R/W

6

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

Symbol

Reset

Access

reserved

0

HCR

0

R/W

Table 13: HcCommandStatus register: bit description

Bit

Symbol

-

Description

31 to 18

17 to 16

reserved

SOC[1:0]

SchedulingOverrunCount: The ﬁeld is incremented on each

scheduling overrun error. It is initialized to 00B and wraps around

at 11B. It will be incremented when a scheduling overrun is

detected even if SchedulingOverrun in HcInterruptStatus has

already been set. This is used by HCD to monitor any persistent

scheduling problems.

15 to 1

0

-

reserved

HCR

HostControllerReset: This bit is set by the HCD to initiate a

software reset of the HC. Regardless of the functional state of the

HC, it moves to the USBSuspend state in which most of the

operational registers are reset, except those stated otherwise, and

no Host bus accesses are allowed. This bit is cleared by the HC

upon the completion of the reset operation. The reset operation

must be completed within 10 µs. This bit, when set, does not

cause a reset to the Root Hub and no subsequent reset signaling

should be asserted to its downstream ports.

10.1.4 HcInterruptStatus register (R/W: 03H/83H)

This register provides the status of the events that cause hardware interrupts. When

an event occurs, the HC sets the corresponding bit in this register. When a bit is set, a

hardware interrupt is generated if the interrupt is enabled in the HcInterruptEnable

register (see Section 10.1.5) and bit MasterInterruptEnable is set. The HCD can clear

individual bits in this register by writing logic 1 to the bit positions to be cleared, but

cannot set any of these bits. Conversely, the HC can set bits in this register, but

cannot clear these bits.

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Code (Hex): 03 — read

Code (Hex): 83 — write

Table 14: HcInteruptStatus register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved

0

R/W

23

R/W

22

R/W

21

R/W

20

R/W

19

R/W

18

R/W

17

R/W

16

Symbol

Reset

Access

Bit

0

R/W

9

0

R/W

8

R/W

15

R/W

14

R/W

13

R/W

12

R/W

11

R/W

10

Symbol

Reset

Access

Bit

0

R/W

7

0

R/W

6

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

Symbol

Reset

Access

reserved

0

RHSC

0

FNO

0

UE

0

RD

0

SF

0

reserved

0

SO

0

R/W

Table 15: HcInterruptStatus register: bit description

Bit

Symbol

-

Description

31 to 7

6

reserved

RHSC

RootHubStatusChange: This bit is set when the content of

HcRhStatus or the content of any of HcRhPortStatus[1:2] has

changed.

5

4

FNO

UE

FrameNumberOverﬂow: This bit is set when the MSB of

HcFmNumber (bit 15) changes value.

UnrecoverableError: This bit is set when the HC detects a

system error not related to USB. The HC does not proceed with

any processing nor signaling before the system error has been

corrected. The HCD clears this bit after the HC has been reset.

OHCI: Always set to logic 0.

3

2

RD

SF

ResumeDetected: This bit is set when the HC detects that a

device on the USB is asserting resume signaling from a state of no

resume signaling. This bit is not set when HCD enters the

USBResume state.

StartOfFrame: At the start of each frame, this bit is set by the HC

and an SOF generated.

1

0

-

reserved

SO

SchedulingOverrun: This bit is set when USB schedules for

current frame overruns. A scheduling overrun will also cause the

SchedulingOverrunCount of HcCommandStatus to be

incremented.

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10.1.5 HcInterruptEnable register (R/W: 04H/84H)

Each enable bit in the HcInterruptEnable register corresponds to an associated

interrupt bit in the HcInterruptStatus register. The HcInterruptEnable register is used

to control which events generate a hardware interrupt. A hardware interrupt is

requested on the host bus when three conditions occur:

• A bit is set in the HcInterruptStatus register

• The corresponding bit in the HcInterruptEnable register is set

• Bit MasterInterruptEnable is set.

Writing a logic 1 to a bit in this register sets the corresponding bit, whereas writing a

logic 0 to a bit in this register leaves the corresponding bit unchanged. On a read, the

current value of this register is returned.

Code (Hex): 04 — read

Code (Hex): 84 — write

Table 16: HcInterruptEnable register: bit allocation

Bit

31

MIE

0

30

29

28

27

reserved

0

26

25

24

Symbol

Reset

Access

Bit

0

R/W

23

R/W

22

R/W

21

R/W

20

R/W

19

R/W

18

R/W

17

R/W

16

Symbol

Reset

Access

Bit

reserved

0

R/W

9

0

R/W

8

R/W

15

R/W

14

R/W

13

R/W

12

R/W

11

R/W

10

Symbol

Reset

Access

Bit

reserved

0

R/W

7

0

R/W

6

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

Symbol

Reset

Access

reserved

0

RHSC

0

FNO

0

UE

0

RD

0

SF

0

reserved

0

SO

0

R/W

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Table 17: HcInterruptEnable register: bit description

Bit

Symbol

Description

31

MIE

MasterInterruptEnable by the HCD: A logic 0 is ignored by the

HC. A logic 1 enables interrupt generation by events speciﬁed in

other bits of this register.

30 to 7

6

-

reserved

RHSC

0 — ignore

1 — enable interrupt generation due to Root Hub Status Change

5

4

3

2

FNO

UE

0 — ignore

1 — enable interrupt generation due to frame Number Overﬂow

0 — ignore

1 — enable interrupt generation due to Unrecoverable Error

RD

SF

0 — ignore

1 — enable interrupt generation due to Resume Detect

0 — ignore

1 — enable interrupt generation due to Start of frame

1

0

-

reserved

SO

0 — ignore

1 — enable interrupt generation due to Scheduling Overrun

10.1.6 HcInterruptDisable register (R/W: 05H/85H)

Each disable bit in the HcInterruptDisable register corresponds to an associated

interrupt bit in the HcInterruptStatus register. The HcInterruptDisable register is

coupled with the HcInterruptEnable register. Thus, writing a logic 1 to a bit in this

register clears the corresponding bit in the HcInterruptEnable register, whereas

writing a logic 0 to a bit in this register leaves the corresponding bit in the

HcInterruptEnable register unchanged. On a read, the current value of the

HcInterruptEnable register is returned.

Code (Hex): 05 — read

Code (Hex): 85 — write

Table 18: HcInterruptDisable register: bit allocation

Bit

31

MIE

0

30

29

28

27

reserved

0

26

25

24

Symbol

Reset

Access

Bit

0

R/W

23

R/W

22

R/W

21

R/W

20

R/W

19

R/W

18

R/W

17

R/W

16

Symbol

Reset

Access

Bit

reserved

0

R/W

9

0

R/W

8

R/W

15

R/W

14

R/W

13

R/W

12

R/W

11

R/W

10

Symbol

Reset

Access

reserved

0

R/W

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Bit

7

reserved

0

6

RHSC

0

5

4

UE

0

3

RD

0

2

SF

0

1

reserved

0

SO

0

Symbol

Reset

Access

FNO

0

R/W

Table 19: HcInterruptDisable register: bit description

Bit

Symbol

Description

31

MIE

A logic 0 is ignored by the HC. A logic 1 disables interrupt

generation due to events speciﬁed in other bits of this register. This

ﬁeld is set after a hardware or software reset.

30 to 7

6

-

reserved

RHSC

0 — ignore

1 — disable interrupt generation due to Root Hub Status Change

5

4

3

2

FNO

UE

0 — ignore

1 — disable interrupt generation due to Frame Number Overﬂow

0 — ignore

1 — disable interrupt generation due to Unrecoverable Error

RD

SF

0 — ignore

1 — disable interrupt generation due to Resume Detect

0 — ignore

1 — disable interrupt generation due to Start of Frame

1

0

-

reserved

SO

0 — ignore

1 — disable interrupt generation due to Scheduling Overrun

10.2 HC frame counter registers

10.2.1 HcFmInterval register (R/W: 0DH/8DH)

The HcFmInterval register contains a 14-bit value which indicates the bit time interval

in a frame (that is, between two consecutive SOFs), and a 15-bit value indicating the

full-speed maximum packet size that the HC may transmit or receive without causing

a scheduling overrun. The HCD may carry out minor adjustments on the

FrameInterval by writing a new value at each SOF. This allows the HC to synchronize

with an external clock resource and to adjust any unknown clock offset.

Code (Hex): 0D — read

Code (Hex): 8D — write

Table 20: HcFmInterval register: bit allocation

Bit

31

FIT

0

30

29

28

27

26

25

24

Symbol

Reset

Access

FSMPS[14:8]

0

R/W

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Bit

23

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

FSMPS[7:0]

0

R/W

9

0

R/W

8

R/W

15

R/W

14

R/W

13

R/W

12

R/W

11

R/W

10

Symbol

Reset

Access

Bit

reserved

FI[13:8]

0

R/W

7

0

R/W

6

1

R/W

5

0

R/W

4

1

R/W

3

1

R/W

2

1

R/W

1

0

R/W

0

Symbol

Reset

Access

FI[7:0]

1

0

1

R/W

Table 21: HcFmInterval register: bit description

Bit

Symbol

Description

31

FIT

FrameIntervalToggle: The HCD toggles this bit whenever it loads

a new value to FrameInterval.

30 to 16

FSMPS

[14:0]

FSLargestDataPacket: Speciﬁes a value which is loaded into the

Largest Data Packet Counter at the beginning of each frame. The

counter value represents the largest amount of data in bits which

can be sent or received by the HC in a single transaction at any

given time without causing a scheduling overrun. The ﬁeld value is

calculated by the HCD.

15 to 14

13 to 0

-

reserved

FI[13:0]

FrameInterval: Speciﬁes the interval between two consecutive

SOFs in bit times. The default value is 11999. The HCD must save

the current value of this ﬁeld before resetting the HC. Setting the

HostControllerReset ﬁeld of the HcCommandStatus register will

cause the HC to reset this ﬁeld to its default value. HCD may

choose to restore the saved value upon completing the reset

sequence.

10.2.2 HcFmRemaining register (R: 0EH)

The HcFmRemaining register is a 14-bit down counter showing the bit time remaining

in the current frame.

Code (Hex): 0E — read

Table 22: HcFmRemaining register: bit allocation

Bit

31

FRT

0

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved

0

R

0

R

0

R

0

R

0

R

0

R

0

R

23

22

21

20

19

18

17

16

Symbol

Reset

Access

reserved

0

R

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Bit

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

reserved

FR[13:8]

0

R

7

0

R

6

0

R

5

0

R

4

0

R

3

0

R

2

0

R

1

0

R

0

Symbol

Reset

Access

FR[7:0]

0

R

Table 23: HcFmRemaining register: bit description

Bit

Symbol

Description

31

FRT

FrameRemainingToggle: This bit is loaded from the

FrameIntervalToggle ﬁeld of the HcFmInterval register whenever

FrameRemaining reaches 0. This bit is used by the HCD for

synchronization between FrameInterval and FrameRemaining.

30 to 14

13 to 0

-

reserved

FR[13:0]

FrameRemaining: This counter is decremented at each bit time.

When it reaches zero, it is reset by loading the FrameInterval value

speciﬁed in the HcFmInterval register at the next bit time boundary.

When entering the USBOperational state, the HC reloads it with

the content of the FrameInterval part of the HcFmInterval register

and uses the updated value from the next SOF.

10.2.3 HcFmNumber register (R: 0FH)

The HcFmNumber register is a 16-bit counter. It provides a timing reference for

events happening in the HC and the HCD. The HCD may use the 16-bit value

speciﬁed in this register and generate a 32-bit frame number without requiring

frequent access to the register.

Code (Hex): 0F — read

Table 24: HcFmNumber register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved

FN[15:8]

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

23

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

0

R

0

R

0

R

0

R

0

R

0

R

0

R

9

0

R

8

15

14

13

12

11

10

Symbol

Reset

Access

0

R

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Bit

7

6

5

4

3

2

1

0

Symbol

Reset

Access

FN[7:0]

0

R

Table 25: HcFmNumber register: bit description

Bit

Symbol

−

Description

31 to 16

15 to 0

reserved

FN[15:0]

FrameNumber: This is incremented when HcFmRemaining is

reloaded. It rolls over to 0000H after FFFFH. When the

USBOperational state is entered, this will be incremented

automatically. The HC will set bit StartofFrame in the

HcInterruptStatus register.

10.2.4 HcLSThreshold register (R/W: 11H/91H)

The HcLSThreshold register contains an 11-bit value used by the HC to determine

whether to commit to the transfer of a maximum of 8-byte LS packet before EOF.

Neither the HC nor the HCD is allowed to change this value.

Code (Hex): 11 — read

Code (Hex): 91 — write

Table 26: HcLSThreshold register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved

0

R/W

23

R/W

22

R/W

21

R/W

20

R/W

19

R/W

18

R/W

17

R/W

16

Symbol

Reset

Access

Bit

0

R/W

13

0

R/W

8

R/W

15

R/W

14

R/W

12

R/W

11

R/W

10

R/W

9

Symbol

Reset

Access

Bit

reserved

0

LST[10:8]

0

R/W

7

0

R/W

6

0

R/W

4

0

R/W

3

1

R/W

2

1

R/W

1

0

R/W

0

R/W

5

Symbol

Reset

Access

LST[7:0]

0

1

0

1

0

R/W

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Table 27: HcLSThreshold register: bit description

Bit

Symbol

−

Description

31 to 11

10 to 0

reserved

LST[10:0]

LSThreshold: Contains a value that is compared to the

FrameRemaining ﬁeld before a low-speed transaction is initiated.

The transaction is started only if FrameRemaining ≥ this ﬁeld. The

value is calculated by the HCD, which considers transmission and

set-up overhead.

10.3 HC Root Hub registers

All registers included in this partition are dedicated to the USB Root Hub, which is an

integral part of the HC although it is functionally a separate entity. The Host Controller

Driver (HCD) emulates USBD accesses to the Root Hub via a register interface. The

HCD maintains many USB-deﬁned hub features that are not required to be supported

in hardware. For example, the Hub’s Device, Conﬁguration, Interface, and Endpoint

Descriptors, as well as some static ﬁelds of the Class Descriptor, are maintained only

in the HCD. The HCD also maintains and decodes the Root Hub’s device address as

well as other minor operations more suited for software than hardware.

The Root Hub registers were developed to match the bit organization and operation

of typical hubs found in the system.

Four 32-bit registers have been deﬁned:

• HcRhDescriptorA

• HcRhDescriptorB

• HcRhStatus

• HcRhPortStatus[1:NDP]

Each register is read and written as a DWORD. These registers are only written

during initialization to correspond with the system implementation. The

HcRhDescriptorA and HcRhDescriptorB registers are writeable regardless of the

HC’s USB states. HcRhStatus and HcRhPortStatus are writeable during the

USBOperational state only.

10.3.1 HcRhDescriptorA register (R/W: 12H/92H)

The HcRhDescriptorA register is the ﬁrst register of two describing the characteristics

of the Root Hub. Reset values are implementation-speciﬁc (IS). The descriptor length

(11), descriptor type and hub controller current (0) ﬁelds of the hub Class Descriptor

are emulated by the HCD. All other ﬁelds are located in registers HcRhDescriptorA

and HcRhDescriptorB.

Remark: IS denotes an implementation-speciﬁc reset value for that ﬁeld.

Code (Hex): 12 — read

Code (Hex): 92 — write

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Table 28: HcRhDescriptorA register: bit description

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

POTPGT[7:0]

IS

R/W

23

IS

R/W

22

IS

R/W

21

IS

R/W

20

IS

R/W

19

IS

R/W

18

IS

R/W

17

IS

R/W

16

Symbol

Reset

Access

Bit

reserved

0

R/W

12

0

R/W

10

DT

0

R/W

9

0

R/W

8

R/W

15

R/W

13

R/W

11

14

Symbol

Reset

Access

Bit

reserved

NOCP

IS

OCPM

IS

NPS

IS

PSM

IS

0

R

7

0

R

6

0

R

5

R/W

4

R/W

3

R

R/W

1

R/W

0

2

Symbol

Reset

Access

reserved

NDP[1:0]

0

IS

R

IS

R

Table 29: HcRhDescriptorA register: bit description

Bit

Symbol

Description

31 to 24

POTPGT

[7:0]

PowerOnToPowerGoodTime: This byte speciﬁes the duration

HCD has to wait before accessing a powered-on port of the Root

Hub. The unit of time is 2 ms. The duration is calculated as

POTPGT × 2 ms.

23 to 13

12

-

reserved

NOCP

NoOverCurrentProtection: This bit describes how the

overcurrent status for the Root Hub ports are reported. When this

bit is cleared, the OverCurrentProtectionMode ﬁeld speciﬁes

global or per-port reporting.

0 — overcurrent status is reported collectively for all downstream

ports

1 — no overcurrent reporting supported

11

OCPM

OverCurrentProtectionMode: This bit describes how the

overcurrent status for the Root Hub ports is reported. At reset, this

ﬁeld reﬂects the same mode as PowerSwitchingMode. This ﬁeld is

valid only if the NoOverCurrentProtection ﬁeld is cleared.

0 — overcurrent status is reported collectively for all downstream

ports

1 — overcurrent status is reported on a per-port basis. On

power-up, clear this bit and then set it to logic 1.

10

DT

DeviceType: This bit speciﬁes that the Root Hub is not a

compound device—it is not permitted. This ﬁeld should always

read/write 0.

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Table 29: HcRhDescriptorA register: bit description…continued

Bit

Symbol

Description

9

NPS

NoPowerSwitching: This bit is used to specify whether power

switching is supported or ports are always powered. When this bit

is cleared, bit PowerSwitchingMode speciﬁes global or per-port

switching.

0 — ports are power switched

1 — ports are always powered on when the HC is powered on

8

PSM

PowerSwitchingMode: This bit is used to specify how the power

switching of the Root Hub ports is controlled. This ﬁeld is valid only

if the NoPowerSwitching ﬁeld is cleared.

0 — all ports are powered at the same time

1 — each port is powered individually. This mode allows port

power to be controlled by either the global switch or per-port

switching. If bit PortPowerControlMask is set, the port responds to

only port power commands (Set/ClearPortPower). If the port mask

is cleared, then the port is controlled only by the global power

switch (Set/ClearGlobalPower).

7 to 2

1 to 0

-

reserved

NDP[1:0]

NumberDownstreamPorts: These bits specify the number of

downstream ports supported by the Root Hub. The maximum

number of ports supported by the ISP1160 is 2.

10.3.2 HcRhDescriptorB register (R/W: 13H/93H)

The HcRhDescriptorB register is the second register of two describing the

characteristics of the Root Hub. These ﬁelds are written during initialization to

correspond with the system implementation. Reset values are

implementation-speciﬁc (IS).

Code (Hex): 13 — read

Code (Hex): 93 — write

Table 30: HcRhDescriptorB register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved

N/A

R

N/A

R

N/A

R

N/A

R

N/A

R

N/A

R

N/A

R

23

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

reserved

N/A

R

PPCM[2:0]

N/A

R

N/A

R

N/A

R

N/A

R

IS

R/W

10

IS

R/W

9

IS

R/W

8

15

14

13

12

11

Symbol

Reset

Access

reserved

N/A

R

N/A

R

N/A

R

N/A

R

N/A

R

N/A

R

N/A

R

N/A

R

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Bit

7

6

5

reserved

N/A

4

3

2

1

DR[2:0]

IS

0

Symbol

Reset

Access

N/A

R

N/A

R

N/A

R

N/A

R

IS

R

R/W

Table 31: HcRhDescriptorB register: bit description

Bit

Symbol

Description

31 to 19

18 to 16

-

reserved

PPCM[2:0] PortPowerControlMask: Each bit indicates whether a port is

affected by a global power control command when

PowerSwitchingMode is set. When set, the port’s power state is

only affected by per-port power control (Set/ClearPortPower).

When cleared, the port is controlled by the global power switch

(Set/ClearGlobalPower). If the device is conﬁgured to global

switching mode (PowerSwitchingMode = 0), this ﬁeld is not valid.

Bit 0 — reserved

Bit 1 — Ganged-power mask on Port #1

Bit 2 — Ganged-power mask on Port #2

15 to 3

2 to 0

-

reserved

DR[2:0]

DeviceRemovable: Each bit is dedicated to a port of the Root

Hub. When cleared, the attached device is removable. When set,

the attached device is not removable.

Bit 0 — reserved

Bit 1 — Device attached to Port #1

Bit 2 — Device attached to Port #2

10.3.3 HcRhStatus register (R/W: 14H/94H)

The HcRhStatus register is divided into two parts. The lower word of a DWORD

represents the Hub Status ﬁeld and the upper word represents the Hub Status

Change ﬁeld. Reserved bits should always be written as logic 0.

Code (Hex): 14 — read

Code (Hex): 94 — write

Table 32: HcRhStatus register: bit allocation

Bit

31

CRWE

0

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved

0

R

0

R

0

R

0

R

0

R

0

R

0

R

W

23

22

21

20

19

18

17

16

Symbol

Reset

Access

reserved

OCIC

0

LPSC

0

R

R/W

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Bit

15

DRWE

0

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

reserved

0

R

6

0

R

5

0

R

4

0

R

3

0

R

2

0

R

0

R

R/W

7

1

0

Symbol

Reset

Access

reserved

OCI

0

LPS

0

R

R/W

Table 33: HcRhStatus register: bit description

Bit

Symbol

Description

31

CRWE

On write—ClearRemoteWakeupEnable: Writing a logic 1 clears

DeviceRemoveWakeupEnable. Writing a logic 0 has no effect.

30 to 18

17

-

reserved

OCIC

OverCurrentIndicatorChange: This bit is set by hardware when a

change has occurred to the OCI ﬁeld of this register. The HCD

clears this bit by writing a logic 1. Writing a logic 0 has no effect.

16

LPSC

On read—LocalPowerStatusChange: The Root Hub does not

support the local power status feature. Therefore, this bit is always

read as logic 0.

On write—SetGlobalPower: In global power mode

(PowerSwitchingMode = 0), this bit is written to logic 1 to turn on

power to all ports (clear PortPowerStatus). In per-port power

mode, it sets PortPowerStatus only on ports whose bit

PortPowerControlMask is not set. Writing a logic 0 has no effect.

15

DRWE

On read—DeviceRemoteWakeupEnable: This bit enables the bit

ConnectStatusChange as a resume event, causing a state

transition USBSuspend to USBResume and setting the

ResumeDetected interrupt.

0 — ConnectStatusChange is not a remote wake-up event

1 — ConnectStatusChange is a remote wake-up event

On write—SetRemoteWakeupEnable: Writing a logic 1 sets

DeviceRemoveWakeupEnable. Writing a logic 0 has no effect.

14 to 2

1

-

reserved

OCI

OverCurrentIndicator: This bit reports overcurrent conditions

when global reporting is implemented. When set, an overcurrent

condition exists. When clear, all power operations are normal. If

per-port overcurrent protection is implemented this bit is always

logic 0.

0

LPS

On read—LocalPowerStatus: The Root Hub does not support the

local power status feature. Therefore, this bit is always read as

logic 0.

On write—ClearGlobalPower: In global power mode

(PowerSwitchingMode = 0), this bit is written to logic 1 to turn off

power to all ports (clear PortPowerStatus). In per-port power

mode, it clears PortPowerStatus only on ports whose

bit PortPowerControlMask is not set. Writing a logic 0 has no

effect.

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10.3.4 HcRhPortStatus[1:2] (R/W [1]:15H/95H, [2]: 16H/96H)

The HcRhPortStatus[1:2] register is used to control and report port events on a

per-port basis. NumberDownstreamPorts represents the number of HcRhPortStatus

registers that are implemented in hardware. The lower word is used to reﬂect the port

status, whereas the upper word reﬂects the status change bits. Some status bits are

implemented with special write behavior. If a transaction (token through handshake)

is in progress when a write to change port status occurs, the resulting port status

change must be postponed until the transaction completes. Reserved bits should

always be written logic 0.

Code (Hex): [1] = 15, [2] = 16 — read

Code (Hex): [1] = 95, [2] = 96 — write

Table 34: HcRhPortStatus[1:2] register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved

0

R/W

22

0

R/W

19

0

R/W

18

0

R/W

17

0

R/W

16

R/W

23

R/W

21

R/W

20

Symbol

Reset

Access

Bit

reserved

0

PRSC

0

OCIC

0

PSSC

0

PESC

0

CSC

0

R/W

15

R/W

14

R/W

13

R/W

12

R/W

11

R/W

10

R/W

9

R/W

8

Symbol

Reset

Access

Bit

reserved

LSDA

0

PPS

0

R/W

7

0

R/W

6

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

2

R/W

1

R/W

0

Symbol

Reset

Access

reserved

0

PRS

0

POCI

0

PSS

0

PES

0

CCS

0

R/W

Table 35: HcRshPortStatus[1:2] register: bit description

Bit

Symbol

-

Description

31 to 21

20

reserved

PRSC

PortResetStatusChange: This bit is set at the end of the 10 ms

port reset signal. The HCD writes a logic 1 to clear this bit. Writing

a logic 0 has no effect.

0 — port reset is not complete

1 — port reset is complete

19

OCIC

PortOverCurrentIndicatorChange: This bit is valid only if

overcurrent conditions are reported on a per-port basis. This bit is

set when Root Hub changes the PortOverCurrentIndicator bit. The

HCD writes a logic 1 to clear this bit. Writing a logic 0 has no

effect.

0 — no change in PortOverCurrentIndicator

1 — PortOverCurrentIndicator has changed

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Table 35: HcRshPortStatus[1:2] register: bit description…continued

Bit

Symbol

Description

18

PSSC

PortSuspendStatusChange: This bit is set when the full resume

sequence has been completed. This sequence includes the 20 s

resume pulse, LS EOP, and 3 ms resynchronization delay. The

HCD writes a logic 1 to clear this bit. Writing a logic 0 has no

effect. This bit is also cleared when ResetStatusChange is set.

0 — resume is not completed

1 — resume is completed

17

16

PESC

PortEnableStatusChange: This bit is set when hardware events

cause the PortEnableStatus bit to be cleared. Changes from HCD

writes do not set this bit. The HCD writes a logic 1 to clear this bit.

Writing a logic 0 has no effect.

0 — no change in PortEnableStatus

1 — change in PortEnableStatus

CSC

ConnectStatusChange: This bit is set whenever a connect or

disconnect event occurs. The HCD writes a logic 1 to clear this bit.

Writing a logic 0 has no effect. If CurrentConnectStatus is cleared

when a SetPortReset, SetPortEnable, or SetPortSuspend write

occurs, this bit is set to force the driver to reevaluate the

connection status since these writes should not occur if the port is

disconnected.

0 — no change in CurrentConnectStatus

1 — change in CurrentConnectStatus

Remark: If bit DeviceRemovable[NDP] is set, this bit is set only

after a Root Hub reset to inform the system that the device is

attached.

15 to 10

9

-

reserved

LSDA

On read—LowSpeedDeviceAttached: This bit indicates the

speed of the device connected to this port. When set, a low-speed

device is connected to this port. When clear, a full-speed device is

connected to this port. This ﬁeld is valid only when the

CurrentConnectStatus is set.

0 — full-speed device attached

1 — low-speed device attached

On write—ClearPortPower: The HCD clears bit PortPowerStatus

by writing a logic 1 to this bit. Writing a logic 0 has no effect.

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Table 35: HcRshPortStatus[1:2] register: bit description…continued

Bit

Symbol

Description

8

PPS

On read—PortPowerStatus: This bit reﬂects the port power

status, regardless of the type of power switching implemented.

This bit is cleared if an overcurrent condition is detected.

The HCD sets this bit by writing SetPortPower or SetGlobalPower.

The HCD clears this bit by writing ClearPortPower or

ClearGlobalPower. Which power control switches are enabled is

determined by PowerSwitchingMode.

In the global switching mode (PowerSwitchingMode = 0), only

Set/ClearGlobalPower controls this bit. In per-port power switching

(PowerSwitchingMode = 1), if bit PortPowerControlMask[NDP] for

the port is set, only Set/ClearPortPower commands are enabled. If

the mask is not set, only Set/ClearGlobalPower commands are

enabled.

When port power is disabled, CurrentConnectStatus,

PortEnableStatus, PortSuspendStatus, and PortResetStatus

should be reset.

0 — port power is off

1 — port power is on

On write—SetPortPower: The HCD writes a logic 1 to set

bit PortPowerStatus. Writing a logic 0 has no effect.

Remark: This bit always reads logic 1 if power switching is not

supported.

7 to 5

4

-

reserved

PRS

On read—PortResetStatus: When this bit is set by a write to

SetPortReset, port reset signaling is asserted. When reset is

completed, this bit is cleared when PortResetStatusChange is set.

This bit cannot be set if CurrentConnectStatus is cleared.

0 — port reset signal is not active

1 — port reset signal is active

On write—SetPortReset: The HCD sets the port reset signaling

by writing a logic 1 to this bit. Writing a logic 0 has no effect. If

CurrentConnectStatus is cleared, this write does not set

PortResetStatus but instead sets ConnectStatusChange. This

informs the driver that it attempted to reset a disconnected port.

3

POCI

On read—PortOverCurrentIndicator: This bit is valid only when

the Root Hub is conﬁgured in such a way that overcurrent

conditions are reported on a per-port basis. If per-port overcurrent

reporting is not supported, this bit is set to logic 0. If cleared, all

power operations are normal for this port. If set, an overcurrent

condition exists on this port. This bit always reﬂects the overcurrent

input signal.

0 — no overcurrent condition

1 — overcurrent condition detected

(write) ClearSuspendStatus: The HCD writes a logic 1 to initiate

a resume. Writing a logic 0 has no effect. A resume is initiated only

if PortSuspendStatus is set.

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Table 35: HcRshPortStatus[1:2] register: bit description…continued

Bit

Symbol

Description

2

PSS

On read—PortSuspendStatus: This bit indicates whether the port

is suspended or in the resume sequence. It is set by a

SetSuspendState write and cleared when

PortSuspendStatusChange is set at the end of the resume

interval. This bit cannot be set if CurrentConnectStatus is cleared.

This bit is also cleared when PortResetStatusChange is set at the

end of the port reset or when the HC is placed in the USBResume

state. If an upstream resume is in progress, it should propagate to

the HC.

0 — port is not suspended

1 — port is suspended

On write—SetPortSuspend: The HCD sets

bit PortSuspendStatus by writing a logic 1 to this bit. Writing a

logic 0 has no effect. If CurrentConnectStatus is cleared, this write

does not set PortSuspendStatus; instead it sets

ConnectStatusChange. This informs the driver that it attempted to

suspend a disconnected port.

1

PES

On read—PortEnableStatus: This bit indicates whether the port is

enabled or disabled. The Root Hub may clear this bit when an

overcurrent condition, disconnect event, switched-off power, or

operational bus error such as babble is detected. This change also

causes PortEnabledStatusChange to be set. The HCD sets this bit

by writing SetPortEnable and clears it by writing ClearPortEnable.

This bit cannot be set when CurrentConnectStatus is cleared. This

bit is also set at the completion of a port reset when

ResetStatusChange is set or port is suspended when

SuspendStatusChange is set.

0 — port is disabled

1 — port is enabled

On write—SetPortEnable: The HCD sets PortEnableStatus by

writing a logic 1. Writing a logic 0 has no effect. If

CurrentConnectStatus is cleared, this write does not set

PortEnableStatus, but instead sets ConnectStatusChange. This

informs the driver that it attempted to enable a disconnected port.

0

CCS

On read—CurrentConnectStatus: This bit reﬂects the current

state of the downstream port.

0 — no device connected

1 — device connected

On write—ClearPortEnable: The HCD writes a logic 1 to this bit to

clear bit PortEnableStatus. Writing a logic 0 has no effect.

CurrentConnectStatus is not affected by any write.

Remark: This bit always reads logic 1 when the attached device is

nonremovable (DeviceRemoveable[NDP]).

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10.4 HC DMA and interrupt control registers

10.4.1 HcHardwareConﬁguration register (R/W: 20H/A0H)

Code (Hex): 20 — read

Code (Hex): A0 — write

Table 36: HcHardwareConﬁguration register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

reserved

2_Down

stream

Suspend

ClkNotStop

AnalogOC

Enable

reserved DACKMode

Port15K

resistorsel

Reset

Access

Bit

0

R/W

7

0

R/W

6

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

Symbol

EOTInput

Polarity

DACKInput

Polarity

DREQ

Output

Polarity

DataBusWidth[1:0]

Interrupt

Output

Polarity

Interrupt

PinTrigger

InterruptPin

Enable

Reset

0

1

0

1

0

Access

R/W

Table 37: HcHardwareConﬁguration register: bit description

Bit

Symbol

Description

15 to 13 -

reserved

12

11

10

2_DownstreamPort15K 0 — use external 15 kΩ resistors for downstream ports

resistorsel

1 — use built-in resistors for downstream ports

SuspendClkNotStop

AnalogOCEnable

0 — clock can be stopped

1 — clock can not be stopped

0 — use external OC detection; digital input

1 — use on-chip OC detection; analog input

reserved

9

8

-

DACKMode

0 — normal operation; pin DACK_N is used with read and

write signals

1 — reserved

7

EOTInputPolarity

0 — active LOW

1 — active HIGH

6

DACKInputPolarity

DREQOutputPolarity

DataBusWidth[1:0]

0 — active LOW

1 — reserved

5

0 — active LOW

1 — active HIGH

4 to 3

These bits are ﬁxed at logic 0 and logic 1 for the ISP1160.

01 — 16 bits

Others — reserved

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Table 37: HcHardwareConﬁguration register: bit description…continued

Bit

Symbol

Description

2

InterruptOutputPolarity 0 — active LOW

1 — active HIGH

1

0

InterruptPinTrigger

0 — interrupt is level-triggered

1 — interrupt is edge-triggered

InterruptPinEnable

This bit is used as pin INT’s master interrupt enable and

should be used together with register

HcµPInterruptEnable to enable pin INT.

0 — pin INT is disabled

1 — pin INT is enabled

10.4.2 HcDMAConﬁguration register (R/W: 21H/A1H)

Code (Hex): 21 — read

Code (Hex): A1 — write

Table 38: HcDMAConﬁguration register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

reserved

0

R/W

0

R/W

6

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

2

0

R/W

0

R/W

7

1

0

Symbol

reserved

BurstLen[1:0]

DMA

Enable

reserved

DMA

Counter

Select

ITL_ATL_

DataSelect WriteSelect

DMARead

Reset

0

Access

R/W

Table 39: HcDMAConﬁguration register: bit description

Bit

Symbol

Description

15 to 7

6 to 5

-

reserved

BurstLen[1:0] 00 — single-cycle burst DMA

01 — 4-cycle burst DMA

10 — 8-cycle burst DMA

11 — reserved

4

3

DMAEnable

-

0 — DMA is terminated

1 — DMA is enabled

This bit will be reset to logic 0 when DMA transfer is completed.

reserved

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Table 39: HcDMAConﬁguration register: bit description…continued

Bit

Symbol

Description

2

DMACounter 0 — DMA counter not used. External EOT must be used

Select

1 — enables the DMA counter for DMA transfer.

HcTransferCounter register must be ﬁlled with non-zero values for

DREQ to be raised after bit DMA Enable is set.

1

0

ITL_ATL_

DataSelect

0 — ITL buffer RAM selected for ITL data

1 — ATL buffer RAM selected for ATL data

0 — read from the HC FIFO buffer RAM

1 — write to the HC FIFO buffer RAM

DMARead

WriteSelect

10.4.3 HcTransferCounter register (R/W: 22H/A2H)

This register holds the number of bytes of a PIO or DMA transfer. For a PIO transfer,

the number of bytes being read or written to the Isochronous Transfer List (ITL) or

Acknowledged Transfer List (ATL) buffer RAM must be written into this register. For a

DMA transfer, the number of bytes must be written into this register as well. However,

for this counter to be read into the DMA counter, the HCD must set bit 2

(DMACounterSelect) of the HcDMAConﬁguration register. The counter value for ATL

must not be greater than 1000H, and for ITL it must not be greater than 800H. When

the byte count of the data transfer reaches this value, the HC will generate an internal

EOT signal to set bit 2 (AllEOTInterrupt) of the HcµPInterrupt register, and also

update the HcBufferStatus register.

Code (Hex): 22 — read

Code (Hex): A2 — write

Table 40: HcTransferCounter register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

Counter value

0

R/W

7

0

R/W

6

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

Symbol

Reset

Access

Counter value

0

R/W

Table 41: HcTransferCounter register: bit description

Bit

Symbol

Description

The number of data bytes to be read to or written from RAM.

15 to 0

Counter

value

10.4.4 HcµPInterrupt register (R/W: 24H/A4H)

All the bits in this register will be active on power-on reset. However, none of the

active bits will cause an interrupt on the interrupt pin (INT) unless they are set by the

respective bits in the HcµPInterruptEnable register, and together with bit 0 of the

HcHardwareConﬁguration register.

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After this register (24H to read) is read, the bits that are active will not be reset, until

logic 1 is written to the bits in this register (A4H to write) to clear it. To clear all the

enabled bits in this register, the HCD must write FFH to this register.

Code (Hex): 24 — read

Code (Hex): A4 — write

Table 42: HcµPInterrupt register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

reserved

0

R/W

0

R/W

0

R/W

5

0

R/W

4

0

R/W

0

R/W

2

0

R/W

1

0

R/W

7

6

3

0

Symbol

reserved

ClkReady

HC

OPR_Reg

reserved

AIIEOT

ATLInt

SOFITLInt

Suspended

Interrupt

Reset

0

Access

R/W

Table 43: HcµPInterrupt register: bit description

Bit

Symbol

-

Description

reserved

15 to 7

6

ClkReady

0 — no event

1 — clock is ready. After a wake-up is sent, there is a wait for clock

ready. Maximum is 1 ms, and typical is 160 µs.

5

HC

0 — no event

Suspended

1 — the HC has been suspended and no USB activity is sent from

the microprocessor for each ms. When the microprocessor wants

to suspend the HC, the microprocessor must write to the

HcControl register. And when all downstream devices are

suspended, then the HC stops sending SOF; the HC is suspended

by having the HcControl register written into.

4

3

OPR_Reg 0 — no event

1 — there are interrupts from HC side. Need to read HcControl

and HcInterrupt registers to detect type of interrupt on the HC (if

the HC requires the operational register to be updated).

-

reserved

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Table 43: HcµPInterrupt register: bit description…continued

Bit

Symbol

Description

2

AllEOT

0 — no event

Interrupt

1 — implies that data transfer has been completed via PIO transfer

or DMA transfer. Occurrence of internal or external EOT will set

this bit.

1

0

ATLInt

0 — no event

1 — implies that the microprocessor must read ATL data from the

HC. This requires that the HcBufferStatus register must ﬁrst be

read. The time for this interrupt depends on the number of clocks

bit set for USB activities in each ms.

SOFITLInt 0 — no event

1 — implies that SOF indicates the 1 ms mark. The ITL buffer that

the HC has handled must be read. To know the ITL buffer status,

the HcBufferStatus register must ﬁrst be read. This is for the

microprocessor to get ISO data to or from the HC. For more

information, see the 6th paragraph in Section 9.5.

10.4.5 HcµPInterruptEnable register (R/W: 25H/A5H)

The bits 6:0 in this register are the same as those in the HcµPInterrupt register. They

are used together with bit 0 of the HcHardwareConﬁguration register to enable or

disable the bits in the HcµPInterrupt register.

On power-on, all bits in this register are masked with logic 0. This means no interrupt

request output on the interrupt pin INT can be generated.

When the bit is set to logic 1, the interrupt for the bit is not masked but enabled.

Code (Hex): 25 — read

Code (Hex): A5 — write

Table 44: HcµPInterruptEnable register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

reserved

0

R/W

0

R/W

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

7

6

Symbol

reserved

ClkReady

HC

OPR

reserved

EOT

ATL

SOF

Suspended

Enable

Interrupt

Enable

Interrupt

Enable

Interrupt

Enable

Interrupt

Enable

Reset

0

Access

R/W

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Table 45: HcµPInterruptEnable register: bit description

Bit

Symbol

-

Description

15 to 7

6

reserved

ClkReady

0 — power-up value

1 — enables ClkReady interrupt

0 — power-up value

5

HC

Suspended

Enable

1 — enables HC suspended interrupt. When the microprocessor

wants to suspend the HC, the microprocessor must write to the

HcControl register. And when all downstream devices are

suspended, then the HC stops sending SOF; the HC is suspended

by having the HcControl register written into.

4

OPR

0 — power-up value

Interrupt

Enable

1 — enables the 32-bit operational register’s interrupt (if the HC

requires the operational register to be updated)

3

2

-

reserved

EOT

0 — power-up value

Interrupt

Enable

1 — enables the EOT interrupt which indicates an end of a

read/write transfer

1

0

ATL

Interrupt

Enable

0 — power-up value

1 — enables ATL interrupt. The time for this interrupt depends on

the number of clock bits set for USB activities in each ms.

SOF

0 — power-up value

Interrupt

Enable

1 — enables the interrupt bit due to SOF (for the microprocessor

DMA to get ISO data from the HC by ﬁrst accessing the

HcDMAConﬁguration register)

10.5 HC miscellaneous registers

10.5.1 HcChipID register (R: 27H)

Read this register to get the ID of the ISP1160 silicon chip. The higher byte stands for

the product name. The lower byte indicates the revision number of the product

including engineering samples.

Code (Hex): 27 — read

Table 46: HcChipID register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

ChipID[15:8]

0

R

7

1

R

6

1

R

5

0

R

4

0

R

3

0

R

2

0

R

1

R

0

Symbol

Reset

Access

ChipID[7:0]

0

1

0

1

X^[1]

R

[1] X is logic 0 for ISP1160BD and ISP1160BM; X is logic 1 for ISP1160BD/01 and ISP1160BM/01.

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Table 47: HcChipID register: bit description

Bit

Symbol

Description

15 to 0

ChipID[15:0]

ISP1160’s chip ID

10.5.2 HcScratch register (R/W: 28H/A8H)

This register is for the HCD to save and restore values when required.

Code (Hex): 28 — read

Code (Hex): A8 — write

Table 48: HcScratch register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

Scratch[15:8]

0

R/W

7

0

R/W

6

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

Symbol

Reset

Access

Scratch[7:0]

0

R/W

Table 49: HcScratch register: bit description

Bit

Symbol

Description

15 to 0

Scratch[15:0] Scratch register value

10.5.3 HcSoftwareReset register (W: A9H)

This register provides a means for software reset of the HC. To reset the HC, the HCD

must write a reset value of F6H to this register. Upon receiving the reset value, the

HC resets all the registers except its buffer memory.

Code (Hex): A9 — write

Table 50: HcSoftwareReset register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

Reset[15:8]

0

W

7

0

W

6

0

W

5

0

W

4

0

W

3

0

W

2

0

W

1

0

W

0

Symbol

Reset

Access

Reset[7:0]

0

W

Table 51: HcSoftwareReset register: bit description

Bit

Symbol

Description

15 to 0

Reset[15:0] Writing a reset value of F6H will cause the HC to reset all the

registers except its buffer memory.

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10.6 HC buffer RAM control registers

10.6.1 HcITLBufferLength register (R/W: 2AH/AAH)

Write to this register to assign the ITL buffer size in bytes: ITL0 and ITL1 are assigned

the same value. For example, if HcITLBufferLength register is set to 2 kbytes, then

ITL0 and ITL1 would be allocated 2 kbytes each.

Must follow the formula:

ATL buffer length + 2 × (ITL buffer size) ≤ 1000H (that is, 4 kbytes)

where: ITL buffer size = ITL0 buffer length = ITL1 buffer length.

Code (Hex): 2A — read

Code (Hex): AA — write

Table 52: HcITLBufferLength register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

ITLBufferLength[15:8]

0

R/W

7

0

R/W

6

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

Symbol

Reset

Access

ITLBufferLength[7:0]

0

R/W

Table 53: HcITLBufferLength register: bit description

Bit Symbol Description

15 to 0 ITLBufferLength[15:0] Assign ITL buffer length

10.6.2 HcATLBufferLength register (R/W: 2BH/ABH)

Write to this register to assign ATL buffer size.

Code (Hex): 2B — read

Code (Hex): AB — write

Remark: The maximum total RAM size is 1000H (4096 in decimal) bytes. That

means ITL0 (length) + ITL1 (length) + ATL (length) ≤ 1000H bytes. For example, if

ATL buffer length has been set to be 800H, then the maximum ITL buffer length can

only be set as 400H.

Table 54: HcATLBufferLength register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Reset

Access

ATLBufferLength[15:8]

0

R/W

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Bit

7

6

5

4

3

2

1

0

Symbol

Reset

Access

ATLBufferLength[7:0]

0

R/W

Table 55: HcATLBufferLength register: bit description

Bit Symbol Description

15 to 0 ATLBufferLength[15:0] Assign ATL buffer length

10.6.3 HcBufferStatus register (R: 2CH)

Code (Hex): 2C — read

Table 56: HcBufferStatus register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

reserved

0

R

7

0

R

6

0

R

5

0

R

4

0

R

3

0

R

2

0

R

1

0

R

0

Symbol

reserved

ATLBuffer

Done

ITL1Buffer ITL0Buffer

ATLBuffer

Full

ITL1Buffer ITL0Buffer

Done

Full

Reset

0

Access

R

Table 57: HcBufferStatus register: bit description

Bit

Symbol

Description

15 to 6

5

-

reserved

ATLBuffer

Done

0 — ATL Buffer not read by HC yet

1 — ATL Buffer read by HC

4

3

2

1

0

ITL1Buffer 0 — ITL1 Buffer not read by HC yet

Done

1 — ITL1 Buffer read by HC

ITL0Buffer 0 — 1TL0 Buffer not read by HC yet

Done

1 — 1TL0 Buffer read by HC

ATLBuffer

Full

0 — ATL Buffer is empty

1 — ATL Buffer is full

ITL1Buffer 0 — 1TL1 Buffer is empty

Full

1 — 1TL1 Buffer is full

ITL0Buffer 0 — ITL0 Buffer is empty

Full

1 — ITL0 Buffer is full

10.6.4 HcReadBackITL0Length register (R: 2DH)

This register’s value stands for the current number of data bytes inside an ITL0 buffer

to be read back by the microprocessor. The HCD must set the HcTransferCounter

equivalent to this value before reading back the ITL0 buffer RAM.

Code (Hex): 2D — read

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Table 58: HcReadBackITL0Length register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

RdITL0BufferLength[15:8]

0

R

7

0

R

6

0

R

5

0

R

4

0

R

3

0

R

2

0

R

1

0

R

0

Symbol

Reset

Access

RdITL0BufferLength[7:0]

0

R

Table 59: HcReadBackITL0Length register: bit description

Bit Symbol Description

15 to 0 RdITL0BufferLength[15:0] The number of bytes for ITL0 data to be read back by

the microprocessor

10.6.5 HcReadBackITL1Length register (R: 2EH)

This register’s value stands for the current number of data bytes inside the ITL1 buffer

to be read back by the microprocessor. The HCD must set the HcTransferCounter

equivalent to this value before reading back the ITL1 buffer RAM.

Code (Hex): 2E — read

Table 60: HcReadBackITL1Length register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

RdITL1BufferLength[15:8]

0

R

7

0

R

6

0

R

5

0

R

4

0

R

3

0

R

2

0

R

1

0

R

0

Symbol

Reset

Access

RdITL1BufferLength[7:0]

0

R

Table 61: HcReadBackITL1Length register: bit description

Bit Symbol Description

15 to 0 RdITL1BufferLength[15:0] The number of bytes for ITL1 data to be read back by

the microprocessor.

10.6.6 HcITLBufferPort register (R/W: 40H/C0H)

This is the ITL buffer RAM read/write port. The bits 15:8 contain the data byte that

comes from the ITL buffer RAM’s even address. The bits 7:0 contain the data byte

that comes from the ITL buffer RAM’s odd address.

Code (Hex): 40 — read

Code (Hex): C0 — write

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Table 62: HcITLBufferPort register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

DataWord[15:8]

0

R/W

7

0

R/W

6

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

Symbol

Reset

Access

DataWord[7:0]

0

R/W

Table 63: HcITLBufferPort register: bit description

Bit Symbol Description

15 to 0 DataWord[15:0] Read/write ITL buffer RAM’s two data bytes.

The HCD must set the byte count into the HcTransferCounter register and check the

HcBufferStatus register before reading from or writing to the buffer. The HCD must

write the command (40H to read, C0H to write) once only, and then read or write both

bytes of the data word. After every read/write, the pointer of ITL buffer RAM will be

automatically increased by two to point to the next data word until it reaches the value

of the HcTransferCounter register; otherwise, an internal EOT signal is not generated

to set bit 2 (AllEOTInterrupt) of the HcµPInterrupt register and update the

HcBufferStatus register.

The HCD must take care of the fact that the internal buffer RAM is organized in bytes.

The HCD must write the byte count into the HcTransferCounter register, but the HCD

reads or writes the buffer RAM by 16 bits (by 1 word).

10.6.7 HcATLBufferPort register (R/W: 41H/C1H)

This is the ATL buffer RAM read/write port. Bits 15 to 8 contain the data byte that

comes from the Acknowledged Transfer List (ATL) buffer RAM’s odd address.

Bits 7 to 0 contain the data byte that comes from the ATL buffer RAM’s even address.

Code (Hex): 41 — read

Code (Hex): C1 — write

Table 64: HcATLBufferPort register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

DataWord[15:8]

0

R/W

7

0

R/W

6

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

Symbol

Reset

Access

DataWord[7:0]

0

R/W

Table 65: HcATLBufferPort register: bit description

Bit Symbol Description

15 to 0 DataWord[15:0] Read/write ATL buffer RAM’s two data bytes.

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The HCD must set the byte count into the HcTransferCounter register and check the

HcBufferStatus register before reading from or writing to the buffer. The HCD must

write the command (41H to read, C1H to write) once only, and then read or write both

bytes of the data word. After every read/write, the pointer of ATL buffer RAM will be

automatically increased by two to point to the next data word until it reaches the value

of the HcTransferCounter register; otherwise, an internal EOT signal is not generated

to set bit 2 (AllEOTInterrupt) of the HcµPInterrupt register and update the

HcBufferStatus register.

The HCD must take care of the difference: the internal buffer RAM is organized in

bytes, so the HCD must write the byte count into the HcTransferCounter register, but

the HCD reads or writes the buffer RAM by 16 bits (by 1 data word).

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11. Power supply

The ISP1160 can operate at either 5 V or 3.3 V.

When using 5 V as the ISP1160’s power supply input, only V_CC(pin 56) can be

connected to the 5 V power supply. An application with a 5 V power supply input is

shown in Figure 29. The ISP1160 has an internal DC/DC regulator to provide 3.3 V

for its internal core. This internal 3.3 V can also be obtained from V_REG(3V3)(pin 58).

When using 3.3 V as the power supply input, the internal DC/DC regulator will be

bypassed. All four power supply pins (V_CC, V_REG(3V3), V_HOLD1and V_HOLD2) can be

used as power supply input.

It is recommended that you connect all four power supply pins to the 3.3 V power

supply, as shown in Figure 30. If, however, you have board space (routing area)

constraints, you must connect at least V_CCand V_REG(3V3)to the 3.3 V power supply.

For both 3.3 V and 5 V operation, all four power supply pins should be connected to a

decoupling capacitor.

+3.3 V

ISP1160

+5 V

ISP1160

V

CC

V

REG(3V3)

V

HOLD1

V

HOLD2

GND

004aaa068

004aaa069

Fig 29. Using a 5 V supply.

Fig 30. Using a 3.3 V supply.

12. Crystal oscillator

The ISP1160 has a crystal oscillator designed for a 6 MHz parallel-resonant crystal

(fundamental). A typical circuit is shown in Figure 31. Alternatively, an external clock

signal of 6 MHz can be applied to input XTAL1, while leaving output XTAL2 open. See

Figure 32. The 6 MHz oscillator frequency is multiplied to 48 MHz by an internal PLL.

V

CC

6 MHz

ISP1160

Out

18 pF

6 MHz

18 pF

OSC

XTAL2

n.c.

XTAL2

XTAL1

004aaa071

004aaa070

Fig 31. Oscillator circuit with external crystal.

Fig 32. Oscillator circuit using external oscillator.

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13. Power-on reset (POR)

When V_CCis directly connected to the RESET_N pin, the internal pulse width (t_PORP

)

will be typically (600 ns to 1000 ns) + X, when V_CCis 3.3 V. The time X depends on

how fast V_CCis rising with respect to V_trip(2.03 V). The time X is decided by the

external power supply circuit.

To give a better view of the functionality, Figure 33 shows a possible curve of

V_CC(POR)with dips at t2-t3 and t4-t5. If the dip at t4-t5 is too short (that is, <11 µs), the

internal POR pulse will not react and will remain LOW. The internal POR starts with a

1 at t0. At t1, the detector will see the passing of the trip level and a delay element will

add another t_PORPbefore it drops to 0.

The internal POR pulse will be generated whenever V_CC(POR)drops below V_tripfor

more than 11 µs.

Even if V_CCis 5.0 V, V_tripstill remains at 2.03 V. This is because the 5 V tolerant pads

and on-chip voltage regulator ensure that 3.3 V is going to the internal POR circuitry

by clipping the voltage above 3.3 V.

V

CC(POR)

V

trip

t1

t3

t0

t4 t5

t2

(1)

PORP

t

PORP

004aaa389

(1) PORP = power-on reset pulse.

Fig 33. Internal POR timing.

The RESET_N pin can be either connected to V_CC(using the internal POR circuit) or

externally controlled (by the microprocessor, ASIC, and so on). Figure 34 shows the

availability of the clock with respect to the external POR.

POWER-ON RESET

EXTERNAL CLOCK

004aaa365

A

Stable external clock is available at A.

Fig 34. Clock with respect to the external POR.

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14. Limiting values

Table 66: Absolute maximum ratings

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_CC(5V0)

V_CC(3V3)

V_I

Parameter

Conditions

Min

−0.5

-

Max

+6.0

+4.6

+6.0

100

Unit

V

supply voltage to pin V_CC

supply voltage to pin V_REG(3V3)

input voltage

V

I_lu

latch-up current

V_I< 0 or V_I> V_CC

mA

V

[1]

V_esd

electrostatic discharge voltage

storage temperature

I_LI< 1 µA

−2000

−60

+2000

+150

T_stg

°C

[1] Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ resistor (Human Body Model).

15. Recommended operating conditions

Table 67: Recommended operating conditions

Symbol Parameter

Conditions

Min

4.0

3.0

0

Typ

5.0

3.3

V_CC

-

Max

Unit

V

V_CC

supply voltage

with internal regulator

internal regulator bypass

5.5

3.6

5.5

3.6

V_CC

+85

V

[1]

V_I

input voltage

V

V_I(AI/O)

V_O(od)

T_amb

input voltage on analog I/O pins D+ and D−

open-drain output pull-up voltage

ambient temperature

0

V

0

-

V

−40

-

°C

[1] Maximum value is 5 V tolerant.

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16. Static characteristics

Table 68: Static characteristics; supply pins

V_CC= 3.0 V to 3.6 V or 4.0 V to 5.5 V; V_GND= 0 V; T_amb= −40 °C to +85 °C; typical values at T_amb= 25 °C; unless otherwise

speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_CC= 5 V

V_REG(3V3)internal regulator output

[1]

3.0

3.3

47

40

3.6

-

V

I_CC

operating supply current

suspend supply current

-

mA

µA

I_CC(susp

)

500

V_CC= 3.3 V

I_CC

operating supply current

suspend supply current

-

50

-

mA

[2]

I_CC(susp

)

150

500

µA

[1] In the suspend mode, the minimum voltage is 2.7 V.

[2] For details on power consumption, refer to Philips Application Note AN10022 ISP1160x Low Power Consumption.

Table 69: Static characteristics: digital pins

V_CC= 3.0 V to 3.6 V or 4.0 V to 5.5 V; V_GND= 0 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

Input levels

V_IL

Parameter

Conditions

Min

Typ

Max

Unit

LOW-level input voltage

HIGH-level input voltage

-

0.8

-

V

V_IH

2.0

Schmitt trigger inputs

V_th(LH)

V_th(HL)

V_hys

positive-going threshold voltage

1.4

0.9

0.4

-

1.9

1.5

0.7

V

negative-going threshold voltage

hysteresis voltage

Output levels

V_OLLOW-level output voltage

I

_OL= 4 mA

_OL= 20 µA

_OH= 4 mA

_OH= 20 µA

-

0.4

0.1

-

V

-

[1]

[2]

V_OH

HIGH-level output voltage

2.4

V

_REG(3V3)− 0.1

-

Leakage current

I_LI

input leakage current

pin capacitance

−5

-

+5

µA

C_IN

pin to GND

-

5

pF

Open-drain outputs

I_OZ

OFF-state output current

−5

-

+5

µA

[1] Not applicable for open-drain outputs.

[2] The maximum and minimum values are applicable to transistor input only. The value will be different if internal pull-up or pull-down

resistors are used.

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Table 70: Static characteristics: analog I/O pins D+ and D−

V_CC= 3.0 V to 3.6 V or 4.0 V to 5.5 V; V_GND= 0 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Input levels

[1]

V_DI

V_CM

V_IL

differential input sensitivity

|V_I(D+)− V_I(D−)

|

0.2

0.8

-

V

differential common mode voltage includes V_DIrange

LOW-level input voltage

2.5

0.8

-

V_IH

HIGH-level input voltage

2.0

Output levels

V_OL

LOW-level output voltage

R_L= 1.5 kΩ to

+3.6 V

-

0.3

3.6

V

V_OH

HIGH-level output voltage

R_L= 15 kΩ to GND

2.8

Leakage current

I_LZ

OFF-state leakage current

−10

-

+10

10

µA

pF

kΩ

Capacitance

C_IN

transceiver capacitance

pin to GND

Resistance

R_PD

pull-down resistance on HC’s

D+/D−

enable internal

resistors

10

20

[2]

Z_DRV

Z_INP

driver output impedance

input impedance

steady-state drive

29

10

-

44

-

Ω

MΩ

[1] D+ is the USB positive data pin; D− is the USB negative data pin.

[2] Includes external resistors of 18 Ω ± 1 % on both pins H_D+ and H_D−.

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17. Dynamic characteristics

Table 71: Dynamic characteristics

V_CC= 3.0 V to 3.6 V or 4.0 V to 5.5 V; V_GND= 0 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

Reset

Parameter

Conditions

Min

Typ

Max

Unit

t_{W(RESET_N)}pulse width on input RESET_N crystal oscillator running

crystal oscillator stopped

160

-

µs

[1]

ms

Crystal oscillator

f_XTAL

R_S

crystal frequency

series resistance

load capacitance

-

6

-

MHz

Ω

-

100

-

C_LOAD

C_x1, C_x2= 22 pF

18

pF

External clock input

t_J

external clock jitter

-

500

55

3

ps

%

t_DUTY

t_CR, t_CF

clock duty cycle

45

-

50

-

rise time and fall time

ns

[1] Dependent on the crystal oscillator start-up time.

Table 72: Dynamic characteristics: analog I/O pins D+ and D−

V_CC= 3.0 V to 3.6 V or 4.0 V to 5.5 V; V_GND= 0 V; T_amb= −40 °C to +85 °C; C_L= 50 pF; see Figure 42 for test circuit; unless

otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Driver characteristics

t_FR

rise time

C_L= 50 pF;

4

-

20

ns

10 % to 90 % of

|V_OH− V_OL

|

t_FF

fall time

C_L= 50 pF;

4

-

20

ns

90 % to 10 % of

|V_OH− V_OL

|

[1]

FRFM

V_CRS

differential rise/fall time

90

-

111.11

2.0

%

matching (t_FR/t_FF

)

[1][2]

output signal crossover voltage

1.3

V

[1] Excluding the ﬁrst transition from Idle state.

[2] Characterized only, not tested. Limits guaranteed by design.

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17.1 Programmed I/O timing

Table 73: Dynamic characteristics: programmed interface timing

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

t_AS

address set-up time before

WR_N HIGH

5

-

ns

t_AH

address hold time after WR_N HIGH

8

-

ns

Read timing

t_SHSL

ﬁrst RD_N/WR_N after A0 HIGH

CS_N LOW to RD_N LOW

RD_N HIGH to CS_N HIGH

RD_N LOW pulse width

RD_N HIGH to next RD_N LOW

RD_N cycle

300

0

-

ns

t_SLRL

-

t_RHSH

t_RLRH

t_RHRL

0

-

33

110

143

3

-

T_RC

-

t_RHDZ

t_RLDV

RD_N data hold time

22

32

RD_N LOW to data valid

-

Write timing

t_WL

WR_N LOW pulse width

WR_N HIGH to next WR_N LOW

WR_N cycle

26

110

136

0

-

ns

t_WHWL

T_WC

t_SLWL

CS_N LOW to WR_N LOW

WR_N HIGH to CS_N HIGH

WR_N data set-up time

WR_N data hold time

t_WHSH

t_WDSU

t_WDH

0

5

8

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CS_N

A0

t

SLRL

SLWL

t

SHSL

t

RLRH

t

WHSH

RHSH

t

RHRL

T

RC

RD_N

t

RLDV

t

RHDZ

[

]

D 15:0

data

valid

data

valid

data

valid

data

valid

t

AS

t

WHWL

t

T

WC

AH

WL

WR_N

t

WDH

WDSU

data

valid

data

valid

data

valid

data

valid

data

valid

[

]

D 15:0

004aaa367

Fig 35. Programmed interface timing.

17.2 DMA timing

17.2.1 Single-cycle DMA timing

Table 74: Dynamic characteristics: single-cycle DMA timing

Symbol Parameter Conditions

Read/write timing

Min

Typ

Max

Unit

t_RLRH

t_RLDV

t_RHDZ

t_WSU

t_WHD

t_AHRH

t_ALRL

T_DC

RD_N pulse width

33

26

0

-

ns

read process data set-up time

read process data hold time

write process data set-up time

write process data hold time

DACK_N HIGH to DREQ HIGH

DACK_N LOW to DREQ LOW

DREQ cycle

-

20

-

5

0

-

72

-

21

-

[1]

-

t_SHAH

RD_N/WR_N HIGH to

DACK_N HIGH

0

-

t_RHAL

t_DS

DREQ HIGH to DACK_N LOW

DREQ pulse spacing

0

-

ns

146

[1] T_DC= t_RHAL+ t_DS+ t_ALRL

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T

DC

DREQ

t

DS

t

ALRL

t

SHAH

t

RHAL

DACK_N

t

AHRH

t

RHDZ

RLDV

[

]

D 15:0

data

valid

(read)

[

D 15:0

data

valid

(write)

t

WSU

RD_N or

WR_N

004aaa371

t

WHD

Fig 36. Single-cycle DMA timing.

17.2.2 Burst mode DMA timing

Table 75: Dynamic characteristics: burst mode DMA timing

Symbol Parameter

Conditions

Min

Typ

Max

Unit

Read/write timing (for 4-cycle and 8-cycle burst mode)

t_RLRH

t_RHRL

WR_N/RD_N LOW pulse width

42

60

-

ns

WR_N/RD_N HIGH to next

WR_N/RD_N LOW

T_RC

WR_N/RD_N cycle

102

22

0

-

ns

t_SLRL

t_SHAH

RD_N/WR_N LOW to DREQ LOW

64

-

RD_N/WR_N HIGH to

DACK_N HIGH

t_SLAL

T_DC

DREQ HIGH to DACK_N LOW

DREQ cycle

0

-

ns

[1]

-

t_DS(read)DREQ pulse spacing (read)

t_DS(write)DREQ pulse spacing (write)

4-cycle burst mode

8-cycle burst mode

4-cycle burst mode

8-cycle burst mode

105

150

72

167

0

t_RLIS

RD_N/WR_N LOW to EOT LOW

[1] T_DC= t_SLAL+ (4 or 8)T_RC+ t_DS

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t

DS

DREQ

t

SLRL

RHSH

t

SLAL

DACK_N

t

SHAH

RHRL

RD_N or

WR_N

004aaa372

T

RC

t

RLRH

Fig 37. Burst mode DMA timing.

17.2.3 External EOT timing for single-cycle DMASETUP

DREQ

DACK_N

RD_N or

WR_N

EOT

004aaa373

t

> 0 ns

RLIS

Fig 38. External EOT timing for single-cycle DMA.

17.2.4 External EOT timing for burst mode DMA

DREQ

DACK_N

RD_N or

WR_N

EOT

004aaa374

t

> 0 ns

RLIS

Fig 39. External EOT timing for burst mode DMA.

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18. Application information

18.1 Typical interface circuit

V

DD

+

3.3 V

+

5 V

5 V 3.3 V

MOSFET

(2×)

SH7709

ISP1160

Vbus_DN2 Vbus_DN1

V

CC

+

3.3 V

5 V

H_OC1_N

H_OC2_N

H_PSW2_N

[

]

[

]

D 15:0

FB1

22 Ω

(2×)

H_PSW1_N

A1

A0

USB

downstream

port #1

H_DM1

H_DP1

H_DM2

H_DP2

CS5

RD_N

RD/WR_N

CS_N

RD_N

WR_N

47 pF

(2×)

FB2

DREQ0

DACK0_N

DREQ

DACK_N

V

reg

+

3.3 V

FB3

V

(3V3)

REG

22 Ω

+

5 V

EOT

(2×)

USB

downstream

port #2

CLKOUT

EXTAL

XTAL

V

1

V

DD

HOLD

IRQ2

INT

V

HOLD2

47 pF

(2×)

FB4

PTC0

PTC1

H_WAKEUP

H_SUSPEND

NDP_SEL

EXTAL2

XTAL2

GND

32

kHz

RESET_N

RSTOUT

XTAL2

XTAL1

6 MHz

7

DGND

AGND

22 pF

004aaa072

For MOSFET, R_DSon= 150 mΩ.

Fig 40. Typical interface circuit to Hitachi SH-3 (SH7709) RISC processor.

18.2 Interfacing a ISP1160 to a SH7709 RISC processor

This section shows a typical interface circuit between the ISP1160 and a RISC

processor. The Hitachi SH-3 series RISC processor SH7709 is used as the example.

The main ISP1160 signals to be taken into consideration for connecting to a SH7709

RISC processor are:

• A 16-bit data bus: D[15:0] for the ISP1160. The ISP1160 is ‘little endian’

compatible.

• The address line A0 is needed for a complete addressing of the ISP1160 internal

registers:

– A0 = 0 will select the Data Port of the Host Controller

– A0 = 1 will select the Command Port of the Host Controller

• The CS_N line is used for chip selection of the ISP1160 in a certain address range

of the RISC system. This signal is active LOW.

• RD_N and WR_N are common read and write signals. These signals are active

LOW.

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• There is a DMA channel standard control line: DREQ and DACK_N. The DREQ

signal has programmable active levels.

• An interrupt line INT is used by the HC. It has programmable level/edge and

polarity (active HIGH or LOW).

• The internal 15 kΩ pull-down resistors are used for the HC’s two USB downstream

ports.

• The RESET_N signal is active LOW.

Remark: SH7709’s system clock input is for reference only. Refer to SH7709’s

speciﬁcation for its actual use.

The ISP1160 can work under either 3.3 V or 5.0 V power supply; however, its internal

core works at 3.3 V. When using 3.3 V as the power supply input, the internal DC/DC

regulator will be bypassed. It is best to connect all four power supply pins (V_CC

,

V_REG(3V3), V_HOLD1and V_HOLD2) to the 3.3 V power supply (for more information, see

Section 11). All of the ISP1160’s I/O pins are 5 V-tolerant. This feature allows the

ISP1160 the ﬂexibility to be used in an embedded system under either a 3.3 V or a

5 V power supply.

A typical SH7709 interface circuit is shown in Figure 40.

18.3 Typical software model

This section shows a typical software requirement for an embedded system that

incorporates the ISP1160. The software model for a Digital Still Camera (DSC) is

used as the example for illustration (as shown in Figure 41). The host stack provides

API for Class driver and device driver, both of which provide API for application tasks

for host function.

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Application

layer

MECHANISM CONTROL TASK

IMAGE PROCESSING TASKS

FILE MANAGEMENT

PRINTER UI/CONTROL

OS

DEVICE DRIVERS

Class

driver

MASS STORAGE CLASS DRIVER

PRINTING CLASS DRIVER

HOST STACK

USB

host stack

ISP1160 HAL

USB Upstream

Printer

RISC

ROM

RAM

ISP1160

LEN

CONTROL

Flash card

Reader/

Writer

USB Downstream

004aaa073

Digital Still Camera

Fig 41. The ISP1160 software model for DSC application.

19. Test information

The dynamic characteristics of the analog I/O pins D+ and D− as listed in Table 72

were determined using the circuit shown in Figure 42.

test point

22 Ω

D.U.T.

C

L

50 pF

15 kΩ

MGT967

Full-speed mode: load capacitance C_L= 50 pF.

Full-speed mode only: internal 1.5 kΩ pull-up resistor on pin D+.

Fig 42. Load impedance.

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20. Package outline

LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm

SOT314-2

y

X

A

48

33

Z

49

32

E

e

H

A

E

2

E

A

(A )

3

A

1

w M

p

θ

b

L

p

pin 1 index

L

64

17

detail X

1

16

Z

v M

D

A

e

w M

b

p

D

B

H

v M

B

D

0

2.5

scale

5 mm

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

L

v

w

y

Z

E

θ

1

2

3

p

D

E

p

D

max.

7^o

0^o

0.20 1.45

0.05 1.35

0.27 0.18 10.1 10.1

0.17 0.12 9.9 9.9

12.15 12.15

11.85 11.85

0.75

0.45

1.45 1.45

1.05 1.05

1.6

mm

0.25

0.5

1

0.2 0.12 0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

00-01-19

03-02-25

SOT314-2

136E10

MS-026

Fig 43. LQFP64 (SOT314-2) package outline.

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LQFP64: plastic low profile quad flat package; 64 leads; body 7 x 7 x 1.4 mm

SOT414-1

y

X

A

48

33

49

32

Z

E

e

A

2

A

H

E

(A )

3

A

1

w M

p

θ

b

pin 1 index

L

p

L

64

17

detail X

1

16

Z

v M

A

D

e

w M

b

p

D

B

H

v M

B

D

0

2.5

scale

5 mm

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

D

H

L

v

w

y

Z

θ

1

2

3

p

E

p

D

E

max.

7^o

0^o

0.15 1.45

0.05 1.35

0.23 0.20 7.1

0.13 0.09 6.9

7.1

6.9

9.15 9.15

8.85 8.85

0.75

0.45

0.64 0.64

0.36 0.36

1.6

mm

0.25

0.4

1

0.2 0.08 0.08

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

00-01-19

03-02-20

SOT414-1

136E06

MS-026

Fig 44. LQFP64 (SOT414-1) package outline.

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21. Soldering

21.1 Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology. A more in-depth account

of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit

Packages (document order number 9398 652 90011).

There is no soldering method that is ideal for all IC packages. Wave soldering can still

be used for certain surface mount ICs, but it is not suitable for ﬁne pitch SMDs. In

these situations reﬂow soldering is recommended. In these situations reﬂow

soldering is recommended.

21.2 Reﬂow soldering

Reﬂow soldering requires solder paste (a suspension of ﬁne solder particles, ﬂux and

binding agent) to be applied to the printed-circuit board by screen printing, stencilling

or pressure-syringe dispensing before package placement. Driven by legislation and

environmental forces the worldwide use of lead-free solder pastes is increasing.

Several methods exist for reﬂowing; for example, convection or convection/infrared

heating in a conveyor type oven. Throughput times (preheating, soldering and

cooling) vary between 100 and 200 seconds depending on heating method.

Typical reﬂow peak temperatures range from 215 to 270 °C depending on solder

paste material. The top-surface temperature of the packages should preferably be

kept:

• below 220 °C (SnPb process) or below 245 °C (Pb-free process)

– for all BGA and SSOP-T packages

– for packages with a thickness ≥ 2.5 mm

– for packages with a thickness < 2.5 mm and a volume ≥ 350 mm³so called

thick/large packages.

• below 235 °C (SnPb process) or below 260 °C (Pb-free process) for packages with

a thickness < 2.5 mm and a volume < 350 mm³so called small/thin packages.

Moisture sensitivity precautions, as indicated on packing, must be respected at all

times.

21.3 Wave soldering

Conventional single wave soldering is not recommended for surface mount devices

(SMDs) or printed-circuit boards with a high component density, as solder bridging

and non-wetting can present major problems.

To overcome these problems the double-wave soldering method was speciﬁcally

developed.

If wave soldering is used the following conditions must be observed for optimal

results:

• Use a double-wave soldering method comprising a turbulent wave with high

upward pressure followed by a smooth laminar wave.

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• For packages with leads on two sides and a pitch (e):

– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be

parallel to the transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the

transport direction of the printed-circuit board.

The footprint must incorporate solder thieves at the downstream end.

• For packages with leads on four sides, the footprint must be placed at a 45° angle

to the transport direction of the printed-circuit board. The footprint must

incorporate solder thieves downstream and at the side corners.

During placement and before soldering, the package must be ﬁxed with a droplet of

adhesive. The adhesive can be applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the adhesive is cured.

Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 °C or

265 °C, depending on solder material applied, SnPb or Pb-free respectively.

A mildly-activated ﬂux will eliminate the need for removal of corrosive residues in

most applications.

21.4 Manual soldering

Fix the component by ﬁrst soldering two diagonally-opposite end leads. Use a low

voltage (24 V or less) soldering iron applied to the ﬂat part of the lead. Contact time

must be limited to 10 seconds at up to 300 °C.

When using a dedicated tool, all other leads can be soldered in one operation within

2 to 5 seconds between 270 and 320 °C.

21.5 Package related soldering information

Table 76: Suitability of surface mount IC packages for wave and reﬂow soldering

methods

Package^[1]

Soldering method

Wave

Reﬂow^[2]

BGA, LBGA, LFBGA, SQFP, SSOP-T^[3],

TFBGA, VFBGA

not suitable

suitable

DHVQFN, HBCC, HBGA, HLQFP, HSQFP,

HSOP, HTQFP, HTSSOP, HVQFN, HVSON,

SMS

not suitable^[4]

suitable

PLCC^[5], SO, SOJ

suitable

LQFP, QFP, TQFP

not recommended^[5][6]

not recommended^[7]

SSOP, TSSOP, VSO, VSSOP

[1] For more detailed information on the BGA packages refer to the (LF)BGA Application Note

(AN01026); order a copy from your Philips Semiconductors sales ofﬁce.

[2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the

maximum temperature (with respect to time) and body size of the package, there is a risk that internal

or external package cracks may occur due to vaporization of the moisture in them (the so called

popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated

Circuit Packages; Section: Packing Methods.

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[3] These transparent plastic packages are extremely sensitive to reﬂow soldering conditions and must

on no account be processed through more than one soldering cycle or subjected to infrared reﬂow

soldering with peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reﬂow

oven. The package body peak temperature must be kept as low as possible.

[4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom

side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with

the heatsink on the top side, the solder might be deposited on the heatsink surface.

[5] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave

direction. The package footprint must incorporate solder thieves downstream and at the side corners.

[6] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it

is deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

[7] Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than

0.65 mm; it is deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

22. Revision history

Table 77: Revision history

Rev Date

CPCN

-

Description

04 20030704

Product data (9397 750 11371)

Modiﬁcations:

• Table 1: added type numbers /01

• Table 2: updated description for pin 40

• Section 6: changed active LOW pin names into NAME_N; also changed pin names in

ﬁgures and parameters in dynamic characteristics tables

• Section 9.4.1: removed the last bullet list under the examples on legal uses of the internal

FIFO buffer RAM

• Section 9.5: updated last paragraph

• Table 8: changed reset value to 10H

• Table 9: updated

• Table 46: updated the chip ID

• Section 13: added (new)

• Table 68: updated the table note

• Deleted section Timing symbols (old section 17.1).

Product data (9397 750 10765)

Product data (9397 750 09628)

Objective data (9397 750 09161)

03 20030227

02 20020912

01 20020104

-

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23. Data sheet status

Level Data sheet status^[1]

Product status^[2][3]

Deﬁnition

I

Objective data

Development

This data sheet contains data from the objective speciﬁcation for product development. Philips

Semiconductors reserves the right to change the speciﬁcation in any manner without notice.

II

Preliminary data

Qualiﬁcation

This data sheet contains data from the preliminary speciﬁcation. Supplementary data will be published

at a later date. Philips Semiconductors reserves the right to change the speciﬁcation without notice, in

order to improve the design and supply the best possible product.

III

Product data

Production

This data sheet contains data from the product speciﬁcation. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant

changes will be communicated via a Customer Product/Process Change Notiﬁcation (CPCN).

[1]

[2]

Please consult the most recently issued data sheet before initiating or completing a design.

The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at

URL http://www.semiconductors.philips.com.

[3]

For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

customers using or selling these products for use in such applications do so

at their own risk and agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

24. Deﬁnitions

Short-form speciﬁcation — The data in a short-form speciﬁcation is

extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Right to make changes — Philips Semiconductors reserves the right to

make changes in the products - including circuits, standard cells, and/or

software - described or contained herein in order to improve design and/or

performance. When the product is in full production (status ‘Production’),

relevant changes will be communicated via a Customer Product/Process

Change Notiﬁcation (CPCN). Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no

licence or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are

free from patent, copyright, or mask work right infringement, unless otherwise

speciﬁed.

Limiting values deﬁnition — Limiting values given are in accordance with

the Absolute Maximum Rating System (IEC 60134). Stress above one or

more of the limiting values may cause permanent damage to the device.

These are stress ratings only and operation of the device at these or at any

other conditions above those given in the Characteristics sections of the

speciﬁcation is not implied. Exposure to limiting values for extended periods

may affect device reliability.

Application information — Applications that are described herein for any

of these products are for illustrative purposes only. Philips Semiconductors

make no representation or warranty that such applications will be suitable for

the speciﬁed use without further testing or modiﬁcation.

26. Trademarks

ARM7 and ARM9 — are trademarks of ARM Ltd.

25. Disclaimers

GoodLink — is a trademark of Koninklijke Philips Electronics N.V.

Hitachi — is a registered trademark of Hitachi Ltd.

MIPS-based — is a trademark of MIPS Technologies, Inc.

SoftConnect — is a trademark of Koninklijke Philips Electronics N.V.

StrongARM — is a registered trademark of ARM Ltd.

SuperH — is a trademark of Hitachi Ltd.

Life support — These products are not designed for use in life support

appliances, devices, or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors

Contact information

For additional information, please visit http://www.semiconductors.philips.com.

For sales ofﬁce addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.

Fax: +31 40 27 24825

87 of 88

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Embedded USB Host Controller

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Contents

1

2

3

4

5

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

17.2

DMA timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 76

18

18.1

18.2

Application information . . . . . . . . . . . . . . . . . 79

Typical interface circuit . . . . . . . . . . . . . . . . . . 79

Interfacing a ISP1160 to a SH7709

RISC processor. . . . . . . . . . . . . . . . . . . . . . . 79

Typical software model. . . . . . . . . . . . . . . . . . 80

18.3

19

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

Test information. . . . . . . . . . . . . . . . . . . . . . . . 81

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 82

20

21

21.1

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Introduction to soldering surface mount

packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Reﬂow soldering. . . . . . . . . . . . . . . . . . . . . . . 84

Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 84

Manual soldering . . . . . . . . . . . . . . . . . . . . . . 85

Package related soldering information. . . . . . 85

7

Functional description . . . . . . . . . . . . . . . . . . . 8

PLL clock multiplier. . . . . . . . . . . . . . . . . . . . . . 8

Bit clock recovery . . . . . . . . . . . . . . . . . . . . . . . 8

Analog transceivers . . . . . . . . . . . . . . . . . . . . . 8

Philips Serial Interface Engine (SIE). . . . . . . . . 8

7.1

7.2

7.3

7.4

21.2

21.3

21.4

21.5

8

Microprocessor bus interface. . . . . . . . . . . . . . 8

Programmed I/O (PIO) addressing mode. . . . . 8

DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Control registers access by PIO mode . . . . . . 10

FIFO buffer RAM access by PIO mode . . . . . 11

FIFO buffer RAM access by DMA mode. . . . . 12

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

8.1

8.2

8.3

8.4

8.5

8.6

22

23

24

25

26

Revision history . . . . . . . . . . . . . . . . . . . . . . . 86

Data sheet status. . . . . . . . . . . . . . . . . . . . . . . 87

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

9

Host Controller (HC) . . . . . . . . . . . . . . . . . . . . 16

HC’s four USB states . . . . . . . . . . . . . . . . . . . 16

Generating USB trafﬁc . . . . . . . . . . . . . . . . . . 17

PTD data structure . . . . . . . . . . . . . . . . . . . . . 19

HC’s internal FIFO buffer RAM structure . . . . 22

HC operational model. . . . . . . . . . . . . . . . . . . 28

Microprocessor loading. . . . . . . . . . . . . . . . . . 31

Internal pull-down resistors for downstream

9.1

9.2

9.3

9.4

9.5

9.6

9.7

ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Overcurrent detection and power switching

control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Suspend and wake-up . . . . . . . . . . . . . . . . . . 34

9.8

9.9

10

HC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

HC control and status registers . . . . . . . . . . . 37

HC frame counter registers. . . . . . . . . . . . . . . 44

HC Root Hub registers . . . . . . . . . . . . . . . . . . 48

HC DMA and interrupt control registers . . . . . 57

HC miscellaneous registers . . . . . . . . . . . . . . 62

HC buffer RAM control registers. . . . . . . . . . . 64

10.1

10.2

10.3

10.4

10.5

10.6

11

12

13

14

15

16

17

17.1

Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . 69

Power-on reset (POR) . . . . . . . . . . . . . . . . . . . 70

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 71

Recommended operating conditions. . . . . . . 71

Static characteristics. . . . . . . . . . . . . . . . . . . . 72

Dynamic characteristics . . . . . . . . . . . . . . . . . 74

Programmed I/O timing. . . . . . . . . . . . . . . . . . 75

Printed in The Netherlands

All rights are reserved. Reproduction in whole or in part is prohibited without the prior

written consent of the copyright owner.

The information presented in this document does not form part of any quotation or

contract, is believed to be accurate and reliable and may be changed without notice. No

liability will be accepted by the publisher for any consequence of its use. Publication

thereof does not convey nor imply any license under patent- or other industrial or

intellectual property rights.

Date of release: 04 July 2003

Document order number: 9397 750 11371


型号：	ISP1160BM
厂家：	NXP
描述：	Embedded Universal Serial Bus Host Controller 嵌入式通用串行总线主控制器控制器
文件：	总88页 (文件大小：1864K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISP1160BM [NXP]

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