ISP1183BS_技术文档

ISP1183

Low-power Universal Serial Bus interface device with DMA

Rev. 01 — 24 February 2004

Product data

1. General description

The ISP1183 is a Universal Serial Bus (USB) interface device that complies with

Universal Serial Bus Speciﬁcation Rev. 2.0, supporting data transfer at full-speed

(12 Mbit/s). It provides full-speed USB communication capacity to microcontroller or

microprocessor-based systems. The ISP1183 communicates with the system’s

microcontroller or microprocessor through a fast general-purpose parallel interface.

The ISP1183 supports fully autonomous, multiconﬁgurable Direct Memory Access

(DMA) operation.

The modular approach to implementing a USB interface device allows designer to

select the optimum system microcontroller from the wide variety available. The ability

to reuse existing architecture and ﬁrmware investments shortens development time,

eliminates risks and reduces costs. The result is fast and efﬁcient development of the

most cost-effective USB peripheral solution.

The ISP1183 supports I/O voltage range of 1.65 V to 3.6 V enabling it to be directly

interfaced to battery-operated devices, such as mobile phones. The ISP1183 is

ideally suited for battery-operated (low power) application in many portable

peripherals such as mobile phones, Personal Digital Assistants (PDAs) and MP3

players. This device can be used in bus-powered or hybrid-powered applications.

Also, more number of endpoints in the ISP1183 enable the device to be used in

applications such as multifunctional printers, other than standard applications such

as printers, communication devices, scanners, external mass storage devices and

digital still cameras.

2. Features

■ Complies with Universal Serial Bus Speciﬁcation Rev. 2.0 and most Device Class

speciﬁcations

■ Complies with ACPI™, OnNow™ and USB power management requirements

■ Supports data transfer at full-speed (12 Mbit/s)

■ High performance USB interface device with integrated Serial Interface Engine

(SIE), FIFO memory, transceiver, and 3.3 V voltage regulator

■ High speed (11.1 Mbyte/s or 90 ns read/write cycle) parallel interface

■ Fully autonomous and multiconﬁguration DMA operation

■ Up to 14 programmable USB endpoints with 2 ﬁxed control IN/OUT endpoints

■ Integrated physical 2462 bytes of multiconﬁguration FIFO memory

■ Endpoints with double buffering to increase throughput and ease real-time data

transfer

■ Seamless interface with most microcontrollers and microprocessors

ISP1183

Low-power USB interface device with DMA

Philips Semiconductors

■ Bus-powered capability with low power consumption and low suspend current

■ Software controlled connection to the USB bus (SoftConnect™)

■ Supports internal power-on and low-voltage reset circuit

■ Supports software reset

■ Hybrid-powered capability with low-power consumption required from the system

■ V_BUSindication

■ 6 MHz crystal oscillator input with integrated PLL for low EMI

■ Good USB connection indicator that blinks with trafﬁc (GoodLink™)

■ Supports I/O voltage range of 1.65 V to 3.6 V

■ Operation over the extended USB bus voltage range (4.0 V to 5.5 V) with 3.3 V

tolerant I/O pads

■ Operating temperature range −40 °C to +85 °C

■ Full-scan design with high fault coverage

■ Available in HVQFN32 lead-free and halogen-free package.

3. Applications

■ Battery-operated device, for example:

◆ Mobile phone

◆ MP3 player

◆ Personal Digital Assistant (PDA)

■ Communication device, for example:

◆ Router

◆ Modem

■ Digital camera

■ Mass storage device, for example:

◆ Zip^®drive

■ Printer

■ Scanner.

4. Abbreviations

CRC — Cyclic Redundancy Check

DMA — Direct Memory Access

EMI — ElectroMagnetic Interference

FIFO — First In, First Out

MMU — Memory Management Unit

PID — Packet IDentiﬁer

PIO — Parallel I/O

PLL — Phase-Locked Loop

SIE — Serial Interface Engine

USB — Universal Serial Bus.

9397 750 11804

Product data

Rev. 01 — 24 February 2004

2 of 62

ISP1183

Low-power USB interface device with DMA

Philips Semiconductors

5. Ordering information

Table 1:

Ordering information

Package

Type

number

Name

Description

Version

ISP1183BS HVQFN32 plastic thermal enhanced very thin quad ﬂat package; SOT617-1

no leads; 32 terminals; body 5 × 5 × 0.85 mm

9397 750 11804

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ISP1183

Low-power USB interface device with DMA

Philips Semiconductors

7. Pinning information

7.1 Pinning

V

8

7

17

18

BUS

A0

V

GND (exposed die pad)

XTAL2

DD(I/O)

19

DATA0

XTAL1

DGND

RD_N

6

5

4

20 DATA1

ISP1183BS

21

V

DD

22

3

2

DGND

WR_N

CS_N

terminal 1

23

24

DATA2

DATA3

INT_N

1

004aaa433

Bottom view

Fig 2. Pin conﬁguration HVQFN32.

7.2 Pin description

Table 2:

Symbol^[1]

Pin description

Pin Type Description

INT_N

CS_N

WR_N

RD_N

1

O

interrupt output; active LOW

3.3 V tolerant I/O pad

chip select input

2

3

4

I

3.3 V tolerant I/O pad

write strobe input

I

3.3 V tolerant I/O pad

read strobe input

I

3.3 V tolerant I/O pad

digital ground supply

DGND

XTAL1

5

6

-

I

crystal oscillator input (6 MHz); connect a fundamental

parallel-resonant crystal or an external clock source (leave

pin XTAL2 unconnected)

XTAL2

7

O

crystal oscillator output (6 MHz); connect a fundamental

parallel-resonant crystal; leave this pin open when using an

external clock source on pin XTAL1

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ISP1183

Low-power USB interface device with DMA

Philips Semiconductors

Table 2:

Pin description…continued

Symbol^[1]

Type Description

V_BUS

8

I

V_BUSsensing input and power supply input; see

Section 8.11

DM

9

AI/O USB D− line connection (analog)

DP

10

11

12

AI/O USB D+ line connection (analog)

AGND

V_REG(3V3)

-

analog ground supply

regulated supply voltage (3.3 V ± 10 %) from internal

regulator; used to connect a 0.1 µF decoupling capacitor

and pull-up resistor on pin DP

Remark: Cannot be used to supply external devices.

VBUSDET_N 13

O

V_BUSindicator output (active LOW); see Table 3

DREQ

14

DMA request output (4 mA; programmable polarity, see

Table 21); signals to the DMA controller that the ISP1183

wants to start a DMA transfer

3.3 V tolerant I/O pad

DACK

15

I

DMA acknowledge input (programmable polarity, see

Table 21); used by the DMA controller to signal the start of a

DMA transfer requested by the ISP1183; when not in use,

connect this pin to ground through a 10 kΩ resistor

3.3 V tolerant I/O pad

RESET_N

A0

16

17

I

reset input (Schmitt trigger); a LOW level produces an

asynchronous reset

3.3 V tolerant I/O pad

address input; selects command (A0 = HIGH) or data

(A0 = LOW)

3.3 V tolerant I/O pad

V_DD(I/O)

DATA0

18

19

-

I/O power supply; add a decoupling capacitor of 0.1 µF

(1.65 V to 3.6 V); see Section 8.11

I/O

data bit 0 input and output

bidirectional (4 mA), 3.3 V tolerant I/O pad

data bit 1 input and output

DATA1

V_DD

20

21

I/O

-

bidirectional (4 mA), 3.3 V tolerant I/O pad

3.3 V output voltage; internally connected to the regulator

output; connect to a decoupling capacitor of 0.1 µF

DGND

DATA2

22

23

digital ground supply

I/O

data bit 2 input and output

bidirectional (4 mA), 3.3 V tolerant I/O pad

data bit 3 input and output

DATA3

24

bidirectional (4 mA), 3.3 V tolerant I/O pad

digital ground supply

DGND

DATA4

25

26

-

I/O

data bit 4 input and output

bidirectional (4 mA), 3.3 V tolerant I/O pad

data bit 5 input and output

DATA5

27

I/O

bidirectional (4 mA), 3.3 V tolerant I/O pad

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ISP1183

Low-power USB interface device with DMA

Philips Semiconductors

Table 2:

Pin description…continued

Symbol^[1]

Type Description

DATA6

28

I/O

data bit 6 input and output

bidirectional (4 mA), 3.3 V tolerant I/O pad

data bit 7 input and output

DATA7

29

I/O

bidirectional (4 mA), 3.3 V tolerant I/O pad

I/O power supply; add a decoupling capacitor of 0.1 µF

V_DD(I/O)

30

31

-

I

WAKEUP

wake-up input (edge triggered, LOW to HIGH); generates a

remote wake-up from the suspend state; when not in use,

connect this pin to ground through a 10 kΩ resistor

3.3 V tolerant I/O pad

SUSPEND

GND

32

O

suspend state indicator output (4 mA)

3.3 V tolerant I/O pad

exposed -

die pad

ground supply; down bonded to the exposed die pad

(heatsink); to be connected to the DGND during PCB layout

[1] Symbol names ending with underscore N (for example, NAME_N) represent active LOW signals.

9397 750 11804

Product data

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ISP1183

Low-power USB interface device with DMA

Philips Semiconductors

8. Functional description

The ISP1183 is a full-speed USB interface device with up to 14 conﬁgurable

endpoints. It has a fast general-purpose parallel interface for communication with

many types of microcontrollers and microprocessors. It supports an 8-bit data bus

with separate address and data. The block diagram is given in Figure 1.

The ISP1183 has 2462 bytes of internal FIFO memory that is shared among the

enabled USB endpoints. The type and FIFO size of each endpoint can be individually

conﬁgured, depending on the required packet size. Isochronous and bulk endpoints

are double-buffered for increased data throughput.

The ISP1183 requires two supply voltages. The core voltage is supplied from V_BUS

through an internal regulator, which transforms +5.0 V to +3.3 V when V_BUSis

powered. The I/O interface voltage is supplied from V_DD(I/O), which can be

1.65 V to 3.6 V.

The ISP1183 operates on a 6 MHz oscillator frequency.

8.1 Analog transceiver

The transceiver is compliant with the Universal Serial Bus Speciﬁcation Rev. 2.0. It

directly interfaces with the USB cable through external termination resistors.

8.2 Philips SIE

The Philips Serial Interface Engine (SIE) implements the full USB protocol layer. It is

completely hardwired for speed and needs no ﬁrmware intervention. The functions of

this block include: synchronization pattern recognition, parallel-to-serial conversion,

bit (de)stufﬁng, CRC checking and generation, Packet IDentiﬁer (PID) veriﬁcation and

generation, address recognition, and handshake evaluation and generation.

8.3 MMU and integrated RAM

The Memory Management Unit (MMU) and the integrated RAM provide the

conversion between the USB speed (full-speed: 12 Mbit/s bursts) and the parallel

interface to the microcontroller (maximum 11.1 Mbyte/s). This allows the

microcontroller to read and write USB packets at its own speed.

8.4 SoftConnect

The connection to USB is accomplished by pulling pin DP (for full-speed USB

devices) HIGH through a 1.5 kΩ pull-up resistor. In the ISP1183, by default, the

1.5 kΩ pull-up resistor is integrated on-chip. The connection is established by a

command sent from the external or system microcontroller. This allows the system

microcontroller to complete its initialization sequence before deciding to establish

connection with the USB. Reinitialization of the USB connection can also be

performed without disconnecting the cable.

Remark: The tolerance of the internal resistors is 25 %. This is higher than the 5 %

tolerance speciﬁed by the USB speciﬁcation. The overall voltage speciﬁcation for the

connection, however, can still be met with a good margin. The decision to make use

of this feature lies with the USB equipment designer.

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ISP1183

Low-power USB interface device with DMA

Philips Semiconductors

8.5 Bit clock recovery

The bit clock recovery circuit recovers the clock from the incoming USB data stream

using a 4 x oversampling principle. It can track jitter and frequency drift as speciﬁed

by the USB Speciﬁcation Rev. 2.0.

8.6 Voltage regulator

A 5 V-to-3.3 V voltage regulator is integrated on-chip to supply the analog transceiver

and internal logic. This voltage is available at pin V_REG(3V3)to supply an external

1.5 kΩ pull-up resistor on pin DP. Alternatively, the ISP1183 provides SoftConnect

technology through an integrated 1.5 kΩ pull-up resistor (see Section 8.4).

8.7 PLL clock multiplier

A 6 MHz-to-48 MHz clock multiplier Phase-Locked Loop (PLL) is integrated on-chip.

This allows for the use of a low-cost 6 MHz crystal, which also minimizes EMI. No

external components are required for the operation of the PLL.

8.8 PIO and DMA interfaces

A generic Parallel I/O (PIO) interface is deﬁned for speed and ease-of-use. It also

allows direct interfacing to most microcontrollers. To a microcontroller, the ISP1183

appears as a memory device with an 8-bit data bus and a 1-bit address bus. The

ISP1183 supports nonmultiplexed address and data buses.

The ISP1183 can also be conﬁgured as a Direct Memory Access (DMA) slave device

to allow more efﬁcient data transfer. One of the 14 endpoint FIFOs may directly

transfer data to or from the local shared memory. The DMA interface can be

independently conﬁgured from the PIO interface.

It can be directly interfaced to microprocessors or microcontrollers with I/O voltage

range as low as 1.65 V.

8.9 V_BUSindicator

The ISP1183 indicates the availability of V_BUSusing the V_BUSpin. When V_BUSis

available (at pin V_BUS), pin VBUSDET_N will output LOW. When V_BUSis not available

(at pin V_BUS), pin VBUSDET_N will output HIGH. Pin VBUSDET_N will change from

HIGH-to-LOW level in approximately 2.5 ms to 3.5 ms. See Section 19.

8.10 Operation modes

The ISP1183 can be operated in several operation modes as given in Table 3.

Table 3:

ISP1183 operation modes

Pin name

Plug-out

state

Dead state

Reset state

Plug-in state Normal state

V_BUS

0 V

1.8 V

X

5 V

1.8 V

L

5 V

1.8 V

L

5 V

1.8 V

L

V_DD(I/O)

WAKEUP

RESET_N

INT_N

0 V

X

L^[1]

L

H

[2]

H

-

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ISP1183

Low-power USB interface device with DMA

Philips Semiconductors

Table 3:

ISP1183 operation modes…continued

Pin name

Plug-out

state

Dead state

Reset state

Plug-in state Normal state

SUSPEND

VBUSDET_N

DATA

H

L^[1]

L

L^[3]

L

-

H

H -> L^[4]

Hi-Z

[1] Not driven LOW. There is, however, no current ﬂow through the pads because no I/O supply voltage is

available. Therefore, no potential will develop at the output.

[2] During the normal operation, when V_BUSis available, pin SUSPEND is LOW. If there is no activity on

the USB bus for 3 ms or more, a suspend interrupt is generated on pin INT_N. On receiving the

suspend interrupt, the external processor issues a GOSUSP command to the device. Once the

GOSUSP command is issued by the processor, the device starts to prepare itself to go to the suspend

mode. During suspend, to reduce power consumption, the internal clocks can be shut down. Once the

device is completely ready to go into the suspend mode, it will assert pin SUSPEND HIGH and go into

the suspend mode. The typical time between the issuing of the GOSUSP command to the device and

the device asserting pin SUSPEND HIGH is approximately 2 ms.

[3] Independent of the external reset. Depends only on the power-on reset.

[4] On connecting the USB cable (V_BUS), pin VBUSDET_N will change from HIGH level to LOW level in

approximately 2.5 ms to 3.5 ms.

8.11 Power supply

The ISP1183 is powered from a single supply voltage, ranging from 4.0 V to 5.5 V. An

integrated voltage regulator provides a 3.3 V supply voltage for the internal logic and

the USB transceiver. This voltage is available at pin V_REG(3V3)for connecting an

external pull-up resistor on USB connection pin DP. See Figure 3.

The ISP1183 can also be operated from a 3.0 V to 3.6 V supply, as shown in

Figure 4. In this case, the internal voltage regulator is disabled and pin V_REG(3V3)

must be connected to V_BUS. For details, see Section 19.

V

4.0 V to 5.5 V

BUS

8

REG(3V3)

12

V

3.0 V to 3.6 V

V

BUS

DD

V

8

DD(I/O)

21

1.65 V to 3.6 V

18

30

REG(3V3)

ISP1183

12

18

V

DD(I/O)

V

DD

21

V

30

DD(I/O)

004aaa295

004aaa296

Fig 3. ISP1183 with a 4.0 V to 5.5 V supply.

Fig 4. ISP1183 with a 3.0 V to 3.6 V supply.

8.12 Crystal oscillator

The ISP1183 has a crystal oscillator designed for a 6 MHz parallel-resonant crystal

(fundamental). A typical circuit is shown in Figure 5. Alternatively, an external clock

signal of 6 MHz can be applied to input XTAL1, while leaving output XTAL2 open.

9397 750 11804

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ISP1183

Low-power USB interface device with DMA

Philips Semiconductors

18 pF

XTAL2

6

7

ISP1183

6 MHz

XTAL1

18 pF

004aaa294

Fig 5. Typical oscillator circuit.

The 6 MHz oscillator frequency is multiplied to 48 MHz by an internal PLL.

In the suspend state, the crystal oscillator and the PLL are switched off to save

power. The oscillator operation is controlled by using bit CLKRUN in the Hardware

Conﬁguration register. CLKRUN switches the oscillator on and off.

8.13 Power-on reset

The ISP1183 has an internal power-on reset (POR) circuit. The clock signal normally

requires 3 ms to 4 ms to stabilize.

The triggering voltage of the POR circuit is 0.5 V nominal. A POR is automatically

generated when V_DD(I/O)goes below the trigger voltage for a duration longer than

50 µs.

POR

V

DD(I/O)

≤ 350 µs

2 ms

0.5 V

0 V

t

2

1

004aaa390

t₁: clock is running

t₂: registers are accessible

Fig 6. POR timing.

POR

EXTERNAL CLOCK

004aaa365

A

Stable external clock available at A.

Fig 7. Clock with respect to the external POR.

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ISP1183

Low-power USB interface device with DMA

Philips Semiconductors

A hardware reset disables all USB endpoints and clears all Endpoint Conﬁguration

registers (ECRs), except for the control endpoint that is ﬁxed and always enabled.

Section 10.3 explains how to (re)initialize endpoints.

9. Interrupts

Figure 8 shows the interrupt logic of the ISP1183. Each of the indicated USB events

is logged in a status bit of the Interrupt register. Corresponding bits in the Interrupt

Enable register determine whether an event will generate an interrupt.

Interrupts can be masked globally using bit INTENA of the Mode register (see

Table 18).

The signaling mode of output INT is controlled by bit INTLVL of the Hardware

Conﬁguration register (see Table 20). Default settings after reset is level mode. When

pulse mode is selected, a pulse of 166 ns is generated when the OR-ed combination

of all interrupt bits changes from logic 0 to logic 1.

(clear EPn interrupt; reading EPn

status register will set this signal)

(clear SUSPEND interrupt; reading

interrupt register will set this signal)

(clear RESET interrupt; reading

interrupt register will set this signal)

reset interrupt source

IERST

IESUSP

IERESM

RESET

suspend interrupt source

SUSPND

RESUME

SOF

.

IESOF

.

INTENA

IEP14

...

EP14

...

PULSE

GENERATOR

.

device mode

register

.

1

0

IEP0IN

EP0IN

EPn interrupt source

INT

IEP0OUT

EP0OUT

INTLVL

004aaa255

interrupt register

hardware configuration

register

RESET

Fig 8. Interrupt logic.

Bits SUSPND, RESET, RESUME, SP_EOT, EOT and SOF are cleared when the

Interrupt register is read. The endpoint bits (EP0OUT to EP14) are cleared when the

associated Endpoint Status register is read.

Bit BUSTATUS follows the USB bus status exactly, allowing the ﬁrmware to get the

current bus status when reading the Interrupt register.

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ISP1183

Low-power USB interface device with DMA

Philips Semiconductors

SETUP and OUT token interrupts are generated after the ISP1183 has

acknowledged the associated data packet. In the bulk transfer mode, the ISP1183 will

issue interrupts for every ACK received for an OUT token or transmitted for an IN

token.

In the isochronous mode, an interrupt is issued on each packet transaction. The

ﬁrmware is responsible for timing synchronization with the host. This can be done

using the Pseudo Start-Of-Frame (PSOF) interrupt, enabled using bit IEPSOF in the

Interrupt Enable register. If a Start-Of-Frame is lost, PSOF interrupts are generated

every 1 ms. This allows the ﬁrmware to keep data transfer synchronized with the host.

After three missed SOF events, the ISP1183 will enter the suspend state.

An alternative way of handling the isochronous data transfer is to enable both the

SOF and PSOF interrupts and disable the interrupt for each isochronous endpoint.

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ISP1183

Low-power USB interface device with DMA

Philips Semiconductors

10. Endpoint description

Each USB device is logically composed of several independent endpoints. An

endpoint acts as a terminus of a communication ﬂow between the host and the

device. At design time, each endpoint is assigned a unique number (endpoint

identiﬁer, see Table 4). The combination of the device address (given by the host

during enumeration), the endpoint number, and the transfer direction allows each

endpoint to be uniquely referenced.

The ISP1183 has 16 endpoints: endpoint 0 (control IN and OUT) plus 14 conﬁgurable

endpoints, which can be individually deﬁned as interrupt, bulk or isochronous—IN or

OUT. Each enabled endpoint has an associated FIFO, which can be accessed either

using the parallel I/O interface or DMA.

10.1 Endpoint access

Table 4 lists the endpoint access modes and programmability. All endpoints support

I/O mode access. Endpoints 1 to 14 also support DMA access. FIFO DMA access is

selected and enabled through bits EPDIX[3:0] and DMAEN of the DMA Conﬁguration

register. A detailed description of the DMA operation is given in Section 11.

Table 4:

Endpoint access and programmability

Endpoint

identiﬁer

FIFO size (bytes)^[1]

Double buffering I/O mode

access

DMA mode

access

Endpoint type

0

64 (ﬁxed)

no

yes

no

control OUT^[2]

control IN^[2]

0

64 (ﬁxed)

no

yes

no

1 to 14

programmable

supported

programmable

[1] The total amount of FIFO storage allocated to enabled endpoints must not exceed 2462 bytes.

[2] IN: input for the USB host (ISP1183 transmits); OUT: output from the USB host (ISP1183 receives). The data ﬂow direction is

determined by bit EPDIR in the Endpoint Conﬁguration register.

10.2 Endpoint FIFO size

The FIFO size determines the maximum packet size that the hardware can support

for a given endpoint. Only enabled endpoints are allocated space in the shared FIFO

storage, disabled endpoints have zero bytes. Table 5 lists programmable FIFO sizes.

The following bits in the Endpoint Conﬁguration register (ECR) affect FIFO allocation:

• Endpoint enable bit (FIFOEN)

• Size bits of an enabled endpoint (FFOSZ[3:0])

• Isochronous bit of an enabled endpoint (FFOISO).

Remark: Register changes that affect the allocation of the shared FIFO storage

among endpoints must not be made while valid data is present in any FIFO of the

enabled endpoints. Such changes will render all FIFO contents undeﬁned.

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ISP1183

Low-power USB interface device with DMA

Philips Semiconductors

Table 5:

Programmable FIFO size

Nonisochronous

FFOSZ[3:0]

Isochronous

16 bytes

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

8 bytes

16 bytes

32 bytes

64 bytes

reserved

32 bytes

48 bytes

64 bytes

96 bytes

128 bytes

160 bytes

192 bytes

256 bytes

320 bytes

384 bytes

512 bytes

640 bytes

768 bytes

896 bytes

1023 bytes

Each programmable FIFO can be independently conﬁgured through its ECR. The

total physical size of all enabled endpoints (IN plus OUT), however, must not exceed

2462 bytes.

Table 6 shows an example of a conﬁguration ﬁtting in the maximum available space of

2462 bytes. The total number of logical bytes in the example is 1311. The physical

storage capacity used for double buffering is managed by the device hardware and is

transparent to the user.

Table 6:

Memory conﬁguration example

Physical size

(bytes)

Logical size

(bytes)

Endpoint description

64

control IN (64-byte ﬁxed)

64

control OUT (64-byte ﬁxed)

double-buffered 1023-byte isochronous endpoint

16-byte interrupt OUT

2046

16

1023

16

16-byte interrupt IN

128

64

double-buffered 64-byte bulk OUT

double-buffered 64-byte bulk IN

64

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ISP1183

Low-power USB interface device with DMA

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10.3 Endpoint initialization

In response to the standard USB request Set Interface, the ﬁrmware must program all

16 ECRs of the ISP1183 in sequence (see Table 4), whether the endpoints are

enabled or not. The hardware will then automatically allocate FIFO storage space.

If all endpoints have been successfully conﬁgured, the ﬁrmware must return an empty

packet to the control IN endpoint to acknowledge success to the host. If there are

errors in the endpoint conﬁguration, the ﬁrmware must stall the control IN endpoint.

When reset by hardware or through the USB bus, the ISP1183 disables all endpoints

and clears all ECRs, except for the control endpoint, which is ﬁxed and always

enabled.

Endpoint initialization can be done at any time. It is, however, valid only after

enumeration.

10.4 Endpoint I/O mode access

When an endpoint event occurs (a packet is transmitted or received), the associated

endpoint interrupt bits (EPn) of the Interrupt register (IR) are set by the SIE. The

ﬁrmware then responds to the interrupt and selects the endpoint for processing.

The endpoint interrupt bit is cleared when the Endpoint Status register (ESR) is read.

The ESR also contains information on the status of the endpoint buffer.

For an OUT (= receive) endpoint, the packet length and the packet data can be read

from the ISP1183 by using the Read Buffer command. When the whole packet is

read, the ﬁrmware sends a Clear Buffer command to enable the reception of new

packets.

For an IN (= transmit) endpoint, the packet length and data to be sent can be written

to the ISP1183 by using the Write Buffer command. When the whole packet is written

to the buffer, the ﬁrmware sends a Validate Buffer command to enable data

transmission to the host.

10.5 Special actions on control endpoints

Control endpoints require special ﬁrmware actions. The arrival of a SETUP packet

ﬂushes the IN buffer and disables the Validate Buffer and Clear Buffer commands for

the control IN and OUT endpoints. The microcontroller needs to re-enable these

commands by sending an Acknowledge Setup command to both control endpoints.

This ensures that the last SETUP packet stays in the buffer and that no packets can

be sent back to the host until the microcontroller has explicitly acknowledged that it

has seen the SETUP packet.

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11. DMA transfer

Direct Memory Access (DMA) is a method to transfer data from one location to

another in a computer system, without intervention of the central processor unit

(CPU). Many implementations of DMA exist. The ISP1183 supports two methods:

• 8237 compatible mode: based on the DMA subsystem of the IBM^®personal

computers (PC, AT and all its successors and clones); this architecture uses the

Intel^®8237 DMA controller and has separate address spaces for memory and I/O

• DACK-only mode: based on the DMA implementation in some embedded RISC

processors, which has a single address space for both memory and I/O.

The ISP1183 supports DMA transfer for all 14 conﬁgurable endpoints (see Table 4).

Only one endpoint can be selected at a time for DMA transfer. The DMA operation of

the ISP1183 can be interleaved with normal I/O mode access to other endpoints.

The following features are supported:

• Single-cycle or burst transfers (up to 16 bytes per cycle)

• Programmable transfer direction (read or write)

• Programmable signal levels on pins DREQ and DACK.

11.1 Selecting an endpoint for DMA transfer

The target endpoint for DMA access is selected through bits EPDIX[3:0] in the DMA

Conﬁguration register, see Table 7. The transfer direction (read or write) is

automatically set by bit EPDIR in the associated ECR, to match the selected endpoint

type (OUT endpoint: read; IN endpoint: write).

Asserting input DACK automatically selects the endpoint speciﬁed in the DMA

Conﬁguration register, regardless of the current endpoint used for I/O mode access.

Table 7:

Endpoint selection for DMA transfer

Endpoint

identiﬁer

EPDIX[3:0]

Transfer direction

EPDIR = 0

OUT: read

EPDIR = 1

IN: write

1

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

2

3

4

5

6

7

8

9

10

11

12

13

14

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11.2 8237 compatible mode

The 8237 compatible DMA mode is selected by clearing bit DAKOLY in the Hardware

Conﬁguration register (see Table 20). The pin functions for this mode are shown in

Table 8.

Table 8:

Symbol

DREQ

DACK

8237 compatible mode: pin functions

Description

DMA request

DMA acknowledge

read strobe

I/O

Function

O

I

ISP1183 requests a DMA transfer

DMA controller conﬁrms the transfer

instructs the ISP1183 to put data on the bus

instructs the ISP1183 to get data from the bus

RD_N

I

WR_N

write strobe

I

The DMA subsystem of an IBM-compatible PC is based on the Intel 8237 DMA

controller. It operates as a ‘ﬂy-by’ DMA controller: the data is not stored in the DMA

controller, but it is transferred between an I/O port and a memory address. A typical

example of the ISP1183 in the 8237-compatible DMA mode is given in Figure 9.

The 8237 has two control signals for each DMA channel: DREQ (DMA request) and

DACK_N (DMA acknowledge). General control signals are HRQ (hold request) and

HLDA (hold acknowledge). The bus operation is controlled using MEMR_N (memory

read), MEMW_N (memory write), IOR_N (I/O read) and IOW_N (I/O write).

MEMR_N

RAM

DATA[7:0]

MEMW_N

DMA

CONTROLLER

8237

CPU

ISP1183

DREQ

DACK

DREQ

HRQ

HLDA

DACK_N

HLDA

RD_N

WR_N

IOR_N

IOW_N

004aaa291

Fig 9. ISP1183 in the 8237-compatible DMA mode.

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The following example shows the steps that occur in a typical DMA transfer:

1. The ISP1183 receives a data packet in one of its endpoint FIFOs; the packet

must be transferred to memory address 1234H.

2. The ISP1183 asserts the DREQ signal requesting the 8237 for a DMA transfer.

3. The 8237 asks the CPU to release the bus by asserting the HRQ signal.

4. After completing the current instruction cycle, the CPU places the bus control

signals (MEMR_N, MEMW_N, IOR_N and IOW_N) and the address lines in

three-state and asserts HLDA to inform the 8237 that it has control of the bus.

5. The 8237 sets its address lines to 1234H and activates the MEMW_N and IOR_N

control signals.

6. The 8237 asserts DACK_N to inform the ISP1183 that it will start a DMA transfer.

7. The ISP1183 places the byte or word to be transferred on the data bus lines

because its RD_N signal was asserted by the 8237.

8. The 8237 waits one DMA clock period and then deasserts MEMW_N and

IOR_N. This latches and stores the byte or word at the desired memory location.

It also informs the ISP1183 that the data on the bus lines has been transferred.

9. The ISP1183 deasserts the DREQ signal to indicate to the 8237 that DMA is no

longer needed. In the single cycle mode this is done after each byte or word, in

the burst mode following the last transferred byte or word of the DMA cycle.

10. The 8237 deasserts the DACK_N output indicating that the ISP1183 must stop

placing data on the bus.

11. The 8237 places the bus control signals (MEMR_N, MEMW_N, IOR_N and

IOW_N) and the address lines in three-state and deasserts the HRQ signal,

informing the CPU that it has released the bus.

12. The CPU acknowledges control of the bus by deasserting HLDA. After activating

the bus control lines (MEMR_N, MEMW_N, IOR_N and IOW_N) and the address

lines, the CPU resumes the execution of instructions.

For a typical bulk transfer, the above process is repeated 64 times, once for each

byte. After each byte, the address register in the DMA controller is incremented and

the byte counter is decremented.

11.3 DACK-only mode

The DACK-only DMA mode is selected by setting bit DAKOLY in the Hardware

Conﬁguration register (see Table 20). The pin functions for this mode are shown in

Table 9. A typical example of the ISP1183 in the DACK-only DMA mode is given in

Figure 10.

Table 9:

Symbol

DREQ

DACK-only mode: pin functions

Description

I/O

O

I

Function

DMA request

ISP1183 requests a DMA transfer

DACK

DMA acknowledge

DMA controller conﬁrms the transfer;

also functions as data strobe

RD_N

WR_N

read strobe

write strobe

I

not used

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In the DACK-only mode, the ISP1183 uses the DACK signal as data strobe. Input

signals RD_N and WR_N are ignored. This mode is used in CPU systems that have a

single address space for memory and I/O access. Such systems have no separate

MEMW_N and MEMR_N signals: the RD_N and WR_N signals are also used as

memory data strobes.

ISP1183

DMA

CONTROLLER

CPU

DREQ

DREQ_N

DACK_N

DACK

HRQ

HLDA

HRQ

HLDA

RD_N

WR_N

RAM

DATA[7:0]

004aaa292

Fig 10. ISP1183 in the DACK-only DMA mode.

11.4 End-Of-Transfer conditions

11.4.1 Bulk endpoints

A DMA transfer to or from a bulk endpoint can be terminated by any of the following

conditions (for bit names, refer to the DMA Conﬁguration register in Table 32):

• The DMA transfer completes as programmed in the DMA Counter register

(CNTREN = 1)

• A short packet is received on an enabled OUT endpoint (SHORTP = 1)

• DMA operation is disabled by clearing bit DMAEN.

DMA Counter register: An EOT from the DMA Counter register is enabled by setting

bit CNTREN in the DMA Conﬁguration register. The ISP1183 has a 16-bit DMA

Counter register, which speciﬁes the number of bytes to be transferred. When DMA is

enabled (DMAEN = 1), the internal DMA counter is loaded with the value from the

DMA Counter register. When the internal counter completes the transfer as

programmed in the DMA counter, an EOT condition is generated and the DMA

operation stops.

Short packet: Normally, the transfer byte count must be set though a control

endpoint before any DMA transfer occurs. When a short packet has been enabled as

EOT indicator (SHORTP = 1), the transfer size is determined by the presence of a

short packet in the data. This mechanism permits the use of a fully autonomous data

transfer protocol.

When reading from an OUT endpoint, reception of a short packet at an OUT token

will stop the DMA operation after transferring the data bytes of this packet.

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Table 10: Summary of EOT conditions for a bulk endpoint

EOT condition

OUT endpoint

IN endpoint

DMA Counter register

transfer completes as

programmed in the DMA

Counter register

transfer completes as

programmed in the DMA

Counter register

Short packet

short packet is received and counter reaches zero in the

transferred

DMAEN = 0^[1]

middle of the buffer

DMAEN = 0^[1]

DMAEN bit in DMA

Conﬁguration register

[1] The DMA transfer stops. No interrupt, however, is generated.

11.4.2 Isochronous endpoints

A DMA transfer to or from an isochronous endpoint can be terminated by any of the

following conditions (for bit names refer to the DMA Conﬁguration register in

Table 32):

• The DMA transfer completes as programmed in the DMA Counter register

(CNTREN = 1)

• DMA operation is disabled by clearing bit DMAEN.

Table 11: Recommended EOT usage for isochronous endpoints

EOT condition

OUT endpoint

do not use

preferred

IN endpoint

preferred

DMA Counter register zero

Clear DMAEN bit

do not use

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12. Suspend and resume

12.1 Suspend conditions

The ISP1183 detects a USB suspend status when a constant idle state is present on

the USB bus for more than 3 ms.

The bus-powered devices that are suspended must not consume more than 500 µA

of current. This is achieved by shutting down power to system components or

supplying them with a reduced voltage.

The steps leading up to suspend status are as follows:

1. On detection of a wakeup-to-suspend transition, the ISP1183 sets bit SUSPND in

the Interrupt register. This will generate an interrupt if bit IESUSP in the Interrupt

Enable register is set.

2. When the ﬁrmware detects a suspend condition, it must prepare all system

components for the suspend state:

a. All signals connected to the ISP1183 must enter appropriate states to meet

the power consumption requirements of the suspend state.

b. All input pins of the ISP1183 must have a CMOS LOW or HIGH level.

3. In the interrupt service routine, the ﬁrmware must check the current status of the

USB bus. When bit BUSTATUS in the Interrupt register is logic 0, the USB bus

has left the suspend mode and the process must be aborted. Otherwise, the next

step can be executed.

4. To meet the suspend current requirements for a bus-powered device, the internal

clocks must be switched off by clearing bit CLKRUN in the Hardware

Conﬁguration register.

5. When the ﬁrmware has set and cleared bit GOSUSP in the Mode register, the

ISP1183 enters the suspend state. In powered-off application, the ISP1183

asserts output SUSPEND and switches off the internal clocks after 2 ms.

Figure 11 shows a typical timing diagram.

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A

C

> 5 ms

10 ms

idle state

K-state

USB BUS

INT_N

> 3 ms

suspend

interrupt

resume

interrupt

D

GOSUSP

WAKEUP

B

SUSPEND

004aaa359

0.5 ms to 3.5 ms

1.8 ms to 2.2 ms

Fig 11. Suspend and resume timing.

In Figure 11:

• A: indicates the point at which the USB bus enters the idle state.

• B: indicates resume condition, which can be a 20 ms K-state on the USB bus, a

HIGH level on pin WAKEUP, or a LOW level on pin CS_N.

• C: indicates remote wake-up. The ISP1183 will drive a K-state on the USB bus for

10 ms after pin WAKEUP goes HIGH or pin CS_N goes LOW.

• D: after detecting the suspend interrupt, set and clear bit GOSUSP in the Mode

register.

12.1.1 Powered-off application

Figure 12 shows a typical bus-powered modem application using the ISP1183. The

SUSPEND output switches off power to the microcontroller and other external circuits

during the suspend state. The ISP1183 is woken up through the USB bus (global

resume) or by the ring detection circuit on the telephone line.

V

BUS

V

CC

8031

RST

V

BUS

DP

USB

DM

ISP1183

SUSPEND

RING DETECTION

LINE

WAKEUP

004aaa293

Fig 12. SUSPEND and WAKEUP signals in a powered-off modem application.

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12.2 Resume conditions

A wake-up from the suspend state is initiated either by the USB host or by the

application:

• USB host: drives a K-state on the USB bus (global resume)

• Application: remote wake-up through a HIGH level on input WAKEUP or a LOW

level on input CS_N (if enabled using bit WKUPCS in the Hardware Conﬁguration

register). Wake-up on CS_N will work only if V_BUSis present.

The steps of a wake-up sequence are as follows:

1. The internal oscillator and the PLL multiplier are re-enabled. When stabilized, the

clock signals are routed to all internal circuits of the ISP1183.

2. The SUSPEND output is deasserted, and bit RESUME in the Interrupt register is

set. This will generate an interrupt if bit IERESUME in the Interrupt Enable

register is set.

3. Maximum 15 ms after starting the wake-up sequence, the ISP1183 resumes its

normal functionality.

4. In case of a remote wake-up, the ISP1183 drives a K-state on the USB bus for

10 ms.

5. Following the deassertion of output SUSPEND, the application restores itself and

other system components to the normal operating mode.

6. After wake-up, the internal registers of the ISP1183 are write-protected to prevent

corruption by inadvertent writing during power-up of external components. The

ﬁrmware must send an Unlock Device command to the ISP1183 to restore its full

functionality. For more details, see Section 13.4.2.

12.3 Control bits in suspend and resume

Table 12: Summary of control bits

Register

Bit

Function

Interrupt

SUSPND

BUSTATUS

a transition from awake to the suspend state was detected

monitors USB bus status (logic 1 = suspend); used when

interrupt is serviced

RESUME

a transition from suspend to the resume state was detected

enables output INT to signal the suspend state

Interrupt Enable IESUSP

IERESUME enables output INT to signal the resume state

Mode

SOFTCT

GOSUSP

EXTPUL

WKUPCS

PWROFF

all

enables SoftConnect pull-up resistor to USB bus

a HIGH-to-LOW transition enables the suspend state

selects internal (SoftConnect) or external pull-up resistor

enables wake-up on LOW level of input CS_N

Hardware

Conﬁguration

selects powered-off mode during the suspend state

Unlock

sending data AA37H unlocks the internal registers for

writing after a resume

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13. Commands and registers

The functions and registers of the ISP1183 are accessed using commands, which

consist of a command code followed by optional data bytes (read or write action). An

overview of the available commands and registers is given in Table 13.

A complete access consists of two phases:

1. Command phase: when address pin A0 = HIGH, the ISP1183 interprets the

data on the lower byte of the bus pins D[7:0] as a command code. Commands

without a data phase are immediately executed.

2. Data phase (optional): when address pin A0 = LOW, the ISP1183 transfers the

data on the bus to or from a register or endpoint FIFO. Multibyte registers are

accessed least signiﬁcant byte or word ﬁrst.

Table 13: Command and register summary

Name

Destination

Code

(hex)

Transaction

Reference

Initialization commands

Write Control OUT

Conﬁguration

Endpoint Conﬁguration

register endpoint 0 OUT

20

21

write 1 byte

Section 13.1.1 on page 27

Write Control IN Conﬁguration

Endpoint Conﬁguration

register endpoint 0 IN

Write Endpoint n Conﬁguration Endpoint Conﬁguration

22 to 2F write 1 byte

(n = 1 to 14)

register endpoints 1 to 14

Read Control OUT

Conﬁguration

Endpoint Conﬁguration

register endpoint 0 OUT

30

31

read 1 byte

Read Control IN Conﬁguration

Endpoint Conﬁguration

register endpoint 0 IN

Read Endpoint n Conﬁguration Endpoint Conﬁguration

32 to 3F read 1 byte

(n = 1 to 14)

register endpoints 1 to 14

Write or read Device Address

Write or read Mode register

Address register

B6/B7

B8/B9

BA/BB

write or read 1 byte Section 13.1.2 on page 28

write or read 1 byte Section 13.1.3 on page 29

write or read 2 bytes Section 13.1.4 on page 29

Mode register

Write or read Hardware

Conﬁguration

Hardware Conﬁguration

register

Write or read Interrupt Enable

register

Interrupt Enable register C2/C3

resets all registers F6

write or read 4 bytes Section 13.1.5 on page 30

Reset Device

-

Section 13.1.6 on page 32

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Table 13: Command and register summary…continued

Name

Destination

Code

(hex)

Transaction

Reference

Data ﬂow commands

Write Control OUT Buffer

illegal: endpoint is

read-only

(00)

01

-

Section 13.2.1 on page 32

Write Control IN Buffer

FIFO endpoint 0 IN

N ≤ 64 bytes

Write Endpoint n Buffer

(n = 1 to 14)

FIFO endpoints 1 to 14

(IN endpoints only)

02 to 0F isochronous:

N ≤ 1023 bytes

interrupt or bulk:

N ≤ 64 bytes

Read Control OUT Buffer

Read Control IN Buffer

FIFO endpoint 0 OUT

10

N ≤ 64 bytes

illegal: endpoint is

write-only

(11)

-

Read Endpoint n Buffer

(n = 1 to 14)

FIFO endpoints 1 to 14

(OUTendpoints only)

12 to 1F isochronous:

N ≤ 1023 bytes

interrupt or bulk:

N ≤ 64 bytes

Stall Control OUT Endpoint

Stall Control IN Endpoint

Stall Endpoint n (n = 1 to 14)

Read Control OUT Status

Endpoint 0 OUT

Endpoint 0 IN

40

-

Section 13.2.3 on page 34

Section 13.2.2 on page 33

41

-

Endpoints 1 to 14

42 to 4F

50

-

Endpoint Status register

endpoint 0 OUT

read 1 byte

Read Control IN Status

Endpoint Status register

endpoint 0 IN

51

read 1 byte

Read Endpoint n Status

(n = 1 to 14)

Endpoint Status register n 52 to 5F read 1 byte

endpoints 1 to 14

Validate Control OUT Buffer

illegal: IN endpoints

only^[1]

(60)

-

Section 13.2.4 on page 34

Section 13.2.5 on page 35

Validate Control IN Buffer

FIFO endpoint 0 IN

61

-

Validate Endpoint n Buffer

(n = 1 to 14)

FIFO endpoints 1 to 14

(IN endpoints only)^[1]

62 to 6F

Clear Control OUT Buffer

Clear Control IN Buffer

FIFO endpoint 0 OUT

illegal^[2]

70

-

(71)

Clear Endpoint n Buffer

(n = 1 to 14)

FIFO endpoints 1 to 14

(OUTendpoints only)^[2]

72 to 7F

Unstall Control OUT Endpoint

Unstall Control IN Endpoint

Endpoint 0 OUT

Endpoint 0 IN

80

-

Section 13.2.3 on page 34

Section 13.2.6 on page 35

81

-

Unstall Endpoint n (n = 1 to 14) Endpoints 1 to 14

Check Control OUT Status^[3]

82 to 8F

D0

-

Endpoint Status Image

register endpoint 0 OUT

read 1 byte

Check Control IN Status^[3]

Endpoint Status Image

register endpoint 0 IN

D1

read 1 byte

Check Endpoint n Status

(n = 1 to 14)^[3]

Endpoint Status Image

register n

D2 to DF read 1 byte

endpoints 1 to 14

Acknowledge Setup

Endpoint 0 IN and OUT

F4

-

Section 13.2.7 on page 36

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Table 13: Command and register summary…continued

Name

Destination

Code

(hex)

Transaction

Reference

DMA commands

Write or read DMA Function and DMA Function and

B2/B3

F0/F1

F2/F3

write or read 2 bytes Section 13.3.1 on page 36

write or read 2 bytes Section 13.3.2 on page 37

write or read 2 bytes Section 13.3.3 on page 38

Scratch register

Write or read DMA

Conﬁguration

DMA Conﬁguration

register

Write or read DMA Counter

General commands

DMA Counter register

Read Control OUT Error Code

Error Code register

endpoint 0 OUT

A0

A1

read 1 byte

Section 13.4.1 on page 38

Read Control IN Error Code

Error Code register

endpoint 0 IN

Read Endpoint n Error Code

(n = 1 to 14)

Error Code register

endpoints 1 to 14

A2 to AF read 1 byte

Unlock Device

all registers with write

access

B0

write 2 bytes

Section 13.4.2 on page 39

Read Frame Number

Read Chip ID

Frame Number register

Chip ID register

B4

B5

C0

read 1 or 2 bytes

read 2 bytes

Section 13.4.3 on page 40

Section 13.4.4 on page 41

Section 13.4.5 on page 41

Read Interrupt register

Interrupt register

read 4 bytes

[1] Validating an OUT endpoint buffer causes unpredictable behavior of the ISP1183.

[2] Clearing an IN endpoint buffer causes unpredictable behavior of the ISP1183.

[3] Reads a copy of the Status register: executing this command does not clear any status bits or interrupt bits.

13.1 Initialization commands

Initialization commands are used during the enumeration process of the USB

network. These commands are used to conﬁgure and enable the embedded

endpoints. They also set the USB assigned address of the ISP1183 and perform

device reset.

13.1.1 Endpoint Conﬁguration register (R/W: 30H–3FH/20H–2FH)

This command accesses the Endpoint Conﬁguration register (ECR) of the target

endpoint. It deﬁnes the endpoint type (isochronous or bulk/interrupt), direction

(OUT/IN), FIFO size and buffering scheme. It also enables the endpoint FIFO. The

register bit allocation is shown in Table 14. A bus reset will disable all endpoints.

The allocation of FIFO memory takes place only after all 16 endpoints have been

conﬁgured in sequence (from endpoint 0 OUT to endpoint 14). Although the control

endpoints have ﬁxed conﬁgurations, they must be included in the initialization

sequence and conﬁgured with their default values (see Table 4). Automatic FIFO

allocation starts when endpoint 14 is conﬁgured.

Remark: If any change is made to an endpoint conﬁguration that affects the allocated

memory (size, enable/disable), the FIFO memory contents of all endpoints become

invalid. Therefore, all valid data must be removed from enabled endpoints before

changing the conﬁguration.

Code (hex): 20 to 2F — write (control OUT, control IN, endpoints 1 to 14)

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Code (hex): 30 to 3F — read (control OUT, control IN, endpoints 1 to 14)

Transaction — write or read 1 byte

Table 14: Endpoint Conﬁguration register: bit allocation

Bit

7

FIFOEN

0

6

EPDIR

0

5

DBLBUF

0

4

FFOISO

0

3

2

1

0

Symbol

Reset^[1][2]

Access

FFOSZ[3:0]

0

R/W

[1] The reset value of the control OUT endpoint is ﬁxed as 0x83 for the Endpoint Conﬁguration register.

[2] The reset value of the control IN endpoint is ﬁxed as 0xC3 for the Endpoint Conﬁguration register.

Table 15: Endpoint Conﬁguration register: bit description

Bit

Symbol

Description

7

FIFOEN

Logic 1 indicates an enabled FIFO with allocated memory.

Logic 0 indicates a disabled FIFO (no bytes allocated).

6

EPDIR

This bit deﬁnes the endpoint direction (0 = OUT, 1 = IN). It also

determines the DMA transfer direction (0 = read, 1 = write).

5

4

DBLBUF

FFOISO

Logic 1 indicates that this endpoint has double buffering.

Logic 1 indicates an isochronous endpoint. Logic 0 indicates a

bulk or interrupt endpoint.

3 to 0

FFOSZ[3:0]

This ﬁeld speciﬁes the FIFO size according to Table 5.

13.1.2 Address register (R/W: B7H/B6H)

This command sets the USB assigned address in the Address register and enables

the USB device. The Address register bit allocation is shown in Table 16.

A USB bus reset sets the device address to 00H (internally) and enables the device.

The value of the Address register (accessible by the microcontroller) is not altered by

the bus reset. In response to the standard USB request (Set Address), the ﬁrmware

must issue a Write Device Address command, followed by sending an empty packet

to the host. The new device address is activated when the host acknowledges the

empty packet.

Code (hex): B6/B7 — write or read Address register

Transaction — write or read 1 byte

Table 16: Address register: bit allocation

Bit

7

DEVEN

0

6

5

4

3

2

1

0

Symbol

Reset

Access

DEVADR[6:0]

0

R/W

Table 17: Address register: bit description

Bit

7

Symbol

Description

DEVEN

Logic 1 enables the device.

6 to 0

DEVADR[6:0] This ﬁeld speciﬁes the USB device address.

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13.1.3 Mode register (R/W: B9H/B8H)

This command accesses the ISP1183 Mode register, which consists of 1 byte (bit

allocation: see Table 18). In the 16-bit bus mode, the upper byte is ignored.

The Mode register controls the DMA bus width, resume and suspend modes,

interrupt activity and SoftConnect operation. It can be used to enable debug mode, in

which all errors and Not Acknowledge (NAK) conditions will generate an interrupt.

Code (hex): B8/B9 — write or read Mode register

Transaction — write or read 1 byte

Table 18: Mode register: bit allocation

Bit

7

reserved

0^[1]

6

reserved

0

5

GOSUSP

0

4

reserved

0

3

INTENA

0^[1]

2

DBGMOD

0^[1]

1

reserved

0^[1]

0

SOFTCT

0^[1]

Symbol

Reset

Access

R/W

[1] Unchanged by a bus reset.

Table 19: Mode register: bit description

Bit

7

Symbol

reserved

-

Description

This bit should be always written as logic 0.

reserved

6

5

GOSUSP

-

Writing logic 1 followed by logic 0 will activate the suspend mode.

reserved

4

3

INTENA

DBGMOD

Logic 1 enables all interrupts. Bus reset value: unchanged.

2

Logic 1 enables the debug mode, in which all NAKs and errors

will generate an interrupt. Logic 0 selects normal operation, in

which interrupts are generated on every ACK (bulk endpoints) or

after every data transfer (isochronous endpoints). Bus reset

value: unchanged.

1

0

-

reserved

SOFTCT

Logic 1 enables SoftConnect (see Section 8.4). This bit is ignored

if EXTPUL = 1 in the Hardware Conﬁguration register (see

Table 20). Bus reset value: unchanged.

13.1.4 Hardware Conﬁguration register (R/W: BBH/BAH)

This command accesses the Hardware Conﬁguration register that consists of

2 bytes. The ﬁrst (lower) byte contains the device conﬁguration and control values,

the second (upper) byte holds the clock control bits and the clock division factor. The

bit allocation is given in Table 20. A bus reset will not change any of the programmed

bit values.

The Hardware Conﬁguration register controls the connection to the USB bus, clock

activity and power supply during the suspend state, output clock frequency, DMA

operating mode and pin conﬁgurations (polarity, signaling mode).

Code (hex): BA/BB — write or read Hardware Conﬁguration register

Transaction — write or read 2 bytes

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Table 20: Hardware Conﬁguration register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

reserved

EXTPUL

reserved

CLKRUN

reserved

0

R/W

7

0

R/W

6

1

R/W

5

0

R/W

4

0

R/W

2

1

R/W

1

R/W

0

R/W

3

WKUPCS

0

Symbol

Reset

Access

DAKOLY

0

DRQPOL

1

DAKPOL

0

reserved

0

reserved

1

INTLVL

0

reserved

0

R/W

Table 21: Hardware Conﬁguration register: bit description

Bit

15

14

Symbol

-

Description

reserved

EXTPUL

Logic 1 indicates that an external 1.5 kΩ pull-up resistor is used

on pin DP and that SoftConnect is not used. Bus reset value:

unchanged.

13

12

-

reserved

CLKRUN

Logic 1 indicates that the internal clocks are always running,

even during the suspend state. Logic 0 switches off the internal

oscillator and PLL, when they are not needed. During the

suspend state, this bit must be made logic 0 to meet the suspend

current requirements. The clock is stopped after a delay of

approximately 2 ms, following the setting of bit GOSUSP in the

Mode register. Bus reset value: unchanged.

11 to 8

7

-

reserved

DAKOLY

Logic 1 selects the DACK-only DMA mode. Logic 0 selects the

8237 compatible DMA mode. Bus reset value: unchanged.

6

5

DRQPOL

DAKPOL

Selects DREQ signal polarity (0 = active LOW, 1 = active HIGH).

Bus reset value: unchanged.

Selects DACK signal polarity (0 = active LOW, 1 = active HIGH).

Bus reset value: unchanged.

4

3

reserved

This bit should be always written as logic 0.

WKUPCS

Logic 1 enables remote wake-up through a LOW level on input

CS_N (For wake-up on CS_N to work, V_BUSmust be present).

Bus reset value: unchanged.

2

1

-

reserved

INTLVL

Selects the interrupt signaling mode on output INT (0 = level,

1 = pulsed). In the pulsed mode, an interrupt produces 166 ns

pulse. For details, see Section 12. Bus reset value: unchanged.

0

reserved

This bit should be always written as logic 0.

13.1.5 Interrupt Enable register (R/W: C3H/C2H)

This command individually enables or disables interrupts from all endpoints, as well

as interrupts caused by events on the USB bus (SOF, SOF lost, EOT, suspend,

resume, reset). A bus reset will not change any of the programmed bit values.

The command accesses the Interrupt Enable register that consists of 4 bytes. The bit

allocation is given in Table 22.

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Code (hex): C2/C3 — write or read Interrupt Enable register

Transaction — write or read 4 bytes

Table 22: Interrupt Enable register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved

0

R/W

23

0

R/W

22

0

R/W

21

0

R/W

19

0

R/W

18

0

R/W

17

0

R/W

16

R/W

20

Symbol

Reset

Access

Bit

IEP14

0

IEP13

0

IEP12

0

IEP11

0

IEP10

0

IEP9

0

IEP8

0

IEP7

0

R/W

15

R/W

14

R/W

13

R/W

12

R/W

11

R/W

10

R/W

9

R/W

8

Symbol

Reset

Access

Bit

IEP6

0

IEP5

0

IEP4

0

IEP3

0

IEP2

0

IEP1

0

IEP0IN

0

IEP0OUT

0

R/W

7

R/W

6

R/W

5

R/W

4

R/W

3

R/W

2

R/W

1

R/W

0

Symbol

Reset

Access

reserved

0

SP_IEEOT

0

IEPSOF

0

IESOF

0

IEEOT

0

IESUSP

0

IERESM

0

IERST

0

R/W

Table 23: Interrupt Enable register: bit description

Bit

31 to 24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

Symbol

-

Description

reserved; must write logic 0

IEP14

IEP13

IEP12

IEP11

IEP10

IEP9

Logic 1 enables interrupts from endpoint 14.

Logic 1 enables interrupts from endpoint 13.

Logic 1 enables interrupts from endpoint 12.

Logic 1 enables interrupts from endpoint 11.

Logic 1 enables interrupts from endpoint 10.

Logic 1 enables interrupts from endpoint 9.

Logic 1 enables interrupts from endpoint 8.

Logic 1 enables interrupts from endpoint 7.

Logic 1 enables interrupts from endpoint 6.

Logic 1 enables interrupts from endpoint 5.

Logic 1 enables interrupts from endpoint 4.

Logic 1 enables interrupts from endpoint 3.

Logic 1 enables interrupts from endpoint 2.

Logic 1 enables interrupts from endpoint 1.

IEP8

IEP7

IEP6

IEP5

IEP4

IEP3

IEP2

IEP1

IEP0IN

IEP0OUT

-

Logic 1 enables interrupts from the control IN endpoint.

Logic 1 enables interrupts from the control OUT endpoint.

reserved

8

7

6

SP_IEEOT

IEPSOF

IESOF

Logic 1 enables interrupt on detection of a short packet.

Logic 1 enables 1 ms interrupts on detection of Pseudo SOF.

Logic 1 enables interrupt on SOF detection.

5

4

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Table 23: Interrupt Enable register: bit description…continued

Bit

3

Symbol

IEEOT

Description

Logic 1 enables interrupt on EOT detection.

2

IESUSP

IERESM

IERST

Logic 1 enables interrupt on detection of a suspend state.

Logic 1 enables interrupt on detection of a resume state.

Logic 1 enables interrupt on detection of a bus reset.

1

0

13.1.6 Reset Device (F6H)

This command resets the ISP1183 in the same way as an external hardware reset

through input RESET_N. All registers are initialized to their reset values.

Code (hex): F6 — reset the device

Transaction — none

13.2 Data ﬂow commands

Data ﬂow commands are used to manage the data transmission between USB

endpoints and the system microcontroller. Much of the data ﬂow is initiated through

an interrupt to the microcontroller. The data ﬂow commands are used to access the

endpoints and determine whether the endpoint FIFOs contain valid data.

Remark: The IN buffer of an endpoint contains input data for the host. The OUT

buffer receives output data from the host.

13.2.1 Endpoint Buffer (R/W: 10H, 12H–1FH/01H–0FH)

This command accesses endpoint FIFO buffers for reading or writing. First, the buffer

pointer is reset to the beginning of the buffer. Following the command, a maximum of

(N + 2) bytes can be written or read, N representing the size of the endpoint buffer.

After each read or write action, the buffer pointer is automatically incremented by one

(8-bit bus width).

In DMA access, the ﬁrst two bytes (the packet length) are skipped: transfers start at

the third byte of the endpoint buffer. When reading, the ISP1183 can detect the last

byte through the EOP condition. When writing to a bulk or interrupt endpoint, the

endpoint buffer must be completely ﬁlled before sending data to the host.

Remark: Reading data after a Write Endpoint Buffer command or writing data after a

Read Endpoint Buffer command data will cause unpredictable behavior of the

ISP1183.

Code (hex): 01 to 0F — write (control IN, endpoints 1 to 14)

Code (hex): 10, 12 to 1F — read (control OUT, endpoints 1 to 14)

Transaction — write or read maximum (N + 2) bytes (isochronous endpoint:

N ≤ 1023, bulk or interrupt endpoint: N ≤ 64)

The data in the endpoint FIFO must be organized as shown in Table 24. Examples of

endpoint FIFO access are given in Table 25.

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Table 24: Endpoint FIFO organization

Byte # (8-bit bus)

Description

0

packet length (lower byte)

packet length (upper byte)

data byte 1

1

2

3

data byte 2

:

(N + 1)

data byte N

Table 25: Example of endpoint FIFO access

A0

Phase

command

data

Bus lines

D[7:0]

:

Byte #

Description

HIGH

LOW

:

-

command code (00H to 1FH)

packet length (lower byte)

packet length (upper byte)

data byte 1

0

1

2

3

4

5

:

data

data byte 2

data

data byte 3

data

data byte 4

:

Remark: There is no protection against writing or reading past a buffer’s boundary,

against writing into an OUT buffer, or reading from an IN buffer. Any of these actions

could cause an incorrect operation. Data residing in an OUT buffer is meaningful only

after a successful transaction. Exception: during DMA access of a double-buffered

endpoint, the buffer pointer automatically points to the secondary buffer after

reaching the end of the primary buffer.

13.2.2 Endpoint Status register (R: 50H–5FH)

This command reads the status of an endpoint FIFO. The command accesses the

Endpoint Status register, the bit allocation of which is shown in Table 26. Reading the

Endpoint Status register will clear the interrupt bit set for the corresponding endpoint

in the Interrupt register (see Table 46).

All bits of the Endpoint Status register are read-only. Bit EPSTAL is controlled by the

Stall or Unstall commands and by the reception of a SETUP token

(see Section 13.2.3).

Code (hex): 50 to 5F — read (control OUT, control IN, endpoints 1 to 14)

Transaction — read 1 byte

Table 26: Endpoint Status register: bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

EPSTAL

EPFULL1

EPFULL0

DATA_PID

OVER

SETUPT

CPUBUF

reserved

WRITE

Reset

0

Access

R

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Table 27: Endpoint Status register: bit description

Bit

Symbol

Description

7

EPSTAL

This bit indicates whether the endpoint is stalled or not

(1 = stalled, 0 = not stalled).

Set by a Stall Endpoint command. Cleared by an Unstall

Endpoint command. The endpoint is automatically unstalled on

reception of a SETUP token.

6

5

4

EPFULL1

EPFULL0

DATA_PID

Logic 1 indicates that the secondary endpoint buffer is full.

Logic 1 indicates that the primary endpoint buffer is full.

This bit indicates the data PID of the next packet

(0 = DATA0 PID, 1 = DATA1 PID).

3

OVERWRITE This bit is set by hardware. Logic 1 indicates that a new Setup

packet has overwritten the previous setup information, before it

was acknowledged or before the endpoint was stalled. This bit is

cleared by reading, if writing the setup data has ﬁnished.

Firmware must check this bit before sending an Acknowledge

Setup command or stalling the endpoint. On reading logic 1, the

ﬁrmware must stop ongoing setup actions and wait for a new

Setup packet.

2

1

SETUPT

CPUBUF

Logic 1 indicates that the buffer contains a Setup packet.

This bit indicates which buffer is currently selected for CPU

access (0 = primary buffer, 1 = secondary buffer).

0

-

reserved

13.2.3 Stall or Unstall Endpoint (40H–4FH/80H–8FH)

These commands are used to stall or unstall an endpoint. The commands modify the

content of the Endpoint Status register (see Table 26).

A stalled control endpoint is automatically unstalled when it receives a SETUP token,

regardless of the packet content. If the endpoint should stay in its stalled state, the

microcontroller can restall it with the Stall Endpoint command.

When a stalled endpoint is unstalled (either by the Unstall Endpoint command or by

receiving a SETUP token), it is also reinitialized. This ﬂushes the buffer: if it is an OUT

buffer, it waits for a DATA 0 PID; if it is an IN buffer, it writes a DATA 0 PID.

Code (hex): 40 to 4F — stall (control OUT, control IN, endpoints 1 to 14)

Code (hex): 80 to 8F — unstall (control OUT, control IN, endpoints 1 to 14)

Transaction — none

Remark: When unstalling a stalled endpoint, issue the unstall command two times.

The ﬁrst unstall command will update the Endpoint Status register in RAM. The

second unstall command will reset the buffer pointers.

13.2.4 Validate Endpoint Buffer (61H–6FH)

This command signals the presence of valid data for transmission to the USB host, by

setting the Buffer Full ﬂag of the selected IN endpoint. This indicates that the data in

the buffer is valid and can be sent to the host, when the next IN token is received. For

a double-buffered endpoint, this command switches the current FIFO for CPU

access.

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Remark: For special aspects of the control IN endpoint, see Section 10.5.

Code (hex): 61 to 6F — validate endpoint buffer (control IN, endpoints 1 to 14)

Transaction — none

13.2.5 Clear Endpoint Buffer (70H, 72H–7FH)

This command unlocks and clears the buffer of the selected OUT endpoint, allowing

the reception of new packets. Reception of a complete packet causes the Buffer Full

ﬂag of an OUT endpoint to be set. Any subsequent packets are refused by returning a

NAK condition, until the buffer is unlocked using this command. For a double-buffered

endpoint, this command switches the current FIFO for CPU access.

Remark: For special aspects of the control OUT endpoint, see Section 10.5.

Code (hex): 70, 72 to 7F — clear endpoint buffer (control OUT, endpoints 1 to 14)

Transaction — none

13.2.6 Check Endpoint Status (D0H–DFH)

This command checks the status of the selected endpoint FIFO without clearing any

status or interrupt bits. The command accesses the Endpoint Status Image register,

which contains a copy of the Endpoint Status register. The bit allocation of the

Endpoint Status Image register is shown in Table 28.

Code (hex): D0 to DF — check status (control OUT, control IN, endpoints 1 to 14)

Transaction — write or read 1 byte

Table 28: Endpoint Status Image register: bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

EPSTAL

EPFULL1

EPFULL0

DATA_PID

OVER

SETUPT

CPUBUF

reserved

WRITE

Reset

0

Access

R

Table 29: Endpoint Status Image register: bit description

Bit

Symbol

Description

7

EPSTAL

This bit indicates whether the endpoint is stalled or not

(1 = stalled, 0 = not stalled).

6

5

4

EPFULL1

EPFULL0

DATA_PID

Logic 1 indicates that the secondary endpoint buffer is full.

Logic 1 indicates that the primary endpoint buffer is full.

This bit indicates the data PID of the next packet

(0 = DATA0 PID, 1 = DATA1 PID).

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Table 29: Endpoint Status Image register: bit description…continued

Bit

Symbol

Description

3

OVERWRITE This bit is set by hardware. Logic 1 indicates that a new Setup

packet has overwritten the previous setup information, before it

was acknowledged or before the endpoint was stalled. This bit is

cleared by reading, if writing the setup data has ﬁnished.

Firmware must check this bit before sending an Acknowledge

Setup command or stalling the endpoint. On reading logic 1, the

ﬁrmware must stop ongoing setup actions and wait for a new

Setup packet.

2

1

SETUPT

CPUBUF

Logic 1 indicates that the buffer contains a Setup packet.

This bit indicates which buffer is currently selected for CPU

access (0 = primary buffer, 1 = secondary buffer).

0

-

reserved

13.2.7 Acknowledge Setup (F4H)

This command acknowledges to the host that a SETUP packet was received. The

arrival of a SETUP packet disables the Validate Buffer and Clear Buffer commands

for the control IN and OUT endpoints. The microcontroller needs to re-enable these

commands by sending an Acknowledge Setup command, see Section 10.5.

Code (hex): F4 — acknowledge setup

Transaction — none

13.3 DMA commands

13.3.1 DMA Function and Scratch register (R/W: B3H/B2H)

This command accesses the 16-bit DMA Function and Scratch register, which can be

used by the ﬁrmware to save and restore information. For example, the device status

before powering down in the suspend state. The register bit allocation is given in

Table 30.

Code (hex): B2/B3 — write or read DMA Function and Scratch register

Transaction — write or read 2 bytes

Table 30: DMA Function and Scratch register: bit allocation

Bit

15

DMAEN

0

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

reserved

SFIRH[4:0]

0

R/W

6

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

R/W

7

Symbol

Reset

Access

SFIRL[7:0]

0

R/W

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Low-power USB interface device with DMA

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Table 31: DMA Function and Scratch register: bit description

Bit

Symbol

DMAEN

-

Description

15

Writing logic 1 enables DMA function.

reserved; must be logic 0

14 to 13

12 to 8

7 to 0

SFIRH[4:0]

SFIRL[7:0]

Scratch Information register (high byte)

Scratch Information register (low byte)

13.3.2 DMA Conﬁguration register (R/W: F1H/F0H)

This command deﬁnes the DMA conﬁguration of the ISP1183 and enables or

disables DMA transfers. The command accesses the DMA Conﬁguration register,

which consists of 2 bytes. The bit allocation is given in Table 32. A bus reset will clear

bit DMAEN (DMA disabled), all other bits remain unchanged.

Code (hex): F0/F1 — write or read DMA Conﬁguration

Transaction — write or read 2 bytes

Table 32: DMA Conﬁguration register: bit allocation

Bit

15

CNTREN

0^[1]

14

SHORTP

0^[1]

13

12

11

10

9

8

Symbol

Reset

Access

Bit

reserved

0^[1]

R/W

5

0^[1]

R/W

4

0^[1]

R/W

3

0^[1]

R/W

2

0^[1]

R/W

1

0^[1]

R/W

0

R/W

6

7

Symbol

EPDIX[3:0]

DMA

reserved

BURSTL[1:0]

START

Reset

0^[1]

0

0^[1]

Access

R/W

[1] Unchanged by a bus reset.

Table 33: DMA Conﬁguration register: bit description

Bit

Symbol

Description

15

CNTREN

Logic 1 enables the generation of an EOT condition, when the

DMA Counter register reaches zero. Bus reset value:

unchanged.

14

SHORTP

Logic 1 enables the short or empty packet mode. When

receiving (OUT endpoint) a short or empty packet, an EOT

condition is generated. When transmitting (IN endpoint), this bit

should be cleared. Bus reset value: unchanged.

13 to 8

7 to 4

-

reserved

EPDIX[3:0]

Indicates the destination endpoint for DMA, see Table 7.

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Low-power USB interface device with DMA

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Table 33: DMA Conﬁguration register: bit description…continued

Bit

Symbol

Description

3

DMASTART

Writing logic 1 starts DMA transfer. Logic 0 forces the end of an

ongoing DMA transfer. Reading this bit indicates whether DMA

is started (0 = DMA stopped, 1 = DMA started). This bit is

cleared by a bus reset.

2

-

reserved

1 to 0

BURSTL[1:0] Selects the DMA burst length:

00 — single-cycle mode (1 byte)

01 — burst mode (4 bytes)

10 — burst mode (8 bytes)

11 — burst mode (16 bytes).

Bus reset value: unchanged.

13.3.3 DMA Counter register (R/W: F3H/F2H)

This command accesses the DMA Counter register, which consists of 2 bytes. The bit

allocation is given in Table 34. Writing to the register sets the number of bytes for a

DMA transfer. Reading the register returns the number of remaining bytes in the

current transfer. A bus reset will not change the programmed bit values.

The internal DMA counter is automatically reloaded from the DMA Counter register

when DMA is re-enabled (DMAEN = 1). For more details, see Section 13.3.2.

Code (hex): F2/F3 — write or read DMA Counter register

Transaction — write or read 2 bytes

Table 34: DMA Counter register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

DMACRH[7:0]

0

R/W

7

0

R/W

6

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

Symbol

Reset

Access

DMACRL[7:0]

0

R/W

Table 35: DMA Counter register: bit description

Bit

Symbol

Description

15 to 8

7 to 0

DMACRH[7:0] DMA Counter register (high byte)

DMACRL[7:0] DMA Counter register (low byte)

13.4 General commands

13.4.1 Endpoint Error Code (R: A0H–AFH)

This command returns the status of the last transaction of the selected endpoint, as

stored in the Error Code register. Each new transaction overwrites the previous status

information. The bit allocation of the Error Code register is shown in Table 36.

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Low-power USB interface device with DMA

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Code (hex): A0 to AF — read error code (control OUT, control IN, endpoints 1 to 14)

Transaction — read 1 byte

Table 36: Error Code register: bit allocation

Bit

7

6

5

4

3

2

1

0

RTOK

0

Symbol

Reset

Access

UNREAD

DATA01

reserved

ERROR[3:0]

0

R

Table 37: Error Code register: bit description

Bit

Symbol

Description

7

UNREAD

Logic 1 indicates that a new event occurred before the previous

status was read.

6

DATA01

This bit indicates the PID type of the last successfully received

or transmitted packet (0 = DATA0 PID, 1 = DATA1 PID).

5

-

reserved

4 to 1

0

ERROR[3:0]

RTOK

Error code. For error description, see Table 38.

Logic 1 indicates that data was successfully received or

transmitted.

Table 38: Transaction error codes

Error code

(binary)

Description

0000

0001

0010

0011

no error

PID encoding error; bits 7 to 4 are not the inverse of bits 3 to 0

PID unknown; encoding is valid, but PID does not exist

unexpected packet; packet is not of the expected type (token, data, or

acknowledge), or is a SETUP token to a noncontrol endpoint

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

token CRC error

data CRC error

timeout error

babble error

unexpected end-of-packet

sent or received NAK (Not AcKnowledge)

sent Stall; a token was received, but the endpoint was stalled

overﬂow; the received packet was larger than the available buffer space

sent empty packet (ISO only)

bit stufﬁng error

sync error

wrong (unexpected) toggle bit in DATA PID; data was ignored

13.4.2 Unlock Device (B0H)

This command unlocks the ISP1183 from write-protection mode after a resume. In

the suspend state, all registers and FIFOs are write-protected to prevent data

corruption by external devices during a resume. Also, the register access for reading

is possible only after the Unlock Device command is executed.

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After waking up from the suspend state, the ﬁrmware must unlock the registers and

FIFOs using this command, by writing the unlock code (AA37H) into the Lock register

(8-bit bus: lower byte ﬁrst). The bit allocation of the Lock register is given in Table 39.

Code (hex): B0 — unlock the device

Transaction — write 2 bytes (unlock code)

Table 39: Lock register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

UNLOCKH[7:0] = AAH

1

W

7

0

W

6

1

W

5

0

W

4

1

W

3

0

W

2

1

W

1

0

W

0

Symbol

Reset

Access

UNLOCKL[7:0] = 37H

0

1

0

1

W

Table 40: Lock register: bit description

Bit

Symbol

Description

15 to 0

UNLOCK[15:0] Sending data AA37H unlocks the internal registers and FIFOs

for writing, following a resume.

13.4.3 Frame Number register (R: B4H)

This command returns the frame number of the last successfully received SOF. It is

followed by reading one or two bytes from the Frame Number register, containing the

frame number (lower byte ﬁrst). The Frame Number register is shown in Table 41.

Remark: After a bus reset, the value of the Frame Number register is undeﬁned.

Code (hex): B4 — read frame number

Transaction — read 1 or 2 bytes

Table 41: Frame Number register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Reset^[1]

Access

Bit

reserved

SOFRH[2:0]

0

R

7

0

R

6

0

R

5

0

R

4

0

R

3

0

R

2

0

R

1

0

R

0

Symbol

Reset^[1]

Access

SOFRL[7:0]

0

R

[1] Reset value undeﬁned after a bus reset.

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ISP1183

Low-power USB interface device with DMA

Philips Semiconductors

Table 42: Frame Number register: bit description

Bit

Symbol

-

Description

15 to 11

10 to 8

7 to 0

reserved

SOFRH[2:0]

SOFRL[7:0]

SOF frame number (upper byte)

SOF frame number (lower byte)

Table 43: Example of Frame Number register access

A0

Phase

command

data

Bus lines

D[7:0]

Byte #

Description

HIGH

LOW

-

command code (B4H)

frame number (lower byte)

frame number (upper byte)

D[7:0]

0

1

data

D[7:0]

13.4.4 Chip ID register (R: B5H)

This command reads the chip identiﬁcation code and hardware version number. The

ﬁrmware must check this information to determine the supported functions and

features. This command accesses the Chip ID register, which is shown in Table 44.

Code (hex): B5 — read chip ID

Transaction — read 2 bytes

Table 44: Chip ID register: bit allocation

Bit

15

14

13

12

CHIPIDH[7:0]

82H

11

10

9

8

Symbol

Reset

Access

Bit

R

7

6

5

4

3

2

1

0

Symbol

Reset

Access

CHIPIDL[7:0]

11H

R

Table 45: Chip ID register: bit description

Bit

Symbol

Description

15 to 8

7 to 0

CHIPIDH[7:0] chip ID code (82H)

CHIPIDL[7:0] silicon version (11H)

13.4.5 Interrupt register (R: C0H)

This command indicates the sources of interrupts as stored in the 4-byte Interrupt

register. Each individual endpoint has its own interrupt bit. The bit allocation of the

Interrupt register is shown in Table 46. Bit BUSTATUS veriﬁes the current bus status

in the interrupt service routine. Interrupts are enabled through the Interrupt Enable

register, see Section 13.1.5.

While reading the interrupt register, read all the 4 bytes completely.

Code (hex): C0 — read Interrupt register

Transaction — read 4 bytes

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ISP1183

Low-power USB interface device with DMA

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Table 46: Interrupt register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved

0

R

0

R

0

R

0

R

23

22

21

EP12

0

20

EP11

0

19

EP10

0

18

17

16

Symbol

Reset

Access

Bit

EP14

EP13

EP9

EP8

EP7

0

R

15

14

13

EP4

0

12

EP3

0

11

EP2

0

10

9

8

Symbol

Reset

Access

Bit

EP6

EP5

EP1

EP0IN

EP0OUT

0

R

7

6

5

4

3

2

1

0

Symbol

Reset

Access

BUSTATUS

SP_EOT

PSOF

0

SOF

0

EOT

0

SUSPND

RESUME

RESET

0^[1]

0

R

[1] The reset value of this bit depends on the current USB bus status. If the bus is idle, the reset value will be 1.

Table 47: Interrupt register: bit description

Bit

31 to 24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

Symbol

-

Description

reserved

EP14

EP13

EP12

EP11

EP10

EP9

Logic 1 indicates the interrupt source: endpoint 14.

Logic 1 indicates the interrupt source: endpoint 13.

Logic 1 indicates the interrupt source: endpoint 12.

Logic 1 indicates the interrupt source: endpoint 11.

Logic 1 indicates the interrupt source: endpoint 10.

Logic 1 indicates the interrupt source: endpoint 9.

Logic 1 indicates the interrupt source: endpoint 8.

Logic 1 indicates the interrupt source: endpoint 7.

Logic 1 indicates the interrupt source: endpoint 6.

Logic 1 indicates the interrupt source: endpoint 5.

Logic 1 indicates the interrupt source: endpoint 4.

Logic 1 indicates the interrupt source: endpoint 3.

Logic 1 indicates the interrupt source: endpoint 2.

Logic 1 indicates the interrupt source: endpoint 1.

EP8

EP7

EP6

EP5

EP4

EP3

EP2

EP1

EP0IN

EP0OUT

BUSTATUS

Logic 1 indicates the interrupt source: control IN endpoint.

Logic 1 indicates the interrupt source: control OUT endpoint.

8

7

It monitors the current USB bus status (0 = awake,

1 = suspend).

6

SP_EOT

Logic 1 indicates that an EOT interrupt has occurred for a short

packet.

9397 750 11804

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Low-power USB interface device with DMA

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Table 47: Interrupt register: bit description…continued

Bit

Symbol

Description

5

PSOF

Logic 1 indicates that an interrupt is issued every 1 ms because

of the Pseudo SOF; after three missed SOFs, suspend state is

entered.

4

3

SOF

EOT

Logic 1 indicates that a SOF condition was detected.

Logic 1 indicates that an internal EOT condition was generated

by the DMA Counter reaching zero.

2

SUSPND

Logic 1 indicates that an awake to suspend change of state was

detected on the USB bus.

1

0

RESUME

RESET

Logic 1 indicates that a resume state was detected.

Logic 1 indicates that a bus reset condition was detected.

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ISP1183

Low-power USB interface device with DMA

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14. Limiting values

Table 48: Absolute maximum ratings

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_BUS

V_DD(I/O)

V_I

Parameter

Conditions

Min

−0.5

-

Max

Unit

V

supply voltage

+6.0

I/O supply voltage

digital input voltage level

latch-up current

+4.6

V

V_DD(I/O)+ 0.5

100

V

I_lu

V_I< 0 or V_I> V_BUS

mA

V

[1]

V_esd

T_stg

electrostatic discharge voltage

storage temperature

total power dissipation

I_LI< 1 µA

−2000

−60

-

+2000

+150

°C

mW

P_tot

V_BUS= 5.5 V

100

[1] Equivalent to discharging a 100 pF capacitor through a 1.5 kΩ resistor (Human Body Model).

15. Recommended operating conditions

Table 49: Recommended operating conditions

Symbol Parameter

Conditions

Min

4.0

1.65

0

Typ

Max

5.5

Unit

V_BUS

V_DD(I/O)

V_I

supply voltage

I/O supply voltage

input voltage

with regulator

5.0

V

-

3.6

V_DD(I/O)

3.6

V_O(I/O)

V_I(AI/O)

output I/O voltage

0

input voltage on analog I/O

pins DP and DM

0

V_O(od)

T_amb

open-drain output pull-up voltage

ambient temperature

0

-

V_BUS

+85

V

−40

°C

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ISP1183

Low-power USB interface device with DMA

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16. Static characteristics

Table 50: Static characteristics; supply pins

V_BUS= 4.0 V to 5.5 V; V_DD(I/O)= 1.65 V to 3.6 V; V_GND= 0 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

3.0

-

Typ

3.3

19

Max

3.6

-

Unit

V

[1][2]

V_REG(3V3)regulated supply voltage

V_BUS= 4.0 V to 5.5 V

I_CC

operating supply current

suspend supply current

V_BUS= 5.0 V;

T_amb= 25 °C

mA

[3]

I_CC(susp)

V_BUS= 5.0 V;

-

250

µA

T_amb= 25 °C

I_ref(static)

I_ref

V_DD(I/O)static I/O supply current

suspend or no V_BUS

-

10

µA

V_DD(I/O)operating I/O supply

current

3.5

mA

[1] For 3.3 V operation, pin V_REG(3V3)must be connected to pin V_BUS

[2] In the suspend mode, the minimum voltage is 2.7 V.

[3] External loading is not included.

.

Table 51: Static characteristics: digital pins

V_BUS= 4.0 V to 5.5 V; V_DD(I/O)= 1.65 V to 3.6 V; V_GND= 0 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

V_IL(I/O)

V_IH(I/O)

V_OL

Parameter

Conditions

Min

Typ

Max

Unit

LOW-level I/O input voltage

HIGH-level I/O input voltage

LOW-level I/O output voltage

HIGH-level I/O output voltage

input leakage current

input capacitance

-

0.2V_DD(I/O)

V

0.7V_DD(I/O)

-

V

-

0.22V_DD(I/O)

V

V_OH

I_LI

0.8V_DD(I/O)

-

V

−1

-

+1

10

-

µA

pF

MΩ

C_i

Z_i

input impedance

2

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ISP1183

Low-power USB interface device with DMA

Philips Semiconductors

Table 52: Static characteristics: analog I/O pins DP and DM^[1]

V_BUS= 4.0 V to 5.5 V; V_DD(I/O)= 1.65 V to 3.6 V; V_GND= 0 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

Input levels

V_DI

Parameter

Conditions

Min

Typ

Max

Unit

differential input sensitivity

|V_I(DP)− V_I(DM)

|

0.2

0.8

-

V

V_CM

differential common mode

voltage

includes V_DIrange

2.5

V_IL

LOW-level input voltage

HIGH-level input voltage

-

0.8

-

V

V_IH

2.0

Output levels

V_OL

V_OH

LOW-level output voltage

HIGH-level output voltage

R_L= 1.5 kΩ to +3.6 V

R_L= 15 kΩ to ground

-

0.3

3.6

V

2.8

Leakage current

I_LZ

OFF-state leakage current

−10

-

+10

20

µA

Capacitance

C_IN

transceiver capacitance

pin to ground

-

pF

Resistance

R_PU

pull-up resistance on DP

driver output impedance

input impedance

SoftConnect = ON

steady-state drive

1

-

2

kΩ

Ω

[2]

Z_DRV

29

10

44

-

Z_INP

MΩ

Termination

V_TERM

[3][4]

termination voltage for

3.0

-

3.6

V

upstream port pull-up (R_pu)

[1] DP is the USB positive data pin; DM is the USB negative data pin.

[2] Includes external resistors of 22 Ω ± 1 % on both DP and DM.

[3] This voltage is available at pin V_REG(3V3)

.

[4] In the suspend mode, the minimum voltage is 2.7 V.

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ISP1183

Low-power USB interface device with DMA

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17. Dynamic characteristics

Table 53: Dynamic characteristics

V_BUS= 4.0 V to 5.5 V; V_DD(I/O)= 1.65 V to 3.6 V; V_GND= 0 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

Reset

Parameter

Conditions

Min

Typ

Max

Unit

t_{W(RESET_N)}

pulse width on input RESET_N crystal oscillator running

crystal oscillator stopped

50

-

µs

[1]

3

ms

Crystal oscillator

f_XTAL

crystal frequency

-

6

-

MHz

[1] Dependent on the crystal oscillator start-up time.

Table 54: Dynamic characteristics: analog I/O pins DP and DM^[1]

V_BUS= 4.0 V to 5.5 V; V_DD(I/O)= 1.65 V to 3.6 V; V_GND= 0 V; T_amb= −40 °C to +85 °C; C_L= 50 pF; R_PU= 1.5 kΩ on DP to

V_TERM; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Driver characteristics

t_FR

rise time

C_L= 50 pF;

4

-

20

ns

10 % to 90 % of

|V_OH− V_OL

|

t_FF

fall time

C_L= 50 pF;

4

-

20

ns

90 % to 10 % of

|V_OH− V_OL

|

[2]

FRFM

V_CRS

differential rise/fall time

90

-

111.11

2.0

%

V

matching (t_FR/t_FF

)

[2][3]

output signal crossover voltage

1.3

Data source timing

t_FEOPTsource EOP width

t_FDEOP

[3]

160

-

175

+5

ns

source differential data-to-EOP

transition skew

−2

Receiver timing

[3]

t_JR1receiver data jitter tolerance for

−18.5

−9

-

+18.5

+9

ns

consecutive transitions

t_JR2

receiver data jitter tolerance for

paired transitions

[3]

t_FEOPR

t_FST

receiver SE0 width

accepted as EOP

82

-

ns

width of SE0 during differential rejected as EOP

transition

14

[1] Test circuit: see Figure 27.

[2] Excluding the ﬁrst transition from Idle state.

[3] Characterized only, not tested. Limits guaranteed by design.

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ISP1183

Low-power USB interface device with DMA

Philips Semiconductors

18. Timing

18.1 Parallel I/O timing

Table 55: Dynamic characteristics: parallel interface timing

V_BUS= V_REG(3V3)= 2.7 V to 3.9 V; V_DD(I/O)= 1.8 V

Symbol

Read timing (see Figure 13)

t_RHAXaddress hold time after RD_N HIGH

t_AVRL

Parameter

Conditions

Min

Max

Unit

C_L= 30 pF

0

-

ns

address setup time before RD_N

LOW

t_RHDZ

data outputs high-impedance time

after RD_N HIGH

0

-

ns

t_RHSH

t_RHRL

t_RLRH

t_SLRL

t_RLDV

chip deselect time after RD_N HIGH

RD_N LOW after RD_N HIGH

RD_N pulse width

−2

65

25

0

-

ns

-

CS_N time before RD_N LOW

data valid time after RD_N LOW

-

20

-

t_RC(t_RHRL+ t_RLRH) read cycle time

90

Write timing (see Figure 14)

t_WHAX

t_AVWL

address hold time after WR_N HIGH

1

0

-

ns

address setup time before WR_N

LOW

t_SLWL

CS_N time before WR_N LOW

write cycle time

0

-

ns

[1]

t_WL

90/180

(t_WHWL+ t_WLWH

)

t_WLWH

t_WHWL

t_WHSH

t_DVWH

t_WHDZ

WR_N pulse width

22

-

ns

WR_N LOW after WR_N HIGH

chip deselect time after WR_N HIGH

data setup time before WR_N HIGH

data hold time after WR_N HIGH

68/158

0

2

1

[1] The minimum value for the data ﬂow commands (see Table 13) is 180 ns.

9397 750 11804

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ISP1183

Low-power USB interface device with DMA

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t

AVRL

RHAX

A0

t

SLRL

CS_N

RD_N

(1)

t

RHRL

RLRH

t

RHSH

t

RLDV

RHDZ

DATA

004aaa256

(1) If required, CS_N can be kept permanently asserted. There is no need to deassert and assert in between the read and

write cycles.

Fig 13. Parallel interface read timing.

t

WHAX

A0

t

AVWL

CS_N

t

WLWH

(1)

t

WHWL

t

WHSH

SLWL

WR_N

DATA

t

DVWH

WHDZ

004aaa257

(1) If required, CS_N can be kept permanently asserted. There is no need to deassert and assert in between the read and

write cycles.

Fig 14. Parallel interface write timing.

18.2 Access cycle timing

Table 56: Dynamic characteristics: access cycle timing

V_BUS= V_REG(3V3)= 2.7 V to 3.9 V; V_DD(I/O)= 1.8 V

Symbol

Parameter

Conditions

Min

Max

Unit

Write command + write data (see Figure 15 and Figure 16)

[1]

T_cy(WC-WD)

T_cy(WD-WD)

T_cy(WD-WC)

cycle time for write command, then write data

cycle time for write data

C_L= 30 pF

100

90

-

ns

cycle time for write data, then write command

90

9397 750 11804

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ISP1183

Low-power USB interface device with DMA

Philips Semiconductors

Table 56: Dynamic characteristics: access cycle timing…continued

V_BUS= V_REG(3V3)= 2.7 V to 3.9 V; V_DD(I/O)= 1.8 V

Symbol

Parameter

Conditions

Min

Max

Unit

Write command + read data (see Figure 17 and Figure 18)

[1]

T_cy(WC-RD)

T_cy(RD-RD)

T_cy(RD-WC)

cycle time for write command, then read data

cycle time for read data

100

90

-

ns

cycle time for read data, then write command

90

[1] The minimum value for the data ﬂow commands (see Table 13) is 180 ns.

DATA

command

data

T

cy(WD-WD)

cy(WC-WD)

WR_N

CS_N

004aaa425

Fig 15. Write command + write data cycle timing.

DATA

data

command

data

T

cy(WD-WC)

WR_N

(1)

RD_N

CS_N

004aaa426

(1) Example: read data.

Fig 16. Write data + write command cycle timing.

DATA

command

data

WR_N

T

cy(WC-RD)

RD_N

CS_N

T

cy(RD-RD)

004aaa427

Fig 17. Write command + read data cycle timing.

9397 750 11804

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ISP1183

Low-power USB interface device with DMA

Philips Semiconductors

DATA

data

command

data

WR_N

T

cy(RD-WC)

(1)

RD_N

CS_N

004aaa428

(1) Example: read data.

Fig 18. Read data + write command cycle timing.

18.3 DMA timing: single-cycle mode

Table 57: Dynamic characteristics: single-cycle DMA timing

V_BUS= V_REG(3V3)= 2.7 V to 3.9 V; V_DD(I/O)= 1.8 V

Symbol

Parameter

Conditions

Min

Max Unit

8237 compatible mode (see Figure 19)

t_ASRP

DREQ off after DACK on

cycle time signal DREQ

-

40

ns

T_cy(DREQ)

90

-

Read in DACK-only mode (see Figure 20)

t_ASRP

t_ASAP

DREQ off after DACK on

DACK pulse width

-

40

-

ns

25

90

-

t_ASAP+ t_APRSDREQ on after DACK off

-

t_ASDV

t_APDZ

data valid after DACK on

data hold after DACK off

22

3

-

Write in DACK-only mode (see Figure 21)

t_ASRPDREQ off after DACK on

t_ASAP+ t_APRSDREQ on after DACK off

-

40

-

ns

90

5

t_DVAP

t_APDZ

data setup before DACK off

data hold after DACK off

-

3

-

T

cy(DREQ)

t

ASRP

DREQ

DACK_N

004aaa429

Fig 19. DMA timing in 8237 compatible mode.

9397 750 11804

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ISP1183

Low-power USB interface device with DMA

Philips Semiconductors

t

ASRP

APRS

DREQ

t

ASAP

DACK_N

t

APDZ

ASDV

DATA

004aaa430

Fig 20. DMA read timing in DACK-only mode.

t

ASAP

t

ASRP

APRS

DREQ

t

DVAP

APDZ

DACK_N

DATA

004aaa431

Fig 21. DMA write timing in DACK-only mode.

18.4 DMA timing: burst mode

Table 58: Dynamic characteristics: burst mode DMA timing

V_BUS= V_REG(3V3)= 2.7 V to 3.9 V; V_DD(I/O)= 1.8 V

Symbol

Parameter

Conditions

Min

Max

Unit

Burst (see Figure 22)

t_RSIH

t_ILRP

t_IHAP

t_IHIL

input RD_N or WR_N HIGH after

DREQ on

22

-

ns

DREQ off after input RD_N or

WR_N LOW

60

-

DACK off after input RD_N or

WR_N HIGH

0

DMA burst repeat interval (input

RD_N or WR_N HIGH to LOW)

90

-

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ISP1183

Low-power USB interface device with DMA

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t

RSIH

ILRP

DREQ

t

IHAP

DACK_N

t

IHIL

RD_N, WR_N

004aaa432

Fig 22. Burst mode DMA timing.

19. Application information

19.1 Bus-powered mode

In the bus-powered mode, pin VBUSDET_N is not necessary. See Figure 23.

V

BUS

8

12

18

V

CC

REG(3V3)

ISP1183

MCU

V

DD(I/O)

REGULATOR

1.65 V to 3.6 V

V

DD(I/O)

30

004aaa451

Fig 23. Bus-powered mode.

19.2 Hybrid-powered mode

In this mode:

• When the USB cable is pulled out, pin VBUSDET_N goes HIGH, thereby

indicating to the MCU that USB is disconnected. See Figure 24.

• When the USB cable is plugged in, pin VBUSDET_N goes LOW. This indicates to

the MCU that the USB cable is plugged in. The MCU can then prepare to

reconﬁgure all registers of the ISP1183. See Figure 24.

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ISP1183

Low-power USB interface device with DMA

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self-powered

V

BUS

8

12

18

V

CC

REG(3V3)

ISP1183

V

MCU

self-powered (1.65 V to 3.6 V)

DD(I/O)

VBUSDET_N

13

V

30

004aaa452

Fig 24. Hybrid-powered mode.

19.3 Self-powered mode

In the self-powered mode, pin VBUSDET_N cannot be used. The V_BUSsensing can

be done in the following two ways:

• Connecting V_BUSto the MCU; see Figure 25.

– When VBUSDET goes LOW, the MCU clears bit SOFTCT.

– When VBUSDET goes HIGH, the MCU sets bit SOFTCT.

• Connecting transistor switching; see Figure 26.

– When V_BUSis HIGH, V_REG(3V3)will bypass to pull up DP. This indicates that the

device is connected.

– When V_BUSis LOW, pull up DP is switched off. This indicates that the device is

disconnected.

Remark: The above implementation is necessary to comply with USB-IF

requirements.

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ISP1183

Low-power USB interface device with DMA

Philips Semiconductors

(3 V or 5 V)

self-powered

V

CC

V

8

BUS

VBUSDET

V

MCU

REG(3V3)

12

ISP1183

V

self-powered (1.65 V to 3.6 V)

DD(I/O)

18

30

V

22 Ω

DP

DM

V

BUS

004aaa454

100 kΩ

Fig 25. V_BUSconnected to MCU.

(3 V or 5 V)

self-powered

V

CC

V

8

REG(3V3)

BUS

VBUSDET

V

MCU

REG(3V3)

12

22 kΩ

V

self-powered (1.65 V to 3.6 V)

DD(I/O)

18

30

ISP1183

1.5 kΩ

V

22 Ω

DP

22 Ω

DM

V

BUS

004aaa453

100 kΩ

Fig 26. Transistor switching.

9397 750 11804

Product data

Rev. 01 — 24 February 2004

55 of 62

ISP1183

Low-power USB interface device with DMA

Philips Semiconductors

20. Test information

The dynamic characteristics of the analog I/O ports (DP and DM) as listed in Table 54

were determined using the circuit shown in Figure 27.

test point

22 Ω

D.U.T

C

L

50 pF

15 kΩ

MGS784

Load capacitance:

C_L= 50 pF (full-speed mode)

Speed:

Full-speed mode only: internal 1.5 kΩ pull-up resistor on DP

Fig 27. Load impedance for the DP and DM pins.

9397 750 11804

Product data

Rev. 01 — 24 February 2004

56 of 62

ISP1183

Low-power USB interface device with DMA

Philips Semiconductors

21. Package outline

HVQFN32: plastic thermal enhanced very thin quad flat package; no leads;

32 terminals; body 5 x 5 x 0.85 mm

SOT617-1

B

A

D

terminal 1

index area

A

1

E

c

detail X

C

e

1

y

e

1/2 e

v

M

b

C

A B

C

1

w

9

16

L

17

8

e

E

h

2

1/2 e

1

24

terminal 1

index area

32

25

X

D

h

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

A

(1)

UNIT

A

b

c

E

e

2

y

D

E

L

v

w

y

1

h

1

h

max.

0.05 0.30

0.00 0.18

5.1

4.9

3.25

2.95

5.1

4.9

3.25

2.95

0.5

0.3

mm

0.05 0.1

1

0.2

0.5

3.5

0.1

0.05

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

01-08-08

02-10-18

SOT617-1

- - -

MO-220

- - -

Fig 28. HVQFN32 package outline.

9397 750 11804

Product data

Rev. 01 — 24 February 2004

57 of 62

ISP1183

Low-power USB interface device with DMA

Philips Semiconductors

22. Soldering

22.1 Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology. A more in-depth account

of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit

Packages (document order number 9398 652 90011).

There is no soldering method that is ideal for all surface mount IC packages. Wave

soldering can still be used for certain surface mount ICs, but it is not suitable for ﬁne

pitch SMDs. In these situations reﬂow soldering is recommended. In these situations

reﬂow soldering is recommended.

22.2 Reﬂow soldering

Reﬂow soldering requires solder paste (a suspension of ﬁne solder particles, ﬂux and

binding agent) to be applied to the printed-circuit board by screen printing, stencilling

or pressure-syringe dispensing before package placement. Driven by legislation and

environmental forces the worldwide use of lead-free solder pastes is increasing.

Several methods exist for reﬂowing; for example, convection or convection/infrared

heating in a conveyor type oven. Throughput times (preheating, soldering and

cooling) vary between 100 and 200 seconds depending on heating method.

Typical reﬂow peak temperatures range from 215 to 270 °C depending on solder

paste material. The top-surface temperature of the packages should preferably be

kept:

• below 225 °C (SnPb process) or below 245 °C (Pb-free process)

– for all BGA, HTSSON..T and SSOP..T packages

– for packages with a thickness ≥ 2.5 mm

– for packages with a thickness < 2.5 mm and a volume ≥ 350 mm³so called

thick/large packages.

• below 240 °C (SnPb process) or below 260 °C (Pb-free process) for packages with

a thickness < 2.5 mm and a volume < 350 mm³so called small/thin packages.

Moisture sensitivity precautions, as indicated on packing, must be respected at all

times.

22.3 Wave soldering

Conventional single wave soldering is not recommended for surface mount devices

(SMDs) or printed-circuit boards with a high component density, as solder bridging

and non-wetting can present major problems.

To overcome these problems the double-wave soldering method was speciﬁcally

developed.

If wave soldering is used the following conditions must be observed for optimal

results:

• Use a double-wave soldering method comprising a turbulent wave with high

upward pressure followed by a smooth laminar wave.

9397 750 11804

Product data

Rev. 01 — 24 February 2004

58 of 62

ISP1183

Low-power USB interface device with DMA

Philips Semiconductors

• For packages with leads on two sides and a pitch (e):

– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be

parallel to the transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the

transport direction of the printed-circuit board.

The footprint must incorporate solder thieves at the downstream end.

• For packages with leads on four sides, the footprint must be placed at a 45° angle

to the transport direction of the printed-circuit board. The footprint must

incorporate solder thieves downstream and at the side corners.

During placement and before soldering, the package must be ﬁxed with a droplet of

adhesive. The adhesive can be applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the adhesive is cured.

Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 °C or

265 °C, depending on solder material applied, SnPb or Pb-free respectively.

A mildly-activated ﬂux will eliminate the need for removal of corrosive residues in

most applications.

22.4 Manual soldering

Fix the component by ﬁrst soldering two diagonally-opposite end leads. Use a low

voltage (24 V or less) soldering iron applied to the ﬂat part of the lead. Contact time

must be limited to 10 seconds at up to 300 °C.

When using a dedicated tool, all other leads can be soldered in one operation within

2 to 5 seconds between 270 and 320 °C.

22.5 Package related soldering information

Table 59: Suitability of surface mount IC packages for wave and reﬂow soldering

methods

Package^[1]

Soldering method

Wave

Reﬂow^[2]

BGA, HTSSON..T^[3], LBGA, LFBGA, SQFP,

SSOP..T^[3], TFBGA, USON, VFBGA

not suitable

suitable

DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, not suitable^[4]

HSQFP, HSSON, HTQFP, HTSSOP, HVQFN,

HVSON, SMS

suitable

PLCC^[5], SO, SOJ

suitable

LQFP, QFP, TQFP

not recommended^[5][6]

not recommended^[7]

not suitable

suitable

SSOP, TSSOP, VSO, VSSOP

CWQCCN..L^[8], PMFP^[9], WQCCN..L^[8]

suitable

not suitable

[1] For more detailed information on the BGA packages refer to the (LF)BGA Application Note

(AN01026); order a copy from your Philips Semiconductors sales ofﬁce.

[2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the

maximum temperature (with respect to time) and body size of the package, there is a risk that internal

or external package cracks may occur due to vaporization of the moisture in them (the so called

popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated

Circuit Packages; Section: Packing Methods.

9397 750 11804

Product data

Rev. 01 — 24 February 2004

59 of 62

ISP1183

Low-power USB interface device with DMA

Philips Semiconductors

[3] These transparent plastic packages are extremely sensitive to reﬂow soldering conditions and must

on no account be processed through more than one soldering cycle or subjected to infrared reﬂow

soldering with peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reﬂow

oven. The package body peak temperature must be kept as low as possible.

[4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom

side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with

the heatsink on the top side, the solder might be deposited on the heatsink surface.

[5] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave

direction. The package footprint must incorporate solder thieves downstream and at the side corners.

[6] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it

is deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

[7] Wave soldering is suitable for SSOP, TSSOP, VSO and VSOP packages with a pitch (e) equal to or

larger than 0.65 mm; it is deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than

0.5 mm.

[8] Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered

pre-mounted on ﬂex foil. However, the image sensor package can be mounted by the client on a ﬂex

foil by using a hot bar soldering process. The appropriate soldering proﬁle can be provided on

request.

[9] Hot bar soldering or manual soldering is suitable for PMFP packages.

23. Revision history

Table 60: Revision history

Rev Date

CPCN Description

Product data (9397 750 11804)

01 20040224 -

9397 750 11804

Product data

Rev. 01 — 24 February 2004

60 of 62

ISP1183

Low-power USB interface device with DMA

Philips Semiconductors

24. Data sheet status

Level Data sheet status^[1]

Product status^[2][3]

Deﬁnition

I

Objective data

Development

This data sheet contains data from the objective speciﬁcation for product development. Philips

Semiconductors reserves the right to change the speciﬁcation in any manner without notice.

II

Preliminary data

Qualiﬁcation

This data sheet contains data from the preliminary speciﬁcation. Supplementary data will be published

at a later date. Philips Semiconductors reserves the right to change the speciﬁcation without notice, in

order to improve the design and supply the best possible product.

III

Product data

Production

This data sheet contains data from the product speciﬁcation. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant

changes will be communicated via a Customer Product/Process Change Notiﬁcation (CPCN).

[1]

[2]

Please consult the most recently issued data sheet before initiating or completing a design.

The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at

URL http://www.semiconductors.philips.com.

[3]

For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

customers using or selling these products for use in such applications do so

at their own risk and agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

25. Deﬁnitions

Short-form speciﬁcation — The data in a short-form speciﬁcation is

extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Right to make changes — Philips Semiconductors reserves the right to

make changes in the products - including circuits, standard cells, and/or

software - described or contained herein in order to improve design and/or

performance. When the product is in full production (status ‘Production’),

relevant changes will be communicated via a Customer Product/Process

Change Notiﬁcation (CPCN). Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no

licence or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are

free from patent, copyright, or mask work right infringement, unless otherwise

speciﬁed.

Limiting values deﬁnition — Limiting values given are in accordance with

the Absolute Maximum Rating System (IEC 60134). Stress above one or

more of the limiting values may cause permanent damage to the device.

These are stress ratings only and operation of the device at these or at any

other conditions above those given in the Characteristics sections of the

speciﬁcation is not implied. Exposure to limiting values for extended periods

may affect device reliability.

Application information — Applications that are described herein for any

of these products are for illustrative purposes only. Philips Semiconductors

make no representation or warranty that such applications will be suitable for

the speciﬁed use without further testing or modiﬁcation.

27. Trademarks

ACPI — is an open industry speciﬁcation for PC power management,

co-developed by Intel Corp., Microsoft Corp. and Toshiba

GoodLink — is a trademark of Koninklijke Philips Electronics N.V.

IBM — is a registered trademark of Internal Machines Corp.

Intel — is a registered trademark of Intel Corp.

OnNow — is a trademark of Microsoft Corp.

SoftConnect — is a trademark of Koninklijke Philips Electronics N.V.

Zip — is a registered trademark of Iomega Corp.

26. Disclaimers

Life support — These products are not designed for use in life support

appliances, devices, or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors

Contact information

For additional information, please visit http://www.semiconductors.philips.com.

For sales ofﬁce addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.

Fax: +31 40 27 24825

61 of 62

9397 750 11804

Product data

Rev. 01 — 24 February 2004

ISP1183

Low-power USB interface device with DMA

Philips Semiconductors

Contents

1

2

3

4

5

6

General description. . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . 3

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

13.2.1

13.2.2

13.2.3

13.2.4

13.2.5

13.2.6

13.2.7

13.3

13.3.1

13.3.2

13.3.3

13.4

13.4.1

13.4.2

13.4.3

13.4.4

13.4.5

Endpoint Buffer (R/W: 10H, 12H–1FH/01H–0FH) . . 32

Endpoint Status register (R: 50H–5FH) . . . . . . . . . . 33

Stall or Unstall Endpoint (40H–4FH/80H–8FH) . . . . 34

Validate Endpoint Buffer (61H–6FH). . . . . . . . . . . . . 34

Clear Endpoint Buffer (70H, 72H–7FH) . . . . . . . . . . 35

Check Endpoint Status (D0H–DFH) . . . . . . . . . . . . . 35

Acknowledge Setup (F4H) . . . . . . . . . . . . . . . . . . . . 36

DMA commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

DMA Function and Scratch register (R/W: B3H/B2H) 36

DMA Conﬁguration register (R/W: F1H/F0H) . . . . . . 37

DMA Counter register (R/W: F3H/F2H) . . . . . . . . . . 38

General commands . . . . . . . . . . . . . . . . . . . . . . . . . 38

Endpoint Error Code (R: A0H–AFH) . . . . . . . . . . . . 38

Unlock Device (B0H). . . . . . . . . . . . . . . . . . . . . . . . . 39

Frame Number register (R: B4H) . . . . . . . . . . . . . . . 40

Chip ID register (R: B5H) . . . . . . . . . . . . . . . . . . . . . 41

Interrupt register (R: C0H) . . . . . . . . . . . . . . . . . . . . 41

7

Pinning information. . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

7.1

7.2

8

Functional description . . . . . . . . . . . . . . . . . . . . . . . . 8

Analog transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Philips SIE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

MMU and integrated RAM . . . . . . . . . . . . . . . . . . . . . 8

SoftConnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Bit clock recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

PLL clock multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . 9

PIO and DMA interfaces . . . . . . . . . . . . . . . . . . . . . . 9

V_BUSindicator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Crystal oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

8.1

8.2

8.3

8.4

8.5

8.6

8.7

8.8

8.9

8.10

8.11

8.12

8.13

14

15

16

17

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Recommended operating conditions. . . . . . . . . . . . 44

Static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 45

Dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . 47

18

Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Parallel I/O timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Access cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . 49

DMA timing: single-cycle mode . . . . . . . . . . . . . . . . 51

DMA timing: burst mode . . . . . . . . . . . . . . . . . . . . . . 52

18.1

18.2

18.3

18.4

9

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

10

Endpoint description. . . . . . . . . . . . . . . . . . . . . . . . . 14

Endpoint access. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Endpoint FIFO size . . . . . . . . . . . . . . . . . . . . . . . . . 14

Endpoint initialization . . . . . . . . . . . . . . . . . . . . . . . . 16

Endpoint I/O mode access. . . . . . . . . . . . . . . . . . . . 16

Special actions on control endpoints . . . . . . . . . . . . 16

10.1

10.2

10.3

10.4

10.5

19

Application information. . . . . . . . . . . . . . . . . . . . . . . 53

Bus-powered mode. . . . . . . . . . . . . . . . . . . . . . . . . . 53

Hybrid-powered mode . . . . . . . . . . . . . . . . . . . . . . . 53

Self-powered mode. . . . . . . . . . . . . . . . . . . . . . . . . . 54

19.1

19.2

19.3

20

21

Test information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

11

DMA transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Selecting an endpoint for DMA transfer . . . . . . . . . . 17

8237 compatible mode. . . . . . . . . . . . . . . . . . . . . . . 18

DACK-only mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

End-Of-Transfer conditions. . . . . . . . . . . . . . . . . . . . 20

Bulk endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Isochronous endpoints. . . . . . . . . . . . . . . . . . . . . . . 21

11.1

11.2

11.3

11.4

11.4.1

11.4.2

22

Soldering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Introduction to soldering surface mount packages . . 58

Reﬂow soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Manual soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Package related soldering information . . . . . . . . . . . 59

22.1

22.2

22.3

22.4

22.5

12

Suspend and resume . . . . . . . . . . . . . . . . . . . . . . . . 22

Suspend conditions . . . . . . . . . . . . . . . . . . . . . . . . . 22

Powered-off application . . . . . . . . . . . . . . . . . . . . . . 23

Resume conditions. . . . . . . . . . . . . . . . . . . . . . . . . . 24

Control bits in suspend and resume. . . . . . . . . . . . . 24

23

24

25

26

27

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Data sheet status . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

12.1

12.1.1

12.2

12.3

13

Commands and registers . . . . . . . . . . . . . . . . . . . . . 25

Initialization commands . . . . . . . . . . . . . . . . . . . . . . 27

Endpoint Conﬁguration register

13.1

13.1.1

(R/W: 30H–3FH/20H–2FH). . . . . . . . . . . . . . . . . . . 27

Address register (R/W: B7H/B6H) . . . . . . . . . . . . . . 28

Mode register (R/W: B9H/B8H) . . . . . . . . . . . . . . . . 29

Hardware Conﬁguration register (R/W: BBH/BAH) . 29

Interrupt Enable register (R/W: C3H/C2H). . . . . . . . 30

Reset Device (F6H) . . . . . . . . . . . . . . . . . . . . . . . . . 32

Data ﬂow commands . . . . . . . . . . . . . . . . . . . . . . . . 32

13.1.2

13.1.3

13.1.4

13.1.5

13.1.6

13.2

Printed in The Netherlands

All rights are reserved. Reproduction in whole or in part is prohibited without the prior

written consent of the copyright owner.

The information presented in this document does not form part of any quotation or

contract, is believed to be accurate and reliable and may be changed without notice. No

liability will be accepted by the publisher for any consequence of its use. Publication

thereof does not convey nor imply any license under patent- or other industrial or

intellectual property rights.

Date of release: 24 February 2004

Document order number: 9397 750 11804


型号：	ISP1183BS
厂家：	NXP
描述：	Low-power Universal Serial Bus interface device with DMA 与DMA的低功耗通用串行总线接口设备
文件：	总62页 (文件大小：282K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISP1183BS [NXP]

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