ISP1362BD,151_技术文档

ISP1362

Single-chip Universal Serial Bus On-The-Go Controller

Rev. 05 — 8 May 2007

Product data sheet

1. General description

The ISP1362 is a single-chip Universal Serial Bus (USB) On-The-Go (OTG) controller

integrated with the advanced NXP Slave Host Controller and the NXP ISP1181B

Peripheral Controller. The USB OTG Controller is compliant with Ref. 1 “On-The-Go

Supplement to the USB 2.0 Speciﬁcation Rev. 1.0a”. The Host and Peripheral Controllers

are compliant with Ref. 2 “Universal Serial Bus Speciﬁcation Rev. 2.0” (full-speed and

low-speed support only), supporting data transfer at full-speed (12 Mbit/s) and low-speed

(1.5 Mbit/s).

The ISP1362 has two USB ports: port 1 and port 2. Port 1 can be hardware conﬁgured to

function as a downstream port, an upstream port or an OTG port whereas port 2 can only

be used as a downstream port. The OTG port can switch roles from host to peripheral, or

from peripheral to host. The OTG port can become a host through Host Negotiation

Protocol (HNP) as speciﬁed in the OTG supplement.

A USB product with OTG capability can function either as a host or as a peripheral. For

instance, with this dual-role capability, a PC peripheral such as a printer may switch roles

from a peripheral to a host for connecting to a digital camera so that the printer can print

pictures taken by the camera without using a PC. When a USB product with OTG

capability is inactive, the USB interface is turned off. This feature has made OTG a

technology well-suited for use in portable devices, such as, Personal Digital Assistant

(PDA), Digital Still Camera (DSC) and mobile phone, in which power consumption is a

concern. The ISP1362 is an OTG Controller designed to perform such functions.

2. Features

I Complies fully with:

N Ref. 2 “Universal Serial Bus Speciﬁcation Rev. 2.0”

N Ref. 1 “On-The-Go Supplement to the USB 2.0 Speciﬁcation Rev. 1.0a”

I Supports data transfer at full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s)

I Adapted from Ref. 4 “Open Host Controller Interface Speciﬁcation for USB

Release 1.0a”

I USB OTG:

N Supports Host Negotiation Protocol (HNP) and Session Request Protocol (SRP)

for OTG dual-role devices

N Provides status and control signals for software implementation of HNP and SRP

N Provides programmable timers required for HNP and SRP

N Supports built-in and external source of V_BUS

N Output current of the built-in charge pump is adjustable by using an external

capacitor

I

USB host:

ISP1362

NXP Semiconductors

Single-chip USB OTG Controller

N Supports integrated physical 4096 bytes of multiconﬁguration memory

N Supports all four types of USB transfers: control, bulk, interrupt and isochronous

N Supports multiframe buffering for isochronous transfer

N Supports automatic interrupt polling rate mechanism

N Supports paired buffering for bulk transfer

N Directly addressable memory architecture; memory can be updated on-the-ﬂy

I USB device:

N Supports high performance USB interface device with integrated Serial Interface

Engine (SIE), buffer memory and transceiver

N Supports fully autonomous and multiconﬁguration Direct Memory Access (DMA)

operation

N Supports up to 14 programmable USB endpoints with two ﬁxed control IN/OUT

endpoints

N Supports integrated physical 2462 bytes of multiconﬁguration memory

N Supports endpoints with double buffering to increase throughput and ease

real-time data transfer

N Supports controllable LazyClock (110 kHz ± 50 %) output during ‘suspend’

I Supports two USB ports: port 1 and port 2

N Port 1 can be conﬁgured to function as a downstream port, an upstream port or an

OTG port

N Port 2 can be used only as a downstream port

I Supports software-controlled connection to the USB bus (SoftConnect)

I Supports good USB connection indicator that blinks with trafﬁc (GoodLink)

I Complies with USB power management requirements

I Supports internal power-on and low-voltage reset circuit, with possibility of a software

reset

I High-speed parallel interface to most CPUs available in the market, such as Hitachi

SH-3, Intel StrongARM, NXP XA, Fujitsu SPARClite, NEC and Toshiba MIPS, ARM7/9,

Freescale DragonBall and PowerPC Reduced Instruction Set Computer (RISC):

N 16-bit data bus

N 10 MB/s data transfer rate between the microprocessor and the ISP1362

I Supports Programmed I/O (PIO) or DMA

I Supports ‘suspend’ and remote wake-up

I Uses 12 MHz crystal or direct clock source with on-chip Phase-Locked Loop (PLL) for

low ElectroMagnetic Interference (EMI)

I Operates at 3.3 V power supply

I Operating temperature range from −40 °C to +85 °C

I Available in 64-pin LQFP and TFBGA packages

3. Applications

The ISP1362 can be used to implement a dual-role USB device in any application, USB

host or USB peripheral, depending on the cable connection. If the dual-role device is

connected to a typical USB peripheral, it behaves like a typical USB host. The dual-role

device, however, can also be connected to a PC or any other USB host and behave like a

typical USB peripheral.

ISP1362_5

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ISP1362

NXP Semiconductors

Single-chip USB OTG Controller

3.1 Host/peripheral roles

I Mobile phone to/from:

N Mobile phone: exchange contact information

N Digital still camera: e-mail pictures or upload pictures to the web

N MP3 player: upload, download and broadcast music

N Mass storage: upload and download ﬁles

N Scanner: scan business cards

I Digital still camera to/from:

N Digital still camera: exchange pictures

N Mobile phone: e-mail pictures, upload pictures to the web

N Printer: print pictures

N Mass storage: store pictures

I Printer to/from:

N Digital still camera: print pictures

N Scanner: print scanned image

N Mass storage: print ﬁles stored in a device

I MP3 player to/from:

N MP3 player: exchange songs

N Mass storage: upload and download songs

I Oscilloscope to/from:

N Printer: print screen image

I Personal digital assistant to/from:

N Personal digital assistant: exchange ﬁles

N Printer: print ﬁles

N Mobile phone: upload and download ﬁles

N MP3 player: upload and download songs

N Scanner: scan pictures

N Mass storage: upload and download ﬁles

N Global Positioning System (GPS): obtain directions, mapping information

N Digital still camera: upload pictures

N Oscilloscope: conﬁgure oscilloscope

ISP1362_5

Product data sheet

Rev. 05 — 8 May 2007

3 of 152

ISP1362

NXP Semiconductors

Single-chip USB OTG Controller

4. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

plastic low proﬁle quad ﬂat package; 64 leads; body 10 × 10 × 1.4 mm

Version

ISP1362BD

ISP1362EE

LQFP64

TFBGA64

SOT314-2

plastic thin ﬁne-pitch ball grid array package; 64 balls; body 6 × 6 × 0.8 mm SOT543-1

ISP1362_5

Product data sheet

Rev. 05 — 8 May 2007

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ISP1362

NXP Semiconductors

Single-chip USB OTG Controller

6. Pinning information

6.1 Pinning

1

2

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

DGND

D2

ID

H_DP2

H_DM2

OTGMODE

X2

3

D3

4

V

CC

5

D4

D5

6

X1

7

D6

H_OC1

H_OC2

8

D7

ISP1362BD

9

DGND

D8

V

CC

10

11

12

13

14

15

16

GL

D9

CLKOUT

D10

D11

DGND

H_PWS2

V

CC

H_PWS1

D12

D13

D_SUSPEND/D_WAKEUP

H_SUSPEND/H_WAKEUP

004aaa050

Fig 2. Pin conﬁguration LQFP64

ball A1

index area

1 2 3 4 5 6 7 8 9 10

A

B

C

D

E

F

ISP1362EE

G

H

J

K

004aaa151

Transparent top view

Fig 3. Pin conﬁguration TFBGA64

ISP1362_5

Product data sheet

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ISP1362

NXP Semiconductors

Single-chip USB OTG Controller

6.2 Pin description

Table 2.

Pin description

Symbol^[1]

Type

Description

LQFP64 TFBGA64

DGND

D2

1

2

B1

C2

-

digital ground

I/O

bit 2 of the bidirectional data bus that connects to the internal registers

and buffer memory of the ISP1362; the bus is in the high-impedance

state when it is idle

bidirectional, push-pull input, 3-state output

D3

3

C1

I/O

bit 3 of the bidirectional data bus that connects to the internal registers

and buffer memory of the ISP1362; the bus is in the high-impedance

state when it is idle

bidirectional, push-pull input, 3-state output

V_CC

D4

4

5

D2

D1

-

supply voltage (3.3 V); it is recommended that you connect a decoupling

capacitor of 0.01 µF

I/O

bit 4 of the bidirectional data bus that connects to the internal registers

and buffer memory of the ISP1362; the bus is in the high-impedance

state when it is idle

bidirectional, push-pull input, 3-state output

D5

D6

D7

6

7

8

E2

E1

F2

I/O

bit 5 of the bidirectional data bus that connects to the internal registers

and buffer memory of the ISP1362; the bus is in the high-impedance

state when it is idle

bidirectional, push-pull input, 3-state output

bit 6 of the bidirectional data bus that connects to the internal registers

and buffer memory of the ISP1362; the bus is in the high-impedance

state when it is idle

bidirectional, push-pull input, 3-state output

bit 7 of the bidirectional data bus that connects to the internal registers

and buffer memory of the ISP1362; the bus is in the high-impedance

state when it is idle

bidirectional, push-pull input, 3-state output

digital ground

DGND

D8

9

F1

-

10

G2

I/O

bit 8 of the bidirectional data bus that connects to the internal registers

and buffer memory of the ISP1362; the bus is in the high-impedance

state when it is idle

bidirectional, push-pull input, 3-state output

D9

11

12

13

G1

H2

H1

I/O

bit 9 of the bidirectional data bus that connects to the internal registers

and buffer memory of the ISP1362; the bus is in the high-impedance

state when it is idle

bidirectional, push-pull input, 3-state output

D10

D11

bit 10 of the bidirectional data bus that connects to the internal registers

and buffer memory of the ISP1362; the bus is in the high-impedance

state when it is idle

bidirectional, push-pull input, 3-state output

bit 11 of the bidirectional data bus that connects to the internal registers

and buffer memory of the ISP1362; the bus is in the high-impedance

state when it is idle

bidirectional, push-pull input, 3-state output

ISP1362_5

Product data sheet

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ISP1362

NXP Semiconductors

Single-chip USB OTG Controller

Table 2.

Pin description …continued

Symbol^[1]

Type

Description

LQFP64 TFBGA64

V_CC

D12

14

J2

-

supply voltage (3.3 V); it is recommended that you connect a decoupling

capacitor of 0.01 µF

15

J1

I/O

bit 12 of the bidirectional data bus that connects to the internal registers

and buffer memory of the ISP1362; the bus is in the high-impedance

state when it is idle

bidirectional, push-pull input, 3-state output

D13

D14

D15

16

17

18

K1

K2

J3

I/O

bit 13 of the bidirectional data bus that connects to the internal registers

and buffer memory of the ISP1362; the bus is in the high-impedance

state when it is idle

bidirectional, push-pull input, 3-state output

bit 14 of the bidirectional data bus that connects to the internal registers

and buffer memory of the ISP1362; the bus is in the high-impedance

state when it is idle

bidirectional, push-pull input, 3-state output

bit 15 of the bidirectional data bus that connects to the internal registers

and buffer memory of the ISP1362; the bus is in the high-impedance

state when it is idle

bidirectional, push-pull input, 3-state output

digital ground

DGND

RD

19

20

K3

J4

-

I

read strobe input; when asserted LOW, it indicates that the Host

Controller/Peripheral Controller driver is requesting a read to the buffer

memory or the internal registers of the Host Controller/Peripheral

Controller

input with hysteresis

CS

21

22

K4

J5

I

chip select input (active LOW); enables the Host Controller/Peripheral

Controller driver to access the buffer memory and registers of the Host

Controller/Peripheral Controller

input

WR

write strobe input; when asserted LOW, it indicates that the Host

Controller/Peripheral Controller driver is requesting a write to the buffer

memory or the internal registers of the Host Controller/Peripheral

Controller

input with hysteresis

TEST0

23

24

K5

J6

I/O

O

for test input and output; pulled HIGH by a 100 kΩ resistor

bidirectional, push-pull input, 3-state output

DREQ1

DMA request output; when active, it signals the DMA controller that a

data transfer is requested by the Host Controller; the active level (HIGH

or LOW) of the request is programmed by using the

HcHardwareConﬁguration register (20h/A0h)

If the OneDMA bit of the HcHardwareConﬁguration register is set to

logic 1, both the Host Controller and the Peripheral Controller DMA

channel will be routed to DREQ1 and DACK1.

push-pull output

ISP1362_5

Product data sheet

Rev. 05 — 8 May 2007

8 of 152

ISP1362

NXP Semiconductors

Single-chip USB OTG Controller

Table 2.

Pin description …continued

Symbol^[1]

Type

Description

LQFP64 TFBGA64

DREQ2

25

K6

O

DMA request output; when active, it signals the DMA controller that a

data transfer is requested by the Peripheral Controller; the active level

(HIGH or LOW) of the request is programmed by using the

DcHardwareConﬁguration register (BAh/BBh)

push-pull output

V_CC

26

J7

-

supply voltage (3.3 V); it is recommended that you connect a decoupling

capacitor of 0.01 µF

DGND

27

28

K7

J8

-

I

digital ground

DACK1

DMA acknowledge input; indicates that a request for DMA transfer from

the Host Controller has been granted by the DMA controller; the active

level (HIGH or LOW) of the acknowledge signal is programmed by using

the HcHardwareConﬁguration register (20h/A0h); when not in use, this

pin must be connected to V_CCthrough a 10 kΩ resistor

input with hysteresis

DACK2

INT1

29

30

K8

J9

I

DMA acknowledge input; indicates that a request for DMA transfer from

the Peripheral Controller has been granted by the DMA controller; the

active level (HIGH or LOW) of the acknowledge signal is programmed by

using the DcHardwareConﬁguration register (BAh/BBh); when not in use,

this pin must be connected to V_CCthrough a 10 kΩ resistor

input with hysteresis

O

interrupt request from the Host Controller; provides a mechanism for the

Host Controller to interrupt the microprocessor; for details, see

HcHardwareConﬁguration register (20h/A0h) Section 14.4.1

If the OneINT bit of the HcHardwareConﬁguration register is set to

logic 1, both the Host Controller and the Peripheral Controller interrupt

request will be routed to INT1.

push-pull output

INT2

31

32

K9

O

interrupt request from the Peripheral Controller; provides a mechanism

for the Peripheral Controller to interrupt the microprocessor; for details,

see DcHardwareConﬁguration register (BAh/BBh) Section 15.1.4

push-pull output

RESET

K10

J10

I

reset input

input with hysteresis and internal pull-up resistor

H_SUSPEND/ 33

H_WAKEUP

I/O

I/O pin (open-drain); goes HIGH when the Host Controller is in suspend

mode; a LOW pulse must be applied to this pin to wake up the Host

Controller; connect a 100 kΩ resistor to V_CC

bidirectional, push-pull input, 3-state open-drain output

D_SUSPEND/ 34

D_WAKEUP

H9

I/O

I/O pin (open-drain); goes HIGH when the Peripheral Controller is in

suspend mode; a LOW pulse must be applied to this pin to wake up the

Peripheral Controller; connect a 100 kΩ resistor to V_CC

bidirectional, push-pull input, 3-state open-drain output

ISP1362_5

Product data sheet

Rev. 05 — 8 May 2007

9 of 152

ISP1362

NXP Semiconductors

Single-chip USB OTG Controller

Table 2.

Pin description …continued

Symbol^[1]

Type

Description

LQFP64 TFBGA64

H_PSW1

35

H10

O

connects to the external PMOS switch; required when the external

charge pump or external V_BUSis used for providing V_BUSto the

downstream port

LOW — switches on the PMOS providing V_BUSto the downstream port

HIGH — switches off the PMOS

when not in use, leave this pin open

open-drain output

H_PSW2

36

G9

O

connects to the external PMOS switch

LOW — switches on the PMOS providing V_BUSto the downstream port

HIGH — switches off the PMOS

when not in use, leave this pin open

open-drain output

DGND

37

38

G10

F9

-

digital ground

CLKOUT

O

programmable clock output; the default clock frequency is 12 MHz and

can be varied from 3 MHz to 48 MHz

push-pull output

GL

39

F10

O

GoodLink LED indicator output; the LED is off by default, blinks on at

USB trafﬁc

open-drain output; 4 mA

V_CC

40

41

E9

-

I

supply voltage (3.3 V); it is recommended that you connect a decoupling

capacitor of 0.01 µF

H_OC2

E10

overcurrent sense input for downstream port 2; both the digital and

analog overcurrent inputs can be used for port 2, depending on the

hardware mode register setting; when not in use, it is recommended that

you connect this pin to the V_DD(5V)pin

H_OC1

42

D9

I

overcurrent sensing input for downstream port 1; both the digital and

analog overcurrent inputs can be used for port 1, depending on the

hardware mode register setting; when not in use, it is recommended that

you connect this pin to the V_DD(5V)pin

X1

43

44

45

D10

C9

AI

AO

I

crystal input; directly connected to a 12 MHz crystal; when this pin is

connected to an external clock oscillator, leave pin X2 open

X2

crystal output; directly connected to a 12 MHz crystal; when pin X1 is

connected to an external clock oscillator, leave this pin open

OTGMODE

C10

to select whether port 1 is operating in OTG or non-OTG mode; see

Table 8

input with hysteresis

H_DM2

H_DP2

ID

46

47

48

B9

AI/O

I

downstream D− signal; host only, port 2; when not in use, leave this pin

open and set bit ConnectPullDown_DS2 of the

HcHardwareConﬁguration register

B10

A10

downstream D+ signal; host only, port 2; when not in use, leave this pin

open and set bit ConnectPullDown_DS2 of the

HcHardwareConﬁguration register

input pin for sensing OTG ID; the status of this input pin is reﬂected in the

OTGStatus register (bit 0); see Table 8

input with hysteresis

ISP1362_5

Product data sheet

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ISP1362

NXP Semiconductors

Single-chip USB OTG Controller

Table 2.

Pin description …continued

Symbol^[1]

Type

Description

LQFP64 TFBGA64

OTG_DM1

OTG_DP1

49

A9

AI/O

D− signal of the OTG port, the downstream host port 1 or the upstream

device port; when not in use, leave this pin open and set

bit ConnectPullDown_DS1 of the HcHardwareConﬁguration register^[2]

50

B8

AI/O

D+ signal of the OTG port, the downstream host port 1 or the upstream

device port; when not in use, leave this pin open and set

bit ConnectPullDown_DS1 of the HcHardwareConﬁguration register^[2]

AGND

V_CC

51

52

A8

B7

-

analog ground; used for OTG ATX

supply voltage (3.3 V); it is recommended that you connect a decoupling

capacitor of 0.01 µF

CP_CAP1

CP_CAP2

V_BUS

53

54

55

A7

B6

A6

AI/O

I/O

charge pump capacitor pin 1; low ESR; see Section 10.6

charge pump capacitor pin 2; low ESR; see Section 10.6

analog input and output

OTG mode — built-in charge pump output or V_BUSvoltage comparators

input; connect to pin V_BUSof the OTG connector

Peripheral Controller mode — input as V_BUSsensing; connect to

pin V_BUSof the upstream connector

Host Controller mode — not used; leave open

V_DD(5V)

56

B5

I

supply reference voltage (5 V); to be used together with built-in

overcurrent circuit; when built-in overcurrent circuit is not in use, this pin

can be tied to V_CC; it is recommended that you connect a decoupling

capacitor of 0.01 µF

DGND

V_CC

57

58

A5

B4

-

digital ground

supply voltage (3.3 V); it is recommended that you connect a decoupling

capacitor of 0.01 µF

TEST1

TEST2

A0

59

60

61

62

A4

B3

A3

B2

I/O

for test input and output, pulled to GND by a 10 kΩ resistor

bidirectional, push-pull input, 3-state output

for test input and output, pulled to GND by a 10 kΩ resistor

bidirectional, push-pull input, 3-state output

command or data phase

I/O

I

input

A1

LOW — PIO bus of the Host Controller is selected

HIGH — PIO bus of the Peripheral Controller is selected

input

D0

D1

63

64

A2

A1

I/O

bit 0 of the bidirectional data bus that connects to the internal registers

and buffer memory of the ISP1362; the bus is in the high-impedance

state when it is idle

bidirectional, push-pull input, 3-state output

bit 1 of the bidirectional data bus that connects to the internal registers

and buffer memory of the ISP1362; the bus is in the high-impedance

state when it is idle

bidirectional, push-pull input, 3-state output

[1] Symbol names with an overscore (for example, NAME) represent active LOW signals.

[2] In OTG mode, this pin is pulled down by an internal resistor.

ISP1362_5

Product data sheet

Rev. 05 — 8 May 2007

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ISP1362

NXP Semiconductors

Single-chip USB OTG Controller

7. Functional description

7.1 On-The-Go (OTG) controller

The OTG Controller provides all the control, monitoring and switching functions required

in OTG operations.

7.2 Advanced NXP Slave Host Controller

The advanced NXP Slave Host Controller is designed for highly optimized USB host

functionality. Many advanced features are integrated to fully utilize the USB bandwidth. A

number of tasks are performed at the hardware level. This reduces the requirement on the

microprocessor and thus speeds up the system.

7.3 NXP Peripheral Controller

The NXP Peripheral Controller is a high performance USB device with up to 14

programmable endpoints. These endpoints can be conﬁgured as double-buffered

endpoints to further enhance the throughput.

7.4 Phase-Locked Loop (PLL) clock multiplier

A 12 MHz-to-48 MHz clock multiplier PLL is integrated on-chip. This allows the use of a

low-cost 12 MHz crystal that also minimizes ElectroMagnetic Interference (EMI) because

of low frequency. No external components are required for the operation of PLL.

7.5 USB and OTG transceivers

The integrated transceivers (for typical downstream port) directly interface to the USB

connectors (type A) and cables through some termination resistors. The transceiver is

compliant with Ref. 2 “Universal Serial Bus Speciﬁcation Rev. 2.0”.

7.6 Overcurrent protection

The ISP1362 has a built-in overcurrent protection circuitry. This feature monitors the

current drawn on the downstream V_BUSand switches off V_BUSwhen the current exceeds

the current threshold. The built-in overcurrent protection feature can be used when the

port acts as a host port.

7.7 Bus interface

The bus interface connects the microprocessor to the USB host and the USB device,

allowing fast and easy access to both.

7.8 Peripheral Controller and Host Controller buffer memory

4096 bytes (host) and 2462 bytes (device) of built-in memory provide sufﬁcient space for

the buffering of USB trafﬁc. Memory in the Host Controller is addressable by using the fast

and versatile direct addressing method.

ISP1362_5

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ISP1362

NXP Semiconductors

Single-chip USB OTG Controller

7.9 GoodLink

Indication of a good USB connection is provided through the GoodLink technology

(open-drain, maximum current: 4 mA). During enumeration, LED indicators momentarily

blink on corresponding to the enumeration trafﬁc of the ISP1362 ports. The LED also

blinks on whenever there is valid trafﬁc to the USB ports. In ‘suspend’ mode, the LED is

off.

This feature of GoodLink provides a user-friendly indication on the status of the USB

trafﬁc between the host and the hub, as well as the connected devices. It is a useful

diagnostics tool to isolate faulty equipment, and helps to reduce ﬁeld support and hotline

costs.

7.10 Charge pump

The charge pump generates a 5 V supply from 3.3 V to drive V_BUSwhen the ISP1362 is

an A-device in OTG mode. For details, see Section 10.6.

8. Host and device bus interface

The interface between the external microprocessor and the ISP1362 Host Controller (HC)

and Peripheral Controller is separately handled by the individual bus interface circuitry.

The host or device automultiplex selects the path for the host access or the device access.

This selection is determined by the A1 address line. For any access to the Host Controller

or Peripheral Controller registers, the command phase and the data phase are needed,

which is determined by the A0 address line.

All the functionality of the ISP1362 can be accessed using a group of registers and two

buffer memory areas (one for the Host Controller and the other for the Peripheral

Controller). Registers can be accessed using Programmed I/O (PIO) mode. The buffer

memory can be accessed using both PIO and Direct Memory Access (DMA) modes.

When CS is LOW (active), address pin A1 has priority over DREQ and DACK. Therefore,

as long as the CS pin is held LOW, the ISP1362 bus interface does not respond to any

DACK signals. When CS is HIGH (inactive), the bus interface will respond to DREQn and

DACKn. Address pin A1 will be ignored when CS is inactive.

An active DACKn signal when DREQn is inactive will be ignored. If DREQ1, DACK1,

DREQ2 and DACK2 are active, the bus interface will be switched off to avoid potential

data corruption.

Table 3 provides the bus access priority for the ISP1362.

Table 3.

Bus access priority table for the ISP1362

Priority CS A1

DACK1

DACK2

DREQ1

DREQ2

Host Controller and Peripheral Controller active

Host Controller

1

2

3

4

5

L

X

L

X

L

X

H

L

X

L

H

X

Peripheral Controller

Host Controller^[1]

Peripheral Controller^[1]

H

X

H

X

H

no driving

[1] Only to enable and disable the bus. Depends only on the DACK signal.

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8.1 Memory organization

The buffer memory in the Host Controller uses a multiconﬁgurable direct addressing

architecture. The 4096 bytes Host Controller buffer memory is shared by the ISTL0,

ISTL1, INTL and ATL buffers. ISTL0 and ISTL1 are used for isochronous trafﬁc (double

buffer), INTL is used for interrupt trafﬁc, and ATL is used for control and bulk trafﬁc.

The allocation of the buffer memory follows the sequence ISTL0, ISTL1, INTL, ATL and

unused memory. For example, consider that the buffer sizes of the ISTL, INTL and ATL

buffers are 1024 bytes, 1024 bytes and 1024 bytes, respectively. Then, ISTL0 will start

from memory location 0, ISTL1 will start from memory location 1024 (size of ISTL0), INTL

will start from memory location 2048 (size of ISTL0 + size of ISTL1) and ATL will start

from memory location 3072 (size of ISTL0 + size of ISTL1 + size of INTL).

The Host Controller Driver (HCD) has the responsibility to ensure that the sum of the four

memory buffers does not exceed the total memory size. If this condition is violated, it will

lead to data corruption. The buffer size must be a multiple of 2 bytes (one word).

The buffer memory of the Peripheral Controller follows a similar architecture. Details on

the Peripheral Controller memory area allocation can be found in Section 12.3. Note that

the Peripheral Controller buffer memory does not support direct addressing mode.

8.1.1 Memory organization for the Host Controller

The Host Controller in the ISP1362 has a total of 4096 bytes of buffer memory. This buffer

area is divided into four parts (see Table 4 and Figure 4).

Table 4.

Buffer memory areas and their applications

Buffer memory area

ISTL0 and ISTL1

INTL

Application

isochronous transfer (double buffering)

interrupt transfer

ATL

control and bulk transfer

The ISTL0 and ISTL1 buffers must have the same size. Memory is allocated by the Host

Controller according to the value set by the HCD in HcISTLBufferSize, HcINTLBufferSize

and HcATLBufferSize. All buffer sizes must be multiples of 2 bytes (one word).

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0000h

ISTL0 area (512 bytes)

03FFh

0400h

ISTL1 area (512 bytes)

INTL area (512 bytes)

07FFh

0800h

09FFh

0A00h

ATL area (1536 bytes)

0FFFh

004aaa053

Fig 4. Recommended values of the ISP1362 buffer memory allocation

The INTL and ATL buffers use ‘blocked memory management’ scheme to enhance the

status and control capability of each and every individual Philips Transfer Descriptor

(PTD) structure. The INTL and ATL buffers are further divided into blocks of equal sizes,

depending on the value written to the HcATLBlkSize register (ATL) and the HcINTLBlkSize

register (INTL). The ISP1362 Host Controller supports up to 32 blocks in the ATL and

INTL buffers. Each of these blocks can be used for one complete PTD data.

Note that the block size does not include the 8 bytes PTD header and is strictly the size of

the payload. Both the ATL and INTL block sizes must be a multiple of double word

(4 bytes).

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Starting address of the

ATL or INTL buffer area

8 bytes PTD header

Block of 72 bytes

64 bytes PTD header

Payload are

(64 + 8,

where 64 is the block size defined)

8 bytes PTD header

72 bytes

64 bytes PTD header

Payload area

8 bytes PTD header

72 bytes

64 bytes PTD header

Payload area

004aaa055

Fig 5. A sample snapshot of the ATL or INTL memory management scheme

Figure 5 provides a snapshot of a sample ATL or INTL buffer area of 256 bytes with a

block size of 64 bytes. The HCD may put a PTD with payload size of up to 64 bytes but not

more. Depending on the ATL or INTL buffer size, up to 32 ATL blocks and 32 INTL blocks

can be allocated. Note that a portion of the ATL or INTL buffer remains unused. This is

allowed but can be avoided by choosing the appropriate ATL or INTL buffer size and block

size.

The ISTL0 or ISTL1 buffer memory (for isochronous transfer) uses a different memory

management scheme (see Figure 6). There is no ﬁxed block size for the ISTL buffer

memory. While the PTD header remains 8 bytes for all PTDs, the PTD payload can be of

any size. The PTD payload, however, is padded to the next double word boundary when

the Host Controller calculates the location of the next PTD header. The ISP1362 Host

Controller checks the payload size from the ‘Total size’ ﬁeld of the PTD itself and

calculates the location of the next PTD header based on this information.

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Starting address of ISTL0 or ISTL1

PTD header (Total size = 64)

72 bytes (64 + 8)

168 bytes (160 + 8)

40 bytes (32 + 8)

PTD payload (64 bytes)

PTD header (Total size = 160)

PTD payload (160 bytes)

PTD header (Total size = 32)

PTD payload (32 bytes)

004aaa054

‘Total size’ is a 10-bit ﬁeld in the PTD.

Fig 6. A sample snapshot of the ISTL memory management scheme

8.1.2 Memory organization for the Peripheral Controller

The ISP1362 Peripheral Controller has a total of 2462 bytes of built-in buffer memory. This

buffer memory is multiconﬁgurable to support the requirements of different applications.

The Peripheral Controller buffer memory is divided into 16 areas to be used by control

OUT, control IN and 14 programmable endpoints.

Figure 7 provides a snapshot of the Peripheral Controller buffer memory.

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Control OUT (64 bytes)

Control IN (64 bytes)

Endpoint 1 (128 bytes)

Endpoint 2 (128 bytes)

Endpoint 3 (512 bytes)

Endpoint 4 (64 bytes)

Endpoint 5 (64 bytes)

Endpoint 6 (96 bytes)

Endpoint 7 (96 bytes)

004aaa057

Fig 7. Peripheral Controller buffer memory organization

The buffer memory is conﬁgured by DcEndpointConﬁguration Registers (ECRs). Although

the control endpoint has a ﬁxed conﬁguration, all 16 endpoints (control OUT, control IN

and 14 programmable endpoints) must be conﬁgured before the Peripheral Controller

internally allocates the buffer. The 14 programmable endpoints can be programmed into

sizes ranging from 16 bytes to 1023 bytes, single or double buffering.

The Peripheral Controller buffer memory for each endpoint can be accessed through the

DcEndpointStatusImage registers.

8.2 PIO access mode

The ISP1362 provides PIO mode for external microprocessors to access its internal

control registers and buffer memory. It occupies only four I/O ports or four memory

locations of a microprocessor. An external microprocessor can read or write to the internal

control registers and buffer memory of the ISP1362 through PIO operating mode. Figure 8

shows the PIO interface between a microprocessor and the ISP1362.

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microprocessor

bus interface

[

]

[

]

D 15:0

RD

WR

CS

A1

RD

WR

CS

A2

MICRO-

PROCESSOR

ISP1362

A0

A1

INT1

INT2

IRQ1

IRQ2

004aaa042

Fig 8. PIO interface between a microprocessor and the ISP1362

8.3 DMA mode

The ISP1362 also provides DMA mode for external microprocessors to access the

internal buffer memory of the ISP1362. The DMA operation enables data to be transferred

between the system memory of a microprocessor and the internal buffer memory of the

ISP1362.

Remark: The DMA operation must be controlled by the DMA controller of the external

microprocessor system (master). Figure 9 shows the DMA interface between a

microprocessor system and the ISP1362.

The ISP1362 provides two DMA channels. DMA channel 1 (controlled by the DREQ1 and

DACK1 signals) is for the DMA transfer between the system memory of a microprocessor

and the internal buffer memory of the ISP1362 Host Controller. DMA channel 2 (controlled

by the DREQ2 and DACK2 signals) is for the DMA transfer between the system memory

of a microprocessor and the internal buffer memory of the ISP1362 Peripheral Controller.

The ISP1362 provides an internal End-Of-Transfer (EOT) signal to terminate the DMA

transfer.

microprocessor

bus interface

[

]

[

]

D 15:0

RD

WR

MICRO-

PROCESSOR

ISP1362

DACK1

DREQ1

DACK1

DREQ1

DACK2

DREQ2

DACK2

DREQ2

004aaa043

Fig 9. DMA interface between a microprocessor and the ISP1362

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8.4 PIO access to internal control registers

Table 5 shows the I/O port addressing in the ISP1362. The complete I/O port address

decoding must combine with the chip select signal (CS) and address lines (A1 and A0).

The direction of access of I/O ports, however, is controlled by the RD and WR signals.

When RD is LOW, the microprocessor reads data from the data port of the ISP1362 (see

Figure 10). When WR is LOW, the microprocessor writes command to the command port

or writes data to the data port (see Figure 11).

Table 5.

I/O port addressing

CS

L

A1

A0

L

Access Data bus width Description

L

R/W

W

16 bits

Host Controller data port

L

H

L

Host Controller command port

Peripheral Controller data port

Peripheral Controller command port

L

H

R/W

W

L

H

The register structure in the ISP1362 is a command-data register pair structure. A

complete register access needs a command phase followed by a data phase. The

command (also named as the index of a register) is used to inform the ISP1362 about the

register that will be accessed at the data phase.

On the 16-bit data bus of a microprocessor, a command occupies the lower byte and the

upper byte is ﬁlled with zeros (see Figure 12).

For 32-bit registers, the access cycle is shown in Figure 13. It consists of a command

phase followed by two data phases.

Bus interface

microprocessor

bus interface

Host bus interface

Device bus interface

004aaa122

0

1

A1

When A1 = L, the microprocessor accesses the Host Controller.

When A1 = H, the microprocessor accesses the Peripheral Controller.

Fig 10. Microprocessor access to the Host Controller or the Peripheral Controller

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CMD/DATA

SWITCH

host or device

bus interface

1

0

command port

data port

COMMANDS

Command register

.

A0

004aaa160

Control registers

When A0 = L, the microprocessor accesses the data port.

When A0 = H, the microprocessor accesses the command port.

Fig 11. Access to internal control registers

Read 16-bit

Write 16-bit

A0/A1

CS

RD

WR

D[15:0]

004aaa045

Fig 12. PIO register access

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Reading from a 16-bit or 32-bit register

32-bit access

16-bit access

A0/A1

CS

RD

WR

D[15:0]

Data phase

Second data phase

for 32-bit register

Command phase

Writing to a 16-bit or 32-bit register

32-bit access

16-bit access

A0/A1

CS

RD

WR

D[15:0]

Data phase

Command phase

Second data phase

for 32-bit register

004aaa046

Fig 13. PIO access for a 16-bit or 32-bit register

The following is a sample code for PIO access to internal control registers:

unsigned long read_reg32(unsigned char reg_no)

{

unsigned int result_l,result_h;

unsigned long result;

outport(hc_com, reg_no); // Command phase

result_l = inport(hc_data); // Data phase

result_h = inport(hc_data); // Data phase

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result = result_h;

result = result<<16;

result = result+result_l;

return(result);

}

void write_reg32(unsigned char reg_no, unsigned long data2write)

{

unsigned int low_word;

unsigned int hi_word;

low_word=data2write&0x0000FFFF;

hi_word=(data2write&0xFFFF0000)>>16;

outport(hc_com,reg_no|0x80); // Command phase

outport(hc_data,low_word); // Data phase

outport(hc_data,hi_word); // Data phase

}

unsigned int read_reg16(unsigned char reg_no)

{

unsigned int result;

outport(hc_com, reg_no); // Command phase

result = inport(hc_data); // Data phase

return(result);

}

void write_reg16(unsigned char reg_no, unsigned int data2write)

{

outport(hc_com,reg_no|0x80); // Command phase

outport(hc_data,data2write); // Data phase

}

8.5 PIO access to the buffer memory

The buffer memory in the ISP1362 can be addressed using either the direct addressing

method or the indirect addressing method.

8.5.1 PIO access to the buffer memory by using direct addressing

This method uses the HcDirectAddressLength register to specify two parameters required

to randomly access the ISP1362 buffer memory (total of 4096 bytes). These two

parameters are:

Starting address — location to start writing or reading

Data length — number of bytes to write or read.

The following is a sample code to set the HcDirectAddressLength register:

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void Set_DirAddrLen(unsigned int data_length,unsigned int addr)

{

unsigned long RegData = 0;

RegData =(long)(addr&0x7FFF);

RegData|=(((long)data_length)<<16);

write_reg32(HcDirAddrLen,RegData);

}

After the proper value is written to the HcDirectAddressLength register, data is accessible

from the HcDirectAddressData register (called as HcDirAddr_Port in the following sample

code). A sample code to write word_size bytes of data from *w_ptr to the memory

locations of the ISP1362 buffer starting from the address start_addr is as follows:

void direct_write(unsigned int *w_ptr,unsigned int start_addr,unsigned int word_size)

{

unsigned int cnt = 0;

Set_DirAddrLen(word_size*2,start_addr);

outport(hc_com,HcDirAddr_Port|0x80); // hc_com is system address of

// HC command port

do

{

outport(hc_data,*(w_ptr+cnt)); // hc_data is system address of

// HC data port

cnt++;

}

while(cnt<word_size);

}

Direct addressing allows fast and random access to any location within the ISP1362

memory. Your program, however, needs the address location of each buffer area to

access them.

8.5.2 PIO access to the buffer memory by using indirect addressing

Indirect addressing is the addressing method that is compatible with NXP ISP1161

addressing mode. This method uses a unique data port for each buffer memory area

(ATL, INTL, ISTL0 and ISTL1). These four data areas share the HcTransferCounter

register that is used to indicate the number of bytes to be transferred.

A sample code to write an array at *a_ptr into the ATL memory area with word_size as the

word size is given as follows:

void write_atl(unsigned int *a_ptr, unsigned int word_size)

{

int cnt;

write_reg16(HcTransferCnt,word_size*2);

outport(hc_com,HcATL_Port|0x80); // hc_com is system address of HC

// command port

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cnt=0;

do

{

outport(hc_data,*(a_ptr+cnt)); // hc_data is system address of HC

// data port

cnt++;

}

while(cnt<(word_size));

Remark: The HcTransferCounter register counts the number of bytes even though the

transfer is in number of words. Therefore, the transfer counter must be set to word_size ×

2. Incorrect setting of the HcTransferCounter register may cause the ISP1362 to go into an

indeterminate state.

The buffer memory access using indirect addressing always starts from location 0 of each

buffer area. Only the front portion of the memory (example: ﬁrst 64 bytes of a 1024 bytes

buffer) can be accessed. Therefore, to access a portion of the memory that does not start

from memory location 0, all memory locations before that location must be accessed in a

sequential order. The method is similar to the sequential ﬁle access method.

8.6 Setting up a DMA transfer

The ISP1362 uses two DMA channels to individually serve the Host Controller and the

Peripheral Controller. The DMA transfer allows the system CPU to work on other tasks

while the DMA controller transfers data to or from the ISP1362. The DMA slave controller,

in the ISP1362, is compatible with the 8327 type DMA controller.

The DMA transfer can be used with direct addressing mode or indirect addressing mode.

The registers used in these two modes are shown in Table 6.

Table 6.

Registers used in addressing modes

Addressing mode^[1]

Direct addressing

Indirect addressing

HcDMAConﬁguration bit[3:1]

Total bytes to transfer

HcDirectAddressLength

HcTransferCounter

1XXB

0XXB

[1] In direct addressing mode, HcTransferCounter must be set to 0001h.

8.6.1 Conﬁguring registers for a DMA transfer

To set up a DMA transfer, the following Host Controller registers must be conﬁgured,

depending on the type of transfer required:

• HcHardwareConﬁguration

– DREQ1 output polarity (bit 5)

– DACK1 input polarity (bit 6)

– DACK mode (bit 8)

• HcµPInterruptEnable

– If you want an interrupt to be generated after the DMA transfer is complete, set

EOTInterruptEnable (bit 3).

• HcµPInterrupt

– Before initiating the DMA transfer, clear AllEOTInterrupt (bit 3). This bit is set when

the DMA transfer is complete.

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• HcTransferCounter

– If DMACounterEnable of the HcDMAConﬁguration register is set (that is, the DMA

counter is enabled), HcTransferCounter must be set to the number of bytes to be

transferred.

• HcDMAConﬁguration

– Read or write DMA (bit 0)

– Targeted buffer: ISTL0, ISTL1, ATL and INTL (bits 1 to 3)

– DMA enable or disable (bit 4)

– Burst length (bits 5 to 6)

– DMA counter enable (bit 7)

Remark: Conﬁgure the HcDMAConﬁguration register only after you have conﬁgured all

the other registers. The ISP1362 will assert DREQ1 once the DMA enable bit in this

register is set.

8.6.2 Combining the two DMA channels

The ISP1362 allows systems with limited DMA channels to use a single DMA channel

(DMA1) for both the Host Controller and the Peripheral Controller. This option can be

enabled by writing logic 1 to the OneDMA bit of the HcHardwareConﬁguration register. If

this option is enabled, the polarity of the Peripheral Controller DMA and the Host

Controller DMA must be set to DACK active LOW and DREQ active HIGH.

8.7 Interrupts

Various events in the Host Controller, the Peripheral Controller and the OTG Controller

can be programmed to generate a hardware interrupt. By default, the interrupt generated

by the Host Controller and the OTG Controller is routed out at the INT1 pin and the

interrupt generated by the Peripheral Controller is routed out at the INT2 pin.

8.7.1 Interrupt in the Host Controller and the OTG Controller

There are two levels of interrupts represented by level 1 and level 2 (see Figure 14).

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OtgInterruptEnable register

OTG_TMR_IE

B_SE0_SRP_IE

A_SRP_DET_IE

OTG_RESUME_IE

OTG_SUSPND_IE

RMT_CONN_IE

B_SESS_VLD_IE

A_SESS_VLD_IE

B_SESS_END_IE

A_VBUS_VLD_IE

OR

ID_REG_IE

OtgInterrupt register

OTG_TMR_TIMEOUT

B_SE0_SRP

A_SRP_DET

level 2

OTG_RESUME

OTG_SUSPND

RMT_CONN_C

B_SESS_VLD_C

A_SESS_VLD_C

B_SESS_END_C

(OTG group)

HcµPInterrupt register

HcµPInterruptEnable register

A_VBUS_VLD_C

ID_REG_C

HcInterruptEnable register

MIE

RHSC

FNO

UE

RD

SF

SO

OR

HcInterruptStatus register

level 2

RHSC

FNO

UE

(OPR group)

RD

SF

OR

level 1

SO

LE

From INT2

LATCH

InterruptPinEnable

INT1

HcHardwareConfiguration

register

OneINT

HcHardwareConfiguration

register

004aaa395

Fig 14. HC and OTG interrupt logic

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Interrupt level 2 (OPR group) contains six possible interrupt events (recorded in the

HcInterruptStatus register). When any of these events occurs, the corresponding bit will

be set to logic 1, and if the corresponding bit in the HcInterruptEnable register is also

logic 1, the 6-input OR gate will output logic 1. This output is combined with the value of

MIE (bit 31 of HcInterruptEnable) using the AND operation and logic 1 output at this AND

gate will cause the OPR bit in the HcµPInterrupt register to be set to logic 1.

Interrupt level 2 (OTG group) contains 11 possible interrupt events (recorded in the

OtgInterrupt register). When any of these events occurs, the corresponding bit will be set

to logic 1, and if the corresponding bit in the OtgInterruptEnable register is also logic 1,

the 11-input OR gate will output logic 1 and cause the OTG_IRQ bit in the HcµPInterrupt

register to be set to logic 1.

Level 1 interrupts contains 10 possible interrupt events. The HcµPInterrupt and

HcµPInterruptEnable registers work in the same way as the HcInterruptStatus and

HcInterruptEnable registers. The output from the 10-input OR gate is connected to a latch,

which is controlled by InterruptPinEnable (the bit 0 of HcHardwareConﬁguration register).

When the software wishes to temporarily disable the interrupt output of the ISP1362 Host

Controller and OTG Controller, follow this procedure:

1. Set the InterruptPinEnable bit in the HcHardwareConﬁguration register to logic 1.

2. Clear all bits in the HcµPInterrupt register.

3. Set the InterruptPinEnable bit to logic 0.

To re-enable the interrupt generation, set the InterruptPinEnable bit to logic 1.

Remark: The InterruptPinEnable bit in the HcHardwareConﬁguration register controls the

latch of the interrupt output. When this bit is set to logic 0, the interrupt output will remain

unchanged, regardless of any operation on interrupt control registers.

If INT1 is asserted, and the HCD wishes to temporarily mask off the INT signal without

clearing the HcµPInterrupt register, follow this procedure:

1. Make sure that the InterruptPinEnable bit is set to logic 1.

2. Clear all bits in the HcµPInterruptEnable register.

3. Set the InterruptPinEnable bit to logic 0.

To re-enable the interrupt generation:

1. Set all bits in the HcµPInterruptEnable register, according to the HCD requirements.

2. Set the InterruptPinEnable bit to logic 1.

8.7.2 Interrupt in the Peripheral Controller

The registers that control the interrupt generation in the ISP1362 Peripheral Controller

are:

• DcMode (bit 3)

• DcHardwareConﬁguration (bits 0 and 1)

• DcInterruptEnable

• DcInterrupt

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The DcMode register (bit 3) is the overall Peripheral Controller interrupt enable.

DcHardwareConﬁguration determines the following features:

• Level-triggered or edge-triggered (bit 1)

• Output polarity (bit 0)

For details on the interrupt logic in the Peripheral Controller, refer to Ref. 5 “Interrupt

Control application note”.

8.7.3 Combining INT1 and INT2

In some embedded systems, interrupt inputs to the CPU are a very scarce resource. The

system designer might want to use just one interrupt line to serve the Host Controller, the

Peripheral Controller and the OTG Controller. In such a case, make sure the OneINT

feature is activated.

When OneINT (bit 9 of the HcHardwareConﬁguration register) is set to logic 1, both the

INT1 (HC or OTG Controller) interrupt and the INT2 (Peripheral Controller) interrupt are

routed to pin INT1, thereby reducing hardware resource requirements.

Remark: Both the Host Controller (or OTG Controller) and the Peripheral Controller

interrupts must be set to the same polarity (active HIGH or active LOW) and the same

trigger type (edge or level). Failure to conform to this will lead to unpredictable behavior of

the ISP1362.

8.7.4 Behavior difference between level-triggered and edge-triggered interrupts

In many microprocessor systems, the operating system disables an interrupt when it is in

an Interrupt Service Routine (ISR). If there is an interrupt event during this period, it will

lead to level-triggered interrupt and edge-triggered interrupt.

8.7.4.1 Level-triggered interrupt

When the ISP1362 interrupt asserts, the operating system takes no action because it

disables the interrupt when it is in the ISR. The interrupt line of the ISP1362 remains

asserted. When the operating system exits the ISR and re-enables the interrupt

processing, it sees the asserted interrupt line and immediately enters the ISR.

8.7.4.2 Edge-triggered interrupt

When the ISP1362 outputs a pulse, the operating system takes no action because it

disables the interrupt when it is in the ISR. The interrupt line of the ISP1362 goes back to

the inactive state. When the operating system exits the ISR and re-enables the interrupt

processing, it sees no pending interrupt. As a result, the interrupt is missed.

If the system needs to know whether an interrupt (approximately 160 ns pulse width)

occurs during this period, it may read the HcµPInterrupt register (see Table 69).

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9. Power-On Reset (POR)

When V_CCis directly connected to the RESET pin, the internal POR pulse width (t_PORP

)

will typically be 800 ns. The pulse is started when V_CCrises above V_trip(2.03 V).

To give a better view of the functionality, Figure 15 shows a possible curve of V_CCwith

dips at t2 to t3 and t4 to t5. If the dip at t4 to t5 is too short (that is, < 11 µs), the internal

POR pulse will not react and will remain LOW. The internal POR starts with a HIGH at t0.

At t1, the detector will see the passing of the trip level and a delay element will add

another t_PORPbefore it drops to LOW.

The internal POR pulse will be generated whenever V_CCdrops below V_tripfor more than

11 µs.

V

CC

V

trip

t0

t1

t2

t3

t4

t5

(1)

t

PORP

t

PORP

004aaa482

(1) PORP = Power-On Reset Pulse.

Fig 15. Internal power-on reset timing

The RESET pin can be either connected to V_CC(using the internal POR circuit) or

externally controlled (by the micro, ASIC, and so on). Figure 16 shows the availability of

the clock with respect to the external reset pulse.

RESET

EXTERNAL CLOCK

004aaa484

A

Stable external clock is available at A.

Fig 16. Clock with respect to the external power-on reset

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10. On-The-Go (OTG) Controller

10.1 Introduction

OTG is a supplement to the Hi-Speed USB (USB 2.0) speciﬁcation that augments existing

USB peripherals by adding to these peripherals limited host capability to support other

targeted USB peripherals. It is primarily targeted at portable devices because it addresses

concerns related to such devices, such as a small connector and low power. Non-portable

devices (even standard hosts), nevertheless, can also beneﬁt from OTG features.

The ISP1362 OTG Controller is designed to perform all the tasks speciﬁed in the OTG

supplement. It supports Host Negotiation Protocol (HNP) and Session Request Protocol

(SRP) for dual-role devices. The ISP1362 uses software implementation of HNP and SRP

for maximum ﬂexibility. A set of OTG registers provides the control and status monitoring

capabilities to support software HNP or SRP.

Besides the normal USB transceiver, timers and analog components required by OTG are

also integrated on-chip. The analog components include:

• Built-in 3.3 V-to-5 V charge pump

• Voltage comparators

• Pull-up or pull-down resistors on data lines

• Charge or discharge resistors for V_BUS

10.2 Dual-role device

When port 1 of the ISP1362 is conﬁgured in OTG mode, it can be used as an OTG

dual-role device. A dual-role device is a USB device that can function either as a host or

as a peripheral. As a host, the ISP1362 can support all four types of transfers (control,

bulk, isochronous and interrupt) at full-speed or low-speed. As a peripheral, the ISP1362

can support two control endpoints and up to 14 conﬁgurable endpoints, which can be

programmed to any of the four transfer types.

The default role of the ISP1362 is controlled by the ID pin, which in turn is controlled by

the type of plug connected to the mini-AB receptacle. If ID = LOW (mini-A plug

connected), it becomes an A-device, which is a host by default. If ID = HIGH (mini-B plug

connected), it becomes a B-device, which is a peripheral by default.

Both the A-device and the B-device work on a session base. A session is deﬁned as the

period of time in which devices exchange data. A session starts when V_BUSis driven and

ends when V_BUSis turned off. Both the A-device and the B-device may start a session.

During a session, the role of the host can be transferred back and forth between the

A-device and the B-device any number of times by using HNP.

If the A-device wants to start a session, it turns on V_BUSby enabling the charge pump. The

B-device detects that V_BUShas risen above the B_SESS_VLD level and assumes the role

of a peripheral, asserting its pull-up resistor on the DP line. The A-device detects the

remote pull-up resistor and assumes the role of a host. Then, the A-device can

communicate with the B-device as long as it wishes. When the A-device ﬁnishes

communicating with the B-device, the A-device turns-off V_BUSand both the devices ﬁnally

go into the idle state. See Figure 18 and Figure 19.

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If the B-device wants to start a session, it must initiate SRP by ‘data line pulsing’ and

‘V_BUSpulsing’. When the A-device detects any of these SRP events, it turns on its V_BUS

(note that only the A-device is allowed to drive V_BUS). The B-device assumes the role of a

peripheral, and the A-device assumes the role of a host. The A-device detects that the

B-device can support HNP by getting the OTG descriptor from the B-device. The A-device

will then enable the HNP hand-off by using SetFeature (b_hnp_enable) and then go into

the ‘suspend’ state. The B-device signals claiming the host role by de-asserting its pull-up

resistor. The A-device acknowledges by going into the peripheral state. The B-device then

assumes the role of a host and communicates with the A-device as long as it wishes.

When the B-device ﬁnishes communicating with the A-device, both the devices ﬁnally go

into the idle state. See Figure 18 and Figure 19.

10.3 Session Request Protocol (SRP)

As a dual-role device, the ISP1362 can initiate and respond to SRP. The B-device initiates

SRP by data line pulsing, followed by V_BUSpulsing. The A-device can detect either data

line pulsing or V_BUSpulsing.

10.3.1 B-device initiating SRP

The ISP1362 can initiate SRP by performing the following steps:

1. Detect initial conditions [read ID_REG, B_SESS_END and SE0_2MS (bits 0, 2 and 9)

of the OtgStatus register].

2. Start data line pulsing [set LOC_CONN (bit 4) of the OtgControl register to logic 1].

3. Wait for 5 ms to 10 ms.

4. Stop data line pulsing [set LOC_CONN (bit 4) of the OtgControl register to logic 0].

5. Start V_BUSpulsing [set CHRG_V_BUS(bit 1) of the OtgControl register to logic 1].

6. Wait for 10 ms to 20 ms.

7. Stop V_BUSpulsing [set CHRG_V_BUS(bit 1) of the OtgControl register to logic 0].

8. Discharge V_BUSfor about 30 ms [by using DISCHRG_V_BUS(bit 2) of the OtgControl

register], optional.

The B-device must complete both data line pulsing and V_BUSpulsing within 100 ms.

10.3.2 A-device responding to SRP

The A-device must be able to respond to one of the two SRP events: data line pulsing or

V_BUSpulsing. The ISP1362 allows you to choose which SRP to support and has a

mechanism to disable or enable the SRP detection. This is useful for some applications

under certain cases. For example, if the A-device battery is low, it may not want to turn on

its V_BUSby detecting SRP. In this case, it may choose to disable the SRP detection

function.

When the data line SRP detection is used, the ISP1362 can detect either the DP pulsing

or the DM pulsing. This means a peripheral-only device can initiate data line pulsing SRP

through DP (full-speed) or DM (low-speed). A dual-role device will always initiate data line

pulsing SRP through DP because it is a full-speed device.

• Steps to enable the SRP detection by V_BUSpulsing:

– Set A_SEL_SRP (bit 9) of the OtgControl register to logic 0.

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– Set A_SRP_DET_EN (bit 10) of the OtgControl register to logic 1.

• Steps to enable the SRP detection by data line pulsing:

– Set A_SEL_SRP (bit 9) of the OtgControl register to logic 1.

– Set A_SRP_DET_EN (bit 10) of the OtgControl register to logic 1.

• Steps to disable the SRP detection:

– Set A_SRP_DET_EN (bit 10) of the OtgControl register to logic 0.

10.4 Host Negotiation Protocol (HNP)

HNP is used to transfer control of the host role between the default host (A-device) and

the default peripheral (B-device) during a session. When the A-device is ready to give up

its role as a host, it will condition the B-device by SetFeature (b_hnp_enable) and will go

into ‘suspend’. If the B-device wants to use the bus at that time, it signals a ‘disconnect’ to

the A-device. Then, the A-device will take the role of a peripheral and the B-device will

take the role of a host.

10.4.1 Sequence of HNP events

The sequence of events for HNP as observed on the USB bus is illustrated in Figure 17.

A-device

1

6

8

3

B-device

5

2

7

4

DP Composite

004aaa079

DP driven

Legend

Pull-up dominates

Pull-down dominates

Normal bus activity

Fig 17. HNP sequence of events

As can be seen in Figure 17:

1. The A-device completes using the bus and stops all bus activities (that is, suspends

the bus).

2. The B-device detects that the bus is idle for more than 5 ms and begins HNP by

turning off the pull-up on DP. This allows the bus to discharge to the SE0 state.

3. The A-device detects SE0 on the bus and recognizes this as a request from the

B-device to become a host. The A-device responds by turning on its DP pull-up within

3 ms of ﬁrst detecting SE0 on the bus.

4. After waiting for 30 µs to ensure that the DP line is not HIGH because of the residual

effect of the B-device pull-up, the B-device notices that the DP line is HIGH and the

DM line is LOW (that is, J state). This indicates that the A-device has recognized the

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HNP request from the B-device. At this point, the B-device becomes a host and

asserts bus reset to start using the bus. The B-device must assert the bus reset (that

is, SE0) within 1 ms of the time that the A-device turns on its pull-up.

5. When the B-device completes using the bus, it stops all bus activities. Optionally, the

B-device may turn on its DP pull-up at this time.

6. The A-device detects lack of bus activities for more than 3 ms and turns off its DP

pull-up. Alternatively, if the A-device has no further need to communicate with the

B-device, the A-device may turn off V_BUSand end the session.

7. The B-device turns on its pull-up.

8. After waiting 30 µs to ensure that the DP line is not HIGH because of the residual

effect of the A-device pull-up, the A-device notices that the DP line is HIGH (and the

DM line is LOW) indicating that the B-device is signaling a connect and is ready to

respond as a peripheral. At this point, the A-device becomes a host and asserts the

bus reset to start using the bus.

10.4.2 OTG state diagrams

Figure 18 and Figure 19 show the state diagrams for the dual-role A-device and the

dual-role B-device, respectively. For a detailed explanation, refer to Ref. 1 “On-The-Go

Supplement to the USB 2.0 Speciﬁcation Rev. 1.0a”.

The OTG state machine is implemented with software. The inputs to the state machine

come from four sources: hardware signals from the USB bus, software signals from the

application program, internal variables with the state machines and timers:

• Hardware inputs: Include id, a_vbus_vld, a_sess_vld, b_sess_vld, b_sess_end,

a_conn, b_conn, a_bus_suspend, b_bus_suspend, a_bus_resume, b_bus_resume,

a_srp_det and b_se0_srp. All these inputs can be derived from the OtgInterrupt and

OtgStatus registers.

• Software inputs: Include a_bus_req, a_bus_drop and b_bus_req.

• Internal variables: Include a_set_b_hnp_en, b_hnp_enable and b_srp_done.

• Timers: The HNP state machine uses four timers: a_wait_vrise_tmr,

a_wait_bcon_tmr, a_aidl_bdis_tmr and b_ase0_brst, tmr. All timers are started on

entry to and reset on exit from their associated states. The ISP1362 provides a

programmable timer that can be used as any of these four timers.

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b_idle

drv_vbus/

chrg_vbus/

loc_conn/

loc_sof/

START

a_idle

drv_vbus/

chrg_vbus/

loc_conn/

loc_sof/

id

id | a_bus_req |

(a_sess_vld/ &

b_conn/)

a_bus_drop/ &

(a_bus_req |

a_srp_det)

id | a_bus_drop |

a_wait_vfall

a_wait_bcon_tmout

a_wait_vrise

drv_vbus

loc_conn/

loc_sof/

drv_vbus/

loc_conn/

loc_sof/

id | a_bus_drop

b_bus_suspend

id | a_bus_drop |

a_vbus_vld |

a_wait_vrise_tmout

id | a_bus_drop

a_vbus_err

drv_vbus/

loc_conn/

loc_sof/

a_vbus_vld/

a_peripheral

drv_vbus

loc_conn

loc_sof/

a_wait_bcon

a_vbus_vld/

drv_vbus

loc_conn/

loc_sof/

b_conn/ &

a_set_b_hnp_en/

b_conn/ &

a_set_b_hnp_en

id |

b_conn/ |

b_conn

id |

a_bus_drop

a_bus_drop |

a_aidl_bdis_tmout

a_bus_req |

b_bus_resume

a_suspend

a_host

drv_vbus

loc_conn/

loc_sof/

drv_vbus

loc_conn/

loc_sof

a_bus_req/ |

a_suspend_req

004aaa077

Fig 18. Dual-role A-device state diagram

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a_idle

drv_vbus/

chrg_vbus/

loc_conn/

loc_sof/

START

b_idle

drv_vbus/

chrg_vbus/

loc_conn/

loc_sof/

id/

b_bus_req &

b_sess_end &

b_se0_srp

id/ |

b_sess_vld/

id/ |

b_srp_done

id/ |

b_sess_vld/

b_host

b_srp_init

pulse loc_conn

pulse chrg_vbus

loc_sof/

chrg_vbus/

loc_conn/

loc_sof

id/ |

b_sess_vld/

b_sess_vld

b_bus_req/ |

a_conn/

a_conn

a_bus_resume |

b_ase0_brst_tmout

b_wait_acon

b_peripheral

chrg_vbus/

loc_conn

chrg_vbus/

loc_conn/

loc_sof/

b_bus_req &

b_hnp_en &

a_bus_suspend

loc_sof/

004aaa078

Fig 19. Dual-role B-device state diagram

10.4.3 HNP implementation and OTG state machine

The OTG state machine is the software behind all the OTG functionality. It is implemented

in the microprocessor system that is connected to the ISP1362. The ISP1362 provides all

input status, the output control and timers to fully support the state machine transitions in

Figure 18 and Figure 19.

These registers include:

• OtgControl register: provides control to V_BUSdriving, charging or discharging, data

line pull-up or pull-down, SRP detection, and so on.

• OtgStatus register: provides status detection on V_BUSand data lines including ID,

V_BUSsession valid, session end, overcurrent, bus status.

• OtgInterrupt register: provides interrupts for status change in OtgStatus register bits

and the OtgTimer time-out event.

• OtgInterruptEnable register: provides interrupt mask for OtgInterrupt register bits.

• OtgTimer register: provides 0.01 ms base programmable timer for use in the OTG

state machine.

The OTG interrupt is generated on the INT1 pin. It is shared with the Host Controller

interrupt. To enable the OTG interrupt, perform these steps:

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1. Set the polarity and level-triggering or edge-triggering mode of the

HcHardwareConﬁguration register (bits 1 and 2, default is level-triggered, active

LOW).

2. Set the corresponding bits of the OtgInterruptEnable register (bits 0 to 8, or some of

them).

3. Set bit OTG_IRQ_InterruptEnable of the HcµPInterruptEnable register (bit 9).

4. Set bit InterruptPinEnable of the HcHardwareConﬁguration register (bit 0).

When an interrupt is generated on INT1, perform these steps in the ISR to get the related

OTG status:

1. Read the HcµPInterrupt register. If OTG_IRQ (bit 9) is set, then step 2.

2. Read the OtgInterrupt register. If any of the bits 0 to 4 are set, then step 3.

3. Read the OtgStatus register.

The OTG state machine routines are called when any of the inputs is changed. These

inputs come from either OTG registers (hardware) or application program (software). The

outputs of the state machine include control signals to the OTG register (for hardware)

and states or error codes (for software). For more information, refer to NXP document Ref.

3 “ISP136x Embedded Programming Guide (UM10008)”.

10.5 Power saving in the idle state and during wake-up

The ISP1362 can be put in power saving mode if the OTG device is not in a session. This

signiﬁcantly reduces the power consumption. In this mode, both the Peripheral Controller

and the Host Controller are suspended. The PLL and the oscillator are stopped, and the

charge pump is in the suspend state.

As an OTG device, however, the ISP1362 is required to respond to the SRP event. To

support this, a LazyClock is kept running when the chip is in power saving mode. An SRP

event will wake-up the chip (that is, enable the PLL and the oscillator). Besides this, an ID

change or B_SESS_VLD detection can also wake-up the chip. These wake-up events can

be enabled or disabled by programming the related bits of the OtgInterruptEnable register

before putting the chip in power saving mode. If the bit is set, then the corresponding

event (status change) will wake-up the ISP1362. If the bit is cleared, then the

corresponding event will not wake-up the ISP1362.

You can also wake-up the ISP1362 from power saving mode by using software. This is

accomplished by accessing any of the ISP1362 registers. Accessing a register will assert

CS of the ISP1362, and therefore, set it awake.

10.6 Current capacity of the OTG charge pump

The ISP1362 uses a built-in charge pump to generate a 5 V V_BUSsupply from a 3.3 V ±

0.3 V voltage source. The only external component required is a capacitor. The value of

this capacitor depends on the amount of current drive required. Table 7 provides two

recommended capacitor values and the corresponding current drive.

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Table 7.

Recommended capacitor values

Capacitance

27 nF

V_CC

Current

8 mA

3.0 V to 3.6 V

3.0 V to 3.3 V

3.3 V to 3.6 V

82 nF

14 mA

20 mA

The connection of the external capacitor (C_ext) is given in the partial schematics in

Figure 20.

Remark: If the internal charge pump is not used, C_extis not required.

V

OTG V

BUS

0.1 µF

4.7 µF

ISP1362

CP_CAP2

CP_CAP1

C

ext

004aaa154

Fig 20. External capacitors connection

11. USB Host Controller (HC)

11.1 USB states of the Host Controller

The USB Host Controller in the ISP1362 has four USB states: USBOperational,

USBReset, USBSuspend and USBResume. These states deﬁne the responsibilities of

the Host Controller related to the USB signaling and bus states. These signals are visible

to the Host Controller Driver (HCD), the software driver of the Host Controller, by using the

control registers of the ISP1362 USB Host Controller.

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USBOperational

USBReset write

USBOperational write

USBReset write

USBOperational write

USBResume

USBReset

USBSuspend write

hardware or software

reset

USBResume write

or

remote wake-up

USBReset write

mgt947

USBSuspend

Fig 21. USB Host Controller states of the ISP1362

The USB states are reﬂected in the HostControllerFunctionalState (HCFS) ﬁeld of the

HcControl register. The HCD is allowed to perform only USB state transitions shown in

Figure 21.

11.2 USB trafﬁc generation

USB trafﬁc can be generated only when the ISP1362 USB Host Controller is under the

USBOperational state. Therefore, the HCD must set the ISP1362 USB HC in the

USBOperational state. This is done by setting the HCFS ﬁeld of the HcControl register

before generating USB trafﬁc.

A brief ﬂow of the USB trafﬁc generation is described as follows:

1. Reset the ISP1362 by using the RESET pin or the software reset.

2. Set the physical size of the ATL, interrupt, ISTL0 and ISTL1 buffers.

3. Write 32-bit hexadecimal value 8000 00FDh to the HcInterruptEnable register. This

will enable all the interrupt events in the register to trigger the hardware interrupt (see

Section 14.1.5).

4. Write 16-bit hexadecimal value 002Dh to the HcHardwareConﬁguration register. This

will set up the Host Controller to level triggered and active HIGH interrupt setting (see

Section 14.4.1).

5. Write 0500 0B02h to HcRhDescriptorA and 0000 0000h to HcRhDescriptorB.

6. Write 16-bit hexadecimal value 0680h to the HcControl register to set the ISP1362

into operation mode (see Section 14.1.2).

7. Read the HcRhPortStatus[1] and HcRhPortStatus[2] registers. These registers

contain 32-bit hexadecimal value 0001 0100h (see Section 14.3.4).

8. Connect a full-speed device to one of the downstream ports or use a 1.5 kΩ resistor

to pull up the DP line (to emulate a full-speed device).

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9. Read the HcRhPortStatus[1] and HcRhPortStatus[2] registers. The hexadecimal

value of one of the registers must change to 0001 0101h, indicating that a device

connection has been detected.

10. Write 32-bit hexadecimal value 0000 0102h into either HcRhPortStatus[1] or

HcRhPortStatus[2], depending on the port that is being used.

11. Read the HcRhPortStatus[1] and HcRhPortStatus[2] registers. Depending on which

port the USB device is connected to, one of the registers should contain hexadecimal

value 0001 0103h.

SOF packets should be visible on DP and DM now.

The HcFmNumber register contains the current frame number, which is updated every

milliseconds.

Remark: The generation of SOF is completely performed by the ISP1362 hardware. In

this state of operation, if a PTD is written to the buffer memory, it will be processed and

sent.

11.3 USB ports

The ISP1362 has two USB ports: port 1 and port 2. Port 1 can be conﬁgured as a

downstream port (host), an upstream port (device) or a dual-role port (OTG). Port 2 is a

ﬁxed downstream port.

The function of port 1 depends on two input pins of the ISP1362, namely ID and

OTGMODE.

Table 8.

Port 1 function

OTGMODE

ID

X

Function of port 1

OTG

L

H

L

host

H

peripheral

In OTG mode, port 2 operates as an internal host. It is not advisable to expose host port 2

to external devices because it will not respond to the SRP and HNP protocols. Besides,

the current capability of V_BUSmay be different from the OTG port’s. The USB compliance

checklist states that one and only one USB mini-AB receptacle is allowed on an OTG

device.

11.4 Philips Transfer Descriptor (PTD)

PTD provides a communication channel between the HCD and the ISP1362 USB Host

Controller. A PTD consists of a PTD header and a payload data. The size of the PTD

header is 8 bytes, and it contains information required for data transfer, such as data

packet size, transfer status and transfer token types. Payload data to be transferred within

a particular frame must have a PTD as the header (see Figure 22).

The ISP1362 has three types of PTDs: control and bulk transfer (aperiodic transfer) PTD,

interrupt transfer PTD and Isochronous (ISO) transfer PTD.

In the control and bulk transfer PTD and the interrupt transfer PTD, the buffer area is

separated into equal sized blocks that are determined by HcATLBlkSize and

HcINTLBlkSize. For example, if the block size is deﬁned as 32 bytes, the ﬁrst PTD

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structure in the memory buffer will have an offset of 0 bytes and the second PTD structure

will have an offset of 40 bytes [sum of the block size (32 bytes) and the PTD header size

(8 bytes)]. Because of the ﬁxed block size of the ISP1362 Host Controller, however, even a

PTD with 4 bytes of payload will occupy all the 40 bytes in a block.

In the isochronous PTD, the Host Controller uses a more ﬂexible method to calculate the

PTD offset because each PTD can have a different payload size. The actual amount of

space for the payload, however, must be a multiple of double word. Therefore, a 10 bytes

payload must have a reserved data size of 12 bytes. Take for example there are four PTDs

in the ISTL0 buffer area with payload sizes of 200 bytes, 10 bytes, 1023 bytes and

30 bytes. Then, the offset of each of these PTDs will be as follows:

PTD1 (200 bytes) — offset = 0

PTD2 (10 bytes) — offset = (200 + 8) = 208

PTD3 (1023 bytes) — offset = (200 + 8) + (12 + 8) = 228

PTD4 (30 bytes) — offset = (200 + 8) + (12 + 8) + (1024 + 8) = 1260

The PTD data stored in the Host Controller buffer memory will not be processed, unless

the respective control bits (ATL_Active, INTL_Active, ISTL0_BufferFull or

ISTL1_BufferFull) in HcBufferStatus are set.

The PTD data in the ATL or interrupt buffer memory can be disabled by setting the

respective skip bit in HcATLPTDSkipMap and HcINTLPTDSkipMap. To skip a particular

PTD in the ATL or interrupt buffer, the HCD may set the corresponding bit of the SkipMap

register. For example, setting the HcATLPTDSkipMap register to 0011h will cause the

Host Controller to skip the ﬁrst and the ﬁfth PTDs in the ATL buffer memory.

Certain ﬁelds in the PTD header are used by the Host Controller to inform the HCD about

the status of the transfer. These ﬁelds are indicated by the ‘Status Update by HC’ column.

These ﬁelds are updated after every transaction to reﬂect the current status of the PTD.

buffer memory

top

PTD header

PTD data #1

payload data

PTD header

PTD data #2

payload data

PTD header

PTD data #N

payload data

bottom

004aaa121

Fig 22. PTD data stored in the buffer memory

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Table 9.

Bit^[1]

Generic PTD structure: bit allocation

7

6

5

4

3

2

1

0

Byte 0

Byte 1

Byte 2

Byte 3

Byte 4

Byte 5

Byte 6

Byte 7

ActualBytes[7:0]

Active

MaxPktSize[7:0]

B3[3]

TotalBytes[7:0]

DirToken[1:0]

CompletionCode[3:0]

EndpointNumber[3:0]

Toggle

Speed

ActualBytes[9:8]

MaxPktSize[9:8]

TotalBytes[9:8]

B5[7]

B5[6]

reserved

FunctionAddress[6:0]

B7[7:0]

[1] All reserved bits should be set to logic 0.

Table 10. Special ﬁelds for ATL, interrupt and ISO

Bit^[1]

ATL

Interrupt

reserved

ISTL (ISO)

Last

B3[3]

B5[6]

B5[7]

B7[7:0]

reserved

Ping-Pong

Paired

reserved

StartingFrame

reserved

PollingRate[7:5];

StartingFrame[4:0]

[1] All reserved bits should be set to logic 0.

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Table 11. Generic PTD structure: bit description

Name

Status update Description

by HC

ActualBytes[9:0]

Yes

This ﬁeld contains the number of bytes that were transferred for this PTD.

CompletionCode[3:0]

0000

NoError

General Transfer Descriptor (TD) or

isochronous data packet processing

completed with no detected errors.

0001

CRC

The last data packet from the endpoint

contained a Cyclic Redundancy Check

(CRC) error.

0010

0011

BitStufﬁng

The last data packet from the endpoint

contained a bit stufﬁng violation.

DataToggleMismatch The last packet from the endpoint had data

toggle Packet ID (PID) that did not match the

expected value.

0100

0101

0110

0111

1000

Stall

TD was moved to the Done queue because

the endpoint returned a STALL PID.

DeviceNot

Responding

The device did not respond to the token (IN)

or did not provide a handshake (OUT).

PIDCheckFailure

UnexpectedPID

DataOverrun

The check bits on PID from the endpoint

failed on data PID (IN) or handshake (OUT).

The received PID was not valid when

encountered, or the PID value is not deﬁned.

The amount of data returned by the endpoint

exceeded either the size of the maximum

data packet allowed from the endpoint (found

in the MaxPacketSize ﬁeld of ED) or the

remaining buffer size.

1001

DataUnderrun

The endpoint returned is less than

MaxPacketSize and that amount was not

sufﬁcient to ﬁll the speciﬁed buffer.

1010

1011

1100

-

reserved

-

BufferOverrun

During an IN, the Host Controller received

data from the endpoint faster than it could be

written to the system memory.

1101

BufferUnderrun

During an OUT, the Host Controller could not

retrieve data from the system memory fast

enough to keep up with the USB data rate.

Active

Toggle

Yes

Set to logic 1 by ﬁrmware to enable the execution of transactions by the Host

Controller. When the transaction associated with this descriptor is completed,

the Host Controller sets this bit to logic 0, indicating that a transaction for this

element should not be executed when it is next encountered in the schedule.

This bit is used to generate or compare the data PID value (DATA0 or DATA1)

for IN and OUT transactions. It is updated after each successful transmission

or reception of a data packet.

MaxPktSize[9:0]

No

This indicates the maximum number of bytes that can be sent to or received

from the endpoint in a single data packet.

EndpointNumber[3:0]

This is the USB address of the endpoint within the function.

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Table 11. Generic PTD structure: bit description …continued

Name

Status update Description

by HC

B3[3] Last (PTD)

No

This indicates that it is the last PTD of a list. Logic 1 means that this PTD is

the last PTD. The last PTD is used only for ISO. This bit is not used in the

interrupt and ATL transfers. The last PTD is indicated by the HcINTLLastPTD

and HcATLLastPTD registers.

Speed (low)

No

This bit indicates the speed of the endpoint.

0 — full-speed

1 — low-speed

TotalBytes[9:0]

No

This speciﬁes the total number of bytes to be transferred with this data

structure. This can be greater than MaxPacketSize.

B5[6] Ping-Pong

0 — This is the ping buffer of the paired buffer. Paired must be logic 1.

1 — This is the pong buffer of the paired buffer. Paired must be logic 1.

B5[7] Paired

No

If this bit is set to logic 1, two PTDs of the same endpoint and address can be

made active at the same time. This bit is used with the Ping-Pong bit. The ﬁrst

paired PTD always starts with Ping = 0. The Pong PTD payload can be sent

out only if the Ping PTD payload is sent out. You can also monitor

RAM_BUFFER _STATUS to see which PTD is currently active on the USB

line.

DirToken[1:0]

No

00 — set up

01 — OUT

10 — IN

11 — reserved

FunctionAddress[6:0]

No

This ﬁeld contains the USB address of the function containing the endpoint

that this PTD refers to.

B7[7:5] PollingRate

B7[4:0] StartingFrame

(interrupt only)

These two ﬁelds together select a start frame number (5 bits) and polls the

interrupt device at a rate speciﬁed by PollingRate (3 bits); see Section 11.6.

B7[7:0] StartingFrame

(ISO only)

No

The Host Controller compares this byte with the current frame number (can be

accessed from the HcFmNumber register). The PTD will be processed and

sent out only if the starting frame number equals to the current frame number.

11.5 Features of the control and bulk transfer (aperiodic transfer)

• A paired PTD is a special feature that provides high performance single endpoint bulk

transfer and handles set-up enumeration sequence within 1 ms. A paired PTD

consists of two PTDs serving the same endpoint of a device that are set active and

placed in the ATL RAM at the same time. A paired PTD is specially designed for high

performance of a single endpoint. They are identiﬁed by hardware by using the

‘Paired’ bit in the PTD.

• Possible to send up to a maximum of 18 USB bulk packets in 1 ms frame

(1.152 MB/s) by using the paired PTD feature.

• Provides the status of every transfer endpoints (PTD) by monitoring the

HcATLPTDDoneMap of the ISP1362. This register provides information on which

PTD transfers are complete.

• Sets the IRQ after the user-speciﬁed number of transfers is done.

• Skips any PTD that is wasting bandwidth by using HcATLPTDSkipMap.

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11.5.1 Sending a USB device request (Get Descriptor)

This section provides an example on how a USB transfer descriptor ‘Get Descriptor’

(commonly used in device enumeration) is used to illustrate the ISP1362 PTD application.

To perform this example, make sure the ISP1362 is in the operational state, and then

connect a USB device (for example, a USB mouse) to a port.

Remark: For details on the USB device request, refer to Chapter 9 of Ref. 2 “Universal

Serial Bus Speciﬁcation Rev. 2.0”.

11.5.1.1 Step 1

Set the HcATLBlkSize, HcATLPTDSkipMap and HcATLLastPTD registers to 0008h,

FFFEh and 0001h, respectively.

11.5.1.2 Step 2

A PTD is then constructed based on the information given in the following sample code.

This sample code places information into the correct bit location within the 8 bytes of the

PTD structure.

ActualBytes (10 bits) = 0x00

CompletionCode (4 bits) = 0x0F

Active (1 bit) = 1

Toggle (1 bit) = 0

MaxPacketSize (10 bits) = 8

EndpointNumber (4 bits) = 0

Speed (1 bit) = 0 (full-speed; use 1 for low-speed)

DirToken (2 bits) = 0 (setup token)

TotalBytes (10 bits) = 8

CompletedPTD

0xF800, 0x0008, 0x0008, 0x0000

11.5.1.3 Step 3

This array is then appended with an 8 bytes payload that speciﬁes the type of request the

Host Controller wants to send. For example, for Get Descriptor, the payload is 0680h,

0100h, 0000h, 0012h.

11.5.1.4 Step 4

The 16 bytes of data is now a complete PTD with an accompanying payload. This array is

then copied into the ATL buffer area. Table 12 shows the ATL buffer area.

Table 12. ATL buffer area

Offset

0

1

2

3

4

5

6

7

Data

F800h

0008h

0000h

0680h

0100h

0000h

0012h

11.5.1.5 Step 5

After copying data into the ATL buffer, the Host Controller must be notiﬁed that the ATL

buffer is now full and ready to be processed. The ATL_Active bit of the HcBufferStatus

register must be set to logic 1 to inform the Host Controller that the data in the ATL buffer

is now ready for processing. Once the ATL_Active bit of the HcBufferStatus register is set,

the USB packet is sent out. The active bit in the PTD is cleared once the PTD is sent.

Depending on the outcome of the USB transfer, the 4-bit completion code is updated.

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11.6 Features of the interrupt transfer

• An interrupt transaction is periodically sent out, according to the ‘interrupt polling rate’

as deﬁned in the PTD.

• An interrupt transaction causes an interrupt to the CPU only if the transaction is

ACK-ed or has error conditions, such as STALL or no respond. An ACK condition

occurs if data is received on the IN token or data is sent out on the OUT token.

• An interrupt is activated only once every ms as long as there is ACK for different

interrupt transactions in the interrupt transfer buffer.

• Each interrupt transfer (PTD) placed in the INTL buffer can automatically hold or send

data for more than 1 ms. This can be done using the parameters in the PTD.

Table 13. Interrupt polling

N bits [7:5]

StartingFrame N[4:0]

frame 0 to 31

Interrupt polling interval (2^N) in ms

0

1

2

3

4

5

6

7

1

2

4

8

16

32

64

128

11.7 Features of the Isochronous (ISO) transfer

• Supports multi-buffering by using the ISTL0 or ISTL1 toggling mechanism.

• The CPU can decide (in ms) how fast it can serve the ISP1362. This gives the CPU

the ﬂexibility to decide how much time it takes to read and ﬁll in the ISO data.

• The ISTL buffer can be updated on-the-ﬂy by using the direct addressing memory

architecture.

11.8 Overcurrent protection circuit

The ISP1362 has a built-in overcurrent protection circuitry. You can enable or disable this

feature by setting or resetting AnalogOCEnable (bit 10) of the HcHardwareConﬁguration

register. If this feature is disabled, it is assumed that there is an external overcurrent

protection circuitry.

11.8.1 Using internal overcurrent detection circuit

An application using the internal overcurrent detection circuit and internal 15 kΩ pull-down

resistors is shown in Figure 23, where DMn denotes either OTG_DM1 or H_DM2, while

DPn denotes either OTG_DP1 or H_DP2. In this example, the HCD must set both

AnalogOCEnable and ConnectPullDown_DS1 (bit 10 and bit 12 of the

HcHardwareConﬁguration register, respectively) to logic 1.

When H_OCn detects an overcurrent status on a downstream port, H_PSWn will output

HIGH to turn off the 5 V power supply to downstream port V_BUS. When there is no such

detection, H_PSWn will output LOW to turn on the 5 V power supply to downstream port

V_BUS

.

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In general applications, you can use a P-channel MOSFET as the power switch for V_BUS

.

Connect the 5 V power supply to the source pole of the P-channel MOSFET, V_BUSto the

drain pole, and H_PSWn to the gate pole. This voltage drop (∆V) across the drain and

source poles can be called the overcurrent trip voltage. For the internal overcurrent

detection circuit, a voltage comparator has been designed-in, with a nominal voltage

threshold of 75 mV. Therefore, when the overcurrent trip voltage (∆V) exceeds the voltage

threshold, H_PSWn will output a HIGH level to turn off the P-channel MOSFET. If the

P-channel MOSFET has R_DSonof 150 mΩ, the overcurrent threshold will be 500 mA. The

selection of a P-channel MOSFET with a different R_DSonwill result in a different

overcurrent threshold.

V

DD(5V)

PSU_5V

source

gate

C18

0.1 µF

R31

10 kΩ

P_channel

MOSFET

H_PSWn

H_OCn

drain

FB2

(1)

C41

C17

0.1 µF

1

2

3

4

5

6

DGND

V

BUS

DM

DP

GND

chassis

004aaa148

DGND

(1) 100 µF for the host port, or 4.7 µF for the OTG port.

Fig 23. Using internal overcurrent detection circuit

11.8.2 Using external overcurrent detection circuit

When V_CC(pin 56) is connected to the 3.3 V power supply instead of the 5 V power

supply, the internal overcurrent detection circuit cannot be used. An external overcurrent

detection circuit must be used instead. Nevertheless, regardless of the V_CCconnection, an

external overcurrent detection circuit can be used from time to time. To use an external

overcurrent detection circuit, set AnalogOCEnable, bit 10 of register

HcHardwareConﬁguration, to logic 0. By default, this bit is set to logic 0 after reset.

Therefore, the HCD does not need to clear this bit.

Figure 24 shows how to use an external overcurrent detection circuit.

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OC detection

PSU_5V

V

IN

OC

H_OCn

FB2

V

EN

H_PSWn

OUT

(1)

C41

C17

0.1 µF

1

2

3

4

5

6

DGND

V

BUS

DM

DP

GND

chassis

004aaa149

DGND

(1) 100 µF for the host port, or 4.7 µF for the OTG port.

Fig 24. Using external overcurrent detection circuit

11.8.3 Overcurrent detection circuit using internal charge pump in OTG mode

When port 1 is operating in OTG mode, you may choose to use the internal charge pump

to provide 5 V V_BUS, or supply V_BUSfrom an external source. In this mode, the overcurrent

condition is detected by a drop in V_BUSthat will be sensed by the built-in comparator. The

overcurrent condition causes a change in the A_VBUS_VLD bit of the OtgStatus register.

The software must clear the DRV_VBUS bit in the OtgControl register when it detects the

A_VBUS_VLD bit turning to logic 0.

H_OCn

FB2

V

BUS

(1)

C41

C17

0.1 µF

1

2

3

4

5

6

DGND

V

BUS

DM

DP

GND

chassis

n.c.

H_PSWn

004aaa150

DGND

(1) 100 µF for the host port, or 4.7 µF for the OTG port.

Fig 25. Using internal charge pump

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11.8.4 Overcurrent detection circuit using external 5 V power source in OTG mode

In OTG mode using external 5 V power source for V_BUS, the circuit and the operation are

the same as that for non-OTG mode (see Section 11.8.1 and Section 11.8.2).

11.9 ISP1362 Host Controller power management

In the ISP1362, the Host Controller and the Peripheral Controller are suspended and

woken up individually. The H_SUSPEND/H_WAKEUP and D_SUSPEND/D_WAKEUP

pins must be pulled-up by a large resistor (100 kΩ). In the suspend state, these pins are

HIGH. To wake up the Host Controller, these pins must be pulled LOW.

The ISP1362 can partially be suspended (only the Host Controller or only the Peripheral

Controller). In the partially suspended state, the clock circuit and PLL continue to work. To

save power, both the Host Controller and the Peripheral Controller must be set to suspend

mode.

The Host Controller can be suspended by writing 06C0h to the HcControl register.

The Host Controller can be set awake by one of the following ways:

• A LOW pulse on the H_SUSPEND/H_WAKEUP pin, minimum length of pulse is

25 ns.

• A LOW pulse on the chip select (CS) pin, minimum length of pulse is 25 ns.

• A resume signal by USB devices connected to the downstream port.

On waking up from the suspend state, the clock to the Host Controller will sustain for

5 ms. Within this 5 ms, the HCD must set the Host Controller to operational mode by

writing 0680h to the HcControl register. If the HcControl register remains in the suspend

state (06C0h) after waking up the Host Controller, the Host Controller will return to the

suspend state after 5 ms.

12. USB Peripheral Controller

The design of the Peripheral Controller in the ISP1362 is compatible with the NXP

ISP1181B USB full-speed interface device IC. The functionality of the Peripheral

Controller in the ISP1362 is similar to the ISP1181B in 16-bit bus mode. In addition, the

command and register sets are also the same.

In general, the Peripheral Controller in the ISP1362 provides 16 endpoints for the USB

device implementation. Each endpoint can be allocated RAM space in the on-chip ping

pong buffer RAM.

Remark: The ping pong buffer RAM for the Peripheral Controller is independent of the

buffer RAM for the Host Controller. When the buffer RAM is full, the Peripheral Controller

transfers the data in the buffer RAM to the USB bus. When the buffer RAM is empty, an

interrupt is generated to notify the microprocessor to feed in data. The transfer of data

between a microprocessor and the Peripheral Controller can be done in either

Programmed I/O (PIO) mode or in Direct Memory Access (DMA) mode.

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12.1 Peripheral Controller data transfer operation

The following sessions explain how the Peripheral Controller in the ISP1362 handles an

IN data transfer and an OUT data transfer. An IN data transfer means transfer from the

ISP1362 to an external USB host (through the upstream port), and an OUT transfer

means transfer from an external USB host to the ISP1362. In device mode, the ISP1362

acts as a USB device.

12.1.1 IN data transfer

1. The arrival of the IN token is detected by the Serial Interface Engine (SIE) by

decoding the Packet Identiﬁer (PID).

2. The SIE also checks the device number and the endpoint number to verify whether

they are okay.

3. If the endpoint is enabled, the SIE checks the contents of the DcEndpointStatus

register (ESR). If the endpoint is full, the contents of the buffer memory are sent

during the data phase else an NAK handshake is sent.

4. After the data phase, the SIE expects a handshake (ACK) from the host (except for

ISO endpoints).

5. On receiving the handshake (ACK), the SIE updates the contents of the

DcEndpointStatus and DcInterrupt registers, which in turn generates an interrupt to

the microprocessor. For ISO endpoints, the DcInterrupt register is updated as soon as

data is sent because there is no handshake phase.

6. On receiving an interrupt, the microprocessor reads the DcInterrupt register. It knows

which endpoint has generated the interrupt and reads the contents of the

corresponding ESR. If the buffer is empty, it ﬁlls up the buffer so that data can be sent

by the SIE at the next IN token phase.

12.1.2 OUT data transfer

1. The arrival of the OUT token is detected by the SIE by decoding the PID.

2. The SIE checks the device and endpoint numbers to verify whether they are okay.

3. If the endpoint is enabled, the SIE checks the contents of the ESR. If the endpoint is

empty, the data from USB is stored in the buffer memory during the data phase else a

NAK handshake is sent.

4. After the data phase, the SIE sends a handshake (ACK) to the host (except for ISO

endpoints).

5. The SIE updates the contents of the DcEndpointStatus register and the DcInterrupt

register, which in turn generates an interrupt to the microprocessor. For ISO

endpoints, the DcInterrupt register is updated as soon as data is received because

there is no handshake phase.

6. On receiving an interrupt, the microprocessor reads the DcInterrupt register. It knows

which endpoint has generated the interrupt and reads the content of the

corresponding ESR. If the buffer is full, it empties the buffer so that data can be

received by the SIE at the next OUT token phase.

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12.2 Device DMA transfer

12.2.1 DMA for an IN endpoint (internal Peripheral Controller to the external USB

host)

When the internal DMA handler is enabled and at least one buffer (ping or pong) is free,

the DREQ2 line is asserted. The external DMA controller then starts negotiating for

control of the bus. As soon as it has access, it asserts the DACK2 line and starts writing

data. The burst length is programmable. When the number of bytes equal to the burst

length has been written, the DREQ2 line is de-asserted. As a result, the DMA controller

de-asserts the DACK2 line and releases the bus. At that moment, the whole cycle restarts

for the next burst.

When the buffer is full, the DREQ2 line is de-asserted and the buffer is validated (which

means that it is sent to the host at the next IN token). When the DMA transfer is

terminated, the buffer is also validated (even if it is not full). A DMA transfer is terminated

when any of the following conditions is met:

• The DMA count is complete.

• DMAEN = 0.

Remark: If the OneDMA bit in the HcHardwareConﬁguration register is set to logic 1,

Peripheral Controller DMA controller handshake signals DREQ2 and DACK2 are routed to

DREQ1 and DACK1.

12.2.2 DMA for OUT endpoint (external USB host to internal Peripheral Controller)

When the internal DMA handler is enabled and at least one buffer is full, the DREQ2 line

is asserted. The external DMA controller then starts negotiating for control of the bus, and

as soon as it has access, it asserts the DACK2 line and starts reading data. The burst

length is programmable. When the number of bytes equal to the burst length has been

read, the DREQ2 line is de-asserted. As a result, the DMA controller de-asserts the

DACK2 line and releases the bus. At that moment, the whole cycle restarts for the next

burst. When all the data is read, the DREQ2 line is de-asserted and the buffer is cleared

(this means that it can be overwritten when a new packet arrives). A DMA transfer is

terminated when any of the following conditions are met:

• The DMA count is complete.

• DMAEN = 0.

Remark: If the OneDMA bit in the HcHardwareConﬁguration register is set to logic 1,

Peripheral Controller DMA controller handshake signals DREQ2 and DACK2 are routed to

DREQ1 and DACK1.

When the DMA transfer is terminated, the buffer is also cleared (even if data is not

completely read) and the DMA handler is automatically disabled. For the next DMA

transfer, the DMA controller as well as the DMA handler must be re-enabled.

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12.3 Endpoint description

12.3.1 Endpoints with programmable buffer memory size

Each USB device is logically composed of several independent endpoints. An endpoint

acts as a terminus of a communication ﬂow between the USB host and the USB device. At

design time, each endpoint is assigned a unique number (endpoint identiﬁer, see

Table 14). The combination of the device address (given by the host during enumeration),

the endpoint number, and the transfer direction allows each endpoint to be uniquely

referenced.

The Peripheral Controller has 16 endpoints: endpoint 0 (control IN and OUT) and 14

conﬁgurable endpoints, which can individually be deﬁned as interrupt, bulk or

isochronous: IN or OUT. Each enabled endpoint has an associated buffer memory, which

can be accessed either by using programmed I/O interface mode or by using DMA mode.

12.3.2 Endpoint access

Table 14 lists the endpoint access modes and programmability. All endpoints support I/O

mode access. Endpoints 1 to 14 also support DMA mode access. The Peripheral

Controller buffer memory DMA access is selected and enabled using bits EPIDX[3:0] and

DMAEN of the DcDMAConﬁguration register. A detailed description of the Peripheral

Controller DMA operation is given in Section 12.4.

Table 14. Endpoint access and programmability

Endpoint

identiﬁer

Buffer memory size Double

PIO mode

access

DMA mode

access

Endpoint type

(bytes)^[1]

buffering

0

64 (ﬁxed)

no

yes

no

control OUT^[2][3]

control IN^[2][3]

programmable

0

64 (ﬁxed)

no

yes

no

1 to 14

programmable

supported

[1] The total amount of the buffer memory storage allocated to enabled endpoints must not exceed 2462 bytes.

[2] IN: input for the USB host (Peripheral Controller transmits); OUT: output from the USB host (Peripheral Controller receives).

[3] The data ﬂow direction is determined by the EPDIR bit of the DcEndpointConﬁguration register.

12.3.3 Endpoint buffer memory size

The size of the buffer memory determines the maximum packet size that the hardware

can support for a given endpoint. Only enabled endpoints are allocated space in the

shared buffer memory storage, disabled endpoints have zero bytes. Table 15 lists the

programmable buffer memory sizes.

The following bits of the DcEndpointConﬁguration register (ECR) affect the buffer memory

allocation:

• Endpoint enable bit (FIFOEN)

• Size bits of an enabled endpoint (FFOSZ[3:0])

• Isochronous bit of an enabled endpoint (FFOISO)

Remark: A register change that affects the allocation of the shared buffer memory storage

among endpoints must not be made while valid data is present in any buffer memory of

the enabled endpoints. Such changes renders all buffer memory contents undeﬁned.

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Table 15. Programmable buffer memory size

FFOSZ[3:0]

Non-isochronous

8 bytes

Isochronous

16 bytes

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

16 bytes

32 bytes

64 bytes

reserved

32 bytes

48 bytes

64 bytes

96 bytes

128 bytes

160 bytes

192 bytes

256 bytes

320 bytes

384 bytes

512 bytes

640 bytes

768 bytes

896 bytes

1023 bytes

Each programmable buffer memory can independently be conﬁgured by using its ECR,

but the total physical size of all enabled endpoints (IN plus OUT) must not exceed

2462 bytes.

Table 16 shows an example of a conﬁguration ﬁtting in the maximum available space of

2462 bytes. The total number of logical bytes in the example is 1311. The physical storage

capacity used for double buffering is managed by the device hardware and is transparent

to the user.

Table 16. Memory conﬁguration example

Physical size (bytes) Logical size (bytes) Endpoint description

64

control IN (64 bytes ﬁxed)

64

control OUT (64 bytes ﬁxed)

double-buffered 1023 bytes isochronous endpoint

16 bytes interrupt OUT

2046

16

1023

16

16 bytes interrupt IN

128

64

double-buffered 64 bytes bulk OUT

double-buffered 64 bytes bulk IN

64

12.3.4 Endpoint initialization

In response to standard USB request Set Interface, ﬁrmware must program all the 16

ECRs of the Peripheral Controller in sequence (see Table 14), whether endpoints are

enabled or not. The hardware then automatically allocates the buffer memory storage

space.

If all endpoints have successfully been conﬁgured, ﬁrmware must return an empty packet

to the control IN endpoint to acknowledge success to the host. If there are errors in the

endpoint conﬁguration, ﬁrmware must stall the control IN endpoint.

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When reset by hardware or by the USB bus occurs, the Peripheral Controller disables all

endpoints and clears all ECRs, except the control endpoint that is ﬁxed and always

enabled.

An endpoint initialization can be done at any time. It is, however, valid only after

enumeration.

12.3.5 Endpoint I/O mode access

When an endpoint event occurs (a packet is transmitted or received), the associated

endpoint interrupt bits (EPn) of the DcInterrupt register (IR) are set by the SIE. The

ﬁrmware then responds to the interrupt and selects the endpoint for processing.

The endpoint interrupt bit is cleared by reading the DcEndpointStatus register (ESR). The

ESR also contains information on the status of the endpoint buffer.

For an OUT (= receive) endpoint, the packet length and packet data can be read from the

Peripheral Controller by using the Read Buffer command. When the whole packet has

been read, ﬁrmware sends a Clear Buffer command to enable the reception of new

packets.

For an IN (= transmit) endpoint, the packet length and data to be sent can be written to the

Peripheral Controller by using the Write Buffer command. When the whole packet has

been written to the buffer, ﬁrmware sends a Validate Buffer command to enable data

transmission to the host.

12.3.6 Special actions on control endpoints

Control endpoints require special ﬁrmware actions. The arrival of a set-up packet ﬂushes

the IN buffer and disables the Validate Buffer and Clear Buffer commands for the control

IN and OUT endpoints. The microprocessor must re-enable these commands by sending

an acknowledge set-up command to both the control endpoints.

This ensures that the last set-up packet stays in the buffer and that no packets can be sent

back to the host, until the microprocessor has explicitly acknowledged that it has received

the set-up packet.

12.4 Peripheral Controller DMA transfer

Direct Memory Access (DMA) is a method to transfer data from one location to another in

a computer system, without the intervention of the CPU. Many different implementations

of DMA exist. The Peripheral Controller supports 8237 compatible mode.

8237 compatible mode: Based on the DMA subsystem of the IBM personal computers

(PC, AT and all its successors and clones). This architecture uses the Intel 8237 DMA

controller and has separate address spaces for memory and I/O.

The following features are supported:

• Single-cycle or burst transfers (up to 16 bytes per cycle)

• Programmable transfer direction (read or write)

• Multiple End-Of-Transfer (EOT) sources: internal conditions, short or empty packet

• Programmable signal levels on pins DREQ2 and DACK2

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12.4.1 Selecting an endpoint for the DMA transfer

The target endpoint for DMA access is selected using bits EPDIX[3:0] of the

DcDMAConﬁguration register, as shown in Table 17. The transfer direction (read or write)

is automatically set by the EPDIR bit in the associated ECR, to match the selected

endpoint type (OUT endpoint: read; IN endpoint: write).

Automatically asserting input DACK2 selects the endpoint speciﬁed in the

DcDMAConﬁguration register, regardless of the current endpoint used for I/O mode

access.

Table 17. Endpoint selection for the DMA transfer

Endpoint

identiﬁer

EPIDX[3:0]

Transfer direction

EPDIR = 0

OUT: read

EPDIR = 1

IN: write

1

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

2

3

4

5

6

7

8

9

10

11

12

13

14

12.4.2 8237 compatible mode

This mode is selected by clearing the DAKOLY bit of the DcHardwareConﬁguration

register (see Table 115). The pin functions for this mode are shown in Table 18.

Table 18. 8237 compatible mode: pin functions

Symbol Description

I/O

Function

DREQ2 DMA request of Peripheral

Controller

O

Peripheral Controller requests a DMA

transfer

DACK2 DMA acknowledge of Peripheral

Controller

I

DMA controller conﬁrms the transfer

EOT

RD

end of transfer

read strobe

I

DMA controller terminates the transfer

instructs the Peripheral Controller to put

data on the bus

WR

write strobe

I

instructs the Peripheral Controller to get

data from the bus

The DMA subsystem of an IBM-compatible PC is based on the Intel 8237 DMA controller.

It operates as a ‘ﬂy-by’ DMA controller. Data is not stored in the DMA controller, but it is

transferred between an I/O port and a memory address. A typical example of the

Peripheral Controller in 8237 compatible DMA mode is given in Figure 26.

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The 8237 has two control signals for each DMA channel: DREQ (DMA Request) and

DACK (DMA Acknowledge). General control signals are HRQ (Hold Request) and HLDA

(Hold Acknowledge). The bus operation is controlled by MEMR (Memory Read), MEMW

(Memory Write), IOR (I/O Read) and IOW (I/O Write).

MEMR

RAM

D[15:0]

MEMW

DMA

CONTROLLER

8237

CPU

ISP1362

DREQ2

DACK2

DREQ

HRQ

HLDA

DACK

HLDA

RD

IOR

WR

IOW

004aaa047

Fig 26. Peripheral Controller in 8327 compatible DMA mode

The following example shows the steps that occur in a typical DMA transfer:

1. The Peripheral Controller receives a data packet in one of its endpoint buffer memory.

The packet must be transferred to memory address 1234h.

2. The Peripheral Controller asserts the DREQ2 signal requesting the 8237 for a DMA

transfer.

3. The 8237 requests the CPU to release the bus, by asserting the HRQ signal.

4. After completing the current instruction cycle, the CPU places bus control signals

(MEMR, MEMW, IOR and IOW) and address lines in 3-state and asserts HLDA to

inform the 8237 that it has control of the bus.

5. The 8237 now sets its address lines to 1234h and activates the MEMW and IOR

control signals.

6. The 8237 asserts DACK to inform the Peripheral Controller that it will start a DMA

transfer.

7. The Peripheral Controller now places the word to be transferred on the data bus lines

because its RD signal was asserted by the 8237.

8. The 8237 waits one DMA clock period and then de-asserts MEMW and IOR. This

latches and stores the word at the desired memory location. It also informs the

Peripheral Controller that the data on the bus lines has been transferred.

9. The Peripheral Controller de-asserts the DREQ2 signal to indicate to the 8237 that

DMA is no longer needed. In single cycle mode, this is done after each byte or word;

in burst mode, following the last transferred byte or word of the DMA cycle.

10. The 8237 de-asserts the DACK output, indicating that the Peripheral Controller must

stop placing data on the bus.

11. The 8237 places bus control signals (MEMR, MEMW, IOR and IOW) and address

lines in 3-state and de-asserts the HRQ signal, informing the CPU that it has released

the bus.

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12. The CPU acknowledges control of the bus by de-asserting HLDA. After activating the

bus control lines (MEMR, MEMW, IOR and IOW) and address lines, the CPU

resumes the execution of instructions.

For a typical bulk transfer, the preceding process is repeated 32 times, once for each

word. After each word, the DcAddress register in the DMA controller is incremented by

two and the byte counter is decremented by two. When using the 16-bit DMA, the number

of transfers is 32, and address incrementing and byte counter decrementing is done by

two for each word.

12.4.3 End-Of-Transfer conditions

12.4.3.1 Bulk endpoints

A DMA transfer to or from a bulk endpoint can be terminated by any of the following

conditions (bit names refer to the DcDMAConﬁguration register, see Table 119 and

Table 120):

• The DMA transfer completes as programmed in the DcDMACounter register

(CNTREN = 1).

• A short packet is received on an enabled OUT endpoint (SHORTP = 1).

• DMA operation is disabled by clearing the DMAEN bit.

DcDMACounter register — An EOT from the DcDMACounter register is enabled by

setting bit CNTREN of the DcDMAConﬁguration register. The Peripheral Controller has a

16-bit DcDMACounter register, which speciﬁes the number of bytes to be transferred.

When DMA is enabled (DMAEN = 1), the internal DMA counter is loaded with the value

from the DcDMACounter register. When the internal counter completes the transfer as

programmed in the DMA counter, an EOT condition is generated and the DMA operation

stops.

Short packet — Normally, the transfer byte count must be set using a control endpoint

before any DMA transfer takes place. When a short packet has been enabled as EOT

indicator (SHORTP = 1), the transfer size is determined by the presence of a short packet

in data. This mechanism permits the use of a fully autonomous data transfer protocol.

When reading from an OUT endpoint, reception of a short packet at an OUT token will

stop the DMA operation after transferring the data bytes of this packet.

Table 19. Summary of EOT conditions for a bulk endpoint

EOT condition

OUT endpoint

IN endpoint

DcDMACounter register

transfer completes as

programmed in the

transfer completes as

programmed in the

DcDMACounter register

Short packet

short packet is received and

transferred

counter reaches zero in the

middle of the buffer

DMAEN bit of the

DMAEN = 0^[1]

DcDMAConﬁguration register

[1] The DMA transfer stops. No interrupt, however, is generated.

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12.4.3.2 Isochronous endpoints

A DMA transfer to or from an isochronous endpoint can be terminated by any of the

following conditions (bit names refer to the DcDMAConﬁguration register, see Table 119

and Table 120):

• The DMA transfer completes as programmed in the DcDMACounter register

(CNTREN = 1).

• An End-Of-Packet (EOP) signal is detected.

• DMA operation is disabled by clearing bit DMAEN.

Table 20. Recommended EOT usage for isochronous endpoints

EOT condition

OUT endpoint

IN endpoint

DcDMACounter register zero

do not use

preferred

12.5 ISP1362 Peripheral Controller suspend and resume

12.5.1 Suspend conditions

The Peripheral Controller in the ISP1362 detects a USB suspend condition in either of the

following cases:

• Constant idle state is present on the USB bus for 3 ms.

• V_BUSis lost.

Bus-powered devices that are suspended must not consume more than 500 µA of current.

This is achieved by shutting down the power to system components or supplying them

with a reduced voltage.

The steps leading the Peripheral Controller to the suspend state are as follows:

1. In the event of no SOF for 3 ms, the Peripheral Controller in the ISP1362 sets

bit SUSPND of the DcInterrupt register. This will generate an interrupt if bit IESUSP of

the DcInterruptEnable register is set.

2. When the ﬁrmware detects a suspend condition (through IESUSP), it must prepare all

system components for the suspend state:

a. All the signals connected to the Peripheral Controller in the ISP1362 must enter

appropriate states to meet the power consumption requirements of the suspend

state.

b. All the input pins of the Peripheral Controller in the ISP1362 must have a CMOS

logic 0 or logic 1 level.

3. In the interrupt service routine, the ﬁrmware must check the current status of the USB

bus. When bit BUSTATUS of the DcInterrupt register is logic 0, the USB bus has left

suspend mode and the process must be aborted. Otherwise, the next step can be

executed.

4. To meet the suspend current requirements for a bus-powered device, internal clocks

must be switched off by clearing bit CLKRUN of the DcHardwareConﬁguration

register.

5. When ﬁrmware has set and cleared the GOSUSP bit of the DcMode register, the

Peripheral Controller in the ISP1362 enters the suspend state. It sets the

D_SUSPEND/D_WAKEUP pin to HIGH and switches off internal clocks after 2 ms.

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The Peripheral Controller in the ISP1362 will remain in the suspend state for at least 5 ms,

before responding to external wake-up events, such as global resume, bus trafﬁc, CS

active or LOW pulse on the D_SUSPEND/D_WAKEUP pin.

Figure 27 shows a typical timing diagram for the Peripheral Controller suspend and

resume operations.

A

D

> 5 ms

10 ms

idle state

K-state

USB bus

INT2

> 3 ms

suspend

interrupt

resume

interrupt

B

GOSUSP (bit)

D_SUSPEND/D_WAKEUP

0.5 ms to 3.5 ms

1.8 ms to

2.2 ms

CS

C

004aaa483

Fig 27. Suspend and resume timing

In Figure 27:

A — indicates the point at which the USB bus goes to the idle state.

B — after detecting the suspend interrupt, set and clear the GOSUSP bit in the Mode

register.

C — indicates resume condition, which can be a resume signal from the host, a LOW

pulse on the D_SUSPEND/D_WAKEUP pin, or a LOW pulse on the CS pin.

D — indicates remote wake-up. The ISP1362 will drive a K-state on the USB bus for

10 ms after the D_SUSPEND/D_WAKEUP pin goes LOW or the CS pin goes LOW.

12.5.2 Resume conditions

Wake-up from the suspend state is initiated either by the USB host or by the application:

• USB host: drives a K-state on the USB bus (global resume).

• Application: remote wake-up using a LOW pulse on pin D_SUSPEND/D_WAKEUP or

a LOW pulse on pin CS (if enabled using bit WKUPCS of the

DcHardwareConﬁguration register).

The steps of a wake-up sequence are as follows:

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1. The internal oscillator and the PLL multiplier are re-enabled. When stabilized, clock

signals are routed to all internal circuits of the Peripheral Controller in the ISP1362.

2. The D_SUSPEND/D_WAKEUP pin goes LOW, and the RESUME bit of the

DcInterrupt register is set. This will generate an interrupt if bit IERESUME of the

DcInterruptEnable register is set.

3. After 5 ms of starting the wake-up sequence, the Peripheral Controller in the ISP1362

resumes its normal functionality (this can be set to 100 µs by setting pin TEST0 to

HIGH).

4. In a remote wake-up, the Peripheral Controller in the ISP1362 drives a K-state on the

USB bus for 10 ms.

5. The application restores itself and other system components to normal operating

mode.

6. After wake-up, internal registers of the Peripheral Controller in the ISP1362 are read

and write-protected to prevent corruption by inadvertent writing during power-up of

external components. The ﬁrmware must send an Unlock Device command to the

Peripheral Controller in the ISP1362 to restore its full functionality.

13. OTG registers

Table 21. OTG Control registers overview

Command (Hex)

Register

Width

References

Functionality

Read

62

Write

E2

OtgControl

16

32

Section 13.1 on page 60 OTG operation registers

Section 13.2 on page 62

67

N/A

E8

OtgStatus

68

OtgInterrupt

OtgInterruptEnable

OtgTimer

Section 13.3 on page 63

69

E9

Section 13.4 on page 65

6A

6C

EA

Section 13.5 on page 66

EC

OtgAltTimer

Section 13.6 on page 67

13.1 OtgControl register (R/W: 62h/E2h)

Code (Hex): 62 — read

Code (Hex): E2 — write

Table 22. OtgControl register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

reserved

OTG_SE0_

EN

A_SRP_

DET_EN

A_SEL_

SRP

SEL_HC_

DC

Reset

Access

Bit

-

0

R/W

3

0

R/W

2

0

R/W

1

R/W

0

-

5

7

6

4

Symbol

LOC_

PULLDN_

DM

LOC_

A_RDIS_

LOC_

CONN

SEL_CP_ DISCHRG_

CHRG_

VBUS

DRV_

VBUS

PULLDN_ LCON_EN

DP

EXT

VBUS

Reset

1

0

Access

R/W

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Table 23. OtgControl register: bit description

Bit

Symbol

Description

15 to 12

11

-

reserved

OTG_SE0_

EN

This bit is used by the Host Controller to send SE0 on remote connect.

0 — no SE0 sent on remote connect detection

1 — SE0 (bus reset) sent on remote connect detection

Remark: This bit is normally set when the B-device goes into the

b_wait_acon state (recommended sequence: LOC_CONN = 0 →

DELAY → 50 µs → OTG_SE0_EN = 1 → SEL_HC_DC = 0) and is

cleared when it comes out of the b_wait_acon state.

10

9

A_SRP_DET This bit is for the A-device only. If set, the A_SRP_DET bit in the

_EN

OtgInterrupt register will be set on detecting an SRP event.

0 — disable

1 — enable

A_SEL_SRP This bit is for the A-device to select a method to detect the SRP event

(V_BUSpulsing or data line pulsing).

0 — A-device responds to the V_BUSpulsing

1 — A-device responds to the data line pulsing

8

SEL_HC_DC This bit is used to select either the Peripheral Controller or the Host

Controller that interfaces with the transceiver.

0 — Host Controller SIE is connected to the OTG transceiver

1 — Peripheral Controller SIE is connected to the OTG transceiver

7

6

5

LOC_

PULLDN_DM

0 — disconnects the on-chip pull-down resistor on DM of the OTG port

1 — connects the on-chip pull-down resistor on DM of the OTG port

0 — disconnects the on-chip pull-down resistor on DP of the OTG port

1 — connects the on-chip pull-down resistor on DP of the OTG port

LOC_

PULLDN_DP

A_RDIS_

LCON_EN

This bit is for the A-device only. If set, the chip will automatically enable

its pull-up resistor on DP on detecting a remote disconnect event. If

cleared, the DP pull-up is controlled by the LOC_CONN bit.

0 — disable

1 — enable

Remark: This bit is normally set when the A-device goes into the

a_suspend state and is cleared when it comes out of the a_suspend

state. The LOC_CONN bit must be set before clearing this bit.

4

3

LOC_CONN 0 — disconnect the on-chip pull-up resistor on DP of the OTG port

1 — connect the on-chip pull-up resistor on DP of the OTG port

SEL_CP_

EXT

This bit is for the A-device only. This bit is used to choose the power

source to drive V_BUS

.

0 — use on-chip charge pump to drive V_BUS

1 — use external power source (5 V) to drive V_BUS

Remark: When using the external power source, the H_PSW1 pin

serves as the power switch that is controlled by the DRV_VBUS bit of

this register.

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Table 23. OtgControl register: bit description …continued

Bit

Symbol

Description

2

DISCHRG_

VBUS

This bit is for the B-device only. If set, it will enable a pull-down resistor

on V_BUS, which will help to speed up discharging of V_BUSbelow session

end threshold voltage.

0 — disable

1 — enable

1

0

CHRG_VBUS This bit is for the B-device only. If set, it will charge V_BUSthrough a

resistor.

0 — disable charging V_BUSof the OTG port

1 — enable charging V_BUSof the OTG port

DRV_VBUS

This bit is used to enable the on-chip charge pump or external power

source to drive V_BUS. For the B-device, it shall not enable this bit at any

time.

0 — disable driving V_BUSof the OTG port

1 — enable driving V_BUSof the OTG port

13.2 OtgStatus register (R: 67h)

Code (Hex): 67 — read only

Table 24. OtgStatus register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

reserved

SE0_2MS

reserved

-

0

R

1

-

0

7

6

5

4

3

2

Symbol

reserved

RMT_

CONN

B_SESS_

VLD

A_SESS_

VLD

B_SESS_

END

A_VBUS_

VLD

ID_REG

Reset

-

0

1

0

1

Access

R

Table 25. OtgStatus register: bit description

Bit

Symbol

-

Description

15 to 10

9

reserved

SE0_2MS

0 — bus is in SE0 for less than 2 ms

1 — bus is in SE0 for more than 2 ms

reserved

8 to 6

5

-

RMT_CONN

0 — remote pull-up resistor disconnected

1 — remote pull-up resistor connected

Remark: When the local pull-up resistor on the DP line is disabled,

a 50 µs delay is applied before the RMT_CONN detection is

enabled.

4

B_SESS_VLD For the B-device (ID_REG = 1), this bit is a B-device session valid

indicator (B_SESS_VLD).

0 — V_BUSis lower than VB_SESS_VLD

1 — V_BUSis higher than VB_SESS_VLD

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Table 25. OtgStatus register: bit description …continued

Bit

Symbol

Description

3

A_SESS_VLD For the A-device (ID_REG = 0), this bit is an A-device session valid

indicator (A_SESS_VLD).

0 — V_BUSis lower than VA_SESS_VLD

1 — V_BUSis higher than VA_SESS_VLD

2

1

0

B_SESS_END For the B-device (ID_REG = 1), this bit is a B-device session end

indicator (B_SESS_END).

0 — V_BUSis higher than VB_SESS_END

1 — V_BUSis lower than VB_SESS_END

A_VBUS_VLD For the A-device (ID_REG = 0), this bit is an A-device V_BUSvalid

indicator (A_VBUS_VLD).

0 — V_BUSis lower than VA_VBUS_VLD

1 — V_BUSis higher than VA_VBUS_VLD

ID_REG

This bit reﬂects the logic level of the ID pin.

0 — ID pin is LOW (mini-A plug is inserted in the device’s mini-AB

receptacle)

1 — ID pin is HIGH (no plug or mini-B plug is inserted in the

device’s mini-AB receptacle)

13.3 OtgInterrupt register (R/W: 68h/E8h)

Code (Hex): 68 — read

Code (Hex): E8 — write

Table 26. OtgInterrupt register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

reserved

OTG_TMR_

TIMEOUT

B_SE0_

SRP

A_SRP_

DET

Reset

Access

Bit

-

0

R/W

2

0

R/W

1

0

R/W

0

7

6

5

4

3

Symbol

OTG_

RESUME

OTG_

SUSPND

RMT_

CONN_C

B_SESS_

VLD_C

A_SESS_

VLD_C

B_SESS_

END_C

A_VBUS_ ID_REG_C

VLD_C

Reset

0

Access

R/W

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Table 27. OtgInterrupt register: bit description

Bit

Symbol

Description

15 to 11

10

-

reserved

OTG_TMR_ This bit is set whenever the OTG timer attains time-out. Writing logic 1

TIMEOUT

clears this bit. Writing logic 0 has no effect.

0 — no event

1 — OTG timer time-out

9

8

B_SE0_SRP This bit is set whenever the device detects more than 2 ms of SE0.

Writing logic 1 clears this bit. Writing logic 0 has no effect.

0 — no event

1 — bus has been in SE0 for more than 2 ms

A_SRP_DET This bit is used to detect the Session Request Event (SRP) from the

remote device. The SRP event can be either V_BUSpulsing or data line

pulsing. Bit 9 (A_SEL_SRP) of the OtgControl register determines

which SRP is selected. Writing logic 1 clears this bit. Writing logic 0

has no effect.

0 — no event

1 — SRP is detected

7

6

OTG_

RESUME

This bit is used to detect a J to K state change when the device is in

the ‘suspend’ state. Writing logic 1 clears this bit. Writing logic 0 has

no effect.

0 — no event

1 — a resume signal (J → K) is detected when the bus is in the

‘suspend’ state

OTG_

SUSPND

This bit is set whenever the OTG port goes into the suspend state (bus

idle for > 3 ms). Write logic 1 to clear this bit. Writing logic 0 has no

effect.

0 — no event

1 — suspend (bus idle for > 3 ms)

5

4

3

RMT_

CONN_C

This bit is set whenever the RMT_CONN bit of the OtgStatus register

changes. Write logic 1 to clear this bit. Writing logic 0 has no effect.

0 — no event

1 — RMT_CONN bit has changed

B_SESS_

VLD_C

This bit is set whenever the B_SESS_VLD bit of the OtgStatus register

changes. Write logic 1 to clear this bit. Writing logic 0 has no effect.

0 — no event

1 — bit B_SESS_VLD has changed

A_SESS_

VLD_C

This bit is set whenever the A_SESS_VLD bit of the OtgStatus register

changes. Write logic 1 to clear this bit. Writing logic 0 has no effect.

0 — no event

1 — bit A_SESS_VLD has changed

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Table 27. OtgInterrupt register: bit description …continued

Bit

Symbol

Description

2

B_SESS_

END_C

This bit is set whenever the B_SESS_END bit of the OtgStatus

register changes. Write logic 1 to clear this bit. Writing logic 0 has no

effect.

0 — no event

1 — bit B_SESS_END has changed

1

0

A_VBUS_

VLD_C

This bit is set whenever the A_VBUS_VLD bit of the OtgStatus register

changes. Write logic 1 to clear this bit. Writing logic 0 has no effect.

0 — no event

1 — bit A_VBUS_VLD has changed

ID_REG_C

This bit is set whenever the ID_REG bit of the OtgStatus register

changes. This is an indication that the mini-A plug is inserted or

removed (that is, the ID pin is shorted to ground or pulled HIGH). Write

logic 1 to clear this bit. Writing logic 0 has no effect.

0 — no event

1 — ID_REG bit has changed

13.4 OtgInterruptEnable register (R/W: 69h/E9h)

Code (Hex): 69 — read

Code (Hex): E9 — write

Table 28. OtgInterruptEnable register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

reserved

OTG_

TMR_IE

B_SE0_

SRP_IE

A_SRP_

DET_IE

Reset

Access

Bit

-

0

R/W

2

0

R/W

1

0

R/W

0

-

7

-

6

5

4

3

Symbol

OTG_

RMT_

CONN_IE

B_SESS_

VLD_IE

A_SESS_

VLD_IE

B_SESS_

END_IE

A_VBUS_

VLD_IE

ID_REG_

IE

RESUME_ SUSPND_

IE

Reset

0

Access

R/W

Table 29. OtgInterruptEnable register: bit description

Bit

Symbol

Description

15 to 11 -

reserved

10

9

OTG_TMR_IE

Logic 1 enables interrupt when the OTG timer attains time-out.

Logic 0 disables interrupt.

B_SE0_SRP_IE

A_SRP_DET_IE

Logic 1 enables interrupt on detecting the B_SE0_SRP status

change. Logic 0 disables interrupt.

8

Logic 1 enables interrupt on detecting the SRP event. Logic 0

disables interrupt.

7

OTG_RESUME_IE Logic 1 enables interrupt on detecting bus resume (J to K only)

event. Logic 0 disables interrupt.

ISP1362_5

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Single-chip USB OTG Controller

Table 29. OtgInterruptEnable register: bit description …continued

Bit

Symbol

Description

6

OTG_SUSPND_IE Logic 1 enables interrupt on detecting the bus ‘suspend’ status

change. Logic 0 disables interrupt.

5

4

3

2

1

0

RMT_CONN_IE

B_SESS_VLD_IE

A_SESS_VLD_IE

Logic 1 enables interrupt on detecting the RMT_CONN status

change. Logic 0 disables interrupt.

Logic 1 enables interrupt on detecting B_SESS_VLD status

change. Logic 0 disables interrupt.

Logic 1 enables interrupt on detecting A_SESS_VLD status

change. Logic 0 disables interrupt.

B_SESS_END_IE Logic 1 enables interrupt on detecting B_SESS_END status

change. Logic 0 disables interrupt.

A_VBUS_VLD_IE

Logic 1 enables interrupt on detecting A_VBUS_VLD status

change. Logic 0 disables interrupt.

ID_REG_IE

Logic 1 enables interrupt on detecting the ID_REG status change.

Logic 0 disables interrupt.

13.5 OtgTimer register (R/W: 6Ah/EAh)

Code (Hex): 6A — read

Code (Hex): EA — write

Table 30. OtgTimer register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

START_

TMR

reserved

Reset

Access

Bit

0

-

R/W

23

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

TMR_INIT_VALUE[23:16]

0

R/W

9

0

R/W

8

R/W

15

R/W

14

R/W

13

R/W

12

R/W

11

R/W

10

Symbol

Reset

Access

Bit

TMR_INIT_VALUE[15:8]

0

R/W

7

0

R/W

6

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

Symbol

Reset

Access

TMR_INIT_VALUE[7:0]

0

R/W

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Single-chip USB OTG Controller

Table 31. OtgTimer register: bit description

Bit

Symbol

Description

31

START_TMR This is the start or stop bit of the OTG timer. Writing logic 1 will cause

the OTG timer to load TMR_INIT_VALUE into the counter and start to

count. Writing logic 0 will stop the timer. This bit is automatically

cleared when the OTG timer is timed out.

0 — stop the timer

1 — start the timer

30 to 24

23 to 0

-

reserved

TMR_INIT_

These bits deﬁne the initial value used by the OTG timer. The timer

VALUE[23:0] interval is 0.01 ms. Maximum timer allowed is 167.772 s.

13.6 OtgAltTimer register (R/W: 6Ch/ECh)

Code (Hex): 6C — read

Code (Hex): EC — write

Table 32. OtgAltTimer register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

START_

TMR

reserved

Reset

Access

Bit

0

-

R/W

23

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

CURRENT_TIME[23:16]

0

R

0

R

0

R

0

R

0

R

0

R

0

R

9

0

R

8

15

14

13

12

11

10

Symbol

Reset

Access

Bit

CURRENT_TIME[15:8]

0

R

7

0

R

6

0

R

5

0

R

4

0

R

3

0

R

2

0

R

1

0

R

0

Symbol

Reset

Access

CURRENT_TIME[7:0]

0

R

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Table 33. OtgAltTimer register: bit description

Bit

Symbol

Description

31

START_

TMR

This is the start or stop bit of the OTG timer 2. Writing logic 1 will

cause OTG timer 2 to start counting from 0. When the counter reaches

FF FFFFh, this bit is auto-cleared (the counter is stopped). Writing

logic 0 will stop the counting.

If any bit of the OTGInterrupt register is set and the corresponding bit

of the OtgInterruptEnable register is also set, this bit will be

auto-cleared and the current value of the counter will be written to the

CURRENT_TIME ﬁeld.

0 — stop the timer

1 — start the timer

reserved

30 to 24

23 to 0

-

CURRENT_ When read, these bits give the current value of the timer. The actual

TIME time is CURRENT_TIME × 0.01 ms.

14. Host Controller registers

The Host Controller contains a set of on-chip control registers. These registers can be

read or written by the Host Controller Driver (HCD). The operational registers are made

compatible to Open Host Controller Interface (OHCI) operational registers. This enables

the OHCI HCD to be easily ported to the ISP1362.

Reserved bits may be deﬁned in future releases of this speciﬁcation. To ensure

interoperability, the HCD that does not use a reserved ﬁeld must not assume that the

reserved ﬁeld contains logic 0. Furthermore, the HCD must always preserve the values of

the reserved ﬁeld. When a R/W register is modiﬁed, the HCD must ﬁrst read the register,

modify the desired bits and then write the register with the reserved bits still containing the

read value. Alternatively, the HCD can maintain an in-memory copy of previously written

values that can be modiﬁed and then written to the Host Controller register. When there is

a write to set or clear the register, bits written to reserved ﬁelds must be logic 0.

As shown in Table 34, the offset locations (commands to read registers) of these

operational registers (32-bit registers) are similar to those deﬁned in the OHCI

speciﬁcation. The addresses, however, are equal to offset divided by 4.

Table 34. Host Controller registers overview

Command (Hex)

Register

Width Reference

Functionality

Read

00

Write

N/A

81

HcRevision

32

Section 14.1.1 on page 70 HC control and status

registers

01

HcControl

Section 14.1.2 on page 70

02

82

HcCommandStatus

HcInterruptStatus

HcInterruptEnable

HcInterruptDisable

HcFmInterval

Section 14.1.3 on page 72

03

83

Section 14.1.4 on page 73

04

84

Section 14.1.5 on page 74

05

85

Section 14.1.6 on page 75

0D

0E

8D

8E

8F

Section 14.2.1 on page 76 HC frame counter

registers

HcFmRemaining

HcFmNumber

Section 14.2.2 on page 77

0F

Section 14.2.3 on page 78

Section 14.2.4 on page 79

11

91

HcLSThreshold

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Single-chip USB OTG Controller

Table 34. Host Controller registers overview …continued

Command (Hex)

Register

Width Reference

Functionality

Read

12

13

14

15

16

20

21

22

24

25

27

28

N/A

2C

32

45

30

40

42

47

33

43

53

17

18

19

1A

34

44

54

1B

1C

1D

1E

51

52

Write

92

HcRhDescriptorA

HcRhDescriptorB

HcRhStatus

32

16

32

16

32

16

32

16

Section 14.3.1 on page 80 HC root hub registers

Section 14.3.2 on page 82

93

94

Section 14.3.3 on page 83

95

HcRhPortStatus[1]

HcRhPortStatus[2]

HcHardwareConﬁguration

HcDMAConﬁguration

HcTransferCounter

HcµPInterrupt

Section 14.3.4 on page 84

96

Section 14.3.4 on page 84

A0

A1

A2

A4

A5

N/A

A8

A9

AC

B2

C5

B0

C0

C2

C7

B3

C3

D3

N/A

98

Section 14.4.1 on page 88 HC DMA and interrupt

control registers

Section 14.4.2 on page 90

Section 14.4.3 on page 91

Section 14.4.4 on page 91

HcµPInterruptEnable

HcChipID

Section 14.4.5 on page 93

Section 14.5.1 on page 94 HC miscellaneous

registers

HcScratch

Section 14.5.2 on page 94

HcSoftwareReset

HcBufferStatus

Section 14.5.3 on page 95

Section 14.6.1 on page 95 HC buffer RAM control

registers

HcDirectAddressLength

HcDirectAddressData

HcISTLBufferSize

HcISTL0BufferPort

HcISTL1BufferPort

HcISTLToggleRate

HcINTLBufferSize

HcINTLBufferPort

HcINTLBlkSize

Section 14.6.2 on page 96

Section 14.6.3 on page 97

Section 14.7.1 on page 97 ISO transfer registers

Section 14.7.2 on page 97

Section 14.7.3 on page 98

Section 14.7.4 on page 98

Section 14.8.1 on page 99 Interrupt transfer

registers

Section 14.8.2 on page 99

Section 14.8.3 on page 100

HcINTLPTDDoneMap

HcINTLPTDSkipMap

HcINTLLastPTD

Section 14.8.4 on page 100

Section 14.8.5 on page 100

99

Section 14.8.6 on page 101

N/A

B4

C4

D4

N/A

9C

9D

N/A

D1

D2

HcINTLCurrentActivePTD

HcATLBufferSize

Section 14.8.7 on page 101

Section 14.9.1 on page 102 Aperiodic transfer

registers

HcATLBufferPort

Section 14.9.2 on page 102

HcATLBlkSize

Section 14.9.3 on page 102

Section 14.9.4 on page 103

Section 14.9.5 on page 103

Section 14.9.6 on page 104

Section 14.9.7 on page 104

Section 14.9.8 on page 105

Section 14.9.9 on page 105

HcATLPTDDoneMap

HcATLPTDSkipMap

HcATLLastPTD

HcATLCurrentActivePTD

HcATLPTDDoneThresholdCount

HcATLPTDDoneThresholdTimeOut 16

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Single-chip USB OTG Controller

14.1 HC control and status registers

14.1.1 HcRevision register (R: 00h)

The bit allocation of the HcRevision register is given in Table 35.

Code (Hex): 00 — read only

Table 35. HcRevision register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved

REV[7:0]

-

23

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

-

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

-

7

6

5

4

3

2

1

0

Symbol

Reset

Access

0

1

0

1

R

Table 36. HcRevision register: bit description

Bit

Symbol

Description

31 to 8

7 to 0

-

Reserved

REV[7:0] Revision: This read-only ﬁeld contains the Binary-Coded Decimal (BCD)

representation of the version of the HCI speciﬁcation that is implemented by

this Host Controller.

14.1.2 HcControl register (R/W: 01h/81h)

The HcControl register deﬁnes operating modes for the Host Controller. The RWE bit is

modiﬁed only by the HCD. Table 37 shows the bit allocation of the register.

Code (Hex): 01 — read

Code (Hex): 81 — write

Table 37. HcControl register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

reserved

-

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Bit

23

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

reserved

-

9

-

15

14

13

12

11

10

RWE

0

8

Symbol

Reset

Access

Bit

reserved

RWC

0

reserved

-

R/W

2

R/W

1

7

6

5

4

3

0

Symbol

Reset

Access

HCFS[1:0]

reserved

0

-

R/W

Table 38. HcControl register: bit description

Bit

Symbol

-

Description

31 to 11

10

reserved

RWE

RemoteWakeupEnable: This bit is used by the HCD to enable or

disable the remote wake-up feature on detecting upstream resume

signaling. When this bit and the ResumeDetected (RD) bit in

HcInterruptStatus are set, a remote wake-up is signaled to the host

system. Setting this bit has no impact on the generation of hardware

interrupt.

9

RWC

RemoteWakeupConnected: This bit indicates whether the Host

Controller supports remote wake-up signaling. If remote wake-up is

supported and used by the system, it is the responsibility of the

system ﬁrmware to set this bit during POST. The Host Controller

clears the bit on a hardware reset but does not alter it on a software

reset. Remote wake-up signaling of the host system is

host-bus-speciﬁc and is not described in this speciﬁcation.

8

-

reserved

7 to 6

HCFS[1:0]

HostControllerFunctionalState for USB

00 — USBReset

01 — USBResume

10 — USBOperational

11 — USBSuspend

A transition to USBOperational from another state causes

Start-Of-Frame (SOF) generation to begin 1 ms later. The HCD may

determine whether the Host Controller has begun sending SOFs by

reading the StartofFrame (SF) ﬁeld of HcInterruptStatus.

This ﬁeld may be changed by the Host Controller only when it is in the

USBSuspend state. The Host Controller may move from the

USBSuspend state to the USBResume state after detecting the

resume signaling from a downstream port.

The Host Controller enters USBReset either by a software reset or by

a hardware reset. The latter also resets the root hub and asserts

subsequent reset signaling to downstream ports.

5 to 0

-

reserved

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14.1.3 HcCommandStatus register (R/W: 02h/82h)

The HcCommandStatus register is a 4 bytes register, and the bit allocation is given in

Table 39. This register is used by the Host Controller to receive commands issued by the

HCD, and it also reﬂects the current status of the Host Controller. To the HCD, it appears

to be a ‘write to set’ register. The Host Controller must ensure that bits written as logic 1

become set in the register while bits written as logic 0 remain unchanged in the register.

The HCD may issue multiple distinct commands to the Host Controller without concern for

corrupting previously issued commands. The HCD has normal read access to all bits.

The SchedulingOverrunCount (SOC) ﬁeld indicates the number of frames with which the

Host Controller has detected the scheduling overrun error. This occurs when the periodic

list does not complete before the End-Of-Frame (EOF). When a scheduling overrun error

is detected, the Host Controller increments the counter and sets the SchedulingOverrun

(SO) ﬁeld of the HcInterruptStatus register.

Code (Hex): 02 — read

Code (Hex): 82 — write

Table 39. HcCommandStatus register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved

-

23

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

reserved

SOC[1:0]

-

0

R

9

0

R

8

15

14

13

12

11

10

Symbol

Reset

Access

Bit

reserved

-

7

6

5

4

3

2

1

0

Symbol

Reset

Access

reserved

HCR

0

-

R/W

ISP1362_5

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Table 40. HcCommandStatus register: bit description

Bit

Symbol

-

Description

31 to 18

17 to 16

reserved

SOC[1:0]

SchedulingOverrunCount: This ﬁeld is incremented on each

scheduling overrun error. It is initialized to 00b and wraps around at

11b. It will be incremented when a scheduling overrun is detected

even if SchedulingOverrun in HcInterruptStatus has already been set.

This is used by the HCD to monitor any persistent scheduling

problems.

15 to 1

0

-

reserved

HCR

HostControllerReset: This bit is set by the HCD to initiate a software

reset to the Host Controller. Regardless of the functional state of the

Host Controller, it moves to the USBSuspend state in which most of

operational registers are reset, except those stated otherwise. This bit

is cleared by the Host Controller on completing the reset operation.

The reset operation must be completed within 10 ms. This bit, when

set, will not cause a reset to the root hub and no subsequent reset

signaling will be asserted to its downstream ports.

14.1.4 HcInterruptStatus register (R/W: 03h/83h)

This register (bit allocation: Table 41) provides the status of the events that cause

hardware interrupts. When an event occurs, the Host Controller sets the corresponding bit

in this register. When a bit is set, a hardware interrupt is generated if the corresponding

interrupt is enabled in the HcInterruptEnable register (see Section 14.1.5) and the

MasterInterruptEnable (MIE) bit is set. The HCD must write logic 1 to the speciﬁc bits to

clear the corresponding interrupt bits. The HCD cannot set any of these bits.

Code (Hex): 03 — read

Code (Hex): 83 — write

Table 41. HcInterruptStatus register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved

-

23

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

-

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

-

6

-

7

5

4

3

2

1

0

Symbol

Reset

Access

reserved

RHSC

0

FNO

0

UE

0

RD

0

SF

0

reserved

SO

0

-

R/W

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Table 42. HcInterruptStatus register: bit description

Bit

Symbol Description

31 to 7

6

-

reserved

RHSC

RootHubStatusChange: This bit is set when any of the bits of

HcRhPortStatus[NumberofDownstreamPort] has changed.

5

4

FNO

UE

FrameNumberOverﬂow: This bit is set when the MSB of the HcFmNumber

register (bit 15) changes from logic 0 to logic 1 or from logic 1 to logic 0.

UnrecoverableError: This bit is set when the Host Controller detects a

system error not related to the USB. The Host Controller should not proceed

with any processing nor signaling before the system error is corrected. The

HCD clears this bit after the Host Controller is reset.

NXP Host Controller interface: always set to logic 0.

3

2

RD

SF

ResumeDetected: This bit is set when the Host Controller detects that a

device on the USB is asserting resume signaling. It is the transition from no

resume signaling to resume signaling, causing this bit to be set. This bit is not

set when the HCD sets the USBResume state.

StartOfFrame: At the start of each frame, this bit is set by the Host Controller

and an SOF is generated.

1

0

-

reserved

SO

SchedulingOverrun: This bit is set when the schedule is overrun for the

current frame. A scheduling overrun also causes SchedulingOverrunCount

(SOC) of HcCommandStatus to be incremented.

14.1.5 HcInterruptEnable register (R/W: 04h/84h)

Each enable bit in the HcInterruptEnable register corresponds to an associated interrupt

bit in the HcInterruptStatus register. The HcInterruptEnable register is used to control

which events generate a hardware interrupt. When the following three conditions occur:

• A bit is set in the HcInterruptStatus register.

• The corresponding bit in the HcInterruptEnable register is set.

• The MasterInterruptEnable (MIE) bit is set.

Then, a hardware interrupt is requested on the host bus.

Writing logic 1 to a bit in the HcInterruptEnable register sets the corresponding bit,

whereas writing logic 0 to a bit in this register leaves the corresponding bit unchanged. On

a read, the current value of this register is returned. Table 43 contains the bit allocation of

the register.

Code (Hex): 04 — read

Code (Hex): 84 — write

Table 43. HcInterruptEnable register: bit allocation

Bit

31

MIE

0

30

29

28

27

26

25

24

Symbol

Reset

Access

reserved

-

R/W

ISP1362_5

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Bit

23

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

reserved

-

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

-

6

-

7

5

4

3

2

1

0

Symbol

Reset

Access

reserved

RHSC

0

FNO

0

UE

0

RD

0

SF

0

reserved

SO

0

-

R/W

Table 44. HcInterruptEnable register: bit description

Bit

Symbol

Description

31

MIE

MasterInterruptEnable by the HCD: Logic 0 is ignored by the Host

Controller. Logic 1 enables interrupt generation by events speciﬁed in

other bits of this register.

30 to 7

6

-

reserved

RHSC

0 — ignore

1 — enable interrupt generation because of root hub status change

5

4

3

2

FNO

UE

0 — ignore

1 — enable interrupt generation because of frame number overﬂow

0 — ignore

1 — enable interrupt generation because of unrecoverable error

RD

SF

0 — ignore

1 — enable interrupt generation because of resume detect

0 — ignore

1 — enable interrupt generation because of start-of-frame

1

0

-

reserved

SO

0 — ignore

1 — enable interrupt generation because of scheduling overrun

14.1.6 HcInterruptDisable register (R/W: 05h/85h)

Each disable bit in the HcInterruptDisable register corresponds to an associated interrupt

bit in the HcInterruptStatus register. The HcInterruptDisable register is coupled with the

HcInterruptEnable register. Therefore, writing logic 1 to a bit in this register clears the

corresponding bit in the HcInterruptEnable register, whereas writing logic 0 to a bit in this

register leaves the corresponding bit in the HcInterruptEnable register unchanged. On a

read, the current value of the HcInterruptEnable register is returned. Table 45 provides the

bit allocation of the HcInterruptDisable register.

Code (Hex): 05 — read

Code (Hex): 85 — write

ISP1362_5

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Table 45. HcInterruptDisable register: bit allocation

Bit

31

MIE

0

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved

-

R/W

23

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

reserved

-

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

reserved

-

6

-

7

5

4

3

2

1

0

Symbol

Reset

Access

reserved

RHSC

0

FNO

0

UE

0

RD

0

SF

0

reserved

SO

0

-

R/W

Table 46. HcInterruptDisable register: bit description

Bit

Symbol

Description

31

MIE

Logic 0 is ignored by the Host Controller. Logic 1 disables interrupt

generation. This ﬁeld is set after a hardware or software reset.

30 to 7

6

-

reserved

RHSC

0 — ignore

1 — disable interrupt generation because of root hub status change

5

4

3

2

FNO

UE

0 — ignore

1 — disable interrupt generation because of frame number overﬂow

0 — ignore

1 — disable interrupt generation because of unrecoverable error

RD

SF

0 — ignore

1 — disable interrupt generation because of resume detect

0 — ignore

1 — disable interrupt generation because of start-of-frame

1

0

-

reserved

SO

0 — ignore

1 — disable interrupt generation because of scheduling overrun

14.2 HC frame counter registers

14.2.1 HcFmInterval register (R/W: 0Dh/8Dh)

The HcFmInterval register (bit allocation: Table 47) contains a 14-bit value that indicates

the bit time interval in a frame between two consecutive SOFs. In addition, it contains a

15-bit value, indicating the full-speed maximum packet size that the Host Controller may

transmit or receive without causing a scheduling overrun. The HCD may carry out minor

ISP1362_5

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Single-chip USB OTG Controller

adjustments on FrameInterval by writing a new value over the present one at each SOF.

This provides the programmability necessary for the Host Controller to synchronize with

an external clocking resource and to adjust any unknown local clock offset.

Code (Hex): 0D — read

Code (Hex): 8D — write

Table 47. HcFmInterval register: bit allocation

Bit

31

FIT

0

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

FSMPS[14:8]

0

R/W

23

R/W

22

R/W

21

R/W

20

R/W

19

R/W

18

R/W

17

R/W

16

Symbol

Reset

Access

Bit

FSMPS[7:0]

0

R/W

9

0

R/W

8

R/W

15

R/W

14

R/W

13

R/W

12

R/W

11

R/W

10

Symbol

Reset

Access

Bit

reserved

FI[13:8]

-

1

R/W

5

0

R/W

4

1

R/W

3

1

R/W

2

1

R/W

1

0

R/W

0

7

6

Symbol

Reset

Access

FI[7:0]

1

0

1

R/W

Table 48. HcFmInterval register: bit description

Bit

Symbol

Description

31

FIT

FrameIntervalToggle: The HCD toggles this bit whenever it loads a

new value to FrameInterval.

30 to 16

FSMPS

[14:0]

FSLargestDataPacket: Speciﬁes a value that is loaded into the

largest data packet counter at the beginning of each frame. The

counter value represents the largest amount of data in bits that can be

sent or received by the Host Controller in a single transaction at any

given time, without causing a scheduling overrun. The ﬁeld value is

calculated by the HCD.

15 to 14

13 to 0

-

reserved

FI[13:0]

FrameInterval: Speciﬁes the interval between two consecutive SOFs

in bit times. The nominal value is set to 11999. The HCD must store

the current value of this ﬁeld before resetting the Host Controller.

Setting the HostControllerReset (HCR) ﬁeld of the HcCommandStatus

register causes the Host Controller to reset this ﬁeld to its nominal

value. The HCD may choose to restore the stored value on completing

the reset sequence.

14.2.2 HcFmRemaining register (R/W: 0Eh/8Eh)

The HcFmRemaining register is a 14-bit down counter, showing the bit time remaining in

the current frame. The bit allocation is given in Table 49.

Code (Hex): 0E — read

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Single-chip USB OTG Controller

Code (Hex): 8E — write

Table 49. HcFmRemaining register: bit allocation

Bit

31

FRT

0

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved

-

R/W

23

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

reserved

-

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

reserved

FR[13:8]

-

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

7

6

Symbol

Reset

Access

FR[7:0]

0

R/W

Table 50. HcFmRemaining register: bit description

Bit

Symbol Description

FRT

31

FrameRemainingToggle: This bit is loaded from the FrameIntervalToggle

(FIT) ﬁeld of HcFmInterval whenever FrameRemaining (FR) reaches 0. This

bit is used by the HCD for synchronization between FrameInterval (FI) and

FrameRemaining (FR).

30 to 14 -

reserved

13 to 0 FR[13:0] FrameRemaining: This counter is decremented at each bit time. When it

reaches zero, it is reset by loading the FrameInterval (FI) value speciﬁed in

HcFmInterval at the next bit time boundary. When entering the

USBOperational state, the Host Controller reloads it with the content of the

FrameInterval (FI) part of the HcFmInterval register and uses the updated

value from the next SOF.

14.2.3 HcFmNumber register (R/W: 0Fh/8Fh)

The HcFmNumber register is a 16-bit counter, and the bit allocation is given in Table 51. It

provides a timing reference for events happening in the Host Controller and the HCD. The

HCD may use the 16-bit value speciﬁed in this register and generate a 32-bit frame

number, without requiring frequent access to the register.

Code (Hex): 0F — read

Code (Hex): 8F — write

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NXP Semiconductors

Single-chip USB OTG Controller

Table 51. HcFmNumber register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved

FN[15:8]

FN[7:0]

-

23

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

-

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

0

R

7

0

R

6

0

R

5

0

R

4

0

R

3

0

R

2

0

R

1

0

R

0

Symbol

Reset

Access

0

R

Table 52. HcFmNumber register: bit description

Bit

Symbol Description

reserved

31 to 16

-

15 to 0 FN[15:0] FrameNumber: This is incremented when HcFmRemaining is reloaded. The

value will be rolled over to 0h after FFFFh. When the USBOperational state is

entered, this is automatically incremented.

14.2.4 HcLSThreshold register (R/W: 11h/91h)

The HcLSThreshold register contains an 11-bit value. This value is used by the Host

Controller to determine whether to start a transfer of a maximum of 8 bytes LS packet

before the EOF. The HCD is not allowed to change this value. Table 53 shows the bit

allocation of the register.

Code (Hex): 11 — read

Code (Hex): 91 — write

Table 53. HcLSThreshold register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved

-

23

22

21

20

19

18

17

16

Symbol

Reset

Access

-

ISP1362_5

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Single-chip USB OTG Controller

Bit

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

reserved

LST[10:8]

-

1

R/W

2

1

R/W

1

0

R/W

0

7

6

5

4

3

Symbol

Reset

Access

LST[7:0]

0

1

0

1

0

R/W

Table 54. HcLSThreshold register: bit description

Bit

Symbol

Description

31 to 11

10 to 0

-

reserved

LST[10:0] LSThreshold: Contains a value that is compared to the FrameRemaining

(FR) ﬁeld before a low-speed transaction is initiated. The transaction is

started only if FrameRemaining (FR) ≥ this ﬁeld. The value is calculated by

the HCD. The HCD must consider transmission and set-up overhead, while

calculating this value.

14.3 HC root hub registers

All registers included in this partition are dedicated to the USB root hub, which is an

integral part of the Host Controller although it is functionally a separate entity. The HCD

emulates USB Driver (USBD) accesses to the root hub by using a register interface. The

HCD maintains many USB-deﬁned hub features that are not required to be supported in

hardware. For example, the hub’s device, conﬁguration, interface and endpoint descriptors

are maintained only in the HCD, as well as some static ﬁelds of the class descriptor. The

HCD also maintains and decodes the address of the root hub device and other trivial

operations that are better suited to software than to hardware.

Root hub registers are developed to maintain the similarity of bit organization and

operation to typical hubs found in the system.

Four registers are deﬁned as follows:

• HcRhDescriptorA

• HcRhDescriptorB

• HcRhStatus

• HcRhPortStatus[1:NDP]

Each register is read and written as a double word. These registers are only written during

initialization to correspond with the system implementation. The HcRhDescriptorA and

HcRhDescriptorB registers can be read or written, regardless of the USB states of the

Host Controller. You can write to HcRhStatus and HcRhPortStatus only when the Host

Controller is in the USBOperational state.

14.3.1 HcRhDescriptorA register (R/W: 12h/92h)

The HcRhDescriptorA register is the ﬁrst of two registers describing the characteristics of

the root hub. The bit allocation is given in Table 55.

Code (Hex): 12 — read

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Single-chip USB OTG Controller

Code (Hex): 92 — write

Table 55. HcRhDescriptorA register: bit description

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

POTPGT[7:0]

1

R/W

23

R/W

22

R/W

21

R/W

20

R/W

19

R/W

18

R/W

17

R/W

16

Symbol

Reset

Access

Bit

reserved

-

12

-

8

15

14

13

11

10

DT

0

9

Symbol

Reset

Access

Bit

reserved

NOCP

0

OCPM

NPS

0

PSM

1

-

1

R/W

3

R/W

4

R

2

R/W

1

R/W

0

7

6

5

Symbol

Reset

Access

reserved

NDP[1:0]

-

1

0

R

Table 56. HcRhDescriptorA register: bit description

Bit Symbol Description

31 to 24 POTPGT PowerOnToPowerGoodTime: This byte speciﬁes the duration HCD must

[7:0]

wait before accessing a powered-on port of the root hub. It is implementation

speciﬁc. The unit of time is 2 ms. The duration is calculated as POTPGT ×

2 ms.

23 to 13

12

-

reserved

NOCP

NoOverCurrentProtection: This bit describes how the overcurrent status for

root hub ports are reported. When this bit is cleared, the

OverCurrentProtectionMode (OCPM) ﬁeld speciﬁes global or per-port

reporting.

0 — overcurrent status is collectively reported for all downstream ports.

1 — no overcurrent reporting supported.

11

OCPM

OverCurrentProtectionMode: This bit describes how the overcurrent status

for root hub ports are reported. At reset, this ﬁeld should reﬂect the same

mode as PowerSwitchingMode. This ﬁeld is valid only if the

NoOverCurrentProtection (NOCP) ﬁeld is cleared.

0 — overcurrent status is collectively reported for all downstream ports.

1 — overcurrent status is reported on a per-port basis. On power up, clear

this bit and then set it to logic 1.

10

9

DT

DeviceType: This bit speciﬁes that the root hub is not a compound device; it

is not permitted. This ﬁeld should always read as 0.

NPS

NoPowerSwitching: This bit is used to specify whether power switching is

supported or ports are always powered. It is implementation speciﬁc. When

this bit is cleared, the PowerSwitchingMode (PSM) bit speciﬁes global or

per-port switching.

0 — Ports are power switched.

1 — Ports are always powered on when the Host Controller is powered on.

ISP1362_5

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Single-chip USB OTG Controller

Table 56. HcRhDescriptorA register: bit description …continued

Bit

Symbol Description

8

PSM

PowerSwitchingMode: This bit is used to specify how the power switching

of Root Hub ports is controlled. It is implementation speciﬁc. This ﬁeld is

valid only if the NoPowerSwitching (NPS) ﬁeld is cleared.

0 — All ports are powered at the same time.

1 — Each port is individually powered. This mode allows port power to be

controlled by either the global switch or per-port switching. If the

PortPowerControlMask (PPCM) bit is set, the port responds to only port

power commands (Set/ClearPortPower). If the port mask is cleared, then the

port is controlled only by the global power switch (Set/ClearGlobalPower).

7 to 2

1 to 0

-

reserved

NDP[1:0] NumberofDownstreamPort: These bits specify the number of downstream

ports supported by the root hub. The ISP1362 supports two ports and

therefore, the value is 2.

14.3.2 HcRhDescriptorB register (R/W: 13h/93h)

The HcRhDescriptorB register is the second of two registers describing the characteristics

of the root hub. These ﬁelds are written during initialization to correspond to the system

implementation. Table 57 shows the bit allocation of the register.

Code (Hex): 13 — read

Code (Hex): 93 — write

Table 57. HcRhDescriptorB register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved

-

23

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

reserved

PPCM[2:0]

-

IS

R/W

9

R/W

15

14

13

12

11

10

8

Symbol

Reset

Access

Bit

reserved

-

1

7

6

5

4

3

2

0

Symbol

Reset

Access

reserved

DR[2:0]

IS

-

R/W

ISP1362_5

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Single-chip USB OTG Controller

Table 58. HcRhDescriptorB register: bit description

Bit

Symbol

Description

31 to 19

-

reserved

18 to 16 PPCM[2:0] PortPowerControlMask: Each bit indicates whether a port is affected by a

global power control command when PowerSwitchingMode is set. When

set, the power state of the port is only affected by per-port power control

(Set/ClearPortPower). When cleared, the port is controlled by the global

power switch (Set/ClearGlobalPower). If the device is conﬁgured to global

switching mode (PowerSwitchingMode = 0), this ﬁeld is not valid.

Bit 2 — ganged-power mask on port 2

Bit 1 — ganged-power mask on port 1

Bit 0 — reserved

15 to 3

2 to 0

-

reserved

DR[2:0]

DeviceRemovable: Each bit is dedicated to a port of the root hub. When

cleared, the attached device is removable. When set, the attached device

is not removable.

Bit 2 — device attached to port 2

Bit 1 — device attached to port 1

Bit 0 — reserved

14.3.3 HcRhStatus register (R/W: 14h/94h)

The HcRhStatus register is divided into two parts. The lower word of a double-word

represents the hub status ﬁeld and the upper word represents the hub status change ﬁeld.

Reserved bits should always be written as logic 0. See Table 59 for bit allocation of the

register.

Code (Hex): 14 — read

Code (Hex): 94 — write

Table 59. HcRhStatus register: bit allocation

Bit

31

CRWE

0

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved

-

W

23

22

21

20

19

18

17

CCIC

0

16

Symbol

Reset

Access

Bit

reserved

LPSC

0

-

15

-

R/W

9

R/W

8

14

13

12

11

10

Symbol

Reset

Access

Bit

DRWE

0

reserved

-

R/W

7

6

5

4

3

2

1

0

Symbol

Reset

Access

reserved

OCI

0

LPS

0

-

R

R/W

ISP1362_5

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Single-chip USB OTG Controller

Table 60. HcRhStatus register: bit description

Bit

Symbol Description

31

CRWE On write ClearRemoteWakeupEnable: Writing logic 1 clears

DeviceRemoteWakeupEnable (DRWE). Writing logic 0 has no effect.

30 to 18

17

-

reserved

CCIC

OverCurrentIndicatorChange: This bit is set by hardware when a change

has occurred to the OverCurrentIndicator (OCI) ﬁeld of this register. The HCD

clears this bit by writing logic 1. Writing logic 0 has no effect.

16

LPSC

On read LocalPowerStatusChange: The root hub does not support the local

power status feature. Therefore, this bit is always read as logic 0.

On write SetGlobalPower: In global power mode (PowerSwitchingMode = 0),

logic 1 is written to this bit to turn on power to all ports (clear

PortPowerStatus). In per-port power mode, it sets PortPowerStatus only on

ports whose PortPowerControlMask bit is not set. Writing logic 0 has no effect.

15

DRWE On read DeviceRemoteWakeupEnable: This bit enables

bit ConnectStatusChange as a resume event, causing a state transition from

USBSuspend to USBResume and setting the ResumeDetected interrupt.

0 — ConnectStatusChange is not a remote wake-up event

1 — ConnectStatusChange is a remote wake-up event

On write SetRemoteWakeupEnable: Writing logic 1 sets

DeviceRemoteWakeupEnable. Writing logic 0 has no effect.

14 to 2

1

-

reserved

OCI

OverCurrentIndicator: This bit reports overcurrent conditions when global

reporting is implemented. When set, an overcurrent condition exists. When

cleared, all power operations are normal. If per-port overcurrent protection is

implemented, this bit is always logic 0.

0

LPS

On read LocalPowerStatus: The root hub does not support the local power

status feature. Therefore, this bit is always read as logic 0.

On write ClearGlobalPower: In global power mode (PowerSwitchingMode =

0), logic 1 is written to this bit to turn-off power to all ports (clear

PortPowerStatus). In per-port power mode, it clears PortPowerStatus only on

ports whose PortPowerControlMask bit is not set. Writing logic 0 has no effect.

14.3.4 HcRhPortStatus[1:2] register (R/W [1]: 15h/95h; [2]: 16h/96h)

The HcRhPortStatus[1:2] register is used to control and report port events on a per-port

basis. NumberofDownstreamPort represents the number of HcRhPortStatus registers that

are implemented in hardware. The lower word is used to reﬂect the port status, whereas

the upper word reﬂects status change bits. Some status bits are implemented with special

write behavior. Reserved bits should always be written logic 0. The bit allocation of the

HcRhPortStatus[1:2] register is given in Table 61.

Code (Hex): [1] = 15, [2] = 16 — read

Code (Hex): [1] = 95, [2] = 96 — write

Table 61. HcRhPortStatus[1:2] register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

reserved

-

ISP1362_5

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Single-chip USB OTG Controller

Bit

23

22

21

20

PRSC

0

19

OCIC

0

18

PSSC

0

17

PESC

0

16

CSC

0

Symbol

Reset

Access

Bit

reserved

-

R/W

12

R/W

11

R/W

10

R/W

9

R/W

8

15

14

13

Symbol

Reset

Access

Bit

reserved

LSDA

0

PPS

0

-

3

R/W

1

R/W

0

7

6

5

4

2

Symbol

Reset

Access

reserved

PRS

0

POCI

0

PSS

0

PES

0

CCS

0

-

R/W

Table 62. HcRhPortStatus[1:2] register: bit description

Bit

Symbol

-

Description

31 to 21

20

reserved

PRSC

PortResetStatusChange: This bit is set at the end of the 10 ms port

reset signal. The HCD writes logic 1 to clear this bit. Writing logic 0

has no effect.

0 — port reset is not complete

1 — port reset is complete

19

18

OCIC

PSSC

PortOverCurrentIndicatorChange: This bit is valid only if overcurrent

conditions are reported on a per-port basis. This bit is set when the

root hub changes the PortOverCurrentIndicator (POCI) bit. The HCD

writes logic 1 to clear this bit. Writing logic 0 has no effect.

0 — no change in PortOverCurrentIndicator (POCI)

1 — PortOverCurrentIndicator (POCI) has changed

PortSuspendStatusChange: This bit is set when the full resume

sequence is complete. This sequence includes the 20 ms resume

pulse, LS EOP and 3 ms re-synchronization delay. The HCD writes

logic 1 to clear this bit. Writing logic 0 has no effect. This bit is also

cleared when PortResetStatusChange is set.

0 — resume is not completed

1 — resume is completed

17

PESC

PortEnableStatusChange: This bit is set when hardware events

cause the PortEnableStatus (PES) bit to be cleared. Changes from the

HCD writes do not set this bit. The HCD writes logic 1 to clear this bit.

Writing logic 0 has no effect.

0 — no change in PortEnableStatus (PES)

1 — change in PortEnableStatus (PES)

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Table 62. HcRhPortStatus[1:2] register: bit description …continued

Bit

Symbol

Description

16

CSC

ConnectStatusChange: This bit is set whenever a connect or

disconnect event occurs. The HCD writes logic 1 to clear this bit.

Writing logic 0 has no effect. If CurrentConnectStatus (CCS) is cleared

when a SetPortReset, SetPortEnable or SetPortSuspend write occurs,

this bit is set to force the driver to re-evaluate the connection status

because these writes should not occur if the port is disconnected.

0 — no change in CurrentConnectStatus (CCS)

1 — change in CurrentConnectStatus (CCS)

Remark: If the DeviceRemovable[NDP] bit is set, this bit is set only

after a root hub reset to inform the system that the device is attached.

15 to 10

9

-

reserved

LSDA

On read LowSpeedDeviceAttached: This bit indicates the speed of

the device attached to this port. When set, a low-speed device is

attached to this port. When cleared, a full-speed device is attached to

this port. This ﬁeld is valid only when CurrentConnectStatus (CCS) is

set.

0 — full-speed device attached

1 — low-speed device attached

On write ClearPortPower: The HCD clears the PortPowerStatus

(PPS) bit by writing logic 1 to this bit. Writing logic 0 has no effect.

8

PPS

On read PortPowerStatus: This bit reﬂects the port power status,

regardless of the type of power switching implemented. This bit is

cleared if an overcurrent condition is detected. The HCD sets this bit

by writing SetPortPower or SetGlobalPower. The HCD clears this bit

by writing ClearPortPower or ClearGlobalPower. PowerSwitchingMode

(PCM) and PortPowerControlMask[NDP] (PPCM[NDP]) determine

which power control switches are enabled. In global switching mode

(PowerSwitchingMode = 0), only the Set/ClearGlobalPower command

controls this bit. In the per-port power switching

(PowerSwitchingMode = 1), if the PortPowerControlMask[NDP]

(PPCM[NDP]) bit for the port is set, only Set/ClearPortPower

commands are enabled. If the mask is not set, only

Set/ClearGlobalPower commands are enabled. When port power is

disabled, CurrentConnectStatus (CCS), PortEnableStatus (PES),

PortSuspendStatus (PSS) and PortResetStatus (PRS) should be

reset.

0 — port power is off

1 — port power is on

On write SetPortPower: The HCD writes logic 1 to set the

PortPowerStatus (PPS) bit. Writing logic 0 has no effect.

Remark: This bit always reads logic 1 if power switching is not

supported.

7 to 5

-

reserved

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Single-chip USB OTG Controller

Table 62. HcRhPortStatus[1:2] register: bit description …continued

Bit

Symbol

Description

4

PRS

On read PortResetStatus: When this bit is set by a write to

SetPortReset, port reset signaling is asserted. When reset is

completed, this bit is cleared when PortResetStatusChange (PRSC) is

set. This bit cannot be set if CurrentConnectStatus (CCS) is cleared.

0 — port reset signal is not active

1 — port reset signal is active

On write SetPortReset: The HCD sets the port reset signaling by

writing logic 1 to this bit. Writing logic 0 has no effect. If

CurrentConnectStatus (CCS) is cleared, this write does not set

PortResetStatus (PRS) but instead sets ConnectStatusChange

(CSC). This informs the driver that it attempted to reset a

disconnected port.

3

POCI

On read PortOverCurrentIndicator: This bit is valid only when the

root hub is conﬁgured in such a way that overcurrent conditions are

reported on a per-port basis. If per-port overcurrent reporting is not

supported, this bit is set to logic 0. If cleared, all power operations are

normal for this port. If set, an overcurrent condition exists on this port.

This bit always reﬂects the overcurrent input signal.

0 — no overcurrent condition

1 — overcurrent condition detected

On write ClearSuspendStatus: The HCD writes logic 1 to initiate a

resume. Writing logic 0 has no effect. A resume is initiated only if

PortSuspendStatus (PSS) is set.

2

PSS

On read PortSuspendStatus: This bit indicates whether the port is

suspended or is in the resume sequence. It is set by a

PortSuspendStatus write and cleared when

PortSuspendStatusChange (PSSC) is set at the end of the resume

interval. This bit cannot be set if CurrentConnectStatus (CCS) is

cleared. This bit is also cleared when PortResetStatusChange

(PRSC) is set at the end of the port reset or when the Host Controller

is placed in the USBResume state. If an upstream resume is in

progress, it should propagate to the Host Controller.

0 — port is not suspended

1 — port is suspended

On write SetPortSuspend: The HCD sets the PortSuspendStatus

(PSS) bit by writing logic 1 to this bit. Writing logic 0 has no effect. If

CurrentConnectStatus (CCS) is cleared, this write does not set

PortSuspendStatus (PSS); instead it sets ConnectStatusChange

(CSC). This informs the driver that it attempted to suspend a

disconnected port.

ISP1362_5

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Single-chip USB OTG Controller

Table 62. HcRhPortStatus[1:2] register: bit description …continued

Bit

Symbol

Description

1

PES

On read PortEnableStatus: This bit indicates whether the port is

enabled or disabled. The root hub may clear this bit when an

overcurrent condition, disconnect event, switched-off power or

operational bus error, such as babble, is detected. This change also

causes PortEnableStatusChange to be set. The HCD sets this bit by

writing SetPortEnable and clears it by writing ClearPortEnable. This bit

cannot be set when CurrentConnectStatus (CCS) is cleared. This bit

is also set, if it is not already, at the completion of a port reset when

PortResetStatusChange is set or port suspend when

PortSuspendStatusChange is set.

0 — port is disabled

1 — port is enabled

On write SetPortEnable: The HCD sets PortEnableStatus (PES) by

writing logic 1. Writing logic 0 has no effect. If CurrentConnectStatus

(CCS) is cleared, this write does not set PortEnableStatus (PES), but

instead sets ConnectStatusChange (CSC). This informs the driver that

it attempted to enable a disconnected port.

0

CCS

On read CurrentConnectStatus: This bit reﬂects the current state of

the downstream port.

0 — no device connected

1 — device connected

On write ClearPortEnable: The HCD writes logic 1 to this bit to clear

the PortEnableStatus (PES) bit. Writing logic 0 has no effect.

CurrentConnectStatus (CSC) is not affected by any write.

Remark: This bit always reads logic 1 when the attached device is

nonremovable (DeviceRemovable[NDP]).

14.4 HC DMA and interrupt control registers

14.4.1 HcHardwareConﬁguration register (R/W: 20h/A0h)

The bit allocation of the HcHardwareConﬁguration register is given in Table 63.

Code (Hex): 20 — read

Code (Hex): A0 — write

Table 63. HcHardwareConﬁguration register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Disable

Suspend_

Wakeup

Global

Power

Down

Connect

PullDown

_DS2

Connect

PullDown ClkNotStop

_DS1

Suspend

AnalogOC

Enable

OneINT

DACK

Mode

Reset

Access

Bit

0

R/W

0

R/W

6

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

7

Symbol

OneDMA

DACKInput

Polarity

DREQ

Output

Polarity

DataBusWidth[1:0]

Interrupt

Output

Polarity

Interrupt

PinTrigger

InterruptPin

Enable

Reset

0

1

0

1

0

Access

R/W

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Single-chip USB OTG Controller

Table 64. HcHardwareConﬁguration register: bit description

Bit

Symbol

Description

15

DisableSuspend_Wakeup This bit when set to logic 1 disables the function of the

D_SUSPEND/D_WAKEUP and H_SUSPEND/H_WAKEUP

pins. Therefore, these pins will always remain HIGH and

pulling them LOW does not wake-up the Host Controller and

the Peripheral Controller.

14

13

GlobalPowerDown

Set this bit to logic 1 to reduce power consumption of the

OTG ATX in suspend mode.

ConnectPullDown_DS2

0 — disconnect built-in pull-down resistors on H_DM2 and

H_DP2

1 — connect built-in pull-down resistors on H_DM2 and

H_DP2 for the downstream port 2

Remark: Port 2 is always used as a host port.

12

ConnectPullDown_DS1

0 — disconnect built-in pull-down resistors on OTG_DM1 and

OTG_DP1

1 — connect built-in pull-down resistors on OTG_DM1 and

OTG_DP1

Remark: This bit is effective only when port 1 is conﬁgured as

the host port (the OTGMODE pin is HIGH, and the ID pin is

LOW). When port 1 is conﬁgured as the OTG port, (the

OTGMODE pin is LOW), the pull-down resistors on

OTG_DM1 and OTG_DP1 are controlled by the

LOC_PULL_DN_DP and LOC_PULL_DN_DM bits of the

OtgControl register.

11

10

9

SuspendClkNotStop

AnalogOCEnable

OneINT

0 — clock can be stopped when suspended

1 — clock cannot be stopped when suspended

0 — use external overcurrent detection; digital input

1 — use on-chip overcurrent detection; analog input

0 — Host Controller interrupt routed to INT1, Peripheral

Controller interrupt routed to INT2

1 — Host Controller and Peripheral Controller interrupts

routed to INT1 only, INT2 is unused

8

7

DACKMode

OneDMA

0 — normal operation; DACK1 is used with read and write

signals

1 — reserved

0 — Host Controller DMA request and acknowledge are

routed to DREQ1 and DACK1, Peripheral Controller DMA

request and acknowledge are routed to DREQ2 and DACK2

1 — Host Controller and Peripheral Controller DMA requests

and acknowledges are routed to DREQ1 and DACK1;

DREQ2 and DACK2 unused

6

DACKInputPolarity

0 — DACK1 is active LOW

1 — DACK1 is active HIGH

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Table 64. HcHardwareConﬁguration register: bit description …continued

Bit

Symbol

Description

5

DREQOutputPolarity

0 — DREQ1 is active LOW

1 — DREQ1 is active HIGH

4 to 3 DataBusWidth[1:0]

01 — microprocessor interface data bus width is 16 bits

Others — reserved

2

1

0

InterruptOutputPolarity

InterruptPinTrigger

InterruptPinEnable

0 — INT1 interrupt is active LOW; power-up value

1 — INT1 interrupt is active HIGH

0 — INT1 interrupt is level-triggered; power-up value

1 — INT1 interrupt is edge-triggered

0 — power-up value

1 — global interrupt pin INT1 is enabled; this bit should be

used with the HcµPInterruptEnable register to enable

pin INT1

14.4.2 HcDMAConﬁguration register (R/W: 21h/A1h)

Table 65 contains the bit allocation of the HcDMAConﬁguration register.

Code (Hex): 21 — read

Code (Hex): A1 — write

Table 65. HcDMAConﬁguration register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

reserved

-

4

-

7

6

5

3

2

1

0

Symbol

DMACounter

Enable

BurstLen[1:0]

DMA

Enable

Buffer_Type_Select[2:0]

DMARead

WriteSelect

Reset

0

Access

R/W

Table 66. HcDMAConﬁguration register: bit description

Bit

Symbol

Description

reserved

15 to 8

7

-

DMACounterEnable

0 — reserved

1 — DMA counter is enabled. Once the counter is enabled, the

HCD must initialize the HcTransferCounter register to a

non-zero value for DREQ to be raised after the DMAEnable bit

is set to HIGH.

6 to 5

BurstLen[1:0]

00 — single-cycle burst DMA

01 — 4-cycle burst DMA

10 — 8-cycle burst DMA

11 — reserved

I/O bus with 32-bit data path width supports only single and

four cycle DMA burst.

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Table 66. HcDMAConﬁguration register: bit description …continued

Bit

Symbol

Description

4

DMAEnable

0 — DMA is disabled

1 — DMA is enabled

This bit needs to be reset when the DMA transfer is completed.

Buffer_Type_Select[2:0] See Table 67.

DMAReadWriteSelect 0 — read from the buffer memory of the Host Controller

1 — write to the buffer memory of the Host Controller

3 to 1

0

Table 67. Buffer_Type_Select[2:0]: bit description

Bit 3

Bit 2

Bit 1

Buffer Type

ISTL0 (default)

ISTL1

0

1

0

1

X

0

1

0

1

X

INTL

ATL

direct addressing

14.4.3 HcTransferCounter register (R/W: 22h/A2h)

Regardless of PIO or DMA data transfer modes, this register is used to initialize the

number of bytes to be transferred to or from the ISTL, INTL or ATL buffer RAM. For the

count value loaded in the register to take effect, the HCD is required to set bit 7 of the

HcDMAConﬁguration register to logic 1. When the count value has reached, the Host

Controller must generate an internal EOT signal to set bit 2 of the HcµPInterrupt register,

AllEOTInterrupt, and update the HcBufferStatus register. The bit allocation of the

HcTransferCounter register is given in Table 68.

Code (Hex): 22 — read

Code (Hex): A2 — write

Table 68. HcTransferCounter register: bit description

Bit

Symbol

Access Value

0000h

Description

15 to 0

CounterValue[15:0] R/W

Number of data bytes to be read from or written to the buffer RAM.

14.4.4 HcµPInterrupt register (R/W: 24h/A4h)

All the bits in this register are active at power-on reset. None of the active bits, however,

will cause an interrupt on the interrupt pin (INT1), unless they are set by the respective

bits in the HcµPInterruptEnable register and bit 0 of the HcHardwareConﬁguration register

is also set.

The bits in this register are cleared only when you write to this register, indicating the bits

to be cleared. To clear all the enabled bits in this register, the HCD must write FFh to this

register.

The bit allocation of the HcµPInterrupt register is given in Table 69.

Code (Hex): 24 — read

Code (Hex): A4 — write

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Table 69. HcµPInterrupt register: bit allocation

Bit

15

14

13

12

11

10

9

8

ATL_IRQ

0

Symbol

Reset

Access

Bit

reserved

OTG_IRQ

-

0

R/W

1

-

7

-

6

R/W

5

4

3

2

0

Symbol

INTL_IRQ

ClkReady

HC

Suspended

OPR_Reg

AllEOT

Interrupt

ISTL1_

INT

ISTL0_

INT

SOF_INT

Reset

0

Access

R/W

Table 70. HcµPInterrupt register: bit description

Bit

Symbol

Description

15 to 10

9

-

reserved

OTG_IRQ 0 — no event

1 — The OTG interrupt event must read the OtgInterrupt register to get

the cause of the interrupt.

8

7

ATL_IRQ

0 — no event

1 — Count value of the HcATLPTDDoneThresholdCount register or the

time-out value of the HcATLPTDDoneThresholdTimeOut register has

reached. The microprocessor is required to read HcATLPTDDoneMap to

check the PTDs that have completed their transactions.

INTL_IRQ 0 — no event

1 — The Host Controller has detected the last PTD, and there is at least

one interrupt transaction that has received ACK from the device. The

microprocessor is required to read HcINTLPTDDoneMap to check the

PTDs that have received ACK from the device.

6

5

ClkReady 0 — no event

1 — The Host Controller has awakened from the ‘suspend’ state, and its

internal clock has turned on again.

HC

0 — no event

Suspended

1 — The Host Controller has been suspended and no USB activities are

sent from the microprocessor for each ms. The microprocessor can

suspend the Host Controller by setting bits 6 and 7 of the HcControl

register to logic 1. Once the Host Controller is suspended, no SOF needs

to be sent to the devices connected to downstream ports.

4

3

OPR_Reg 0 — no event

1 — A Host Controller operation has caused a hardware interrupt. It is

necessary for the HCD to read the HcInterruptStatus register to determine

the cause of the interrupt.

AllEOT

0 — no event

Interrupt

1 — Data transfer has been completed by using the PIO transfer or the

DMA transfer. This bit is set either when the value of the

HcTransferCounter register has reached zero, or the EOT pin of the Host

Controller is triggered by an external signal.

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Table 70. HcµPInterrupt register: bit description …continued

Bit

Symbol

Description

2

ISTL1_

INT

0 — no event

1 — The transaction of the last PTD stored in the ISTL1 buffer has been

completed. The microprocessor is required to read data from the ISTL1

buffer. The HCD must ﬁrst read the HcBufferStatus register to check the

status of the ISTL1 buffer, before reading data to the microprocessor.

1

0

ISTL0_

INT

0 — no event

1 — The transaction of the last PTD stored in the ISTL0 buffer has been

completed. The microprocessor is required to read data from the ISTL0

buffer. The HCD must ﬁrst read the HcBufferStatus register to check the

status of the ISTL0 buffer, before reading data to the microprocessor.

SOF_INT

0 — no event

1 — The Host Controller is in the SOF state and it indicates the start of a

new frame. The HCD must ﬁrst read the HcBufferStatus register to check

the status of the ISTL buffer, before reading data to the microprocessor.

For the microprocessor to perform the DMA transfer of ISO data from or to

the ISTL buffer, the Host Controller must ﬁrst initialize the

HcDMAConﬁguration register.

14.4.5 HcµPInterruptEnable register (R/W: 25h/A5h)

Bits 9 to 0 in this register are the same as those in the HcµPInterrupt register. The bits in

this register are used together with bit 0 of the HcHardwareConﬁguration register to

enable or disable the bits in the HcµPInterrupt register.

At power-on, all the bits in this register are masked with logic 0. This means no interrupt

request output on interrupt pin INT1 can be generated. When a bit is set to logic 1, the

interrupt for that bit is enabled.

The bit allocation of the register is given in Table 71.

Code (Hex): 25 — read

Code (Hex): A5 — write

Table 71. HcµPInterruptEnable register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

reserved

OTG_IRQ_ ATL_IRQ_

Interrupt

Enable

Interrupt

Enable

Reset

Access

Bit

-

0

R/W

1

0

R/W

0

7

6

5

4

3

2

Symbol

INTL_IRQ_ ClkReady

Interrupt

Enable

HC

Suspended

Enable

OPR

Interrupt

Enable

EOT

Interrupt

Enable

ISTL1

Interrupt

Enable

ISTL0

Interrupt

Enable

SOF

Interrupt

Enable

Reset

0

Access

R/W

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Table 72. HcµPInterruptEnable register: bit description

Bit

Symbol

Description

15 to 10

9

-

reserved

OTG_IRQ_InterruptEnable 0 — power-up value

1 — enables the OTG_IRQ interrupt

ATL_IRQ_InterruptEnable 0 — power-up value

1 — enables the ATL_IRQ interrupt

INTL_IRQ_InterruptEnable 0 — power-up value

1 — enables the INT_IRQ interrupt

0 — power-up value

8

7

6

5

4

3

2

1

0

ClkReady

1 — enables the ClkReady interrupt

0 — power-up value

HCSuspendedEnable

OPRInterruptEnable

EOTInterruptEnable

ISTL1InterruptEnable

ISTL0InterruptEnable

SOFInterruptEnable

1 — enables the Host Controller suspended interrupt

0 — power-up value

1 — enables the 32-bit operational register’s interrupt

0 — power-up value

1 — enables the EOT interrupt

0 — power-up value

1 — enables the ISTL1 interrupt

0 — power-up value

1 — enables the ISTL0 interrupt

0 — power-up value

1 — enables the SOF interrupt

14.5 HC miscellaneous registers

14.5.1 HcChipID register (R: 27h)

This register contains the ID of the ISP1362. The upper byte identiﬁes the product name

(here 36h stands for the ISP1362). The lower byte indicates the revision number of the

product, including engineering samples. Table 73 contains the bit description of the

register.

Code (Hex): 27 — read only

Table 73. HcChipID register: bit description

Bit

Symbol

Access

Value

Description

15 to 0

CHIPID[15:0]

R

3630h

chip ID of the ISP1362.

14.5.2 HcScratch register (R/W: 28h/A8h)

This register is for the HCD to save and restore values when required. The bit description

is given in Table 74.

Code (Hex): 28 — read

Code (Hex): A8 — write

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Table 74. HcScratch register: bit description

Bit

Symbol

Access

Value

Description

15 to 0

Scratch[15:0]

R/W

0000h

scratch register value.

14.5.3 HcSoftwareReset register (W: A9h)

This register provides a means for the software reset of the Host Controller. To reset the

Host Controller, the HCD must write a reset value of F6h to this register. On receiving this

reset value, the Host Controller resets all the Host Controller and OTG registers, except its

buffer memory.

Table 75 contains the bit description of the register.

Code (Hex): A9 — write only

Table 75. HcSoftwareReset register: bit description

Bit

Symbol

Access

Value

Description

15 to 0

ResetValue[15:0] W

0000h

Writing a reset value of F6h causes the Host Controller to reset all the

Host Controller and OTG registers, except its buffer memory.

14.6 HC buffer RAM control registers

14.6.1 HcBufferStatus register (R/W: 2Ch/ACh)

The bit allocation of the HcBufferStatus register is given in Table 76.

Code (Hex): 2C — read

Code (Hex): AC — write

Table 76. HcBufferStatus register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

reserved

PairedPTD

ISTL1

ISTL0

PingPong BufferDone BufferDone

Reset

Access

Bit

-

0

R

2

0

R

1

0

R

0

-

7

6

5

4

3

Symbol

reserved

ISTL1_

Active

Status

ISTL0_

Active

Status

Reset_HW ATL_Active

PingPong

Reg

INTL_

Active

ISTL1

BufferFull

ISTL0

BufferFull

Reset

-

0

Access

R

R/W

Table 77. HcBufferStatus register: bit description

Bit

Symbol

Description

15 to 11

10

-

reserved

PairedPTDPingPong 0 — Ping of the paired PTD in ATL is active.

1 — Pong of the paired PTD in ATL is active.

9

ISTL1BufferDone

0 — The ISTL1 buffer has not yet been read by the Host

Controller.

1 — The ISTL1 buffer has been read by the Host Controller.

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Table 77. HcBufferStatus register: bit description …continued

Bit

Symbol

Description

8

ISTL0BufferDone

0 — The ISTL0 buffer has not yet been read by the Host

Controller.

1 — The ISTL0 buffer has been read by the Host Controller.

7

6

-

reserved

ISTL1_ActiveStatus 0 — The ISTL1 buffer is not accessed by the slave host.

1 — The ISTL1 buffer is accessed by the slave host.

5

4

ISTL0_ActiveStatus 0 — The ISTL0 buffer is not accessed by the slave host.

1 — The ISTL0 buffer is accessed by the slave host.

Reset_HWPingPong 0 to 1 — Resets the internal hardware ping pong register to 0

Reg

when ATL_Active is 0. The hardware ping pong register can be

read from bit 10 of this register.

1 to 0 — Has no effect.

3

2

1

0

ATL_Active

0 — The Host Controller does not process the ATL buffer.

1 — The Host Controller processes the ATL buffer.

0 — The Host Controller does not process the INTL buffer.

1 — The Host Controller processes the INTL buffer.

0 — The Host Controller does not process the ISTL1 buffer.

1 — The Host Controller processes the ISTL1 buffer.

0 — The Host Controller does not process the ISTL0 buffer.

1 — The Host Controller processes the ISTL0 buffer.

INTL_Active

ISTL1BufferFull

ISTL0BufferFull

14.6.2 HcDirectAddressLength register (R/W: 32h/B2h)

The HcDirectAddressLength register is used for direct addressing of the ISTL, INTL or

ATL buffers. This register speciﬁes the starting address of the buffer and byte count of

data to be addressed. Therefore, it allows the programmer to randomly access the buffer.

The bit allocation of the register is given in Table 78.

Code (Hex): 32 — read

Code (Hex): B2 — write

Table 78. HcDirectAddressLength register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

DataByteCount[15:8]

0

R/W

23

R/W

22

R/W

21

R/W

20

R/W

19

R/W

18

R/W

17

R/W

16

Symbol

Reset

Access

Bit

DataByteCount[7:0]

0

R/W

9

0

R/W

8

R/W

14

R/W

13

R/W

12

R/W

11

R/W

10

15

Symbol

Reset

Access

reserved

BufferStartAddress[14:8]

0

-

0

R/W

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Bit

7

6

5

4

3

2

1

0

Symbol

Reset

Access

BufferStartAddress[7:0]

0

R/W

Table 79. HcDirectAddressLength register: bit description

Bit

Symbol

Description

31 to 16

15

DataByteCount[15:0]

-

Total number of bytes to be accessed.

reserved

14 to 0

BufferStartAddress[14:0] The starting address of the buffer to access data.

14.6.3 HcDirectAddressData register (R/W: 45h/C5h)

This is a data port for the HCD to access the ISTL, INTL or ATL buffers under direct

addressing mode. Table 80 contains the bit description of the register.

Code (Hex): 45 — read

Code (Hex): C5 — write

Table 80. HcDirectAddressData register: bit description

Bit Symbol Access Value Description

15 to 0 DataWord R/W

[15:0]

0000h The data port to access the ISTL, INTL or ATL buffers. The address of the buffer and

byte count of the data must be speciﬁed in the HcDirectAddressLength register.

14.7 Isochronous (ISO) transfer registers

14.7.1 HcISTLBufferSize register (R/W: 30h/B0h)

This register requires you to allocate the size of the buffer to be used for ISO transactions.

The buffer size speciﬁed in the register is applied to the ISTL0 and ISTL1 buffers.

Therefore, ISTL0 and ISTL1 always have the same buffer size.

Table 81 shows the bit description of the register.

Code (Hex): 30 — read

Code (Hex): B0 — write

Table 81. HcISTLBufferSize register: bit description

Bit

Symbol

Access Value

Description

15 to 0 ISTLBufferSize[15:0] R/W

0000h The size of the buffer to be used for ISO transactions and must be

speciﬁed in bytes.

14.7.2 HcISTL0BufferPort register (R/W: 40h/C0h)

In addition to the HcDirectAddressData register, the ISP1362 provides this register to act

as another data port to access the ISTL0 buffer. The starting address to access the buffer

is always ﬁxed at 0000h. Therefore, random access of the ISTL0 buffer is not allowed. The

bit description of the register is given in Table 82.

Code (Hex): 40 — read

Code (Hex): C0 — write

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Table 82. HcISTL0BufferPort register: bit description

Bit

Symbol

Access

Value

Description

The data in the ISTL0 buffer to be accessed through this data port.

15 to 0 DataWord[15:0] R/W

0000h

The HCD is ﬁrst required to initialize the HcTransferCounter register with the byte count to

be transferred and check the HcBufferStatus register. The HCD then sends the command

(40h to read from the ISTL0 buffer, and C0h to write to the ISTL0 buffer) to the Host

Controller through the I/O port of the microprocessor. After the command is sent, the HCD

starts reading data from the ISTL0 buffer or writing data to the ISTL0 buffer. While the

HCD is accessing the buffer, the buffer pointer of ISTL0 also automatically increases.

When the pointer has reached the initialized byte count of the HcTransferCounter register,

the Host Controller sets the AllEOTInterrupt bit of the HcµPInterrupt register to logic 1 and

updates the HcBufferStatus register.

14.7.3 HcISTL1BufferPort register (R/W: 42h/C2h)

In addition to the HcDirectAddressData register, the ISP1362 provides this register to act

as another data port to access the ISTL1 buffer. The starting address to access the buffer

is always ﬁxed at 0000h. Therefore, random access of the ISTL1 buffer is not allowed. The

bit description of the register is given in Table 83.

Code (Hex): 42 — read

Code (Hex): C2 — write

Table 83. HcISTL1BufferPort register: bit description

Bit

Symbol

Access Value

0000h

Description

15 to 0

DataWord[15:0] R/W

Data in the ISTL1 buffer to be accessed through this data port.

The HCD is ﬁrst required to initialize the HcTransferCounter register with the byte count to

be transferred and check the HcBufferStatus register. The HCD then sends the command

(42h to read from the ISTL1 buffer, and C2h to write to the ISTL1 buffer) to the Host

Controller through the I/O port of the microprocessor. After the command is sent, the HCD

starts reading data from the ISTL1 buffer or writing data to the ISTL1 buffer. While the

HCD is accessing the buffer, the buffer pointer of ISTL1 also automatically increases.

When the pointer has reached the initialized byte count of the HcTransferCounter register,

the Host Controller sets the AllEOTInterrupt bit in the HcµPInterrupt register to logic 1 and

updates the HcBufferStatus register.

14.7.4 HcISTLToggleRate register (R/W: 47h/C7h)

The rate of toggling between ISTL0 and ISTL1 is programmable. The HcISTLToggleRate

register is provided to program the required toggle rate in the range of 0 ms to 15 ms at

intervals of 1 ms. The bit allocation of the register is shown in Table 84.

Code (Hex): 47 — read

Code (Hex): C7 — write

Table 84. HcISTLToggleRate register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Reset

Access

reserved

-

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Bit

7

6

5

4

3

2

1

0

Symbol

Reset

Access

reserved

ISTLToggleRate[3:0]

-

0

R/W

Table 85. HcISTLToggleRate register: bit description

Bit

Symbol

Description

15 to 4

3 to 0

-

reserved

ISTLToggleRate[3:0]

The required toggle rate in ms.

14.8 Interrupt transfer registers

14.8.1 HcINTLBufferSize register (R/W: 33h/B3h)

This register allows you to allocate the size of the INTL buffer to be used for interrupt

transactions. The default value of the buffer size is set to 128 bytes, and the maximum

allowable allocated size is 4096 bytes. Table 86 shows the bit description of the register.

Code (Hex): 33 — read

Code (Hex): B3 — write

Table 86. HcINTLBufferSize register: bit description

Bit

Symbol

Access

Value

Description

15 to 0 INTLBufferSize[15:0] R/W

0080h

The size of the buffer to be used for interrupt transactions and must

be speciﬁed in bytes.

14.8.2 HcINTLBufferPort register (R/W: 43h/C3h)

In addition to the HcDirectAddressData register, the ISP1362 provides this register to act

as another data port to access the INTL buffer. The starting address to access the buffer

is always ﬁxed at 0000h. Therefore, random access of the INTL buffer is not allowed. The

bit description of the HcINTLBufferPort register is given in Table 87.

Code (Hex): 43 — read

Code (Hex): C3 — write

Table 87. HcINTLBufferPort register: bit description

Bit

Symbol

Access Value

0000h

Description

15 to 0

DataWord[15:0] R/W

Data in the INTL buffer to be accessed through this data port.

The HCD is ﬁrst required to initialize the HcTransferCounter register with the byte count to

be transferred and check the HcBufferStatus register. The HCD then sends the command

(43h to read the INTL buffer, and C3h to write to the INTL buffer) to the Host Controller

through the I/O port of the microprocessor. After the command is sent, the HCD starts

reading data from the INTL buffer or writing data to the INTL buffer. While the HCD is

accessing the buffer, the buffer pointer of INTL also automatically increases. When the

pointer has reached the initialized byte count of the HcTransferCounter register, the Host

Controller sets the AllEOTInterrupt bit of the HcµPInterrupt register to logic 1 and updates

the HcBufferStatus register.

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14.8.3 HcINTLBlkSize register (R/W: 53h/D3h)

The ISP1362 requires the INTL buffer to be partitioned into several equal sized blocks so

that the Host Controller can skip the current PTD and proceed to process the next PTD

easily. The block size of the INTL buffer is required to be speciﬁed in this register and must

be a multiple of 8 bytes. The default value of the block size is 64 bytes, and the maximum

allowable block size is 1024 bytes. Table 88 shows the bit allocation of the register.

Code (Hex): 53 — read

Code (Hex): D3 — write

Table 88. HcINTLBlkSize register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

reserved

BlockSize[9:8]

-

0

R/W

1

0

R/W

0

7

6

5

4

3

2

Symbol

Reset

Access

BlockSize[7:0]

0

R/W

Table 89. HcINTLBlkSize register: bit description

Bit

Symbol

Description

15 to 10

9 to 0

-

reserved

BlockSize[9:0]

The block size of the INTL buffer.

14.8.4 HcINTLPTDDoneMap register (R: 17h)

This is a 32-bit register, and the bit description is given in Table 90. Every bit of the

register represents the processing status of a PTD. Bit 0 of the register represents the ﬁrst

PTD stored in the INTL buffer, bit 1 represents the second PTD stored in the buffer, and so

on. The register is updated once every ms by the Host Controller and is cleared on read

by the HCD. Bits that are set represent its corresponding PTDs are processed by the Host

Controller and the ACK token is received from the device.

Code (Hex): 17 — read only

Table 90. HcINTLPTDDoneMap register: bit description

Bit

Symbol

Access

Value

Description

31 to 0 PTDDoneBits[31:0]

R

0000h

0 — The PTD stored in the INTL buffer has not successfully been

processed by the Host Controller.

1 — The PTD stored in the INTL buffer has successfully been

processed by the Host Controller.

14.8.5 HcINTLPTDSkipMap register (R/W: 18h/98h)

This is a 32-bit register, and the bit description is given in Table 91. Bit 0 of the register

represents the ﬁrst PTD stored in the INTL buffer, bit 1 represents the second PTD stored

in the buffer, and so on. When a bit is set by the HCD, the corresponding PTD is skipped

and is not processed by the Host Controller. The Host Controller processes the skipped

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PTD if the HCD has reset its corresponding skipped bit to logic 0. Clearing the

corresponding bit in the HcINTLPTDSkipMap register when there is no valid data in the

block will cause unpredictable behavior of the Host Controller.

Code (Hex): 18 — read

Code (Hex): 98 — write

Table 91. HcINTLPTDSkipMap register: bit description

Bit

Symbol

Access

Value

Description

31 to 0

SkipBits[31:0] R/W

0000h

0 — The Host Controller processes the PTD.

1 — The Host Controller skips processing the PTD.

14.8.6 HcINTLLastPTD register (R/W: 19h/99h)

This is a 32-bit register, and Table 92 shows its bit description. Bit 0 of the register

represents the ﬁrst PTD stored in the INTL buffer, bit 1 represents the second PTD stored

in the buffer, and so on. The bit that is set to logic 1 by the HCD is used as an indication to

the Host Controller that its corresponding PTD is the last PTD stored in the INTL buffer.

When the processing of the last PTD is complete, the Host Controller proceeds to process

ATL transactions.

Code (Hex): 19 — read

Code (Hex): 99 — write

Table 92. HcINTLLastPTD register: bit description

Bit

Symbol

Access

Value

Description

31 to 0 LastPTDBits[31:0] R/W

0000h

0 — The PTD is not the last PTD stored in the buffer.

1 — The PTD is the last PTD stored in the buffer.

14.8.7 HcINTLCurrentActivePTD register (R: 1Ah)

This register indicates which PTD stored in the INTL buffer is currently active and is

updated by the Host Controller. The HCD can use it as a buffer pointer to decide which

PTD locations are currently free to ﬁll in new PTDs to the buffer. This indication is to

prevent the HCD from accidentally writing into the currently active PTD buffer location.

Table 93 shows the bit allocation of the register.

Code (Hex): 1A — read only

Table 93. HcINTLCurrentActivePTD register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

reserved

-

7

6

5

4

3

2

1

0

Symbol

Reset

Access

reserved

ActivePTD[4:0]

-

0

R

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Table 94. HcINTLCurrentActivePTD register: bit description

Bit

Symbol

Description

15 to 5

4 to 0

-

reserved

ActivePTD[4:0]

This 5-bit number represents the PTD that is currently active.

14.9 Control and bulk transfer (aperiodic transfer) registers

14.9.1 HcATLBufferSize register (R/W: 34h/B4h)

This register allows you to allocate the size of the ATL buffer to be used for aperiodic

transactions. The default value of the buffer size is set to 512 bytes, and the maximum

allowable allocated size is 4096 bytes. The bit description of the register is given in

Table 95.

Code (Hex): 34 — read

Code (Hex): B4 — write

Table 95. HcATLBufferSize register: bit description

Bit Symbol Access Value

15 to 0 ATLBufferSize[15:0] R/W 0200h

Description

The size of the buffer to be used for aperiodic transactions and must

be speciﬁed in bytes.

14.9.2 HcATLBufferPort register (R/W: 44h/C4h)

In addition to the HcDirectAddressData register, the ISP1362 provides this register to act

as another data port to access the ATL buffer. The starting address to access the buffer is

always ﬁxed at 0000h. Therefore, random access of the ATL buffer is not allowed. The bit

description of the HcATLBufferPort register is given in Table 96.

Code (Hex): 44 — read

Code (Hex): C4 — write

Table 96. HcATLBufferPort register: bit description

Bit

Symbol

Access

Value

Description

15 to 0

DataWord[15:0] R/W

0000h

The data of the ATL buffer to be accessed through this data port.

The HCD is ﬁrst required to initialize the HcTransferCounter register with the byte count to

be transferred and check the HcBufferStatus register. The HCD then sends the command

(44h to read from the ATL buffer, and C4h to write to the ATL buffer) to the Host Controller

through the I/O port of the microprocessor. After the command is sent, the HCD starts

reading data from the ATL buffer or writing data to the ATL buffer. While the HCD is

accessing the buffer, the buffer pointer of ATL also automatically increases. When the

pointer has reached the initialized byte count of the HcTransferCounter register, the Host

Controller sets the AllEOTInterrupt bit of the HcµPInterrupt register to logic 1 and updates

the HcBufferStatus register.

14.9.3 HcATLBlkSize register (R/W: 54h/D4h)

The ISP1362 partitions the ATL buffer into several equal sized blocks so that the Host

Controller can skip the current PTD and proceed to process the next PTD easily. The

block size of the ATL buffer must be speciﬁed in this register and must be a multiple of

8 bytes. The bit allocation of the HcATLBlkSize register is given in Table 97.

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Code (Hex): 54 — read

Code (Hex): D4 — write

Table 97. HcATLBlkSize register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

reserved

BlockSize[9:8]

-

0

R/W

1

0

R/W

0

7

6

5

4

3

2

Symbol

Reset

Access

BlockSize[7:0]

0

R/W

Table 98. HcATLBlkSize register: bit description

Bit

Symbol

Description

15 to 10

9 to 0

-

reserved

BlockSize[9:0] The block size of the ATL buffer.

14.9.4 HcATLPTDDoneMap register (R: 1Bh)

This is a 32-bit register. The bit description of the register is given in Table 99. Every bit of

the register represents the processing status of a PTD. Bit 0 of the register represents the

ﬁrst PTD stored in the ATL buffer, bit 1 represents the second PTD stored in the buffer,

and so on. The register is immediately updated after the completion of each ATL PTD

processing. It is cleared when read by the HCD. Bits that are set represent its

corresponding PTDs have been processed by the Host Controller and an ACK token has

been received from the device.

Code (Hex): 1B — read only

Table 99. HcATLPTDDoneMap register: bit description

Bit

Symbol

Access Value

0000h

Description

31 to 0 PTDDoneBits

[31:0]

R

0 — The PTD stored in the ATL buffer was not successfully processed by the

Host Controller.

1 — The PTD stored in the ATL buffer was successfully processed by the

Host Controller.

14.9.5 HcATLPTDSkipMap register (R/W: 1Ch/9Ch)

This is a 32-bit register, and the bit description is given in Table 100. Bit 0 of the register

represents the ﬁrst PTD stored in the ATL buffer, bit 1 represents the second PTD stored

in the buffer, and so on. When the bit is set by the HCD, the corresponding PTD is skipped

and is not processed by the Host Controller. The Host Controller processes the skipped

PTD only if the HCD has reset its corresponding skipped bit to logic 0. Clearing the

corresponding bit in the HcATLPTDSkipMap register when there is no valid data in the

block will cause unpredictable behavior of the Host Controller.

Code (Hex): 1C — read

Code (Hex): 9C — write

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Table 100. HcATLPTDSkipMap register: bit description

Bit

Symbol

Access

Value

Description

31 to 0

SkipBits

[31:0]

R/W

0000h

0 — The Host Controller processes the PTD.

1 — The Host Controller skips processing the PTD.

14.9.6 HcATLLastPTD register (R/W: 1Dh/9Dh)

This is a 32-bit register. Table 101 gives the bit description of the register. Bit 0 of the

register represents the ﬁrst PTD stored in the ATL buffer, bit 1 represents the second PTD

stored in the buffer, and so on. The bit that is set to logic 1 by the HCD is used as an

indication to the Host Controller that its corresponding PTD is the last PTD stored in the

ATL buffer. When the processing of the last PTD is complete, the Host Controller loops

back to process the ﬁrst PTD stored in the buffer.

Code (Hex): 1D — read

Code (Hex): 9D — write

Table 101. HcATLLastPTD register: bit description

Bit

Symbol

Access

Value

Description

31 to 0

LastPTD

Bits[31:0]

R/W

0000h

0 — The PTD is not the last PTD stored in the buffer.

1 — The PTD is the last PTD stored in the buffer.

14.9.7 HcATLCurrentActivePTD register (R: 1Eh)

This register indicates which PTD stored in the ATL buffer is currently active and is

updated by the Host Controller. The HCD can use it as a buffer pointer to decide which

PTD locations are currently free to ﬁll in new PTDs to the buffer. This indication helps to

prevent the HCD from accidentally writing into the currently active PTD buffer location.

Table 102 shows the bit allocation of the register.

Code (Hex): 1E — read only

Table 102. HcATLCurrentActivePTD register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

reserved

-

7

6

5

4

3

2

1

0

Symbol

Reset

Access

reserved

ActivePTD[4:0]

-

0

R

Table 103. HcATLCurrentActivePTD register: bit description

Bit

Symbol

Description

15 to 5

4 to 0

-

reserved

ActivePTD[4:0] This 5-bit number represents the PTD that is currently active.

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14.9.8 HcATLPTDDoneThresholdCount register (R/W: 51h/D1h)

This register speciﬁes the number of ATL PTDs to be done to trigger an ATL interrupt. If

set to 08h, the Host Controller will trigger the ATL interrupt (in the HcµPInterrupt register)

once every eight ATL PTDs are done. Table 104 shows the bit allocation of the register.

Remark: Do not write 0000h to this register.

Code (Hex): 51 — read

Code (Hex): D1 — write

Table 104. HcATLPTDDoneThresholdCount register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

reserved

-

7

6

5

4

3

2

1

0

Symbol

Reset

Access

reserved

PTDDoneCount[4:0]

-

0

1

R/W

Table 105. HcATLPTDDoneThresholdCount register: bit description

Bit

Symbol

Description

15 to 5

4 to 0

-

reserved

PTDDoneCount Number of PTDs to be processed by the Host Controller to generate an

[4:0] ATL interrupt.

14.9.9 HcATLPTDDoneThresholdTimeOut register (R/W: 52h/D2h)

This is a time-out register used to generate an ATL interrupt. The value in this register

indicates the maximum allowable time in milliseconds for the Host Controller to retry a

NAK transaction. This register can be used in combination with

HcATLPTDDoneThresholdCount. Table 106 shows the bit allocation of the

HcATLPTDDoneThresholdCount register.

Remark: If the time-out indication is not required by software, or there is no active PTD in

the ATL buffer, write 0000h to this register.

Code (Hex): 52 — read

Code (Hex): D2 — write

Table 106. HcATLPTDDoneThresholdTimeOut register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

reserved

-

7

6

5

4

3

2

1

0

Symbol

Reset

Access

PTDDoneTimeOut[7:0]

0

1

R/W

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Table 107. HcATLPTDDoneThresholdTimeOut register: bit description

Bit

Symbol

Description

15 to 8

7 to 0

-

reserved

PTDDoneTimeOut[7:0 Maximum allowable time in ms for the Host Controller to retry a

transaction with NAK returned.

]

15. Peripheral Controller registers

The functions and registers of the Peripheral Controller are accessed using commands,

which consist of a command code followed by optional data bytes (read or write action).

An overview of the available commands and registers is given in Table 108.

A complete access consists of two phases:

1. Command phase: when address pin A0 = HIGH, the Peripheral Controller interprets

the data on the lower byte of the bus (bits D7 to D0) as command code. Commands

without a data phase are immediately executed.

2. Data phase (optional): when address pin A0 = LOW, the Peripheral Controller

transfers the data on the bus to or from a register or endpoint buffer memory. In case

of multi-byte registers, the least signiﬁcant byte or word is accessed ﬁrst.

The following applies to a register or buffer memory access in 16-bit bus mode:

• The upper byte (bits D15 to D8) in the command phase or the undeﬁned byte in the

data phase are ignored.

• The access of registers is word-aligned: byte access is not allowed.

• If the packet length is odd, the upper byte of the last word in an IN endpoint buffer is

not transmitted to the host. When reading from an OUT endpoint buffer, the upper

byte of the last word must be ignored by the ﬁrmware. The packet length is stored in

the ﬁrst two bytes of the endpoint buffer.

Table 108. Peripheral Controller command and register overview

Name

Destination

Code (Hex)

Transaction^[1]

Initialization commands

Write control OUT conﬁguration

DcEndpointConﬁguration register 20

endpoint 0 OUT

write 1 byte^[2]

read 1 byte^[2]

Write control IN conﬁguration

DcEndpointConﬁguration register 21

endpoint 0 IN

Write endpoint n conﬁguration (n = 1

to 14)

DcEndpointConﬁguration register 22 to 2F

endpoint 1 to 14

Read control OUT conﬁguration

DcEndpointConﬁguration register 30

endpoint 0 OUT

Read control IN conﬁguration

DcEndpointConﬁguration register 31

endpoint 0 IN

Read endpoint n conﬁguration (n = 1 DcEndpointConﬁguration register 32 to 3F

to 14)

endpoint 1 to 14

DcAddress register

DcMode register

Write or read device address

Write or read Mode register

B6/B7

B8/B9

write or read 1 byte^[2]

write or read 2 bytes

Write or read hardware conﬁguration DcHardwareConﬁguration register BA/BB

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Table 108. Peripheral Controller command and register overview …continued

Name

Destination

Code (Hex)

Transaction^[1]

Write or read DcInterruptEnable

register

DcInterruptEnable register

C2/C3

write or read 4 bytes

Write or read DMA conﬁguration

Write or read DMA counter

Reset device

DcDMAConﬁguration register

DcDMACounter register

resets all registers

F0/F1

F2/F3

F6

write or read 2 bytes

-

Data ﬂow commands

Write control OUT buffer

Write control IN buffer

illegal: endpoint is read-only

buffer memory endpoint 0 IN

(00)

-

01

N ≤ 64 bytes

Write endpoint n buffer (n = 1 to 14)

buffer memory endpoint 1 to 14

(IN endpoints only)

02 to 0F

isochronous: N ≤

1023 bytes

interrupt/bulk: N ≤ 64 bytes

Read control OUT buffer

buffer memory endpoint 0 OUT

illegal: endpoint is write-only

10

N ≤ 64 bytes

Read control IN buffer

(11)

-

Read endpoint n buffer (n = 1 to 14)

buffer memory endpoint 1 to 14

(OUT endpoints only)

12 to 1F

isochronous: N ≤

1023 bytes^[3]

interrupt/bulk: N ≤ 64 bytes

Stall control OUT endpoint

Stall control IN endpoint

Stall endpoint n (n = 1 to 14)

Read control OUT status

endpoint 0 OUT

endpoint 0 IN

40

-

41

-

endpoint 1 to 14

42 to 4F

50

-

DcEndpointStatus register

endpoint 0 OUT

read 1 byte^[2]

Read control IN status

DcEndpointStatus register

endpoint 0 IN

51

read 1 byte^[2]

Read endpoint n status (n = 1 to 14)

DcEndpointStatus register n

endpoint 1 to 14

52 to 5F

Validate control OUT buffer

Validate control IN buffer

illegal: IN endpoints only^[4]

buffer memory endpoint 0 IN^[4]

(60)

-

61

Validate endpoint n buffer (n = 1 to 14) buffer memory endpoint 1 to 14

(IN endpoints only)^[4]

62 to 6F

Clear control OUT buffer

buffer memory endpoint 0 OUT

illegal^[5]

70

-

Clear control IN buffer

(71)

Clear endpoint n buffer (n = 1 to 14)

buffer memory endpoint 1 to 14

(OUT endpoints only)^[5]

72 to 7F

Unstall control OUT endpoint

Unstall control IN endpoint

Unstall endpoint n (n = 1 to 14)

Check control OUT status^[6]

endpoint 0 OUT

endpoint 0 IN

80

-

81

-

endpoint 1 to 14

82 to 8F

-

DcEndpointStatusImage register D0

endpoint 0 OUT

read 1 byte^[2]

Check control IN status^[6]

DcEndpointStatusImage register D1

endpoint 0 IN

read 1 byte^[2]

-

Check endpoint n status (n = 1 to

14)^[6]

DcEndpointStatusImageregister n D2 to DF

endpoint 1 to 14

Acknowledge set up

endpoint 0 IN and OUT

F4

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Table 108. Peripheral Controller command and register overview …continued

Name

Destination

Code (Hex)

Transaction^[1]

General commands

Read control OUT error code

DcErrorCode register endpoint 0 A0

OUT

read 1 byte^[2]

Read control IN error code

DcErrorCode register endpoint 0 A1

IN

Read endpoint n error code (n = 1 to

14)

DcErrorCode register endpoint 1 A2 to AF

to 14

Unlock device

all registers with write access

DcScratch register

B0

write 2 bytes

Write or read DcScratch register

Read frame number

Read chip ID

B2/B3

B4

write or read 2 bytes

read 1 byte or 2 bytes

read 2 bytes

DcFrameNumber register

DcChipID register

B5

Read DcInterrupt register

DcInterrupt register

C0

read 4 bytes

[1] With N representing the number of bytes, the number of words for 16-bit bus width is: (N + 1) divided by 2.

[2] When accessing an 8-bit register in 16-bit mode, the upper byte is invalid.

[3] During the isochronous transfer in 16-bit mode, because N ≤ 1023, ﬁrmware must manage the upper byte.

[4] Validating an OUT endpoint buffer causes unpredictable behavior of the Peripheral Controller.

[5] Clearing an IN endpoint buffer causes unpredictable behavior of the Peripheral Controller.

[6] Reads a copy of the Status register, executing this command does not clear any status bits or interrupt bits.

15.1 Initialization commands

Initialization commands are used during the enumeration process of the USB network.

These commands are used to conﬁgure and enable embedded endpoints. They also

serve to set the USB assigned address of the Peripheral Controller and to perform a

device reset.

15.1.1 DcEndpointConﬁguration register (R/W: 30h to 3Fh/20h to 2Fh)

This command is used to access the DcEndpointConﬁguration register (ECR) of the

target endpoint. It deﬁnes the endpoint type (isochronous or bulk/interrupt), direction

(OUT/IN), buffer memory size and buffering scheme. It also enables the endpoint buffer

memory. The register bit allocation is shown in Table 109. A bus reset will disable all

endpoints.

The allocation of the buffer memory takes place only after all 16 endpoints have been

conﬁgured in sequence (from endpoint 0 OUT to endpoint 14). Although control endpoints

have ﬁxed conﬁgurations, they must be included in the initialization sequence and must be

conﬁgured with their default values (see Table 14). Automatic buffer memory allocation

starts when endpoint 14 has been conﬁgured.

Remark: If any change is made to an endpoint conﬁguration that affects the allocated

memory (size, enable/disable), the buffer memory contents of all endpoints becomes

invalid. Therefore, all valid data must be removed from enabled endpoints before changing

the conﬁguration.

Code (Hex): 20 to 2F — write (control OUT, control IN, endpoints 1 to 14)

Code (Hex): 30 to 3F — read (control OUT, control IN, endpoints 1 to 14)

Transaction — write or read 1 byte (code or data)

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Table 109. DcEndpointConﬁguration register: bit allocation

Bit

7

FIFOEN

0

6

EPDIR

0

5

DBLBUF

0

4

FFOISO

0

3

2

1

0

Symbol

Reset

Access

FFOSZ[3:0]

0

R/W

Table 110. DcEndpointConﬁguration register: bit description

Bit

7

Symbol

FIFOEN

EPDIR

Description

Logic 1 enables the FIFO buffer. Logic 0 disables the FIFO buffer.

6

This bit deﬁnes the endpoint direction (0 = OUT, 1 = IN); it also determines

the DMA transfer direction (0 = read, 1 = write).

5

4

DBLBUF

FFOISO

Logic 1 enables the double buffering.

Logic 1 indicates an isochronous endpoint. Logic 0 indicates a bulk or

interrupt endpoint.

3 to 0 FFOSZ[3:0] Selects the buffer memory size according to Table 15.

15.1.2 DcAddress register (R/W: B7h/B6h)

This command is used to set the USB assigned address in the DcAddress register and

enable the USB device. The DcAddress register bit allocation is shown in Table 111.

A USB bus reset sets the device address to 00h (internally) and enables the device. The

value of the DcAddress register (accessible by the microprocessor) is not altered by the

USB bus reset. In response to standard USB request Set Address, ﬁrmware must issue a

Write Device Address command, followed by sending an empty packet to the host. The

new device address is activated when the host acknowledges the empty packet.

Code (Hex): B6/B7 — write or read DcAddress register

Transaction — write or read 1 byte (code or data)

Table 111. DcAddress register: bit allocation

Bit

7

DEVEN

0

6

5

4

3

2

1

0

Symbol

Reset

Access

DEVADR[6:0]

0

R/W

Table 112. DcAddress register: bit description

Bit

7

Symbol

Description

DEVEN

Logic 1 enables the device.

6 to 0

DEVADR[6:0]

This ﬁeld speciﬁes the USB device address.

15.1.3 DcMode register (R/W: B9h/B8h)

This command is used to access the DcMode register, which consists of 1 byte (bit

allocation: see Table 113). In 16-bit bus mode, the upper byte is ignored.

The DcMode register controls the DMA bus width, resume and suspend modes, interrupt

activity, and SoftConnect operation. It can be used to enable debug mode, in which all

errors and Not Acknowledge (NAK) conditions will generate an interrupt.

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Code (Hex): B8/B9 — write or read DcMode register

Transaction — write or read 1 byte (code or data)

Table 113. DcMode register: bit allocation

Bit

7

6

5

GOSUSP

0

4

reserved

0

3

INTENA

0^[1]

2

DBGMOD

0^[1]

1

reserved

0^[1]

0

SOFTCT

0^[1]

Symbol

Reset

Access

reserved

1^[1]

0

R/W

[1] Unchanged by a bus reset.

Table 114. DcMode register: bit description

Bit

Symbol

Description

7 to 6

-

reserved

5

4

3

2

GOSUSP

-

Writing logic 1 followed by logic 0 will activate suspend mode.

reserved

INTENA

Logic 1 enables all interrupts. Bus reset value: unchanged.

DBGMOD Logic 1 enables debug mode, in which all NAKs and errors will generate an

interrupt. Logic 0 selects normal operation, in which interrupts are generated

on every ACK (bulk or interrupt endpoints) or after every data transfer

(isochronous endpoints). Bus reset value: unchanged.

1

0

-

reserved

SOFTCT

Logic 1 enables SoftConnect. This bit is ignored if EXTPUL = 1 in the

DcHardwareConﬁguration register (see Table 115). Bus reset value:

unchanged.

Remark: In OTG mode, this bit is ignored. The LOC_CONN bit of the

OtgControl register controls the pull-up resistor on the OTG_DP1 pin.

15.1.4 DcHardwareConﬁguration register (R/W: BBh/BAh)

This command is used to access the DcHardwareConﬁguration register, which consists of

2 bytes. The ﬁrst (lower) byte contains the device conﬁguration and control values, the

second (upper) byte holds clock control bits and the clock division factor. The bit allocation

is given in Table 115. A bus reset will not change any of programmed bit values.

The DcHardwareConﬁguration register controls the connection to the USB bus, clock

activity and power supply during the ‘suspend’ state, as well as output clock frequency,

DMA operating mode and pin conﬁgurations (polarity, signaling mode).

Code (Hex): BA/BB — write or read DcHardwareConﬁguration register

Transaction — write or read 2 bytes (code or data)

Table 115. DcHardwareConﬁguration register: bit allocation

Bit

15

14

EXTPUL

0

13

NOLAZY

1

12

CLKRUN

0

11

10

9

8

Symbol

Reset

Access

reserved

CKDIV[3:0]

-

0

1

R/W

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Bit

7

DAKOLY

0

6

DRQPOL

1

5

DAKPOL

0

4

3

WKUPCS

0

2

reserved

1

INTLVL

0

INTPOL

0

Symbol

Reset

Access

reserved

0

-

R/W

Table 116. DcHardwareConﬁguration register: bit description

Bit

15

14

Symbol

-

Description

reserved

EXTPUL

Logic 1 indicates that an external 1.5 kΩ pull-up resistor is used on

pin OTG_DP1 (in device mode) and that SoftConnect is not used. Bus

reset value: unchanged.

13

12

NOLAZY

CLKRUN

Logic 1 disables output on pin CLKOUT of the LazyClock frequency

(115 kHz ± 50 %) during the suspend state. Logic 0 causes pin CLKOUT

to switch to LazyClock output after approximately 2 ms delay, following the

setting of bit GOSUSP of the DcMode register. Bus reset value:

unchanged.

Logic 1 indicates that internal clocks are always running, even during the

‘suspend’ state. Logic 0 switches off the internal oscillator and PLL, when

they are not needed. During the ‘suspend’ state, this bit must be made

logic 0 to meet suspend current requirements. The clock is stopped after a

delay of approximately 2 ms, following the setting of bit GOSUSP of the

DcMode register. Bus reset value: unchanged.

11 to 8 CKDIV[3:0] This ﬁeld speciﬁes clock division factor N, which controls the clock

frequency on output CLKOUT pin. The output frequency in MHz is given

by 48 ⁄ (N + 1) . The clock frequency range is 3 MHz to 48 MHz (N = 0 to

15), with a reset value of 12 MHz (N = 3). The hardware design

guarantees no glitches during frequency change. Bus reset value:

unchanged.

7

6

5

DAKOLY

DRQPOL

DAKPOL

Logic 1 selects DACK-only DMA mode. Logic 0 selects 8237 compatible

DMA mode. Bus reset value: unchanged.

Selects the DREQ2 pin signal polarity (0 = active LOW; 1 = active HIGH).

Bus reset value: unchanged.

Selects the DACK2 pin signal polarity (0 = active LOW; 1 = active HIGH).

Bus reset value: unchanged.

4

3

-

reserved

WKUPCS

Logic 1 enables remote wake-up using a LOW level on input CS. Bus reset

value: unchanged.

2

1

-

reserved

INTLVL

Selects interrupt signaling mode on output (0 = level; 1 = pulsed). In

pulsed mode, an interrupt produces 166 ns pulse. Bus reset value:

unchanged.

0

INTPOL

Selects the INT2 signal polarity (0 = active LOW; 1 = active HIGH). Bus

reset value: unchanged.

15.1.5 DcInterruptEnable register (R/W: C3h/C2h)

This command is used to individually enable or disable interrupts from all endpoints, as

well as interrupts caused by events on the USB bus (SOF, EOT, suspend, resume, reset).

A bus reset will not change any of the programmed bit values.

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The command accesses the DcInterruptEnable register, which consists of 4 bytes. The bit

allocation is given in Table 117.

Code (Hex): C2/C3 — write or read DcInterruptEnable register

Transaction — write or read 4 bytes (code or data)

Table 117. DcInterruptEnable register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved

-

17

-

23

22

21

20

19

18

16

Symbol

Reset

Access

Bit

IEP14

IEP13

IEP12

0

IEP11

0

IEP10

0

IEP9

0

IEP8

0

IEP7

0

R/W

13

R/W

12

R/W

11

R/W

10

R/W

9

R/W

15

14

8

Symbol

Reset

Access

Bit

IEP6

IEP5

IEP4

0

IEP3

0

IEP2

0

IEP1

0

IEP0IN

0

IEP0OUT

0

R/W

0

R/W

5

R/W

4

R/W

3

R/W

2

R/W

1

7

6

SP_IEEOT

0

Symbol

Reset

Access

reserved

IEPSOF

0

IESOF

0

IEEOT

0

IESUSP

0

IERESM

0

IERST

0

-

R/W

Table 118. DcInterruptEnable register: bit description

Bit

Symbol

Description

31 to 24

-

reserved; must write logic 0

23 to 10 IEP14 to IEP1 Logic 1 enables interrupts from the indicated endpoint. Logic 0

disables interrupts from the indicated endpoint.

9

IEP0IN

Logic 1 enables interrupts from the control IN endpoint. Logic 0

disables interrupts from the control IN endpoint.

8

IEP0OUT

Logic 1 enables interrupts from the control OUT endpoint. Logic 0

disables interrupts from the control OUT endpoint.

7

6

-

reserved

SP_IEEOT

Logic 1 enables interrupt on detecting a short packet. Logic 0

disables interrupt.

5

4

3

IEPSOF

IESOF

IEEOT

Logic 1 enables 1 ms interrupts on detecting pseudo SOF. Logic 0

disables interrupts.

Logic 1 enables interrupt on the SOF detection. Logic 0 disables

interrupt.

Logic 1 enables interrupt on the EOT detection. Logic 0 disables

interrupt.

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Table 118. DcInterruptEnable register: bit description …continued

Bit

Symbol

Description

2

IESUSP

Logic 1 enables interrupt on detecting a suspend state. Logic 0

disables interrupt.

1

0

IERESM

IERST

Logic 1 enables interrupt on detecting a resume state. Logic 0

disables interrupt.

Logic 1 enables interrupt on detecting a bus reset. Logic 0 disables

interrupt.

15.1.6 DcDMAConﬁguration (R/W: F1h/F0h)

This command deﬁnes the DMA conﬁguration of the Peripheral Controller, and enables or

disables DMA transfers. The command accesses the DcDMAConﬁguration register, which

consists of two bytes. The bit allocation is given in Table 119. A bus reset will clear

bit DMAEN (DMA disabled), all other bits remain unchanged.

Code (Hex): F0/F1 — write or read DMA Conﬁguration

Transaction — write or read 2 bytes (code or data)

Table 119. DcDMAConﬁguration register: bit allocation

Bit

15

CNTREN

0^[1]

14

SHORTP

0^[1]

13

12

11

10

9

8

Symbol

Reset

Access

Bit

reserved

-

R/W

6

-

7

5

4

3

2

1

0

Symbol

Reset

Access

EPDIX[3:0]

DMAEN

0

reserved

BURSTL[1:0]

0^[1]

-

0^[1]

R/W

[1] Unchanged by a bus reset.

Table 120. DcDMAConﬁguration register: bit description

Bit

Symbol

Description

15

CNTREN

Logic 1 enables the generation of an EOT condition, when the

DcDMACounter register reaches zero. Bus reset value: unchanged.

14

SHORTP

Logic 1 enables short or empty packet mode. When receiving (OUT

endpoint) a short or empty packet, an EOT condition is generated. When

transmitting (IN endpoint), this bit must be cleared. Bus reset value:

unchanged.

13 to 8

7 to 4

-

reserved

EPDIX[3:0]

Indicates the destination endpoint for DMA, see Table 17.

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Table 120. DcDMAConﬁguration register: bit description …continued

Bit

Symbol

Description

3

DMAEN

Writing logic 1 enables DMA transfer, logic 0 forces the end of an ongoing

DMA transfer. Reading this bit indicates whether DMA is enabled or not

(0 = DMA stopped; 1 = DMA enabled). This bit is cleared by a bus reset.

2

-

reserved

1 to 0

BURSTL[1:0] Selects the DMA burst length:

00 — single-cycle mode (1 byte)

01 — burst mode (4 bytes)

10 — burst mode (8 bytes)

11 — burst mode (16 bytes)

Bus reset value: unchanged.

15.1.7 DcDMACounter register (R/W: F3h/F2h)

This command accesses the DcDMACounter register, which consists of two bytes. The bit

allocation is given in Table 121. Writing to the register sets the number of bytes for a DMA

transfer. Reading the register returns the number of remaining bytes in the current

transfer. A bus reset will not change programmed bit values.

The internal DMA counter is automatically reloaded from the DcDMACounter register. For

details, see Section 15.1.6.

Code (Hex): F2/F3 — write or read DcDMACounter register

Transaction — write or read 2 bytes (code or data)

Table 121. DcDMACounter register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

DMACR[15:8]

0

R/W

7

0

R/W

6

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

Symbol

Reset

Access

DMACR[7:0]

0

R/W

Table 122. DcDMACounter register: bit description

Bit

Symbol

Description

This ﬁeld indicates the number of bytes for a DMA transfer.

15 to 0

DMACR[15:0]

15.1.8 Reset device (F6h)

This command resets the Peripheral Controller in the same way as an external hardware

reset by using input RESET. All registers are initialized to their ‘reset’ values.

Code (Hex): F6 — reset the device

Transaction — none (code only)

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15.2 Data ﬂow commands

Data ﬂow commands are used to manage data transmission between USB endpoints and

the system microprocessor. Much of the data ﬂow is initiated using an interrupt to the

microprocessor. Data ﬂow commands are used to access endpoints and determine

whether the endpoint buffer memory contains valid data.

Remark: The IN buffer of an endpoint contains input data for the host. The OUT buffer

receives output data from the host.

15.2.1 Write or read endpoint buffer (R/W: 10h,12h to 1Fh/01h to 0Fh)

This command is used to access endpoint buffer memory to read/write. First, the buffer

pointer is reset to the start of the buffer. Following the command, a maximum of (N + 2)

bytes can be written or read, N represents the size of the endpoint buffer. For 16-bit

access, the maximum number of words is (M + 1), with M given as (N + 1) divided by 2.

After each read or write action, the buffer pointer is automatically incremented by two.

In Direct Memory Access (DMA), the ﬁrst two bytes or the ﬁrst word (the packet length) is

skipped: transfers start at the third byte or the second word of the endpoint buffer. When

reading, the Peripheral Controller can detect the last byte or word by using the EOP

condition. When writing to a bulk or interrupt endpoint, the endpoint buffer must be

completely ﬁlled before sending data to the host. Exception: when a DMA transfer is

stopped by an external EOT condition, the current buffer content (full or not) is sent to the

host.

Remark: Reading data after a Write Endpoint Buffer command or writing data after a

Read Endpoint Buffer command data will cause unpredictable behavior of the Peripheral

Controller.

Code (Hex): 01 to 0F — write (control IN, endpoints 1 to 14)

Code (Hex): 10, 12 to 1F — read (control OUT, endpoints 1 to 14)

Transaction — write or read maximum N + 2 bytes (isochronous endpoint: N ≤ 1023,

bulk/interrupt endpoint: N ≤ 32) (code or data)

The data in the endpoint buffer memory must be organized as shown in Table 123. An

example of endpoint buffer memory access is given in Table 124.

Table 123. Endpoint buffer memory organization

Word #

Description

0 (lower byte)

0 (upper byte)

1 (lower byte)

1 (upper byte)

…

packet length (lower byte)

packet length (upper byte)

data byte 1

data byte 2

…

M = (N + 1) / 2

data byte N

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Table 124. Example of endpoint buffer memory access

A0

Phase

Bus lines

D[7:0]

Word #

Description

HIGH

command

-

command code (00h to 1Fh)

D[15:8]

D[15:0]

…

-

ignored

LOW

…

data

…

0

1

2

…

packet length

data word 1 (data byte 2, data byte 1)

data word 2 (data byte 4, data byte 3)

…

Remark: There is no protection against writing or reading past a buffer’s boundary,

against writing into an OUT buffer or reading from an IN buffer. Any of these actions can

cause an incorrect operation. Data residing in an OUT buffer is only meaningful after a

successful transaction. Exception: during the DMA access of a double-buffered endpoint,

the buffer pointer automatically points to the secondary buffer after reaching the end of the

primary buffer.

15.2.2 Read endpoint status (R: 50h to 5Fh)

This command is used to read the status of an endpoint buffer memory. The command

accesses the DcEndpointStatus register, the bit allocation of which is shown in Table 125.

Reading the DcEndpointStatus register will clear the interrupt bit set for the corresponding

endpoint in the DcInterrupt register (see Table 141).

All bits of the DcEndpointStatus register are read-only. Bit EPSTAL is controlled by the

Stall or Unstall commands and by the reception of a set-up token (see Section 15.2.3).

Code (Hex): 50 to 5F — read (control OUT, control IN, endpoints 1 to 14)

Transaction — read 1 byte (code only)

Table 125. DcEndpointStatus register: bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

EPSTAL

EPFULL1

EPFULL0

DATA_PID

OVER

SETUPT

CPUBUF

reserved

WRITE

Reset

0

-

Access

R

Table 126. DcEndpointStatus register: bit description

Bit

Symbol

Description

7

EPSTAL

This bit indicates whether the endpoint is stalled or not (1 = stalled; 0 =

not stalled).

Set to logic 1 by a stall endpoint command, cleared to logic 0 by an

Unstall Endpoint command. The endpoint is automatically unstalled on

receiving a set-up token.

6

5

4

EPFULL1

EPFULL0

DATA_PID

Logic 1 indicates that the secondary endpoint buffer is full.

Logic 1 indicates that the primary endpoint buffer is full.

This bit indicates data PID of the next packet (0 = DATA PID; 1 = DATA1

PID).

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Table 126. DcEndpointStatus register: bit description …continued

Bit

Symbol

Description

3

OVERWRITE This bit is set by hardware. Logic 1 indicates that a new set-up packet has

overwritten the previous set-up information, before it was acknowledged

or before the endpoint was stalled. Once writing of the set-up data is

completed, a read back of this register clears this bit.

Firmware must check this bit before sending an acknowledge set-up

command or stalling the endpoint. On reading logic 1, ﬁrmware must stop

ongoing set-up actions and wait for a new set-up packet.

2

1

SETUPT

CPUBUF

Logic 1 indicates that the buffer contains a set-up packet.

This bit indicates which buffer is currently selected for the CPU access

(0 = primary buffer; 1 = secondary buffer).

0

-

reserved

15.2.3 Stall endpoint or unstall endpoint (40h to 4Fh/80h to 8Fh)

These commands are used to stall or unstall an endpoint. The commands modify the

content of the DcEndpointStatus register (see Table 125).

A stalled control endpoint is automatically unstalled when it receives a set-up token,

regardless of the packet content. If the endpoint must stay in its stalled state, the

microprocessor can re-stall it with the Stall Endpoint command.

When a stalled endpoint is unstalled (either by using the Unstall Endpoint command or by

receiving a set-up token), it is also re-initialized. This ﬂushes the buffer: if it is an OUT

buffer, it waits for a DATA 0 PID; if it is an IN buffer, it writes a DATA 0 PID.

Code (Hex): 40 to 4F — stall (control OUT, control IN, endpoints 1 to 14)

Code (Hex): 80 to 8F — unstall (control OUT, control IN, endpoints 1 to 14)

Transaction — none (code only)

15.2.4 Validate endpoint buffer (61h to 6Fh)

This command signals the presence of valid data for transmission to the USB host. The

validation occurs by setting the Buffer Full ﬂag of the selected IN endpoint. This indicates

that the data in the buffer is valid and can be sent to the host, when the next IN token is

received. For a double-buffered endpoint, this command switches the current buffer

memory for CPU access.

Remark: For special aspects of the control IN endpoint, see Section 12.3.6.

Code (Hex): 61 to 6F — validate endpoint buffer (control IN, endpoints 1 to 14)

Transaction — none (code only)

15.2.5 Clear endpoint buffer (70h, 72h to 7Fh)

This command unlocks and clears the buffer of the selected OUT endpoint, allowing the

reception of new packets. Reception of a complete packet causes the Buffer Full ﬂag of an

OUT endpoint to be set. Any subsequent packets are refused by returning a NAK

condition, until the buffer is unlocked using this command. For a double-buffered endpoint,

this command switches the current buffer memory for CPU access.

Remark: For special aspects of the control OUT endpoint, see Section 12.3.6.

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Code (Hex): 70, 72 to 7F — clear endpoint buffer (control OUT, endpoints 1 to 14)

Transaction — none (code only)

15.2.6 DcEndpointStatusImage register (D0h to DFh)

This command is used to check the status of the selected endpoint buffer memory, without

clearing any status or interrupt bits. The command accesses the DcEndpointStatusImage

register, which contains a copy of the DcEndpointStatus register. The bit allocation of the

DcEndpointStatusImage register is shown in Table 127.

Code (Hex): D0 to DF — check status (control OUT, control IN, endpoints 1 to 14)

Transaction — write or read 1 byte (code or data)

Table 127. DcEndpointStatusImage register: bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

EPSTAL

EPFULL1

EPFULL0

DATA_PID

OVER

SETUPT

CPUBUF

reserved

WRITE

Reset

0

-

Access

R

Table 128. DcEndpointStatusImage register: bit description

Bit

Symbol

Description

7

EPSTAL

This bit indicates whether the endpoint is stalled or not (1 = stalled; 0 =

not stalled).

6

5

4

EPFULL1

EPFULL0

DATA_PID

Logic 1 indicates that the secondary endpoint buffer is full.

Logic 1 indicates that the primary endpoint buffer is full.

This bit indicates data PID of the next packet (0 = DATA0 PID; 1 =

DATA1 PID).

3

OVERWRITE

This bit is set by hardware. Logic 1 indicates that a new set-up packet

has overwritten the previous set-up information, before it was

acknowledged or before the endpoint was stalled. Once writing of the

set-up data is completed, a read back of this register clears this bit.

Firmware must check this bit before sending an acknowledge set-up

command or stalling the endpoint. On reading logic 1, ﬁrmware must

stop ongoing set-up actions and wait for a new set-up packet.

2

1

SETUPT

CPUBUF

Logic 1 indicates that the buffer contains a set-up packet.

This bit indicates which buffer is currently selected for CPU access (0 =

primary buffer; 1 = secondary buffer).

0

-

reserved

15.2.7 Acknowledge set up (F4h)

This command acknowledges to the host that a set-up packet is received. The arrival of a

set-up packet disables the Validate Buffer and Clear Buffer commands for the control IN

and OUT endpoints. The microprocessor must re-enable these commands by sending an

acknowledge set-up command, see Section 12.3.6.

Code (Hex): F4 — acknowledge set up

Transaction — none (code only)

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15.3 General commands

15.3.1 Read endpoint error code (R: A0h to AFh)

This command returns the status of the last transaction of the selected endpoint, as

stored in the DcErrorCode register. Each new transaction overwrites the previous status

information. The bit allocation of the DcErrorCode register is shown in Table 129.

Code (Hex): A0 to AF — read error code (control OUT, control IN, endpoints 1 to 14)

Transaction — read 1 byte (code or data)

Table 129. DcErrorCode register: bit allocation

Bit

7

6

5

4

3

2

1

0

RTOK

0

Symbol

Reset

Access

UNREAD

DATA01

reserved

ERROR[3:0]

0

-

0

R

Table 130. DcErrorCode register: bit description

Bit

Symbol

Description

7

UNREAD

Logic 1 indicates that a new event occurred before the previous status is

read.

6

DATA01

This bit indicates the PID type of the last successfully received or

transmitted packet (0 = DATA0 PID; 1 = DATA1 PID).

5

-

reserved

4 to 1 ERROR[3:0] Error code. For error description, see Table 131.

RTOK Logic 1 indicates that data was successfully received or transmitted.

0

Table 131. Transaction error codes

Error code

(Binary)

Description

0000

0001

0010

0011

no error

PID encoding error; bits 7 to 4 are not the inverse of bits 3 to 0

PID unknown; encoding is valid, but PID does not exist

unexpected packet; packet is not of the expected type (token, data or

acknowledge) or is a set-up token to a non-control endpoint

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

token CRC error

data CRC error

time-out error

babble error

unexpected end-of-packet

sent or received NAK (Not Acknowledge)

sent stall; a token was received, but the endpoint was stalled

overﬂow; the received packet was larger than the available buffer space

sent empty packet (ISO only)

bit stufﬁng error

sync error

wrong (unexpected) toggle bit in DATA PID; data was ignored

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15.3.2 Unlock Device (B0h)

This command unlocks the Peripheral Controller from write-protection mode after a

‘resume’. In the ‘suspend’ state, all registers and buffer memory are write-protected to

prevent data corruption by external devices during a ‘resume’. Also, the register access to

read is possible only after the ‘unlock device’ command is executed.

After waking up from the ‘suspend’ state, ﬁrmware must unlock registers and buffer

memory by using this command, by writing the unlock code (AA37h) into the DcLock

register (8-bit bus: lower byte ﬁrst). The bit allocation of the DcLock register is given in

Table 132.

Code (Hex): B0 — unlock the device

Transaction — write 2 bytes (unlock code) (code or data)

Table 132. DcLock register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

UNLOCK[15:8] = AAh

1

W

7

0

W

6

1

W

5

0

W

4

1

W

3

0

W

2

1

W

1

0

W

0

Symbol

Reset

Access

UNLOCK[7:0] = 37h

0

1

0

1

W

Table 133. DcLock register: bit description

Bit Symbol Description

15 to 0 UNLOCK[15:0] Sending data AA37h unlocks internal registers and buffer memory to

write, following a resume.

15.3.3 DcScratch register (R/W: B3h/B2h)

This command accesses the 16-bit DcScratch register, which can be used by ﬁrmware to

save and restore information. For example, the device status before powering down in the

‘suspend’ state.

The register bit allocation is given in Table 134.

Code (Hex): B2/B3 — write or read DcScratch register

Transaction — write or read 2 bytes (code or data)

Table 134. DcScratch Information register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

reserved

SFIR[12:8]

-

0

R/W

4

0

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

7

6

5

Symbol

Reset

Access

SFIR[7:0]

0

R/W

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Table 135. DcScratch Information register: bit description

Bit

Symbol

-

Description

15 to 13

12 to 0

reserved; must be logic 0

scratch information register

SFIR[12:0]

15.3.4 DcFrameNumber register (R: B4h)

This command returns the frame number of the last successfully received SOF. It is

followed by reading one word from the DcFrameNumber register, containing the frame

number. The DcFrameNumber register is shown in Table 136.

Remark: After a bus reset, the value of the DcFrameNumber register is undeﬁned.

Code (Hex): B4 — read frame number

Transaction — read 1 byte or 2 bytes (code or data)

Table 136. DcFrameNumber register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Reset^[1]

Access

Bit

reserved

SOFR[9:8]

-

0

R

2

0

R

1

0

R

0

7

6

5

4

3

Symbol

Reset^[1]

Access

SOFR[7:0]

0

R

[1] Reset value undeﬁned after a bus reset.

Table 137. DcFrameNumber register: bit description

Bit

Symbol

-

Description

reserved

15 to 11

10 to 0

SOFR[9:0]

frame number

Table 138. Example of the DcFrameNumber register access

A0

Phase

Bus lines

D[15:8]

D[7:0]

Word#

Description

HIGH

command

-

ignored

-

command code (B4h)

frame number

LOW

data

D[15:0]

0

15.3.5 DcChipID (R: B5h)

This command reads the chip identiﬁcation code and hardware version number. The

ﬁrmware must check this information to determine supported functions and features. This

command accesses the DcChipID register, which is shown in Table 139.

Code (Hex): B5 — read chip ID

Transaction — read 2 bytes (code or data)

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Table 139. DcChipID register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

CHIPIDH[7:0]

0

R

7

0

R

6

1

R

5

1

R

4

0

R

3

1

R

2

1

R

1

0

R

0

Symbol

Reset

Access

CHIPIDL[7:0]

0

1

0

R

Table 140. DcChipID register: bit description

Bit

Symbol

Description

15 to 8

7 to 0

CHIPIDH[7:0] chip ID code (36h)

CHIPIDL[7:0] silicon version (30h, with 30 representing the BCD encoded version

number)

15.3.6 DcInterrupt register (R: C0h)

This command indicates the sources of interrupts as stored in the 4 bytes DcInterrupt

register. Each individual endpoint has its own interrupt bit. The bit allocation of the

DcInterrupt register is shown in Table 141. Bit BUSTATUS is used to verify the current bus

status in the interrupt service routine. Interrupts are enabled using the DcInterruptEnable

register, see Section 15.1.5.

While reading the DcInterrupt register, it is recommended that both 2 bytes words are

read completely.

Code (Hex): C0 — read DcInterrupt register

Transaction — read 4 bytes (code or data)

Table 141. DcInterrupt register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved

-

21

EP12

0

-

23

22

20

EP11

0

19

EP10

0

18

17

16

Symbol

Reset

Access

Bit

EP14

EP13

EP9

EP8

EP7

0

R

15

14

13

EP4

0

12

EP3

0

11

EP2

0

10

9

8

Symbol

Reset

Access

Bit

EP6

EP5

EP1

EP0IN

EP0OUT

0

R

7

6

5

4

3

2

1

0

Symbol

Reset

Access

BUSTATUS

SP_EOT

PSOF

0

SOF

0

EOT

0

SUSPND

RESUME

RESET

0

R

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Table 142. DcInterrupt register: bit description

Bit

Symbol

Description

31 to 24

-

reserved

23 to 10

EP14 to EP1 Logic 1 indicates the interrupt source(s): endpoints 14 to 1.

9

8

7

6

EP0IN

Logic 1 indicates the interrupt source: control IN endpoint.

Logic 1 indicates the interrupt source: control OUT endpoint.

Monitors the current USB bus status (0 = awake, 1 = suspend).

EP0OUT

BUSTATUS

SP_EOT

Logic 1 indicates that an EOT interrupt has occurred for a short

period.

5

PSOF

Logic 1 indicates that an interrupt is issued every 1 ms because of

the pseudo SOF; after three missed SOFs, the ‘suspend’ state is

entered.

4

3

SOF

EOT

Logic 1 indicates that an SOF condition was detected.

Logic 1 indicates that an internal EOT condition was generated by

the DMA Counter reaching zero.

2

SUSPND

Logic 1 indicates that an ‘awake’ to ‘suspend’ change of state was

detected on the USB bus.

1

0

RESUME

RESET

Logic 1 indicates that a ‘resume’ state was detected.

Logic 1 indicates that a bus reset condition was detected.

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16. Limiting values

Table 143. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter

Conditions

Min

−0.5

-

Max

+4.6

+6.0

100

Unit

V

V_CC

V_I

supply voltage

input voltage

V

I_lu

latch-up current

V_I< 0 V or V_I> V_CC

mA

V

[1]

V_esd

T_stg

electrostatic discharge voltage

storage temperature

I_LI< 1 µA

−2000

−60

+2000

+150

°C

[1] Equivalent to discharging a 100 pF capacitor through a 1.5 kΩ resistor (Human Body Model).

17. Recommended operating conditions

Table 144. Recommended operating conditions

DP represents OTG_DP1 and H_DP2, and DM represents OTG_DM1 and H_DM2.

Symbol Parameter

Conditions

Min

3.0

0

Typ

3.3

5.0

3.3

Max

Unit

V

V_CC

V_I

supply voltage

input voltage

3.6

5.5

3.6

[1]

3.3 V tolerant pins

5 V tolerant pins

V

0

V

on pin X1 when external

clock is used

3.0

V

V_IA(I/O)

V_O(od)

input voltage on analog I/O lines

open-drain output pull-up voltage

pins DP and DM

5 V tolerant pins

non 5 V tolerant pins

0

-

3.6

5.5

3.6

+85

V

0

V

0

V

T_amb

ambient temperature

−40

°C

[1] Input voltage on digital I/O lines.

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18. Static characteristics

Table 145. Static characteristics: supply pins

V_CC= 3.3 V to 3.6 V; GND = 0 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

Parameter

operating supply current for Peripheral Controller

the Host Controller suspended

Conditions

Min

Typ

Max

Unit

I_CC(HC)

-

33

-

mA

I_CC(DC)

operating supply current for Host Controller suspended

the Peripheral Controller

-

20

50

60

-

mA

µA

I_CC(HC+DC)operating supply current for

the host and the device

[1]

I_CC(susp)

suspend supply current

Host Controller and Peripheral

Controller are suspended

[1] The power consumption on the charge pump is not included.

Table 146. Static characteristics: digital pins

V_CC= 3.0 V to 3.6 V; GND = 0 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

Input levels

V_IL

Parameter

Conditions

Min

Typ

Max

Unit

LOW-level input voltage

HIGH-level input voltage

-

0.8

-

V

V_IH

2.0

Schmitt-trigger inputs

V_th(LH)

positive-going threshold voltage

1.4

0.9

0.4

-

1.9

1.5

0.7

V

V_th(HL)

negative-going threshold voltage

hysteresis voltage

V_hys

Output levels

V_OL

LOW-level output voltage

HIGH-level output voltage

I_OL= 4 mA

I_OL= 20 µA

I_OH= 4 mA

I_OH= 20 µA

-

0.4

0.1

-

V

-

[1]

[2]

V_OH

2.4

V

_CC− 0.1 V

-

Leakage current

I_LI

input leakage current

pin capacitance

−5

-

+5

5

µA

C_IN

pin to GND

-

pF

Open-drain outputs

I_OZ

off-state output current

−5

-

+5

µA

[1] Not applicable for open-drain outputs.

[2] These values are applicable to transistor inputs. The value will be different if internal pull-up or pull-down resistors are used.

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Table 147. Static characteristics: analog I/O pins (D+, D−)

V_CC= 3.0 V to 3.6 V; GND = 0 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.^[1]

Symbol

Input levels

V_DI

Parameter

Conditions

Min

Typ

Max

Unit

differential input sensitivity

|V_I(D+)− V_I(D−)

|

0.2

0.8

-

V

V_CM

differential common mode

voltage

includes V_DIrange

2.5

V_IL

LOW-level input voltage

HIGH-level input voltage

-

0.8

-

V

V_IH

2.0

Output levels

V_OL

V_OH

LOW-level output voltage

HIGH-level output voltage

R_L= 1.5 kΩ to +3.6 V

R_L= 15 kΩ to GND

-

0.3

3.6

V

2.8

Leakage current

I_LZ

off-state leakage current

−10

-

+10

10

µA

Capacitance

C_IN

transceiver capacitance

pull-down resistance on

pin to GND

-

pF

Resistance

R_pd(OTG)

enable internal

14.25

10

-

24.8

20

kΩ

pins OTG_DP1 and OTG_DM1 resistors

R_pd(H)

pull-down resistance on

pins H_DP2 and H_DM2

enable internal

resistors

R_pu(OTG)

pull-up resistance on

OTG_DP1

bus idle

900

1425

29

-

1575

3090

44

Ω

bus driven

steady-state drive

Ω

[2]

[3]

Z_DRV

driver output impedance

input impedance

Ω

Z_INP

10

-

MΩ

Termination

V_TERM

termination voltage

for upstream port pull

3.0

-

3.6

V

up (R_PU

)

[1] DP represents OTG_DP1 and H_DP2, and DM represents OTG_DM1 and H_DM2. D+ is the USB positive data line and D− is the USB

negative data line.

[2] Includes external resistors of 18 Ω ± 10 % on H_DP2 and H_DM2, and 27 Ω ± 10 % on OTG_DP1 and OTG_DM1.

[3] In suspend mode, the minimum voltage is 2.7 V.

Table 148. Static characteristics: charge pump

V_CC= 3.0 V to 3.6 V; GND = 0 V; T_amb= −40 °C to +85 °C; C_LOAD= 2 µF; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_BUS

regulated V_BUSvoltage

I_LOAD= 8 mA from

-

5

5.25

V

_BUS(OTG); see Figure 29

external capacitor of 27 nF;

_CC= 3.0 V to 3.6 V

I_LOAD

maximum load current

-

8

mA

V

external capacitor of 82 nF;

V_CC= 3.0 V to 3.3 V

14

20

external capacitor of 82 nF;

V_CC= 3.3 V to 3.6 V

C_LOAD

output capacitance

1

-

6.5

0.2

µF

V_BUS(LEAK)

V_BUS(OTG)leakage voltage

V_BUS(OTG)not driven

V

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Table 148. Static characteristics: charge pump …continued

V_CC= 3.0 V to 3.6 V; GND = 0 V; T_amb= −40 °C to +85 °C; C_LOAD= 2 µF; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

I_CC(cp)(susp)

suspend supply current for

charge pump

GlobalPowerDown bit of the

HcHardwareConﬁguration

register is logic 0

-

45

µA

GlobalPowerDown bit of the

HcHardwareConﬁguration

register is logic 1

-

15

µA

I_CC(cp)

operating supply current in

charge pump mode

ATX is idle

I_LOAD= 8 mA

I_LOAD= 0 mA

-

20

mA

µA

V

-

300

V_{th(VBUS_VLD)}

V_{th(SESS_END)}

V_BUSvalid threshold

4.4

-

V_BUSsession end threshold

0.2

-

0.8

V

V_{hys(SESS_END)}V_BUSsession end hysteresis

V_{th(ASESS_VLD)}V_BUSA valid threshold

V_{hys(ASESS_VLD)}V_BUSA valid hysteresis

V_{th(BSESS_VLD)}V_BUSB valid threshold

V_{hys(BSESS_VLD)}V_BUSB valid hysteresis

-

150

-

mV

V

0.8

2

-

200

-

mV

V

2

-

4

-

200

75

mV

%

E

efﬁciency when loaded

I_LOAD= 8 mA; V_IN= 3 V;

see Figure 28

-

I_VBUS(leak)

R_VBUS(PU)

R_VBUS(PD)

R_VBUS(IDLE)

leakage current from V_BUS

V_BUSpull-up resistance

V_BUSpull-down resistance

-

15

-

µA

Ω

pull to V_CCwhen enabled

pull to GND when enabled

281

656

40

-

Ω

V_BUSidle impedance for the

A-device

when ID = LOW and

DRV_VBUS = 0

-

100

kΩ

R_VBUS(ACTIVE)

V_BUSactive pull-down

impedance

when ID = HIGH and

DRV_VBUS =1

-

350

-

kΩ

001aaf829

100

E

efficiency

(%)

V

= 3.0 V

3.3 V

3.6 V

CC

80

60

40

20

0

5

10

15

20

25

I

(mA)

LOAD

82 nF charge pump capacitor.

Fig 28. Efﬁciency as a function of load current

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001aaf830

5.2

V

= 3.6 V

3.3 V

CC

V

BUS

(V)

3.0 V

5.0

4.8

4.6

0

5

10

15

20

25

I

(mA)

LOAD

82 nF charge pump capacitor.

Fig 29. Output voltage as a function of load current

ISP1362_5

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19. Dynamic characteristics

Table 149. Dynamic characteristics

V_CC= 3.0 V to 3.6 V; GND = 0 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol Parameter

Reset

Conditions

Min

Typ

Max

Unit

t_W(RESET)pulse width on input RESET crystal oscillator running

crystal oscillator stopped

10

-

ms

[1]

[2]

Crystal oscillator

f_xtal

crystal frequency

series resistance

load capacitance

-

12

-

MHz

Ω

R_S

100

-

C_LOAD

C_X1, C_X2= 22 pF

12

pF

External clock input

J

external clock jitter

-

500

55

3

ps

%

t_DUTY

t_CR

t_CF

clock duty cycle

rise time

45

-

50

-

ns

fall time

-

3

[1] Dependent on the crystal oscillator startup time.

[2] Tolerance of the clock frequency is ±50 ppm.

Table 150. Dynamic characteristics: analog I/O lines (D+, D−)

V_CC= 3.0 V to 3.6 V; GND = 0 V; T_amb= −40 °C to +85 °C; C_L= 50 pF; R_PU= 1.5 kΩ ± 5 % on DP to V_TERM; unless otherwise

speciﬁed.^[1]

Symbol Parameter

Driver characteristics

Conditions

Min

Typ

Max

Unit

t_FR

rise time

C_L= 50 pF; 10 % to

4

-

20

ns

%

V

90 % of |V_OH− V_OL

C_L= 50 pF; 90 % to

10 % of |V_OH− V_OL

(t_FR/t_FF

|

t_FF

fall time

4

20

|

[2]

FRFM

V_CRS

differential rise time/fall time

matching

)

90

1.3

111.11

2.0

[2][3]

output signal crossover voltage

[1] DP represents OTG_DP1 and H_DP2, and DM represents OTG_DM1 and H_DM2. Test circuit.

[2] Excluding the ﬁrst transition from the idle state.

[3] Characterized only, not tested. Limits guaranteed by design.

Table 151. Dynamic characteristics: charge pump

V_CC= 3.0 V to 3.6 V; GND = 0 V; T_amb= −40 °C to +85 °C; C_LOAD= 2 µF; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Driver characteristics

t_START-UP

rise time to V_BUS= 4.4 V

clock period

I_LOAD= 8 mA; C_LOAD

10 µF

=

-

100

ms

t_{COMP_CLK}

1.5

-

3

µs

t_{VBUS(VALID_dly)}minimum time V_BUS(VALID)

error

100

200

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Table 151. Dynamic characteristics: charge pump …continued

V_CC= 3.0 V to 3.6 V; GND = 0 V; T_amb= −40 °C to +85 °C; C_LOAD= 2 µF; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

10

50

-

Typ

Max

30

-

Unit

ms

t_VBUS(PULSE)

V_BUSpulsing time

-

t_{VBUS(VALID_dly)}V_BUSpull-down time

ms

V_RIPPLE

output ripple with constant

load

I_LOAD= 8 mA

50

mV

19.1 Programmed I/O timing

• If you are accessing only the Host Controller, then the Host Controller programmed

I/O timing applies.

• If you are accessing only the Peripheral Controller, then the Peripheral Controller

programmed I/O timing applies.

• If you are accessing both the Host Controller and the Peripheral Controller, then the

Peripheral Controller programmed I/O timing applies.

19.1.1 Host Controller programmed I/O timing

Table 152. Dynamic characteristics: Host Controller programmed interface timing

V_CC= 3.0 V to 3.6 V; GND = 0 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol Parameter

t_ASaddress set-up time before CS

t_AHaddress hold time after WR

Conditions

Min

5

Typ

Max

Unit

ns

-

2

ns

Read timing

t_{SHSL_R}ﬁrst RD/WR after command (A0 = HIGH)

t_{SHSL_B}ﬁrst RD/WR after command (A0 = HIGH)

register access

buffer access

300

462

0

-

ns

-

t_SLRL

t_RHSH

t_RL

CS LOW to RD LOW

RD HIGH to CS HIGH

RD LOW pulse width

RD HIGH to next RD LOW

RD cycle

-

0

-

33

110

143

-

t_RHRL

T_RC

t_RHDZ

t_RLDV

-

RD data hold time

3

22

RD LOW to data valid

-

Write timing

t_WL

WR LOW pulse width

26

110

136

0

-

ns

t_WHWL

T_WC

WR HIGH to next WR LOW

WR cycle

t_SLWL

t_WHSH

t_WDSU

t_WDH

CS LOW to WR LOW

WR HIGH to CS HIGH

WR data set-up time

WR data hold time

0

3

4

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CS

t

SLWL

t

SHSL

t

SLRL

t

RLRH

t

WHSH

RHSH

A0

t

RHRL

T

RC

RD

t

RLDV

t

RHDZ

[

]

D 15:0

data

valid

data

valid

WHWL

data

valid

data

valid

t

AS

t

AH

t

T

WC

WL

WR

t

WDSU

WDH

data

valid

data

valid

data

valid

data

valid

data

valid

[

]

D 15:0

mgt969

Fig 30. Host Controller programmed interface timing

19.1.2 Peripheral Controller programmed I/O timing

Table 153. Dynamic characteristics: Peripheral Controller programmed interface timing

V_CC= 3.0 V to 3.6 V; GND = 0 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Read timing (see Figure 31)

t_RHAX

t_AVRL

t_SHDZ

address hold time after RD HIGH

0

-

ns

address set-up time before RD LOW

-

data outputs high-impedance time after CS

HIGH

3

t_RHSH

t_RLRH

t_RLDV

t_SHRL

chip deselect time after RD HIGH

RD pulse width

0

-

ns

25

-

data valid time after RD LOW

CS HIGH until next ISP1362 RD

22

-

120

180

t_SHRL+ t_RLRH+ t_RHSHread cycle time

-

Write timing (see Figure 32)

t_WHAX

t_AVWL

t_SHWL

address hold time after WR HIGH

1

-

ns

address set-up time before WR LOW

CS HIGH until next ISP1362 WR

0

120

180

22

[1]

t_SHWL+ t_WLWH+ t_WHSHwrite cycle time

t_WLWH

WR pulse width

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ISP1362

NXP Semiconductors

Single-chip USB OTG Controller

Table 153. Dynamic characteristics: Peripheral Controller programmed interface timing …continued

V_CC= 3.0 V to 3.6 V; GND = 0 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

t_WHSH

t_DVWH

Parameter

Conditions

Min

0

Typ

Max

Unit

ns

chip deselect time after WR HIGH

data set-up time before WR HIGH

data hold time after WR HIGH

-

5

ns

t_WHDZ

3

ns

[1] In the command to data phase, the minimum value of the write command to the read data or write data cycle time must be 205 ns.

t

RHAX

A0

t

AVRL

t

SHDZ

CS/DACK2⁽²⁾

(1)

t

SHRL

RLRH

RD

t

RHSH

t

RLDV

D[15:0]

004aaa105

(1) For t_SHRLboth CS and RD must be de-asserted.

(2) Programmable polarity: shown as active LOW.

Fig 31. Peripheral Controller programmed interface read timing (I/O and 8237 compatible DMA)

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t

WHAX

A0

t

AVWL

CS/DACK2⁽²⁾

t

WLWH

(1)

t

SHWL

t

WHSH

WR

t

DVWH

WHDZ

D[15:0]

004aaa106

(1) For t_SHWL, both CS and WR must be de-asserted.

(2) Programmable polarity: shown as active LOW.

Fig 32. Peripheral Controller programmed interface write timing (I/O and 8237 compatible DMA)

19.2 DMA timing

19.2.1 Host Controller single-cycle DMA timing

Table 154. Dynamic characteristics: Host Controller single-cycle DMA timing

V_CC= 3.0 V to 3.6 V; GND = 0 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Read/write timing

t_RL

RD pulse width

33

30

0

-

ns

t_RLDV

t_RHDZ

t_WSU

t_WHD

t_AHRH

t_ALRL

T_DC

read process data set-up time

read process data hold time

write process data set-up time

write process data hold time

DACK1 HIGH to DREQ1 HIGH

DACK1 LOW to DREQ1 LOW

DREQ1 cycle

-

5

-

0

-

72

-

21

-

[1]

t_SHAH

t_RHAL

t_DS

RD/WR HIGH to DACK1 HIGH

DREQ1 HIGH to DACK1 LOW

DREQ1 pulse spacing

0

-

0

-

146

-

[1] t_RHAL+ t_DS+ t_ALRL

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T

DC

DREQ1

DACK1

t

DS

t

ALRL

SHAH

t

RHAL

t

AHRH

t

RHDZ

RLDV

[

]

data

valid

D 15:0

(read)

[

D 15:0

data

valid

(write)

t

WSU

RD or WR

004aaa107

t

WHD

Fig 33. Host Controller single-cycle DMA timing

19.2.2 Host Controller burst mode DMA timing

Table 155. Dynamic characteristics: Host Controller burst mode DMA timing

V_CC= 3.0 V to 3.6 V; GND = 0 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

Read/write timing (for 4-cycle and 8-cycle burst mode)

t_RL

RD/WR LOW pulse width

RD/WR HIGH to next RD/WR LOW

RD/WR cycle

42

60

102

22

0

-

ns

t_RHRL

T_RC

-

t_SLRL

t_SHAH

t_RHAL

T_DC

RD/WR LOW to DREQ1 LOW

RD/WR HIGH to DACK1 HIGH

DREQ1 HIGH to DACK1 LOW

DREQ1 cycle

64

-

0

[1]

-

t_DS(read)DREQ1 pulse spacing (read)

4-cycle burst mode

8-cycle burst mode

4-cycle burst mode

8-cycle burst mode

105

150

72

t_DS(write)DREQ1 pulse spacing (write)

167

[1] t_SLAL+ (4 or 8)t_RC+ t_DS

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t

DS

DREQ1

t

RHSH

t

RHAL

t

SLRL

DACK1

t

SHAH

RHRL

RD or WR

004aaa108

T

RC

t

RLRH

Fig 34. Host Controller burst mode DMA timing

19.2.3 Peripheral Controller single-cycle DMA timing (8237 mode)

Table 156. Dynamic characteristics: Peripheral Controller single-cycle DMA timing (8237 mode)

V_CC= 3.0 V to 3.6 V; GND = 0 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

-

Typ

Max

40

-

Unit

ns

t_ASRP

DREQ2 off after DACK2 on

-

T_cy(DREQ2)cycle time signal DREQ2

180

ns

T

RC

t

ASRP

DREQ2

DACK2⁽¹⁾

004aaa111

(1) Programmable polarity: shown as active LOW.

Fig 35. Peripheral Controller single-cycle DMA timing (8237 mode)

19.2.4 Peripheral Controller single-cycle DMA read timing in DACK-only mode

Table 157. Dynamic characteristics: Peripheral Controller single-cycle DMA read timing in DACK-only mode

V_CC= 3.0 V to 3.6 V; GND = 0 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

t_ASRP

Parameter

Conditions

Min

Typ

Max

40

-

Unit

ns

DREQ off after DACK on

DACK pulse width

-

t_ASAP

25

ns

t_ASAP+ t_APRSDREQ on after DACK off

180

-

ns

t_ASDV

t_APDZ

data valid after DACK on

data hold after DACK off

-

22

3

ns

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t

APRS

ASRP

DREQ2

t

ASAP

DACK2⁽¹⁾

t

APDZ

ASDV

DATA

004aaa112

(1) Programmable polarity: shown as active LOW.

Fig 36. Peripheral Controller single-cycle DMA read timing in DACK-only mode

19.2.5 Peripheral Controller single-cycle DMA write timing in DACK-only mode

Table 158. Dynamic characteristics: Peripheral Controller single-cycle DMA write timing in DACK-only mode

V_CC= 3.0 V to 3.6 V; GND = 0 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

t_ASRP

Parameter

Conditions

Min

Typ

Max

40

-

Unit

ns

DREQ2 off after DACK2 on

DACK2 pulse width

-

t_ASAP

25

ns

t_ASAP+ t_APRSDREQ2 on after DACK2 off

180

-

ns

t_ASDV

t_APDZ

data valid after DACK2 on

data hold after DACK2 off

-

22

3

ns

t

ASAP

t

APRS

ASRP

DREQ2

t

ASDV

APDZ

(1)

DACK2

DATA

004aaa113

(1) Programmable polarity: shown as active LOW.

Fig 37. Peripheral Controller single-cycle DMA write timing in DACK-only mode

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19.2.6 Peripheral Controller burst mode DMA timing

Table 159. Dynamic characteristics: Peripheral Controller burst mode DMA timing

V_CC= 3.0 V to 3.6 V; GND = 0 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

t_RSIH

t_ILRP

Parameter

Conditions

Min

22

-

Typ

Max

Unit

ns

input RD/WR HIGH after DREQ on

DREQ off after input RD/WR LOW

DACK off after input RD/WR HIGH

-

ns

t_IHAP

0

60

-

ns

t_IHIL

DMA burst repeat interval (input

RD/WR HIGH to LOW)

t_RLor t_WLis 30 ns (min)

160

ns

t

ILRP

RSIH

DREQ2

(1)

t

IHAP

DACK2

t

IHIL

RD or WR

004aaa115

(1) Programmable polarity: shown as active LOW.

Fig 38. Peripheral Controller burst mode DMA timing

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20. Package outline

LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm

SOT314-2

y

X

A

48

33

Z

49

32

E

e

H

A

E

2

E

A

(A )

3

A

1

w M

p

θ

b

L

p

pin 1 index

L

64

17

detail X

1

16

Z

v

M

A

D

e

w M

b

p

D

B

H

v

M

B

D

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

L

v

w

y

Z

E

θ

1

2

3

p

D

E

p

D

max.

7^o

0^o

0.20 1.45

0.05 1.35

0.27 0.18 10.1 10.1

0.17 0.12 9.9 9.9

12.15 12.15

11.85 11.85

0.75

0.45

1.45 1.45

1.05 1.05

1.6

mm

0.25

0.5

1

0.2 0.12 0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

00-01-19

03-02-25

SOT314-2

136E10

MS-026

Fig 39. Package outline SOT314-2 (LQFP64)

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TFBGA64: plastic thin fine-pitch ball grid array package; 64 balls; body 6 x 6 x 0.8 mm

SOT543-1

D

A

B

ball A1

index area

A

2

A

E

A

1

detail X

C

e

1

y

e

1/2 e

v M

b

C

A

B

C

1

w M

K

J

H

G

F

e

2

E

D

C

B

A

1/2 e

ball A1

index area

1

2

3

4

5

6

7

8

9 10

X

0

2.5

scale

5 mm

DIMENSIONS (mm are the original dimensions)

A

UNIT

A

b

e

y

D

E

e

v

w

y

1

2

1

2

1

max.

0.25 0.85 0.35

0.15 0.75 0.25

6.1

5.9

6.1

5.9

mm

1.1

0.08

0.5

4.5

0.15 0.05

0.1

REFERENCES

JEDEC JEITA

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

00-11-22

02-04-09

SOT543-1

- - -

MO-195

- - -

Fig 40. Package outline SOT543-1 (TFBGA64)

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21. Soldering

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reﬂow

soldering description”.

21.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

21.2 Wave and reﬂow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reﬂow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature proﬁle. Leaded packages,

packages with solder balls, and leadless packages are all reﬂow solderable.

Key characteristics in both wave and reﬂow soldering are:

• Board speciﬁcations, including the board ﬁnish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus PbSn soldering

21.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and ﬂux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath speciﬁcations, including temperature and impurities

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21.4 Reﬂow soldering

Key characteristics in reﬂow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 41) than a PbSn process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classiﬁed in accordance with

Table 160 and 161

Table 160. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

235

≥ 350

220

< 2.5

≥ 2.5

220

Table 161. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reﬂow

soldering, see Figure 41.

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maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 41. Temperature proﬁles for large and small components

For further information on temperature proﬁles, refer to Application Note AN10365

“Surface mount reﬂow soldering description”.

22. Abbreviations

Table 162. Abbreviations

Acronym

ACK

ASIC

ATL

Description

Acknowledge

Application-Speciﬁc Integrated Circuit

Asynchronous Transfer List

Analog USB Transceiver

Complementary Metal-Oxide Semiconductor

Cyclic Redundancy Check

Direct Memory Access

Digital Still Camera

ATX

CMOS

CRC

DMA

DSC

ED

Endpoint Descriptor

EHCI

EMI

Enhanced Host Controller Interface

ElectroMagnetic Interference

End-Of-Frame

EOF

EOP

EOT

ESR

GPS

HC

End-Of-Packet

End-Of-Transfer

Equivalent Series Resistance

Global Positioning System

Host Controller

HCCA

HCD

Host Controller Communication Area

Host Controller Driver

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Table 162. Abbreviations …continued

Acronym

Description

HNP

INTL

IS

Host Negotiation Protocol

Interrupt Transfer List

Implementation-Speciﬁc

Isochronous

ISO

ISR

Interrupt Service Routine

Isochronous Transfer List

Low-Speed

ISTL

LS

MOSFET

MSB

NAK

OHCI

OPR

OTG

PDA

PID

Metal-Oxide Semiconductor Field-Effect Transistor

Most Signiﬁcant Bit

Not Acknowledged

Open Host Controller Interface

Operational

On-The-Go

Personal Digital Assistant

Packet IDentiﬁer

PIO

Programmed Input/Output

Phase-Locked Loop

PLL

PMOS

POR

PORP

POST

PTD

RISC

SIE

Positive Metal-Oxide Semiconductor

Power-On Reset

Power-On Reset Pulse

Power-On Self Test

Philips Transfer Descriptor

Reduced Instruction Set Computing

Serial Interface Engine

Start-Of-Frame

SOF

SRP

TD

Session Request Protocol

Transfer Descriptor

USB

USBD

Universal Serial Bus

Universal Serial Bus Device

23. References

[1] On-The-Go Supplement to the USB 2.0 Speciﬁcation Rev. 1.0a

[2] Universal Serial Bus Speciﬁcation Rev. 2.0

[3] ISP136x Embedded Programming Guide (UM10008)

[4] Open Host Controller Interface Speciﬁcation for USB Release 1.0a

[5] Interrupt Control application note

ISP1362_5

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24. Revision history

Table 163. Revision history

Document ID

ISP1362_5

Release date

Data sheet status

Change notice

Supersedes

20070508

Product data sheet

-

ISP1362-04

Modiﬁcations:

• The format of this data sheet has been redesigned to comply with the new presentation and

information standard of NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

• Section 2 “Features”: updated.

• Table 2 “Pin description”: removed table note “All I/O pads are 5 V tolerant”.

• Table 29 “OtgInterruptEnable register: bit description”: updated description for all the bits.

• Section 14 “Host Controller registers”: updated the ﬁrst paragraph.

• Table 36 “HcRevision register: bit description”: updated description for bits 7 to 0.

• Table 38 “HcControl register: bit description”: updated description for bits 7 to 6.

• Section 14.1.4 “HcInterruptStatus register (R/W: 03h/83h)”: updated the ﬁrst paragraph.

• Table 42 “HcInterruptStatus register: bit description”: updated description for bits 6 and 0.

• Table 46 “HcInterruptDisable register: bit description”: updated description for bit 31.

• Table 52 “HcFmNumber register: bit description”: updated description for bits 15 to 0.

• Section 14.2.4 “HcLSThreshold register (R/W: 11h/91h)”: updated the ﬁrst paragraph.

• Table 54 “HcLSThreshold register: bit description”: updated description for bits 10 to 0.

• Section 14.3 “HC root hub registers”: updated the last paragraph.

• Table 56 “HcRhDescriptorA register: bit description”: updated description for bits 1 to 0.

• Section 14.3.2 “HcRhDescriptorB register (R/W: 13h/93h)”: updated the ﬁrst paragraph.

• Section 14.3.4 “HcRhPortStatus[1:2] register (R/W [1]: 15h/95h; [2]: 16h/96h)”: updated the ﬁrst

paragraph.

• Table 64 “HcHardwareConﬁguration register: bit description”: updated description for bits 8, 6 and

5.

• Section 14.4.4 “HcmPInterrupt register (R/W: 24h/A4h)”: removed the second paragraph.

• Table 75 “HcSoftwareReset register: bit description”: updated the description column.

• Section 14.9.8 “HcATLPTDDoneThresholdCount register (R/W: 51h/D1h)”: updated the ﬁrst

paragraph.

• Table 105 “HcATLPTDDoneThresholdCount register: bit description”: updated description for bits

4 to 0.

• Section 14.9.9 “HcATLPTDDoneThresholdTimeOut register (R/W: 52h/D2h)”: updated the ﬁrst

paragraph.

• Table 110 “DcEndpointConﬁguration register: bit description”: updated description for bits 7 and 5.

• Table 114 “DcMode register: bit description”: updated description for bit 2.

• Section 15.1.5 “DcInterruptEnable register (R/W: C3h/C2h)”: updated the ﬁrst paragraph.

• Table 118 “DcInterruptEnable register: bit description”: updated the description column.

• Section 15.1.7 “DcDMACounter register (R/W: F3h/F2h)”: updated the second paragraph.

• Table 122 “DcDMACounter register: bit description”: added description for bits 15 to 0.

• Table 126 “DcEndpointStatus register: bit description”: updated description for bit 3.

• Table 128 “DcEndpointStatusImage register: bit description”: updated description for bit 3.

• Table 144 “Recommended operating conditions”: added V_I(clk)and removed 1.8 V tolerant under V_I.

• Section 19.1 “Programmed I/O timing” and Section 19.2 “DMA timing”: added conditions to tables.

• Table 152 “Dynamic characteristics: Host Controller programmed interface timing”: updated

description for t_AH

.

ISP1362_5

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Single-chip USB OTG Controller

Table 163. Revision history …continued

Document ID

Release date

Data sheet status

Change notice

Supersedes

ISP1362-04

(9397 750 13957)

20041224

Product data

-

ISP1362-03

(9397 750 12337)

20040106

20030219

20021120

Product data

Preliminary data

ISP1362-02

ISP1362-01

-

ISP1362-02

(9397 750 10767)

ISP1362-01

(9397 750 10087)

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25. Legal information

25.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

result in personal injury, death or severe property or environmental damage.

25.2 Deﬁnitions

NXP Semiconductors accepts no liability for inclusion and/or use of NXP

Semiconductors products in such equipment or applications and therefore

such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

25.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

25.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of a NXP Semiconductors product can reasonably be expected to

GoodLink — is a trademark of NXP B.V.

SoftConnect — is a trademark of NXP B.V.

26. Contact information

For additional information, please visit: http://www.nxp.com

For sales ofﬁce addresses, send an email to: salesaddresses@nxp.com

ISP1362_5

Product data sheet

Rev. 05 — 8 May 2007

146 of 152

ISP1362

NXP Semiconductors

Single-chip USB OTG Controller

27. Tables

Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .4

Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .7

Table 3. Bus access priority table for the ISP1362 . . . .13

Table 4. Buffer memory areas and their applications . .14

Table 5. I/O port addressing . . . . . . . . . . . . . . . . . . . . .20

Table 6. Registers used in addressing modes . . . . . . . .25

Table 7. Recommended capacitor values . . . . . . . . . . .38

Table 8. Port 1 function . . . . . . . . . . . . . . . . . . . . . . . . .40

Table 9. Generic PTD structure: bit allocation . . . . . . . .42

Table 10. Special ﬁelds for ATL, interrupt and ISO . . . . .42

Table 11. Generic PTD structure: bit description . . . . . . .43

Table 12. ATL buffer area . . . . . . . . . . . . . . . . . . . . . . . .45

Table 13. Interrupt polling . . . . . . . . . . . . . . . . . . . . . . . .46

Table 14. Endpoint access and programmability . . . . . . .52

Table 15. Programmable buffer memory size . . . . . . . . .53

Table 16. Memory conﬁguration example . . . . . . . . . . . .53

Table 17. Endpoint selection for the DMA transfer . . . . .55

Table 18. 8237 compatible mode: pin functions . . . . . . .55

Table 19. Summary of EOT conditions for a bulk

Table 47. HcFmInterval register: bit allocation . . . . . . . . 77

Table 48. HcFmInterval register: bit description . . . . . . . 77

Table 49. HcFmRemaining register: bit allocation . . . . . 78

Table 50. HcFmRemaining register: bit description . . . . 78

Table 51. HcFmNumber register: bit allocation . . . . . . . . 79

Table 52. HcFmNumber register: bit description . . . . . . 79

Table 53. HcLSThreshold register: bit allocation . . . . . . 79

Table 54. HcLSThreshold register: bit description . . . . . 80

Table 55. HcRhDescriptorA register: bit description . . . . 81

Table 56. HcRhDescriptorA register: bit description . . . . 81

Table 57. HcRhDescriptorB register: bit allocation . . . . . 82

Table 58. HcRhDescriptorB register: bit description . . . . 83

Table 59. HcRhStatus register: bit allocation . . . . . . . . . 83

Table 60. HcRhStatus register: bit description . . . . . . . . 84

Table 61. HcRhPortStatus[1:2] register: bit allocation . . 84

Table 62. HcRhPortStatus[1:2] register: bit description . 85

Table 63. HcHardwareConﬁguration register:

bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 64. HcHardwareConﬁguration register:

endpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 20. Recommended EOT usage for isochronous

endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

Table 65. HcDMAConﬁguration register: bit allocation . . 90

Table 66. HcDMAConﬁguration register: bit description . 90

Table 67. Buffer_Type_Select[2:0]: bit description . . . . . 91

Table 68. HcTransferCounter register: bit description . . . 91

Table 69. HcmPInterrupt register: bit allocation . . . . . . . 92

Table 70. HcmPInterrupt register: bit description . . . . . . 92

Table 71. HcmPInterruptEnable register: bit allocation . . 93

Table 72. HcmPInterruptEnable register: bit description 94

Table 73. HcChipID register: bit description . . . . . . . . . . 94

Table 74. HcScratch register: bit description . . . . . . . . . 95

Table 75. HcSoftwareReset register: bit description . . . . 95

Table 76. HcBufferStatus register: bit allocation . . . . . . . 95

Table 77. HcBufferStatus register: bit description . . . . . . 95

Table 78. HcDirectAddressLength register: bit allocation 96

Table 79. HcDirectAddressLength register:

Table 21. OTG Control registers overview . . . . . . . . . . . .60

Table 22. OtgControl register: bit allocation . . . . . . . . . .60

Table 23. OtgControl register: bit description . . . . . . . . .61

Table 24. OtgStatus register: bit allocation . . . . . . . . . . .62

Table 25. OtgStatus register: bit description . . . . . . . . . .62

Table 26. OtgInterrupt register: bit allocation . . . . . . . . .63

Table 27. OtgInterrupt register: bit description . . . . . . . .64

Table 28. OtgInterruptEnable register: bit allocation . . . .65

Table 29. OtgInterruptEnable register: bit description . . .65

Table 30. OtgTimer register: bit allocation . . . . . . . . . . . .66

Table 31. OtgTimer register: bit description . . . . . . . . . .67

Table 32. OtgAltTimer register: bit allocation . . . . . . . . .67

Table 33. OtgAltTimer register: bit description . . . . . . . .68

Table 34. Host Controller registers overview . . . . . . . . . .68

Table 35. HcRevision register: bit allocation . . . . . . . . . .70

Table 36. HcRevision register: bit description . . . . . . . . .70

Table 37. HcControl register: bit allocation . . . . . . . . . . .70

Table 38. HcControl register: bit description . . . . . . . . . .71

Table 39. HcCommandStatus register: bit allocation . . .72

Table 40. HcCommandStatus register: bit description . .73

Table 41. HcInterruptStatus register: bit allocation . . . . .73

Table 42. HcInterruptStatus register: bit description . . . .74

Table 43. HcInterruptEnable register: bit allocation . . . . .74

Table 44. HcInterruptEnable register: bit description . . .75

Table 45. HcInterruptDisable register: bit allocation . . . .76

Table 46. HcInterruptDisable register: bit description . . .76

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 97

Table 80. HcDirectAddressData register: bit description 97

Table 81. HcISTLBufferSize register: bit description . . . 97

Table 82. HcISTL0BufferPort register: bit description . . . 98

Table 83. HcISTL1BufferPort register: bit description . . . 98

Table 84. HcISTLToggleRate register: bit allocation . . . . 98

Table 85. HcISTLToggleRate register: bit description . . . 99

Table 86. HcINTLBufferSize register: bit description . . . 99

Table 87. HcINTLBufferPort register: bit description . . . . 99

Table 88. HcINTLBlkSize register: bit allocation . . . . . . 100

Table 89. HcINTLBlkSize register: bit description . . . . . 100

Table 90. HcINTLPTDDoneMap register:

bit description . . . . . . . . . . . . . . . . . . . . . . . . 100

continued >>

ISP1362_5

Product data sheet

Rev. 05 — 8 May 2007

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ISP1362

NXP Semiconductors

Single-chip USB OTG Controller

Table 91. HcINTLPTDSkipMap register: bit description 101

Table 92. HcINTLLastPTD register: bit description . . . .101

Table 93. HcINTLCurrentActivePTD register:

bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . .101

Table 94. HcINTLCurrentActivePTD register:

bit description . . . . . . . . . . . . . . . . . . . . . . . .102

Table 95. HcATLBufferSize register: bit description . . .102

Table 96. HcATLBufferPort register: bit description . . . .102

Table 97. HcATLBlkSize register: bit allocation . . . . . . .103

Table 98. HcATLBlkSize register: bit description . . . . . .103

Table 99. HcATLPTDDoneMap register: bit description 103

Table 100.HcATLPTDSkipMap register: bit description .104

Table 101.HcATLLastPTD register: bit description . . . . .104

Table 102.HcATLCurrentActivePTD register:

Table 128.DcEndpointStatusImage register:

bit description . . . . . . . . . . . . . . . . . . . . . . . . 118

Table 129.DcErrorCode register: bit allocation . . . . . . . 119

Table 130.DcErrorCode register: bit description . . . . . . 119

Table 131.Transaction error codes . . . . . . . . . . . . . . . . . 119

Table 132.DcLock register: bit allocation . . . . . . . . . . . . 120

Table 133.DcLock register: bit description . . . . . . . . . . . 120

Table 134.DcScratch Information register: bit allocation 120

Table 135.DcScratch Information register:

bit description . . . . . . . . . . . . . . . . . . . . . . . . 121

Table 136.DcFrameNumber register: bit allocation . . . . 121

Table 137.DcFrameNumber register: bit description . . . 121

Table 138.Example of the DcFrameNumber

register access . . . . . . . . . . . . . . . . . . . . . . . 121

Table 139.DcChipID register: bit allocation . . . . . . . . . . 122

Table 140.DcChipID register: bit description . . . . . . . . . 122

Table 141.DcInterrupt register: bit allocation . . . . . . . . . 122

Table 142.DcInterrupt register: bit description . . . . . . . . 123

Table 143.Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 124

Table 144.Recommended operating conditions . . . . . . . 124

Table 145.Static characteristics: supply pins . . . . . . . . . 125

Table 146.Static characteristics: digital pins . . . . . . . . . 125

Table 147.Static characteristics: analog I/O pins

(D+, D−) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Table 148.Static characteristics: charge pump . . . . . . . 126

Table 149.Dynamic characteristics . . . . . . . . . . . . . . . . 129

Table 150.Dynamic characteristics: analog I/O

lines (D+, D−) . . . . . . . . . . . . . . . . . . . . . . . . 129

Table 151.Dynamic characteristics: charge pump . . . . . 129

Table 152.Dynamic characteristics: Host Controller

programmed interface timing . . . . . . . . . . . . . 130

Table 153.Dynamic characteristics: Peripheral

Controller programmed interface timing . . . . 131

Table 154.Dynamic characteristics: Host Controller

single-cycle DMA timing . . . . . . . . . . . . . . . . 133

Table 155.Dynamic characteristics: Host Controller burst

mode DMA timing . . . . . . . . . . . . . . . . . . . . . 134

Table 156.Dynamic characteristics: Peripheral Controller

single-cycle DMA timing (8237 mode) . . . . . 135

Table 157.Dynamic characteristics: Peripheral

bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . .104

Table 103.HcATLCurrentActivePTD register:

bit description . . . . . . . . . . . . . . . . . . . . . . . .104

Table 104.HcATLPTDDoneThresholdCount register:

bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . .105

Table 105.HcATLPTDDoneThresholdCount register:

bit description . . . . . . . . . . . . . . . . . . . . . . . .105

Table 106.HcATLPTDDoneThresholdTimeOut register:

bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . .105

Table 107.HcATLPTDDoneThresholdTimeOut register:

bit description . . . . . . . . . . . . . . . . . . . . . . . .106

Table 108.Peripheral Controller command and register

overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106

Table 109.DcEndpointConﬁguration register:

bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . .109

Table 110.DcEndpointConﬁguration register:

bit description . . . . . . . . . . . . . . . . . . . . . . . .109

Table 111.DcAddress register: bit allocation . . . . . . . . .109

Table 112.DcAddress register: bit description . . . . . . . .109

Table 113.DcMode register: bit allocation . . . . . . . . . . .110

Table 114.DcMode register: bit description . . . . . . . . . .110

Table 115.DcHardwareConﬁguration register:

bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . .110

Table 116.DcHardwareConﬁguration register:

bit description . . . . . . . . . . . . . . . . . . . . . . . .111

Table 117.DcInterruptEnable register: bit allocation . . . .112

Table 118.DcInterruptEnable register: bit description . .112

Table 119.DcDMAConﬁguration register: bit allocation .113

Table 120.DcDMAConﬁguration register: bit description 113

Table 121.DcDMACounter register: bit allocation . . . . . .114

Table 122.DcDMACounter register: bit description . . . .114

Table 123.Endpoint buffer memory organization . . . . . .115

Table 124.Example of endpoint buffer memory access .116

Table 125.DcEndpointStatus register: bit allocation . . . .116

Table 126.DcEndpointStatus register: bit description . . .116

Table 127.DcEndpointStatusImage register:

Controller single-cycle DMA read timing in

DACK-only mode . . . . . . . . . . . . . . . . . . . . . . 135

Table 158.Dynamic characteristics: Peripheral

Controller single-cycle DMA write timing in

DACK-only mode . . . . . . . . . . . . . . . . . . . . . . 136

Table 159.Dynamic characteristics: Peripheral

Controller burst mode DMA timing . . . . . . . . 137

Table 160.SnPb eutectic process (from J-STD-020C) . . 141

Table 161.Lead-free process (from J-STD-020C) . . . . . 141

Table 162.Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 142

Table 163.Revision history . . . . . . . . . . . . . . . . . . . . . . . 144

bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . .118

continued >>

ISP1362_5

Product data sheet

Rev. 05 — 8 May 2007

148 of 152

ISP1362

NXP Semiconductors

Single-chip USB OTG Controller

28. Figures

Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Fig 2. Pin conﬁguration LQFP64 . . . . . . . . . . . . . . . . . . .6

Fig 3. Pin conﬁguration TFBGA64 . . . . . . . . . . . . . . . . . .6

Fig 4. Recommended values of the ISP1362 buffer

memory allocation . . . . . . . . . . . . . . . . . . . . . . . .15

Fig 5. A sample snapshot of the ATL or INTL memory

management scheme . . . . . . . . . . . . . . . . . . . . .16

Fig 6. A sample snapshot of the ISTL memory

timing in DACK-only mode . . . . . . . . . . . . . . . . 136

Fig 37. Peripheral Controller single-cycle DMA

write timing in DACK-only mode . . . . . . . . . . . . 136

Fig 38. Peripheral Controller burst mode DMA timing. . 137

Fig 39. Package outline SOT314-2 (LQFP64). . . . . . . . 138

Fig 40. Package outline SOT543-1 (TFBGA64) . . . . . . 139

Fig 41. Temperature proﬁles for large and small

components. . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

management scheme . . . . . . . . . . . . . . . . . . . . .17

Fig 7. Peripheral Controller buffer memory

organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Fig 8. PIO interface between a microprocessor

and the ISP1362 . . . . . . . . . . . . . . . . . . . . . . . . .19

Fig 9. DMA interface between a microprocessor

and the ISP1362 . . . . . . . . . . . . . . . . . . . . . . . . .19

Fig 10. Microprocessor access to the Host Controller

or the Peripheral Controller . . . . . . . . . . . . . . . . .20

Fig 11. Access to internal control registers . . . . . . . . . . .21

Fig 12. PIO register access . . . . . . . . . . . . . . . . . . . . . . .21

Fig 13. PIO access for a 16-bit or 32-bit register . . . . . . .22

Fig 14. HC and OTG interrupt logic . . . . . . . . . . . . . . . . .27

Fig 15. Internal power-on reset timing . . . . . . . . . . . . . . .30

Fig 16. Clock with respect to the external

power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . .30

Fig 17. HNP sequence of events . . . . . . . . . . . . . . . . . . .33

Fig 18. Dual-role A-device state diagram. . . . . . . . . . . . .35

Fig 19. Dual-role B-device state diagram. . . . . . . . . . . . .36

Fig 20. External capacitors connection . . . . . . . . . . . . . .38

Fig 21. USB Host Controller states of the ISP1362 . . . . .39

Fig 22. PTD data stored in the buffer memory. . . . . . . . .41

Fig 23. Using internal overcurrent detection circuit . . . . .47

Fig 24. Using external overcurrent detection circuit. . . . .48

Fig 25. Using internal charge pump. . . . . . . . . . . . . . . . .48

Fig 26. Peripheral Controller in 8327 compatible

DMA mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Fig 27. Suspend and resume timing . . . . . . . . . . . . . . . .59

Fig 28. Efﬁciency as a function of load current . . . . . . .127

Fig 29. Output voltage as a function of load current . . .128

Fig 30. Host Controller programmed interface timing . .131

Fig 31. Peripheral Controller programmed interface

read timing (I/O and 8237 compatible DMA) . . .132

Fig 32. Peripheral Controller programmed interface

write timing (I/O and 8237 compatible DMA) . . .133

Fig 33. Host Controller single-cycle DMA timing . . . . . .134

Fig 34. Host Controller burst mode DMA timing . . . . . .135

Fig 35. Peripheral Controller single-cycle DMA timing

(8237 mode). . . . . . . . . . . . . . . . . . . . . . . . . . . .135

Fig 36. Peripheral Controller single-cycle DMA read

continued >>

ISP1362_5

Product data sheet

Rev. 05 — 8 May 2007

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NXP Semiconductors

Single-chip USB OTG Controller

29. Contents

1

General description . . . . . . . . . . . . . . . . . . . . . . 1

9

Power-On Reset (POR) . . . . . . . . . . . . . . . . . . 30

2

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Host/peripheral roles. . . . . . . . . . . . . . . . . . . . . 3

Ordering information. . . . . . . . . . . . . . . . . . . . . 4

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5

10

10.1

10.2

10.3

10.3.1

10.3.2

10.4

10.4.1

10.4.2

10.4.3

10.5

On-The-Go (OTG) Controller . . . . . . . . . . . . . 31

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Dual-role device . . . . . . . . . . . . . . . . . . . . . . . 31

Session Request Protocol (SRP). . . . . . . . . . 32

B-device initiating SRP. . . . . . . . . . . . . . . . . . 32

A-device responding to SRP . . . . . . . . . . . . . 32

Host Negotiation Protocol (HNP) . . . . . . . . . . 33

Sequence of HNP events. . . . . . . . . . . . . . . . 33

OTG state diagrams. . . . . . . . . . . . . . . . . . . . 34

HNP implementation and OTG state machine 36

Power saving in the idle state and during

3

3.1

4

5

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 6

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7

7

Functional description . . . . . . . . . . . . . . . . . . 12

On-The-Go (OTG) controller. . . . . . . . . . . . . . 12

Advanced NXP Slave Host Controller. . . . . . . 12

NXP Peripheral Controller. . . . . . . . . . . . . . . . 12

Phase-Locked Loop (PLL) clock multiplier . . . 12

USB and OTG transceivers . . . . . . . . . . . . . . 12

Overcurrent protection . . . . . . . . . . . . . . . . . . 12

Bus interface. . . . . . . . . . . . . . . . . . . . . . . . . . 12

Peripheral Controller and Host Controller

7.1

7.2

7.3

7.4

7.5

7.6

7.7

7.8

wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Current capacity of the OTG charge pump . . 37

10.6

11

USB Host Controller (HC) . . . . . . . . . . . . . . . . 38

USB states of the Host Controller . . . . . . . . . 38

USB trafﬁc generation . . . . . . . . . . . . . . . . . . 39

USB ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Philips Transfer Descriptor (PTD). . . . . . . . . . 40

Features of the control and bulk transfer

11.1

11.2

11.3

11.4

11.5

buffer memory. . . . . . . . . . . . . . . . . . . . . . . . . 12

GoodLink . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . 13

7.9

7.10

(aperiodic transfer) . . . . . . . . . . . . . . . . . . . . . 44

Sending a USB device request

11.5.1

8

8.1

8.1.1

8.1.2

Host and device bus interface . . . . . . . . . . . . 13

Memory organization . . . . . . . . . . . . . . . . . . . 14

Memory organization for the Host Controller . 14

Memory organization for the Peripheral

Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

PIO access mode . . . . . . . . . . . . . . . . . . . . . . 18

DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

PIO access to internal control registers . . . . . 20

PIO access to the buffer memory . . . . . . . . . . 23

PIO access to the buffer memory by using

(Get Descriptor) . . . . . . . . . . . . . . . . . . . . . . . 45

11.5.1.1 Step 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

11.5.1.2 Step 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

11.5.1.3 Step 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

11.5.1.4 Step 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

11.5.1.5 Step 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

8.2

8.3

8.4

8.5

11.6

11.7

11.8

11.8.1

11.8.2

11.8.3

Features of the interrupt transfer . . . . . . . . . . 46

Features of the Isochronous (ISO) transfer . . 46

Overcurrent protection circuit . . . . . . . . . . . . . 46

Using internal overcurrent detection circuit . . 46

Using external overcurrent detection circuit . . 47

Overcurrent detection circuit using internal

8.5.1

direct addressing . . . . . . . . . . . . . . . . . . . . . . 23

PIO access to the buffer memory by using

8.5.2

charge pump in OTG mode . . . . . . . . . . . . . . 48

Overcurrent detection circuit using external

5 V power source in OTG mode. . . . . . . . . . . 49

ISP1362 Host Controller power management 49

indirect addressing . . . . . . . . . . . . . . . . . . . . . 24

Setting up a DMA transfer . . . . . . . . . . . . . . . 25

Conﬁguring registers for a DMA transfer . . . . 25

Combining the two DMA channels . . . . . . . . . 26

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Interrupt in the Host Controller and the OTG

Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Interrupt in the Peripheral Controller. . . . . . . . 28

Combining INT1 and INT2 . . . . . . . . . . . . . . . 29

Behavior difference between level-triggered

11.8.4

11.9

8.6

8.6.1

8.6.2

8.7

12

12.1

12.1.1

12.1.2

12.2

USB Peripheral Controller . . . . . . . . . . . . . . . 49

Peripheral Controller data transfer operation . 50

IN data transfer. . . . . . . . . . . . . . . . . . . . . . . . 50

OUT data transfer. . . . . . . . . . . . . . . . . . . . . . 50

Device DMA transfer . . . . . . . . . . . . . . . . . . . 51

DMA for an IN endpoint (internal Peripheral

8.7.1

8.7.2

8.7.3

8.7.4

12.2.1

and edge-triggered interrupts . . . . . . . . . . . . . 29

Level-triggered interrupt . . . . . . . . . . . . . . . . . 29

Edge-triggered interrupt . . . . . . . . . . . . . . . . . 29

Controller to the external USB host) . . . . . . . 51

DMA for OUT endpoint (external USB host

to internal Peripheral Controller) . . . . . . . . . . 51

8.7.4.1

8.7.4.2

12.2.2

continued >>

ISP1362_5

Product data sheet

Rev. 05 — 8 May 2007

150 of 152

ISP1362

NXP Semiconductors

Single-chip USB OTG Controller

12.3

12.3.1

Endpoint description. . . . . . . . . . . . . . . . . . . . 52

14.4.5

14.5

14.5.1

14.5.2

14.5.3

14.6

HcmPInterruptEnable register (R/W: 25h/A5h) 93

HC miscellaneous registers . . . . . . . . . . . . . . 94

HcChipID register (R: 27h). . . . . . . . . . . . . . . 94

HcScratch register (R/W: 28h/A8h) . . . . . . . . 94

HcSoftwareReset register (W: A9h). . . . . . . . 95

HC buffer RAM control registers . . . . . . . . . . 95

HcBufferStatus register (R/W: 2Ch/ACh) . . . . 95

HcDirectAddressLength register

(R/W: 32h/B2h) . . . . . . . . . . . . . . . . . . . . . . . 96

HcDirectAddressData register (R/W: 45h/C5h) 97

Isochronous (ISO) transfer registers . . . . . . . 97

HcISTLBufferSize register (R/W: 30h/B0h) . . 97

HcISTL0BufferPort register (R/W: 40h/C0h) . 97

HcISTL1BufferPort register (R/W: 42h/C2h) . 98

HcISTLToggleRate register (R/W: 47h/C7h) . 98

Interrupt transfer registers . . . . . . . . . . . . . . . 99

HcINTLBufferSize register (R/W: 33h/B3h) . . 99

HcINTLBufferPort register (R/W: 43h/C3h) . . 99

HcINTLBlkSize register (R/W: 53h/D3h) . . . 100

HcINTLPTDDoneMap register (R: 17h) . . . . 100

HcINTLPTDSkipMap register (R/W: 18h/98h) 100

HcINTLLastPTD register (R/W: 19h/99h). . . 101

HcINTLCurrentActivePTD register (R: 1Ah). 101

Control and bulk transfer

Endpoints with programmable buffer memory

size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Endpoint access . . . . . . . . . . . . . . . . . . . . . . . 52

Endpoint buffer memory size . . . . . . . . . . . . . 52

Endpoint initialization . . . . . . . . . . . . . . . . . . . 53

Endpoint I/O mode access . . . . . . . . . . . . . . . 54

Special actions on control endpoints . . . . . . . 54

Peripheral Controller DMA transfer. . . . . . . . . 54

Selecting an endpoint for the DMA transfer . . 55

8237 compatible mode . . . . . . . . . . . . . . . . . . 55

End-Of-Transfer conditions . . . . . . . . . . . . . . . 57

12.3.2

12.3.3

12.3.4

12.3.5

12.3.6

12.4

12.4.1

12.4.2

12.4.3

14.6.1

14.6.2

14.6.3

14.7

14.7.1

14.7.2

14.7.3

14.7.4

14.8

14.8.1

14.8.2

14.8.3

14.8.4

14.8.5

14.8.6

14.8.7

14.9

12.4.3.1 Bulk endpoints . . . . . . . . . . . . . . . . . . . . . . . . 57

12.4.3.2 Isochronous endpoints . . . . . . . . . . . . . . . . . . 58

12.5

ISP1362 Peripheral Controller suspend and

resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Suspend conditions . . . . . . . . . . . . . . . . . . . . 58

Resume conditions . . . . . . . . . . . . . . . . . . . . . 59

12.5.1

12.5.2

13

OTG registers . . . . . . . . . . . . . . . . . . . . . . . . . . 60

OtgControl register (R/W: 62h/E2h) . . . . . . . . 60

OtgStatus register (R: 67h). . . . . . . . . . . . . . . 62

OtgInterrupt register (R/W: 68h/E8h) . . . . . . . 63

OtgInterruptEnable register (R/W: 69h/E9h). . 65

OtgTimer register (R/W: 6Ah/EAh) . . . . . . . . . 66

OtgAltTimer register (R/W: 6Ch/ECh). . . . . . . 67

13.1

13.2

13.3

13.4

13.5

13.6

(aperiodic transfer) registers . . . . . . . . . . . . 102

HcATLBufferSize register (R/W: 34h/B4h) . . 102

HcATLBufferPort register (R/W: 44h/C4h) . . 102

HcATLBlkSize register (R/W: 54h/D4h) . . . . 102

HcATLPTDDoneMap register (R: 1Bh) . . . . 103

HcATLPTDSkipMap register (R/W: 1Ch/9Ch) 103

HcATLLastPTD register (R/W: 1Dh/9Dh). . . 104

HcATLCurrentActivePTD register (R: 1Eh) . 104

HcATLPTDDoneThresholdCount register

14.9.1

14.9.2

14.9.3

14.9.4

14.9.5

14.9.6

14.9.7

14.9.8

14

14.1

Host Controller registers. . . . . . . . . . . . . . . . . 68

HC control and status registers . . . . . . . . . . . 70

HcRevision register (R: 00h). . . . . . . . . . . . . . 70

HcControl register (R/W: 01h/81h) . . . . . . . . . 70

HcCommandStatus register (R/W: 02h/82h) . 72

HcInterruptStatus register (R/W: 03h/83h) . . . 73

HcInterruptEnable register (R/W: 04h/84h) . . 74

HcInterruptDisable register (R/W: 05h/85h) . . 75

HC frame counter registers. . . . . . . . . . . . . . . 76

HcFmInterval register (R/W: 0Dh/8Dh). . . . . . 76

HcFmRemaining register (R/W: 0Eh/8Eh) . . . 77

HcFmNumber register (R/W: 0Fh/8Fh). . . . . . 78

HcLSThreshold register (R/W: 11h/91h). . . . . 79

HC root hub registers . . . . . . . . . . . . . . . . . . . 80

HcRhDescriptorA register (R/W: 12h/92h) . . . 80

HcRhDescriptorB register (R/W: 13h/93h) . . . 82

HcRhStatus register (R/W: 14h/94h) . . . . . . . 83

HcRhPortStatus[1:2] register (R/W [1]:

14.1.1

14.1.2

14.1.3

14.1.4

14.1.5

14.1.6

14.2

14.2.1

14.2.2

14.2.3

14.2.4

14.3

(R/W: 51h/D1h) . . . . . . . . . . . . . . . . . . . . . . 105

HcATLPTDDoneThresholdTimeOut register

(R/W: 52h/D2h) . . . . . . . . . . . . . . . . . . . . . . 105

14.9.9

15

15.1

15.1.1

Peripheral Controller registers. . . . . . . . . . . 106

Initialization commands . . . . . . . . . . . . . . . . 108

DcEndpointConﬁguration register (R/W:

30h to 3Fh/20h to 2Fh). . . . . . . . . . . . . . . . . 108

DcAddress register (R/W: B7h/B6h) . . . . . . 109

DcMode register (R/W: B9h/B8h). . . . . . . . . 109

DcHardwareConﬁguration register (R/W:

14.3.1

14.3.2

14.3.3

14.3.4

15.1.2

15.1.3

15.1.4

BBh/BAh) . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

DcInterruptEnable register (R/W: C3h/C2h). 111

DcDMAConﬁguration (R/W: F1h/F0h) . . . . . 113

DcDMACounter register (R/W: F3h/F2h) . . . 114

Reset device (F6h). . . . . . . . . . . . . . . . . . . . 114

Data ﬂow commands . . . . . . . . . . . . . . . . . . 115

15h/95h; [2]: 16h/96h). . . . . . . . . . . . . . . . . . . 84

HC DMA and interrupt control registers . . . . . 88

HcHardwareConﬁguration register (R/W:

20h/A0h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

HcDMAConﬁguration register (R/W: 21h/A1h) 90

HcTransferCounter register (R/W: 22h/A2h). . 91

HcmPInterrupt register (R/W: 24h/A4h) . . . . . 91

15.1.5

15.1.6

15.1.7

15.1.8

15.2

14.4

14.4.1

14.4.2

14.4.3

14.4.4

continued >>

ISP1362_5

Product data sheet

Rev. 05 — 8 May 2007

151 of 152

ISP1362

NXP Semiconductors

Single-chip USB OTG Controller

15.2.1

Write or read endpoint buffer (R/W:

26

27

28

29

Contact information . . . . . . . . . . . . . . . . . . . 146

Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

10h,12h to 1Fh/01h to 0Fh) . . . . . . . . . . . . . 115

Read endpoint status (R: 50h to 5Fh). . . . . . 116

Stall endpoint or unstall endpoint

(40h to 4Fh/80h to 8Fh) . . . . . . . . . . . . . . . . 117

Validate endpoint buffer (61h to 6Fh) . . . . . . 117

Clear endpoint buffer (70h, 72h to 7Fh) . . . . 117

DcEndpointStatusImage register

15.2.2

15.2.3

15.2.4

15.2.5

15.2.6

(D0h to DFh). . . . . . . . . . . . . . . . . . . . . . . . . 118

Acknowledge set up (F4h) . . . . . . . . . . . . . . 118

General commands . . . . . . . . . . . . . . . . . . . 119

Read endpoint error code (R: A0h to AFh). . 119

Unlock Device (B0h) . . . . . . . . . . . . . . . . . . . 120

DcScratch register (R/W: B3h/B2h) . . . . . . . 120

DcFrameNumber register (R: B4h). . . . . . . . 121

DcChipID (R: B5h) . . . . . . . . . . . . . . . . . . . . 121

DcInterrupt register (R: C0h) . . . . . . . . . . . . 122

15.2.7

15.3

15.3.1

15.3.2

15.3.3

15.3.4

15.3.5

15.3.6

16

17

18

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . 124

Recommended operating conditions. . . . . . 124

Static characteristics. . . . . . . . . . . . . . . . . . . 125

19

19.1

Dynamic characteristics . . . . . . . . . . . . . . . . 129

Programmed I/O timing. . . . . . . . . . . . . . . . . 130

Host Controller programmed I/O timing . . . . 130

Peripheral Controller programmed I/O timing 131

DMA timing . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Host Controller single-cycle DMA timing . . . 133

Host Controller burst mode DMA timing . . . . 134

Peripheral Controller single-cycle DMA

19.1.1

19.1.2

19.2

19.2.1

19.2.2

19.2.3

timing (8237 mode). . . . . . . . . . . . . . . . . . . . 135

Peripheral Controller single-cycle DMA

read timing in DACK-only mode . . . . . . . . . . 135

Peripheral Controller single-cycle DMA

write timing in DACK-only mode . . . . . . . . . . 136

Peripheral Controller burst mode DMA

19.2.4

19.2.5

19.2.6

timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

20

Package outline . . . . . . . . . . . . . . . . . . . . . . . 138

21

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Introduction to soldering . . . . . . . . . . . . . . . . 140

Wave and reﬂow soldering . . . . . . . . . . . . . . 140

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 140

Reﬂow soldering . . . . . . . . . . . . . . . . . . . . . . 141

21.1

21.2

21.3

21.4

22

23

24

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . 142

References . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Revision history. . . . . . . . . . . . . . . . . . . . . . . 144

25

Legal information. . . . . . . . . . . . . . . . . . . . . . 146

Data sheet status . . . . . . . . . . . . . . . . . . . . . 146

Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . 146

25.1

25.2

25.3

25.4

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 8 May 2007

Document identifier: ISP1362_5


型号：	ISP1362BD,151
厂家：	NXP
描述：	USB Bus Controller, CMOS, PQFP64, 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件：	总152页 (文件大小：677K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISP1362BD,151 [NXP]

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