ISP1504ABS_技术文档

ISP1504A; ISP1504C

ULPI Hi-Speed Universal Serial Bus On-The-Go transceiver

Rev. 01 — 19 October 2006

Product data sheet

1. General description

The ISP1504 is a Universal Serial Bus (USB) On-The-Go (OTG) transceiver that is fully

compliant with Universal Serial Bus Speciﬁcation Rev. 2.0, On-The-Go Supplement to the

USB 2.0 Speciﬁcation Rev. 1.2 and UTMI+ Low Pin Interface (ULPI) Speciﬁcation

Rev. 1.1.

The ISP1504 can transmit and receive USB data at high-speed (480 Mbit/s), full-speed

(12 Mbit/s) and low-speed (1.5 Mbit/s), and provides a pin-optimized, physical layer

front-end attachment to USB host, peripheral and OTG devices.

It is ideal for use in portable electronic devices, such as mobile phones, digital still

cameras, digital video cameras, Personal Digital Assistants (PDAs) and digital audio

players. It allows USB Application-Speciﬁc Integrated Circuits (ASICs), Programmable

Logic Devices (PLDs) and any system chip set to interface with the physical layer of the

USB through a 12-pin interface.

The ISP1504 can interface to the link with digital I/O voltages in the range of

1.65 V to 3.6 V.

The ISP1504 is available in HVQFN32 package.

2. Features

I Fully complies with:

N Universal Serial Bus Speciﬁcation Rev. 2.0

N On-The-Go Supplement to the USB 2.0 Speciﬁcation Rev. 1.2

N UTMI+ Low Pin Interface (ULPI) Speciﬁcation Rev. 1.1

I Interfaces to host, peripheral and OTG device cores; optimized for portable devices or

system ASICs with built-in USB OTG device core

I Complete Hi-Speed USB physical front-end solution that supports high-speed

(480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s)

N Integrated 45 Ω ± 10 % high-speed termination resistors, 1.5 kΩ ± 5 % full-speed

device pull-up resistor, and 15 kΩ ± 5 % host termination resistors

N Integrated parallel-to-serial and serial-to-parallel converters to transmit and receive

N USB clock and data recovery to receive USB data at ±500 ppm

N Insertion of stuff bits during transmit and discarding of stuff bits during receive

N Non-Return-to-Zero Inverted (NRZI) encoding and decoding

N Supports bus reset, suspend, resume and high-speed detection handshake (chirp)

I Complete USB OTG physical front-end that supports Host Negotiation Protocol (HNP)

and Session Request Protocol (SRP)

ISP1504A; ISP1504C

NXP Semiconductors

ULPI HS USB OTG transceiver

N Integrated 5 V charge pump; also supports external charge pump or 5 V V_BUS

switch

N Complete control over bus resistors

N Data line and V_BUSpulsing session request methods

N Integrated V_BUSvoltage comparators

N Integrated cable (ID) detector

I Highly optimized ULPI-compliant interface

N 60 MHz, 8-bit interface between the core and the transceiver

N Supports both 60 MHz input clock and 60 MHz output clock conﬁgurations

N Integrated Phase-Locked Loop (PLL) with auto-conﬁguring support for 60 MHz

input clock, or one crystal or clock frequency: 19.2 MHz (ISP1504ABS) and

26 MHz (ISP1504CBS)

N Fully programmable ULPI-compliant register set

N Internal Power-On Reset (POR) circuit

I Flexible system integration and very low current consumption, optimized for portable

devices

N Power-supply input range is 3.0 V to 3.6 V

N Internal voltage regulator supplies 3.3 V and 1.8 V

N Charge pump regulator outputs 4.75 V to 5.25 V at a current of up to 50 mA,

tunable using an external capacitor

N Supports external V_BUScharge pump or 5 V V_BUSswitch:

External V_BUSsource is controlled using the PSW_N pin; open-drain PSW_N

allows per-port or ganged power control

Digital FAULT input to monitor the external V_BUSsupply status

N Pin CHIP_SELECT_N 3-states the ULPI interface, allowing bus reuse for other

applications

N Supports wide range interfacing I/O voltage of 1.65 V to 3.6 V; separate I/O voltage

pins minimize crosstalk

N Typical operating current of 10 mA to 48 mA, depending on the USB speed and

bus utilization; not including the charge pump

N Typical suspend current of 35 µA

I Full industrial grade operating temperature range from −40 °C to +85 °C

I 4 kV ElectroStatic Discharge (ESD) protection at pins DP, DM, ID, V_BUSand GND

I Available in a small HVQFN32 (5 mm × 5 mm) Restriction of Hazardous Substances

(RoHS) compliant, halogen-free and lead-free package

3. Applications

I Digital still camera

I Digital TV

I Digital Video Disc (DVD) recorder

I External storage device, for example:

N Zip drive

N Magneto-Optical (MO) drive

N Optical drive: CD-ROM, CD-RW, DVD

I Mobile phone

ISP1504A_ISP1504C_1

Product data sheet

Rev. 01 — 19 October 2006

2 of 84

ISP1504A; ISP1504C

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ULPI HS USB OTG transceiver

I MP3 player

I PDA

I Printer

I Scanner

I Set-Top Box (STB)

I Video camera

4. Ordering information

Table 1.

Part

Ordering information

Package

Type number Marking Crystal or Name

Description

Version

clock

frequency

ISP1504ABS 504A^[1]

ISP1504CBS 504C^[1]

19.2 MHz HVQFN32 plastic thermal enhanced very thin quad ﬂat package;

SOT617-1

no leads; 32 terminals; body 5 × 5 × 0.85 mm

26 MHz

HVQFN32 plastic thermal enhanced very thin quad ﬂat package;

no leads; 32 terminals; body 5 × 5 × 0.85 mm

[1] The package marking is the ﬁrst line of text on the IC package and can be used for IC identiﬁcation.

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ISP1504A; ISP1504C

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ULPI HS USB OTG transceiver

5. Block diagram

27

CLOCK

USB DATA

SERIALIZER

5

DP

HI-SPEED USB ATX

1, 23 to 26,

8

28, 31, 32

DATA

[7:0]

ULPI

INTERFACE

CONTROLLER

TERMINATION

4

USB DATA

DESERIALIZER

DM

RESISTORS

19

DIR

DRV V

BUS

20

21

USB

CABLE

STP

NXT

V

VALID

BUS

ON-THE-GO MODULE

EXTERNAL

REGISTER

MAP

DRV V

BUS

ID

7

EXTERNAL

29

17

ID

DETECTOR

CHIP_SELECT_N

RESET_N

V

POWER-ON

RESET

BUS

COMPARATORS

GLOBAL

RESET

13

V

BUS

SRP CHARGE

AND DISCHARGE

RESISTORS

PLL

GLOBAL

CLOCKS

15

16

XTAL1

XTAL2

5 V CHARGE

PUMP SUPPLY

10

9

CRYSTAL

OSCILLATOR

C_A

C_B

8

CPGND

ISP1504

2, 22, 30

interface voltage

V

CC(I/O)

6

internal power

FAULT

14

18

12

REG3V3

REG1V8

PSW_N

BAND GAP

REFERENCE

VOLTAGE

11

3

VOLTAGE

REGULATOR

V

REF

RREF

V

CC

004aaa478

Fig 1. Block diagram

ISP1504A_ISP1504C_1

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ISP1504A; ISP1504C

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ULPI HS USB OTG transceiver

6. Pinning information

6.1 Pinning

terminal 1

index area

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

DATA0

DATA6

DATA7

V

CC(I/O)

RREF

V

CC(I/O)

DM

DP

NXT

ISP1504

STP

FAULT

ID

DIR

REG1V8

RESET_N

CPGND

004aaa479

Transparent top view

Fig 2. Pin conﬁguration HVQFN32; top view

6.2 Pin description

Table 2.

Pin description

Symbol^[1][2]

Type^[3]

Description^[4]

DATA0

1

I/O

pin 0 of the bidirectional ULPI data bus

slew-rate controlled output (1 ns); plain input; programmable pull down

I/O supply rail

V_CC(I/O)

RREF

DM

2

3

4

5

6

P

AI/O

I

resistor reference

data minus (D−) pin of the USB cable

data plus (D+) pin of the USB cable

DP

FAULT

input pin for the external V_BUSdigital overcurrent or fault detector signal

plain input; 5 V tolerant

ID

7

I

identiﬁcation (ID) pin of the mini-USB cable

plain input; TTL level

CPGND

C_B

8

P

charge pump ground

9

AI/O

P

ﬂying capacitor pin connection for the charge pump

input supply voltage or battery source

active LOW external V_BUSpower switch or external charge pump enable

open-drain; 5 V tolerant

C_A

10

11

12

V_CC

PSW_N

OD

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ISP1504A; ISP1504C

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ULPI HS USB OTG transceiver

Table 2.

Symbol^[1][2]

V_BUS

Pin description …continued

Type^[3]

Description^[4]

13

AI/O

V_BUSpin of the USB cable

5 V tolerant

REG3V3

XTAL1

14

15

16

17

P

3.3 V regulator output

crystal oscillator or clock input

crystal oscillator output

AI

AO

I

XTAL2

RESET_N

active LOW, asynchronous reset input

plain input

REG1V8

DIR

18

19

P

1.8 V regulator output

O

ULPI direction signal

slew-rate controlled output (1 ns)

STP

NXT

20

21

I

ULPI stop signal

plain input; programmable pull up

O

ULPI next signal

slew-rate controlled output (1 ns)

V_CC(I/O)

DATA7

22

23

P

I/O supply rail

I/O

pin 7 of the bidirectional ULPI data bus

slew-rate controlled output (1 ns); plain input; programmable pull down

pin 6 of the bidirectional ULPI data bus

slew-rate controlled output (1 ns); plain input; programmable pull down

pin 5 of the bidirectional ULPI data bus

slew-rate controlled output (1 ns); plain input; programmable pull down

pin 4 of the bidirectional ULPI data bus

slew-rate controlled output (1 ns); plain input; programmable pull down

DATA6

DATA5

DATA4

CLOCK

24

25

26

27

I/O

60 MHz clock output when a crystal is attached; requires 60 MHz clock input when

the crystal is not attached

slew-rate controlled output (1 ns); plain input

pin 3 of the bidirectional ULPI data bus

slew-rate controlled output (1 ns); plain input; programmable pull down

active LOW chip select

DATA3

28

I/O

I

CHIP_SELECT_ 29

N

plain input

V_CC(I/O)

DATA2

30

31

P

I/O supply rail

I/O

pin 2 of the bidirectional ULPI data bus

slew-rate controlled output (1 ns); plain input; programmable pull down

pin 1 of the bidirectional ULPI data bus

slew-rate controlled output (1 ns); plain input; programmable pull down

DATA1

GND

32

I/O

P

die

pad

ground supply; down bonded to the exposed die pad (heat sink); to be connected to

the PCB ground

[1] Symbol names ending with underscore N, for example, NAME_N, indicate active LOW signals.

[2] For details on external components required on each pin, see bill of materials and application diagrams in Section 16.

[3] I = input; O = output; I/O = digital input/output; OD = open-drain output; AI = analog input; AO = analog output; AI/O = analog

input/output; P = power or ground pin.

[4] A detailed description of these pins can be found in Section 7.9.

ISP1504A_ISP1504C_1

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ISP1504A; ISP1504C

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ULPI HS USB OTG transceiver

7. Functional description

7.1 ULPI interface controller

The ISP1504 provides a 12-pin interface that is compliant with UTMI+ Low Pin Interface

(ULPI) Speciﬁcation Rev. 1.1. This interface must be connected to the USB link.

The ULPI interface controller provides the following functions:

• ULPI-compliant interface and register set

• Allows full control over the USB peripheral, host and OTG functionality

• Parses the USB transmit and receive data

• Prioritizes the USB receive data, USB transmit data, interrupts and register operations

• Low-power mode

• Control of the V_BUScharge pump or external source

• V_BUSmonitoring, charging and discharging

• 6-pin serial mode and 3-pin serial mode

• Generates RXCMDs; status updates

• Maskable interrupts

• Control over the ULPI bus state, allowing pins to 3-state or attach active weak

pull-down resistors

For more information on the ULPI protocol, see Section 9.

7.2 USB data serializer and deserializer

The USB data serializer prepares data to transmit on the USB bus. To transmit data, the

USB link sends a transmit command and data on the ULPI bus. The serializer performs

parallel-to-serial conversion, bit stufﬁng and NRZI encoding. For packets with a PID, the

serializer adds a SYNC pattern to the start of the packet, and an EOP pattern to the end

of the packet. When the serializer is busy and cannot accept any more data, the ULPI

interface controller de-asserts NXT.

The USB data deserializer decodes data received from the USB bus. When data is

received, the deserializer strips the SYNC and EOP patterns, and then performs

serial-to-parallel conversion, NRZI decoding and discarding of stuff bits on the data

payload. The ULPI interface controller sends data to the USB link by asserting DIR, and

then asserting NXT whenever a byte is ready. The deserializer also detects various

receive errors, including bit stuff errors, elasticity buffer underrun or overrun, and

byte-alignment errors.

7.3 Hi-Speed USB (USB 2.0) ATX

The Hi-Speed USB ATX block is an analog front-end containing the circuitry needed to

transmit, receive and terminate the USB bus in high-speed, full-speed and low-speed, for

USB peripheral, host and OTG implementations. The following circuitry is included:

• Differential drivers to transmit data at high-speed, full-speed and low-speed

ISP1504A_ISP1504C_1

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ISP1504A; ISP1504C

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ULPI HS USB OTG transceiver

• Differential receiver and single-ended receivers to receive data at high-speed,

full-speed and low-speed

• Squelch circuit to detect high-speed bus activity

• High-speed disconnect detector

• 45 Ω high-speed bus terminations on DP and DM for peripheral and host modes

• 1.5 kΩ pull-up resistor on DP for full-speed peripheral mode

• 15 kΩ bus terminations on DP and DM for host and OTG modes

For details on controlling resistor settings, see Table 8.

7.4 Voltage regulator

The ISP1504 contains a built-in voltage regulator that conditions the V_CCsupply for use

inside the ISP1504. The voltage regulator:

• Supports input supply range of 3.0 V < V_CC< 3.6 V

• Supplies internal circuitry with 1.8 V and 3.3 V

Remark: The REG1V8 and REG3V3 pins require external decoupling capacitors. For

details, see Section 16.

7.5 Crystal oscillator and PLL

The ISP1504 has a built-in crystal oscillator and a Phase-Locked Loop (PLL) for clock

generation.

The crystal oscillator takes a sine-wave input from an external crystal, on the XTAL1 pin,

and converts it to a square wave clock for internal use. Alternatively, a square wave clock

of the same frequency can also be directly driven into the XTAL1 pin. Using an existing

square wave clock can save the cost of a crystal and also reduce the board size.

The PLL takes the square wave clock from the crystal oscillator and multiplies or divides it

into various frequencies for internal use. The PLL can also take a 60 MHz input from the

CLOCK pin. This eliminates the need for an external crystal or clock on XTAL1.

The PLL produces the following frequencies, irrespective of the clock source:

• 60 MHz clock for the ULPI interface controller

• 1.5 MHz for the low-speed USB data

• 12 MHz for the full-speed USB data

• 480 MHz for the high-speed USB data

• Other internal frequencies for data conversion and data recovery

7.6 OTG module

This module contains several sub-blocks that provide all the functionality required by the

USB OTG speciﬁcation. Speciﬁcally, it provides the following circuits:

• The ID detector to sense the ID pin of the mini-USB cable. The ID pin dictates which

device is initially conﬁgured as the host and which as the peripheral.

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ISP1504A; ISP1504C

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ULPI HS USB OTG transceiver

• V_BUScomparators to determine the V_BUSvoltage level. This is required for the V_BUS

detection, SRP and HNP.

• Resistors to temporarily charge and discharge V_BUS. This is required for SRP.

• Charge pump to provide 5 V power on V_BUS. The downstream peripheral can draw its

power from the ISP1504 V_BUS

.

7.6.1 ID detector

The ID detector detects which end of the mini-USB cable is plugged in. The detector must

ﬁrst be enabled by setting the ID_PULLUP register bit to logic 1. If the ISP1504 senses a

value on ID that is different from the previously reported value, an RXCMD status update

will be sent to the USB link, or an interrupt will be asserted.

• If the mini-B end of the cable is plugged in, the ISP1504 will report that ID_GND is

logic 1. The USB link must change to peripheral mode.

• If the mini-A end of the cable is plugged in, the ISP1504 will report that ID_GND is

logic 0. The USB link must change to host mode.

7.6.2 V_BUScomparators

The ISP1504 provides three comparators, V_BUSvalid comparator, session valid

comparator and session end comparator, to detect the V_BUSvoltage level.

7.6.2.1 V_BUSvalid comparator

This comparator is used by hosts and A-devices to determine whether the voltage on

V_BUSis at a valid level for operation. The ISP1504 minimum threshold for the V_BUSvalid

comparator is V_{A_VBUS_VLD}. Any voltage on V_BUSbelow V_{A_VBUS_VLD}is considered a fault.

During power-up, it is expected that the comparator output will be ignored.

7.6.2.2 Session valid comparator

The session valid comparator is a TTL-level input that determines when V_BUSis high

enough for a session to start. Peripherals, A-devices and B-devices use this comparator to

detect when a session is started. The A-device also uses this comparator to determine

when a session is completed. The session valid threshold of the ISP1504 is V_{B_SESS_VLD}

,

with a hysteresis of V_{hys(B_SESS_VLD)}

.

7.6.2.3 Session end comparator

The ISP1504 session end comparator determines when V_BUSis below the B-device

session end threshold. The B-device uses this threshold to determine when a session has

ended. The session end threshold of the ISP1504 is V_{B_SESS_END}

.

7.6.3 SRP charge and discharge resistors

The ISP1504 provides on-chip resistors for short-term charging and discharging of V_BUS

These are used by the B-device to request a session, prompting the A-device to restore

the V_BUSpower. First, the B-device makes sure that V_BUSis fully discharged from the

previous session by setting the DISCHRG_VBUS register bit to logic 1 and waiting for

SESS_END to be logic 1. Then the B-device charges V_BUSby setting the CHRG_VBUS

register bit to logic 1. The A-device sees that V_BUSis charged above the session valid

threshold and starts a session by turning on the V_BUSpower.

.

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ISP1504A; ISP1504C

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ULPI HS USB OTG transceiver

7.6.4 Charge pump

The ISP1504 uses a built-in charge pump to supply current to V_BUSat a nominal voltage

of 5 V. The charge pump works as a capacitive DC-DC converter. An external holding

capacitor, C_{cp(C_A)-(C_B)}, is required between the C_A and C_B pins as shown in Figure 3,

which also shows a typical OTG V_BUSload. The value of C_{cp(C_A)-(C_B)}depends on the

amount of current drive required. If the internal charge pump is not used, the C_{cp(C_A)-(C_B)}

capacitor is not required.

For details on the C_A and C_B pins, see Section 7.9.8.

V

OTG V

BUS

0.1 µF

4.7 µF

ISP1504

C_B

C

cp(C_A)-(C_B)

C_A

004aaa515

Fig 3. External capacitors connection

7.7 Band gap reference voltage

The band gap circuit provides a stable internal voltage reference to bias analog circuitry.

The band gap requires an accurate external reference, R_RREF, resistor connected

between the RREF pin and GND. For details, see Section 16.

7.8 Power-On Reset (POR)

The ISP1504 has an internal power-on reset circuit that resets all internal logic on

power-up. The ULPI interface is also reset on power-up.

Remark: When CLOCK starts toggling after power-up, the USB link must issue a reset

command over the ULPI bus to ensure correct operation of the ISP1504.

7.9 Detailed description of pins

7.9.1 DATA[7:0]

Bidirectional data bus. The USB link must drive DATA[7:0] to LOW when the ULPI bus is

idle. When the link has data to transmit to the PHY, it drives a nonzero value.

The data bus can be reconﬁgured to carry various data types, as given in Section 8 and

Section 9.

The DATA[7:0] pins can be 3-stated by driving pin CHIP_SELECT_N to HIGH. Weak

pull-down resistors are incorporated into the DATA[7:0] pins as part of the interface protect

feature. For details, see Section 9.3.1.

7.9.2 V_CC(I/O)

The input power pin that sets the I/O voltage level. For details, see Section 12, Section 13

and Section 16. V_CC(I/O)provides power to on-chip pads of the following pins:

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ISP1504A; ISP1504C

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ULPI HS USB OTG transceiver

• CHIP_SELECT_N

• CLOCK

• DATA[7:0]

• DIR

• NXT

• RESET_N

• STP

If the ISP1504 CLOCK pin is conﬁgured as an input, the V_CC(I/O)power must be provided

at the same time as the V_CCpower. If the V_CC(I/O)power input is delayed with respect to

V_CC, input clock mode stability cannot be guaranteed.

7.9.3 RREF

Resistor reference analog I/O pin. A resistor, R_RREF, must be connected between RREF

and GND, as shown in Section 16. This provides an accurate voltage reference that

biases internal analog circuitry. Less accurate resistors cannot be used and will render the

ISP1504 unusable.

7.9.4 DP and DM

The DP (data plus) and DM (data minus) are USB differential data pins. These must be

connected to the D+ and D− pins of the USB receptacle.

7.9.5 FAULT

If an external V_BUSovercurrent or fault circuit is used, the output fault indicator of that

circuit can be connected to the ISP1504 FAULT input pin. The ISP1504 will inform the link

of V_BUSfault events by sending RXCMDs on the ULPI bus. To use the FAULT pin, the link

must:

• Set the USE_EXT_VBUS_IND register bit to logic 1.

• Set the polarity of the external fault signal using the IND_COMPL register bit.

• Set the IND_PASSTHRU register bit to logic 1.

If the FAULT pin is not used, it is recommended to connect to GND.

7.9.6 ID

For OTG implementations, the ID (identiﬁcation) pin is connected to the ID pin of the

mini-USB receptacle. As deﬁned in On-The-Go Supplement to the USB 2.0 Speciﬁcation

Rev. 1.2, the ID pin dictates the initial role of the link. If ID is detected as HIGH, the link

must assume the role of a peripheral. If ID is detected as LOW, the link must assume a

host role. Roles can be swapped at a later time by using HNP.

If the ISP1504 is not used as an OTG PHY, but as a standard USB host or peripheral PHY,

the ID pin must be connected to ground.

7.9.7 CPGND

CPGND indicates the analog ground for the on-board charge pump. CPGND must always

be connected to ground, even when the charge pump is not used.

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ISP1504A; ISP1504C

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ULPI HS USB OTG transceiver

7.9.8 C_A and C_B

The C_A and C_B pins are to connect the ﬂying capacitor of the charge pump. The output

current capability of the charge pump depends on the value of capacitor used, as shown

in Table 3. For maximum efﬁciency, place capacitors as close as possible to pins. For

details, see Section 16.

If the charge pump is not used, C_A and C_B must be left ﬂoating (not connected).

C_A

C

cp(C_A)-(C_B)

C_B

ISP1504

V

BUS

I

L

004aaa516

Fig 4. Charge pump capacitor

Table 3. Recommended charge pump capacitor value

C_{cp(C_A)-(C_B)}

22 nF

I_L(max)

8 mA

270 nF

50 mA

7.9.9 V_CC

V_CCis the main input supply voltage for the ISP1504. Decoupling capacitors are

recommended. For details, see Section 16.

7.9.10 PSW_N

PSW_N is an active LOW, open-drain output pin. This pin can be connected to an active

LOW, external V_BUSswitch or charge pump enable circuit to control the external V_BUS

power source. An external pull-up resistor, R_pullup, is required when PSW_N is used. This

pin is open-drain, allowing ganged-mode power control for multiple USB ports. For

application details, see Section 16.

If the link is in host mode, it can enable the external V_BUSpower source by setting the

DRV_VBUS_EXT bit in the OTG Control register to logic 1. The ISP1504 will drive

PSW_N to LOW to enable the external V_BUSpower source. If the link detects an

overcurrent condition (the V_BUSstate in RXCMD is not 11b), it must disable the external

V_BUSpower source by setting DRV_VBUS_EXT to logic 0.

7.9.11 V_BUS

This pin acts as an input to V_BUScomparators, and also as a power pin for the charge

pump, and SRP charge and discharge resistors.

When the DRV_VBUS bit of the OTG Control register is set to logic 1, the ISP1504 drives

V_BUSto a voltage of 4.4 V to 5.25 V, with a minimum output current capability of 8 mA.

The V_BUSpin requires a capacitive load as shown in Section 16.

ISP1504A_ISP1504C_1

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ISP1504A; ISP1504C

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ULPI HS USB OTG transceiver

To prevent electrical overstress, it is strongly recommended that you attach a series

resistor on the V_BUSpin (R_VBUS). R_VBUSmust not be attached when using the ISP1504

internal charge pump. For details, see Section 16.

7.9.12 REG3V3 and REG1V8

Regulator output voltage. These supplies are used to power the ISP1504 internal digital

and analog circuits, and must not be used to power external circuits.

For correct operation of the regulator, it is recommended that you connect REG3V3 and

REG1V8 to decoupling capacitors. For examples, see Section 16.

7.9.13 XTAL1 and XTAL2

XTAL1 is the crystal input, and XTAL2 is the crystal output. The allowed frequency on the

XTAL1 pin depends on the ISP1504 product version.

If the link requires a 60 MHz clock from the ISP1504, then either a crystal must be

attached, or a clock of the same frequency must be driven into XTAL1, with XTAL2 left

ﬂoating. If the link drives a 60 MHz clock into the CLOCK pin, then XTAL1 must be

connected to REG1V8, and XTAL2 must be left ﬂoating.

If a crystal is attached, it requires external load capacitors to GND on each terminal of the

crystal. For details, see Section 16.

If at any time the system wants to stop the clock on XTAL1, the link must ﬁrst put the

ISP1504 into low-power mode. The clock on XTAL1 must be restarted before low-power

mode is exited.

7.9.14 RESET_N

An active LOW asynchronous reset pin that resets all circuits in the ISP1504. The

ISP1504 contains an internal power-on reset circuit, and therefore using the RESET_N

pin is optional. If RESET_N is not used, it must be connected to V_CC(I/O)

.

For details on using RESET_N, see Section 9.3.2.

7.9.15 DIR

ULPI direction output pin. Controls the direction of the data bus. By default, the ISP1504

holds DIR at LOW, causing the data bus to be an input. When DIR is LOW, the ISP1504

listens for data from the link. The ISP1504 pulls DIR to HIGH only when it has data to

send to the link, which is for one of two reasons:

• To send the USB receive data, RXCMD status updates and register read data to the

link.

• To block the link from driving the data bus during power-up, reset and low-power

mode (suspend).

The DIR pin can also be 3-stated by driving CHIP_SELECT_N to HIGH.

For details on DIR usage, refer to UTMI+ Low Pin Interface (ULPI) Speciﬁcation Rev. 1.1.

ISP1504A_ISP1504C_1

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7.9.16 STP

ULPI HS USB OTG transceiver

ULPI stop input pin. The link must assert STP to signal the end of a USB transmit packet

or a register write operation. When DIR is asserted, the link can optionally assert STP to

abort the ISP1504, causing it to de-assert DIR in the next clock cycle. A weak pull-up

resistor is incorporated into the STP pin as part of the interface protect feature. For details,

see Section 9.3.1.

The STP input will be ignored when CHIP_SELECT_N is driven to HIGH.

For details on STP usage, refer to UTMI+ Low Pin Interface (ULPI) Speciﬁcation Rev. 1.1.

7.9.17 NXT

ULPI next data output pin. The ISP1504 holds NXT at LOW, by default. When DIR is LOW

and the link is sending data to the ISP1504, NXT will be asserted to notify the link to

provide the next data byte. When DIR is at HIGH and the ISP1504 is sending data to the

link, NXT will be asserted to notify the link that another valid byte is on the bus. NXT is not

used for register read data or the RXCMD status update.

The NXT pin can also be 3-stated by driving CHIP_SELECT_N to HIGH.

For details on NXT usage, refer to UTMI+ Low Pin Interface (ULPI) Speciﬁcation Rev. 1.1.

7.9.18 CLOCK

A 60 MHz interface clock to synchronize the ULPI bus. CLOCK can be conﬁgured as input

or output. The ISP1504 provides three clocking options:

• A crystal attached between the XTAL1 and XTAL2 pins.

• A clock driven into the XTAL1 pin, with the XTAL2 pin left ﬂoating.

• A 60 MHz clock driven into the CLOCK pin, with XTAL1 tied to REG1V8 and XTAL2

left ﬂoating.

For details on CLOCK usage, refer to UTMI+ Low Pin Interface (ULPI) Speciﬁcation

Rev. 1.1.

7.9.19 CHIP_SELECT_N

Active LOW chip select pin. If CHIP_SELECT_N is not used, it must be tied to GND. For

more information on using CHIP_SELECT_N, see Section 9.3.3.

7.9.20 GND (die pad)

Global ground signal, except for the charge pump that uses CPGND. The die pad is

exposed on the underside of the package as a ground plate. This acts as a ground to all

circuits in the ISP1504, except the charge pump. To ensure correct operation of the

ISP1504, GND must be soldered to the cleanest ground available.

ISP1504A_ISP1504C_1

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ISP1504A; ISP1504C

NXP Semiconductors

ULPI HS USB OTG transceiver

8. Modes of operation

8.1 ULPI modes

The ISP1504 ULPI bus can be programmed to operate in four modes. Each mode

reconﬁgures the signals on the data bus as described in the following subsections. Setting

more than one mode will lead to undeﬁned behavior.

8.1.1 Synchronous mode

This is default mode. At power-up, and when CLOCK is stable, the ISP1504 will enter

synchronous mode. The link must synchronize all ULPI signals to CLOCK, meeting the

set-up and hold times as deﬁned in Section 15. A description of the ULPI pin behavior in

synchronous mode is given in Table 4.

This mode is used by the link to perform the following tasks:

• High-speed detection handshake (chirp)

• Transmit and receive USB packets

• Read and write to registers

• Receive USB status updates (RXCMDs)

For more information on various synchronous mode protocols, see Section 9.

Table 4.

ULPI signal description

Signal

name

Direction

on ISP1504

Signal description

CLOCK

I/O

60 MHz interface clock. If a crystal is attached or a clock is driven into

the XTAL1 pin, the ISP1504 will drive a 60 MHz output clock; otherwise,

the ISP1504 requires a 60 MHz input clock.

DATA[7:0] I/O

8-bit data bus. In synchronous mode, the link drives DATA[7:0] to LOW

by default. The link initiates transfers by sending a nonzero data pattern

called TXCMD (transmit command). In synchronous mode, the direction

of DATA[7:0] is controlled by DIR. Contents of DATA[7:0] lines must be

ignored for exactly one clock cycle whenever DIR changes value. This is

called the turnaround cycle.

Data lines have ﬁxed direction and different meaning in low-power and

serial modes.

ISP1504A_ISP1504C_1

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ULPI HS USB OTG transceiver

Table 4.

ULPI signal description …continued

Signal

name

Direction

on ISP1504

Signal description

DIR

O

Direction: Controls the direction of data bus DATA[7:0]. In synchronous

mode, the ISP1504 drives DIR to LOW by default, making the data bus

an input so that the ISP1504 can listen for TXCMDs from the link. The

ISP1504 drives DIR to HIGH only when it has data for the link. When

DIR and NXT are HIGH, the byte on the data bus contains decoded

USB data. When DIR is HIGH and NXT is LOW, the byte contains status

information called RXCMD (receive command). The only exception to

this rule is when the PHY returns register read data, where NXT is also

LOW, replacing the usual RXCMD byte. Every change in DIR causes a

turnaround cycle on the data bus, during which DATA[7:0] is not valid

and must be ignored by the link.

DIR is always asserted during low-power and serial modes.

STP

NXT

I

Stop: In synchronous mode, the link drives STP to HIGH for one cycle

after the last byte of data is sent to the ISP1504. The link can optionally

assert STP to force DIR to be de-asserted.

In low-power and serial modes, the link holds STP at HIGH to wake up

the ISP1504, causing the ULPI bus to return to synchronous mode.

O

Next: In synchronous mode, the ISP1504 drives NXT to HIGH to throttle

data. If DIR is LOW, the ISP1504 asserts NXT to notify the link to place

the next data byte on DATA[7:0] in the following clock cycle. If DIR is

HIGH, the ISP1504 asserts NXT to notify the link that a valid USB data

byte is on DATA[7:0] in the current cycle. The ISP1504 always drives an

RXCMD when DIR is HIGH and NXT is LOW, unless register read data

is to be returned to the link in the current cycle.

NXT is not used in low-power or serial mode.

8.1.2 Low-power mode

When the USB is idle, the link can place the ISP1504 into low-power mode (also called

suspend mode). In low-power mode, the data bus deﬁnition changes to that shown in

Table 5. To enter low-power mode, the link sets the SUSPENDM bit in the Function

Control register to logic 0. To exit low-power mode, the link asserts the STP signal. The

ISP1504 will draw only suspend current from the V_CCsupply (see Table 43).

During low-power mode, the clock on XTAL1 may be stopped. The clock must be started

again before asserting STP to exit low-power mode. After exiting low-power mode, the

ISP1504 will send an RXCMD to the link if a change was detected in any interrupt source,

and the change still exists. An RXCMD may not be sent if the interrupt condition is

removed before exiting.

For more information on low-power mode enter and exit protocols, refer to UTMI+ Low Pin

Interface (ULPI) Speciﬁcation Rev. 1.1.

Table 5.

Signal mapping during low-power mode

Signal

Maps to

DATA0

DATA1

Direction

Description

LINESTATE0

LINESTATE1

O

combinatorial LINESTATE0 directly driven by analog receiver

combinatorial LINESTATE1 directly driven by analog receiver

ISP1504A_ISP1504C_1

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ISP1504A; ISP1504C

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ULPI HS USB OTG transceiver

Table 5.

Signal

Reserved

INT

Signal mapping during low-power mode …continued

Maps to

DATA2

DATA3

Direction

Description

O

reserved; the ISP1504 will drive this pin to LOW

active HIGH interrupt indication; will be asserted whenever any unmasked

interrupt occurs

Reserved

DATA[7:4]

O

reserved; the ISP1504 will drive this pin to LOW

8.1.3 6-pin full-speed or low-speed serial mode

If the link requires a 6-pin serial interface to transmit and receive full-speed or low-speed

USB data, it can set the ISP1504 to 6-pin serial mode. In 6-pin serial mode, the DATA[7:0]

bus deﬁnition changes to that shown in Table 6. To enter 6-pin serial mode, the link sets

the 6PIN_FSLS_SERIAL bit in the Interface Control register to logic 1. To exit 6-pin serial

mode, the link asserts STP. This is provided primarily for links that contain legacy

full-speed or low-speed functionality, providing a more cost-effective upgrade path to

high-speed. An interrupt pin is also provided to inform the link of USB events. If the link

requires CLOCK to be running during 6-pin serial mode, the CLOCK_SUSPENDM

register bit must be set to logic 1.

For more information on 6-pin serial mode enter and exit protocols, refer to UTMI+ Low

Pin Interface (ULPI) Speciﬁcation Rev. 1.1.

Table 6.

Signal

Signal mapping for 6-pin serial mode

Maps to

DATA0

DATA1

DATA2

DATA3

Direction

Description

TX_ENABLE

TX_DAT

TX_SE0

INT

I

active HIGH transmit enable

transmit differential data on DP and DM

transmit single-ended zero on DP and DM

I

O

active HIGH interrupt indication; will be asserted whenever any

unmasked interrupt occurs

RX_DP

DATA4

DATA5

DATA6

DATA7

O

single-ended receive data from DP

RX_DM

RX_RCV

Reserved

single-ended receive data from DM

differential receive data from DP and DM

reserved; the ISP1504 will drive this pin to LOW

8.1.4 3-pin full-speed or low-speed serial mode

If the link requires a 3-pin serial interface to transmit and receive full-speed or low-speed

USB data, it can set the ISP1504 to 3-pin serial mode. In 3-pin serial mode, the data bus

deﬁnition changes to that shown in Table 7. To enter 3-pin serial mode, the link sets the

3PIN_FSLS_SERIAL bit in the Interface Control register to logic 1. To exit 3-pin serial

mode, the link asserts STP. This is primarily provided for links that contain legacy

full-speed or low-speed functionality, providing a more cost-effective upgrade path to

high-speed. An interrupt pin is also provided to inform the link of USB events. If the link

requires CLOCK to be running during 3-pin serial mode, the CLOCK_SUSPENDM

register bit must be set to logic 1.

For more information on 3-pin serial mode enter and exit protocols, refer to UTMI+ Low

Pin Interface (ULPI) Speciﬁcation Rev. 1.1.

ISP1504A_ISP1504C_1

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ULPI HS USB OTG transceiver

Table 7.

Signal

Signal mapping for 3-pin serial mode

Maps to

DATA0

DATA1

Direction

Description

TX_ENABLE

DAT

I

active HIGH transmit enable

I/O

transmit differential data on DP and DM when TX_ENABLE is HIGH

receive differential data from DP and DM when TX_ENABLE is LOW

transmit single-ended zero on DP and DM when TX_ENABLE is HIGH

receive single-ended zero from DP and DM when TX_ENABLE is LOW

SE0

DATA2

I/O

INT

DATA3

O

active HIGH interrupt indication; will be asserted whenever any

unmasked interrupt occurs

Reserved

DATA[7:4]

reserved; the ISP1504 will drive this pin to LOW

8.2 USB and OTG state transitions

A Hi-Speed USB host or an OTG device handles more than one electrical state as deﬁned

in Universal Serial Bus Speciﬁcation Rev. 2.0 and On-The-Go Supplement to the USB 2.0

Speciﬁcation Rev. 1.2. The ISP1504 accommodates the various states through register bit

settings of XCVRSELECT[1:0], TERMSELECT, OPMODE[1:0], DP_PULLDOWN and

DM_PULLDOWN.

Table 8 summarizes operating states. The values of register settings in Table 8 will force

resistor settings as also given in Table 8. Resistor setting signals are deﬁned as follows:

• RPU_DP_EN enables the 1.5 kΩ pull-up resistor on DP

• RPD_DP_EN enables the 15 kΩ pull-down resistor on DP

• RPD_DM_EN enables the 15 kΩ pull-down resistor on DM

• HSTERM_EN enables the 45 Ω termination resistors on DP and DM

It is up to the link to set the desired register settings.

Table 8.

Operating states and their corresponding resistor settings

Signaling mode

Register settings

Internal resistor settings

OPMODE DP_PULL DM_PULL RPU_ RPD_ RPD_

DP_EN DP_EN DM_EN _EN

XCVR TERM

SELECT SELECT [1:0]

[1:0]

HSTERM

DOWN

General settings

3-state drivers

XXb

01b

Xb

0b

01b

00b

Xb

1b

Xb

1b

0b

1b

0b

1b

0b

Power-up or

V_BUS< V_{B_SESS_END}

Host settings

Host chirp

00b

X1b

01b

0b

1b

10b

00b

1b

0b

1b

0b

Host high-speed

Host full-speed

Host high-speed or

full-speed suspend

Host high-speed or

full-speed resume

01b

10b

1b

10b

00b

1b

0b

1b

0b

Host low-speed

ISP1504A_ISP1504C_1

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ULPI HS USB OTG transceiver

Table 8.

Operating states and their corresponding resistor settings …continued

Signaling mode

Register settings

XCVR TERM

Internal resistor settings

OPMODE DP_PULL DM_PULL RPU_

RPD_

HSTERM

SELECT SELECT [1:0]

[1:0]

DOWN

DP_EN DP_EN DM_EN _EN

Host low-speed

suspend

10b

1b

0b

00b

10b

1b

0b

1b

0b

1b

Host low-speed

resume

10b

1b

Host Test J or Test K 00b

1b

Peripheral settings

Peripheral chirp

00b

1b

0b

10b

00b

0b

1b

0b

1b

Peripheral

high-speed

Peripheral full-speed 01b

1b

00b

0b

1b

0b

Peripheral

01b

high-speed or

full-speed suspend

Peripheral

high-speed or

full-speed resume

01b

1b

0b

10b

0b

1b

0b

1b

Peripheral Test J or 00b

Test K

OTG settings

OTG device

peripheral chirp

00b

1b

0b

10b

00b

0b

1b

0b

1b

0b

1b

OTG device

peripheral

high-speed

OTG device

peripheral full-speed

01b

1b

00b

0b

1b

0b

1b

0b

OTG device

peripheral

high-speed and

full-speed suspend

OTG device

peripheral

high-speed and

full-speed resume

01b

00b

1b

0b

10b

0b

1b

0b

1b

0b

1b

OTG device

peripheral Test J or

Test K

ISP1504A_ISP1504C_1

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9. Protocol description

The following subsections describe the protocol for using the ISP1504.

9.1 ULPI references

The ISP1504 provides a 12-pin ULPI interface to communicate with the link. It is highly

recommended that you read UTMI+ Low Pin Interface (ULPI) Speciﬁcation Rev. 1.1 and

UTMI+ Speciﬁcation Rev. 1.0.

9.2 Power-On Reset (POR)

An internal POR is generated when REG1V8 rises above V_POR(trip), for at least

t_{w(REG1V8_H)}. The internal POR pulse will also be generated whenever REG1V8 drops

below V_POR(trip)for more than t_{w(REG1V8_L)}, and then rises above V_POR(trip)again. The

voltage on REG1V8 is generated from V_CC

.

To give a better view of the functionality, Figure 5 shows a possible curve of REG1V8. The

internal POR starts with logic 0 at t0. At t1, the detector will see the passing of the trip

level so that POR turns to logic 1 and a delay element will add another t_PORPbefore it

drops to logic 0. If REG1V8 dips from t2 to t3 for > t_{w(REG1V8_L)}, another POR pulse is

generated. If the dip at t4 to t5 is too short, that is, < t_{w(REG1V8_L)}, the internal POR pulse

will not react and will remain LOW.

REG1V8

V

POR(trip)

t4

t3

t5

t0

t1

t

t2

POR

t

PORP

004aaa751

Fig 5. Internal power-on reset timing

9.3 Power-up, reset and bus idle sequence

Figure 6 shows a typical start-up sequence.

On power-up, the ISP1504 performs an internal power-on reset and asserts DIR to

indicate to the link that the ULPI bus cannot be used. On power-up, CLOCK is an input

unless several edges are detected on XTAL1. When the internal PLL is stable, the

ISP1504 de-asserts DIR. The power-up time depends on the V_CCsupply rise time, the

crystal start-up time, and PLL start-up time t_{startup(o)(CLOCK)}. Whenever DIR is asserted,

the ISP1504 drives the NXT pin to LOW and drives DATA[7:0] with RXCMD values. When

DIR is de-asserted, the link must drive the data bus to a valid level. By default, the link

must drive data to LOW. When the ISP1504 initially de-asserts DIR on power-up, the link

must ignore all RXCMDs until it resets the ISP1504. Before beginning USB packets, the

link must set the RESET bit in the Function Control register to reset the ISP1504. After the

RESET bit is set, the ISP1504 will assert DIR until the internal reset completes. The

ISP1504 will automatically de-assert DIR and clear the RESET bit when reset has

ISP1504A_ISP1504C_1

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ISP1504A; ISP1504C

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ULPI HS USB OTG transceiver

completed. After every reset, an RXCMD is sent to the link to update USB status

information. After this sequence, the ULPI bus is ready for use and the link can start USB

operations.

If a crystal is attached or a clock is driven into the XTAL1 pin, the ISP1504 will drive a

60 MHz clock out from the CLOCK pin when DIR de-asserts. This is shown as CLOCK

(output) in Figure 6. If no crystal is attached and a 60 MHz clock is driven into the CLOCK

pin, DIR will de-assert when internal clocks have synchronized. This is shown as CLOCK

(input) in Figure 6.

The recommended power-up sequence for the link is as follows:

• The link waits for 1 ms, ignoring all the ULPI pin status.

• The link may start to detect DIR status level. If DIR is detected as LOW for three clock

cycles, the link may send a RESET command.

• The ULPI interface is ready for use.

ISP1504A_ISP1504C_1

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ULPI HS USB OTG transceiver

V

CC

V

CC(I/O)

REG1V8

t

PWRUP

internal

REG1V8

detector

internal

POR

XTAL1

(input)

CLOCK

(input)

XTAL1

(output)

bus idle

internal clocks stable

RESET command

t

startup(PLL)

CLOCK

(output)

DATA[7:0]

TXCMD

D

RXCMD

update

internal reset

DIR

STP

NXT

t6

t2

t3

t4

t5

t1

004aaa885

t1 = V_CCand V_CC(I/O)are applied to the ISP1504. The ISP1504 regulator starts to turn on. If the ISP1504 CLOCK pin is

conﬁgured as an input, the V_CC(I/O)power must be provided at the same time as the V_CCpower. If the V_CC(I/O)power input is

delayed with respect to V_CC, input clock mode stability cannot be guaranteed.

t2 = ULPI pads detect REG1V8 rising above the REG1V8 regulator threshold and are not in 3-state. These pads may drive

either LOW or HIGH. It is recommended that the link ignores the ULPI pins status during t_PWRUP

.

t3 = The POR threshold is reached and a POR pulse is generated. After the POR pulse, ULPI pins are driven to a deﬁned

level. DIR is driven to HIGH and the other pins are driven to LOW.

t4 = The 19.2 MHz or 26 MHz input clock starts. This clock may be started any time.

t5 = The internal PLL is stabilized after t_startup(PLL). If the 19.2 MHz or 26 MHz clock is started before POR, the internal PLL

will be stabilized after t_startup(PLL)from POR. The CLOCK pin starts to output 60 MHz. The DIR pin will transition from HIGH

to LOW. The DIR pin will remain LOW before the link issues a RESET command to the ISP1504.

t6 = The power-up sequence is completed and the ULPI bus interface is ready for use.

Fig 6. Power-up and reset sequence required before the ULPI bus is ready for use

ISP1504A_ISP1504C_1

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9.3.1 Interface protection

By default, the ISP1504 enables a weak pull-up resistor on STP. If the STP pin is

unexpectedly HIGH at any time, the ISP1504 will protect the ULPI interface by enabling

weak pull-down resistors on DATA[7:0].

The interface protect feature prevents unwanted activity of the ISP1504 whenever the

ULPI interface is not correctly driven by the link. For example, when the link powers up

more slowly than the ISP1504.

The interface protect feature can be disabled by setting the INTF_PROT_DIS bit to logic 1.

9.3.2 Interface behavior with respect to RESET_N

The use of the RESET_N pin is optional. When RESET_N is asserted (LOW), the

ISP1504 will assert DIR. All logic in the ISP1504 will be reset, including the analog

circuitry and ULPI registers. During reset, the link must drive DATA[7:0] and STP to LOW;

otherwise undeﬁned behavior may result. When RESET_N is de-asserted (HIGH), the

DIR output will de-assert (LOW) four or ﬁve clock cycles later. Figure 7 shows the ULPI

interface behavior when RESET_N is asserted (LOW), and when RESET_N is

subsequently de-asserted (HIGH). The behavior of Figure 7 applies only when

CHIP_SELECT_N is asserted (LOW). If RESET_N is not used, it must be tied to V_CC(I/O)

.

CLOCK

RESET_N

DATA[7:0]

Hi-Z (input)

Hi-Z (link must drive)

Hi-Z (input)

DIR

Hi-Z (input)

STP

NXT

004aaa720

Fig 7. Interface behavior with respect to RESET_N

9.3.3 Interface behavior with respect to CHIP_SELECT_N

At any time that CHIP_SELECT_N is HIGH, the ISP1504 will 3-state DATA[7:0], NXT, and

DIR, and the STP input will be ignored. The link can reuse these pins for other purposes.

When CHIP_SELECT_N is LOW, ULPI output pins operate normally. During normal

operation, the PLL is always powered, regardless of the level of CHIP_SELECT_N.

During power-up, if CHIP_SELECT_N is HIGH, the PLL is not powered up to reduce

power consumption. During power-up, if CHIP_SELECT_N is LOW, the PLL is powered

and the ISP1504 operates normally.

If CHIP_SELECT_N is HIGH:

ISP1504A_ISP1504C_1

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ULPI HS USB OTG transceiver

• The DATA[7:0], NXT and DIR pins are 3-stated and ignored.

• If the ISP1504 was previously in synchronous mode, the STP pin is ignored. If the

ISP1504 was previously in serial or suspend mode, STP is used to exit.

• The pull-down resistors on DATA[7:0] are disabled.

• The ULPI controller is forced into an idle state and any ULPI command is ignored.

entering 3-state mode

exiting 3-state mode

CLOCK

CHIP_

SELECT_N

3-stated pins

DATA[7:0]

DIR

NXT

STP

input ignored

004aaa690

Fig 8. Entering and exiting 3-state in normal mode

ISP1504A_ISP1504C_1

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ISP1504A; ISP1504C

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ULPI HS USB OTG transceiver

entering

exiting

3-state mode

CLOCK

(output)

CHIP_

SELECT_N

3-stated pins

DATA[7:0]

DIR

TXCMD

DATA

NXT

STP

input ignored

exiting

entering

suspend mode

SUSPENDM

004aaa691

Remark: Clock timing is not to scale.

Fig 9. Entering and exiting 3-state in suspend mode

9.4 V_BUSpower and fault detection

9.4.1 Driving 5 V on V_BUS

The ISP1504 provides a built-in charge pump. To enable the charge pump, the link must

set the DRV_VBUS bit in the OTG Control register.

The ISP1504 also supports external 5 V supplies. The ISP1504 can control the external

supply using the active-LOW PSW_N open-drain output pin. To enable the external supply

by driving PSW_N to LOW, the link must set the DRV_VBUS_EXT bit in the OTG Control

register to logic 1. The link can optionally set both the DRV_VBUS and DRV_VBUS_EXT

bits to logic 1 to enable the external supply.

Table 9 summarizes settings to drive 5 V on V_BUS

.

Table 9.

OTG Control register power control bits

DRV_VBUS DRV_VBUS_EXT

Power source used

0

1

X

0

1

internal and external V_BUSpower sources are disabled

internal V_BUScharge pump is enabled

external 5 V V_BUSsupply is enabled

9.4.2 Fault detection

The ISP1504 supports external V_BUSfault detector circuits that output a digital fault

indicator signal. The indicator signal must be connected to the FAULT pin. To enable the

ISP1504 to monitor the digital fault input, the link must set the USE_EXT_VBUS_IND bit

in the OTG Control register. By default, the digital indicator is interpreted by the ISP1504

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ULPI HS USB OTG transceiver

as active LOW. That is, a LOW level on FAULT indicates a V_BUSfault condition has been

detected. If the external fault detector provides an active HIGH digital indicator, the link

must set the IND_COMPL bit in the Interface Control register to logic 1.

By default, the ISP1504 will qualify the external FAULT input with the internal V_BUSvalid

comparator. This can be disabled by setting the IND_PASSTHRU bit to logic 0.

9.5 TXCMD and RXCMD

Commands between the ISP1504 and the link are described in the following subsections.

9.5.1 TXCMD

By default, the link must drive the ULPI bus to its idle state of 00h. To send commands and

USB packets, the link drives a nonzero value on DATA[7:0] to the ISP1504 by sending a

byte called TXCMD. Commands include USB packet transmissions, and register reads

and writes. Once the TXCMD is interpreted and accepted by the ISP1504, the NXT signal

is asserted and the link can follow up with the required number of data bytes. The TXCMD

byte format is given in Table 10. Any values other than those in Table 10 are illegal and

may result in undeﬁned behavior.

Various TXCMD packet and register sequences are shown in later sections.

Table 10. TXCMD byte format

Command

type name

Command code Command payload Command Command description

DATA[7:6]

DATA[5:0]

name

Idle

00b

00 0000b

NOOP

No operation. 00h is the idle value of the data bus.

The link must drive NOOP by default.

Packet

transmit

01b

10b

00 0000b

NOPID

Transmit USB data that does not have a PID, such as

chirp and resume signaling. The ISP1504 starts

transmitting only after accepting the next data byte.

00 XXXXb

10 1111b

PID

Transmit USB packet. DATA[3:0] indicates USB

packet identiﬁer PID[3:0].

Register

write

EXTW

Extended register write command (optional). The

8-bit address must be provided after the command is

accepted.

XX XXXXb

10 1111b

REGW

EXTR

Register write command with 6-bit immediate

address.

Register read 11b

Extended register read command (optional). The

8-bit address must be provided after the command is

accepted.

XX XXXXb

REGR

Register read command with 6-bit immediate

address.

9.5.2 RXCMD

The ISP1504 communicates status information to the link by asserting DIR and sending

an RXCMD byte on the DATA bus. The RXCMD data byte format is given in Table 11.

The ISP1504 will automatically send an RXCMD whenever there is a change in any of the

RXCMD data ﬁelds. The link must be able to accept an RXCMD at any time; including

single RXCMDs, back-to-back RXCMDs, and RXCMDs at any time during USB receive

packets when NXT is LOW. An example is shown in Figure 10. For details and diagrams,

refer to UTMI+ Low Pin Interface (ULPI) Speciﬁcation Rev. 1.1.

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An RXCMD may not be sent when exiting low-power mode or serial mode, if the interrupt

condition is removed before exiting.

Table 11. RXCMD byte format

DATA

Name

Description and value

1 to 0

LINESTATE LINESTATE signals: For a deﬁnition of LINESTATE, see Section 9.5.2.1.

DATA0 — LINESTATE[0]

DATA1 — LINESTATE[1]

3 to 2

V_BUSstate

Encoded V_BUSvoltage state: For an explanation of the V_BUSstate, see Section 9.5.2.2.

Value

00

V

_BUSvoltage

SESS_END

SESS_VLD A_VBUS_VLD

V_BUS< V_{B_SESS_END}

1

0

X

0

1

X

0

1

01

V_{B_SESS_END}≤ V_BUS< V_{B_SESS_VLD}

V_{B_SESS_VLD}≤ V_BUS< V_{A_VBUS_VLD}

V_BUS≥ V_{A_VBUS_VLD}

10

11

5 to 4

RxEvent

Encoded USB event signals: For an explanation of RxEvent, see Section 9.5.2.3.

Value RxActive

RxError

HostDisconnect

00

01

11

10

0

1

X

0

1

X

0

1

6

7

ID

Set to the value of the ID pin.

ALT_INT

By default, this signal is not used and is not needed in typical designs. Optionally, the link can

enable the BVALID_RISE and/or BVALID_FALL bits in the Power Control register. Corresponding

changes in BVALID will cause an RXCMD to be sent to the link with the ALT_INT bit asserted.

CLOCK

Single RXCMD

RXCMD

Back-to-back RXCMDs

RXCMD RXCMD

turnaround

[

]

DATA 7:0

DIR

STP

NXT

004aaa695

Fig 10. Single and back-to-back RXCMDs from the ISP1504 to the link

9.5.2.1 Linestate encoding

LINESTATE[1:0] reﬂects the current state of DP and DM. Whenever the ISP1504 detects

a change in DP or DM, an RXCMD will be sent to the link with the new LINESTATE[1:0]

value. The value given on LINESTATE[1:0] depends on the setting of various registers.

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Table 12 shows the LINESTATE[1:0] encoding for upstream facing ports, which applies to

peripherals. Table 13 shows the LINESTATE[1:0] encoding for downstream facing ports,

which applies to Host Controllers. Dual-role devices must choose the correct table,

depending on whether it is in peripheral or host mode.

Table 12. LINESTATE[1:0] encoding for upstream facing ports: peripheral

DP_PULLDOWN = 0.^[1]

Mode

Full-speed

01, 11

1

High-speed

00

Chirp

XCVRSELECT[1:0]

TERMSELECT

00

0

1

LINESTATE[1:0]

00

SE0

squelch

!squelch

invalid

squelch

01

10

11

FS-J

!squelch and HS_Differential_Receiver_Output

!squelch and !HS_Differential_Receiver_Output

invalid

FS-K

SE1

[1] !squelch indicates inactive squelch. !HS_Differential_Receiver_Output indicates inactive HS_Differential_Receiver_Output.

Table 13. LINESTATE[1:0] encoding for downstream facing ports: host

DP_PULLDOWN and DM_PULLDOWN = 1.^[1]

Mode

Low-speed Full-speed

High-speed

00

Chirp

XCVRSELECT[1:0]

TERMSELECT

OPMODE[1:0]

LINESTATE[1:0]

10

01, 11

1

00

1

0

X

00, 01 or 11

squelch

!squelch

invalid

10

00

01

10

11

SE0

LS-K

LS-J

SE1

SE0

FS-J

FS-K

SE1

squelch

!squelch and HS_Differential_Receiver_Output

!squelch and !HS_Differential_Receiver_Output

invalid

[1] !squelch indicates inactive squelch. !HS_Differential_Receiver_Output indicates inactive HS_Differential_Receiver_Output.

9.5.2.2 V_BUSstate encoding

USB devices must monitor the V_BUSvoltage for purposes such as overcurrent detection,

starting a session and SRP. The V_BUSstate ﬁeld in the RXCMD is an encoding of the

voltage level on V_BUS

.

The SESS_END and SESS_VLD indicators in the V_BUSstate are directly taken from

internal comparators built-in to the ISP1504, and encoded as shown in Table 11.

The A_VBUS_VLD indicator in the V_BUSstate provides several options and must be

conﬁgured based on current draw requirements. A_VBUS_VLD can input from one or

more V_BUSvoltage indicators, as shown in Figure 11.

A description on how to use and select the V_BUSstate encoding is given in Section “Using

and selecting the V_BUSstate encoding”.

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A_VBUS_VLD comparator

internal A_VBUS_VLD

V

BUS

(0, X)

(1, 0)

RXCMD

A_VBUS_VLD

complement

output

FAULT indicator

FAULT

(1, 1)

IND_COMPL

USE_EXT_VBUS_IND,

IND_PASSTHRU

004aaa698

Fig 11. RXCMD A_VBUS_VLD indicator source

Using and selecting the V_BUSstate encoding: The V_BUSstate encoding is shown in

Table 11. The ISP1504 will send an RXCMD to the link whenever there is a change in the

V_BUSstate. To receive the V_BUSstate updates, the link must ﬁrst enable the corresponding

interrupts in the USB Interrupt Enable Rising Edge and USB Interrupt Enable Falling Edge

registers.

The link can use the V_BUSstate to monitor V_BUSand take appropriate action. Table 14

shows the recommended usage for typical applications.

Table 14. V_BUSindicators in RXCMD required for typical applications

Application

A_VBUS_VLD

SESS_VLD

SESS_END

Standard host

yes

no

yes

Standard peripheral no

yes

OTG A-device

OTG B-device

yes

no

Standard USB Host Controllers: For standard hosts, the system must be able to provide

500 mA on V_BUSin the range of 4.75 V to 5.25 V. An external circuit must be used to

detect overcurrent conditions. If the external overcurrent detector provides a digital fault

signal, then the fault signal should be connected to the ISP1504 FAULT input pin, and the

link must do the following:

1. If the external overcurrent circuit has an active LOW fault or overcurrent indicator, set

the IND_COMPL bit in the Interface Control register to logic 1.

2. Set the USE_EXT_VBUS_IND bit in the OTG Control register to logic 1.

3. If it is not necessary to qualify the fault indicator with the internal A_VBUS_VLD

comparator, set the IND_PASSTHRU bit in the Interface Control register to logic 1.

Standard USB Peripheral Controllers: Standard peripherals must be able to detect

when V_BUSis at a sufﬁcient level for operation. SESS_VLD must be enabled to detect the

start and end of USB peripheral operations. Detection of A_VBUS_VLD and SESS_END

thresholds is not needed for standard peripherals.

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OTG devices: When an OTG device is conﬁgured as an OTG A-device, it must be able to

provide a minimum of 8 mA on V_BUS. If the OTG A-device provides less than 100 mA, then

there is no need for an overcurrent detection circuit because the internal A_VBUS_VLD

comparator is sufﬁcient. If the OTG A-device provides more than 100 mA on V_BUS, an

overcurrent detector must be used and "Standard USB Host Controllers" applies. The

OTG A-device also uses SESS_VLD to detect when an OTG A-device is initiating V_BUS

pulsing SRP.

When an OTG device is conﬁgured as an OTG B-device, SESS_VLD must be used to

detect when V_BUSis at a sufﬁcient level for operation. SESS_END must be used to detect

when V_BUShas dropped to a LOW level, allowing the B-device to safely initiate V_BUS

pulsing SRP.

9.5.2.3 RxEvent encoding

The RxEvent ﬁeld of the RXCMD informs the link of information related packets received

on the USB bus. RxActive and RxError are deﬁned in USB 2.0 Transceiver Macrocell

Interface (UTMI) Speciﬁcation Ver. 1.05. HostDisconnect is deﬁned in UTMI+

Speciﬁcation Rev. 1.0. A short deﬁnition is also given in the following subsections.

RxActive: When the ISP1504 has detected a SYNC pattern on the USB bus, it signals an

RxActive event to the link. An RxActive event can be communicated using two methods.

The ﬁrst method is for the ISP1504 to simultaneously assert DIR and NXT. The second

method is for the ISP1504 to send an RXCMD to the link with the RxActive ﬁeld in

RxEvent bits set to logic 1. The link must be able to detect both methods. RxActive frames

the receive packet from the ﬁrst byte to the last byte.

The link must assume that RxActive is set to logic 0 when indicated in an RXCMD or when

DIR is de-asserted, whichever occurs ﬁrst.

The link uses RxActive to time high-speed packets and ensure that bus turnaround times

are met. For more information on the USB packet timing, see Section 9.8.1.

RxError: When the ISP1504 has detected an error while receiving a USB packet, it

de-asserts NXT and sends an RXCMD with the RxError ﬁeld set to logic 1. The received

packet is no longer valid and must be dropped by the link.

HostDisconnect: HostDisconnect is encoded into the RxEvent ﬁeld of the RXCMD.

HostDisconnect is valid only when the ISP1504 is conﬁgured as a host (both

DP_PULLDOWN and DM_PULLDOWN are set to logic 1), and indicates to the Host

Controller when a peripheral is connected or disconnected. The Host Controller must

enable HostDisconnect by setting the HOST_DISCON_R and HOST_DISCON_F bits in

the USB Interrupt Enable Rising Edge and USB Interrupt Enable Falling Edge registers,

respectively. Changes in HostDisconnect will cause the PHY to send an RXCMD to the

link with the updated value.

9.6 Register read and write operations

Figure 12 shows register read and write sequences. The ISP1504 supports immediate

addressing and extended addressing register operations. Extended register addressing is

optional for links. Note that register operations will be aborted if the ISP1504 unexpectedly

asserts DIR during the operation. When a register operation is aborted, the link must retry

until successful. For more information on register operations, refer to UTMI+ Low Pin

Interface (ULPI) Speciﬁcation Rev. 1.1.

ISP1504A_ISP1504C_1

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ISP1504A; ISP1504C

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ULPI HS USB OTG transceiver

CLOCK

TXCMD

(REGW) D

TXCMD

(REGR)

TXCMD

(EXTW) AD

TXCMD

(EXTW) AD

D

DATA[7:0]

immediate

register write

extended

register write

immediate

register read

extended

register read

DIR

STP

NXT

004aaa710

AD indicates the address byte, and D indicates the data byte.

Fig 12. Example of register write, register read, extended register write and extended register read

9.7 USB reset and high-speed detection handshake (chirp)

Figure 13 shows the sequence of events for USB reset and high-speed detection

handshake (chirp). The sequence is shown for hosts and peripherals. Figure 13 does not

show all RXCMD updates and timing is not to scale. The sequence is as follows:

1. USB reset: The host detects a peripheral attachment as low-speed if DM is HIGH and

as full-speed if DP is HIGH. If a host detects a low-speed peripheral, it does not follow

the remainder of this protocol. If a host detects a full-speed peripheral, it resets the

peripheral by writing to the Function Control register and setting

XCVRSELECT[1:0] = 00b (high-speed) and TERMSELECT = 0b, which drives SE0

on the bus (DP and DM connected to ground through 45 Ω). The host also sets

OPMODE[1:0] = 10b for correct chirp transmit and receive. The start of SE0 is labeled

T₀.

Remark: To receive chirp signaling, the host must also consider the high-speed

differential receiver output. The Host Controller must interpret LINESTATE[1:0] as

shown in Table 13.

2. High-speed detection handshake (chirp)

a. Peripheral chirp: After detecting SE0 for no less than 2.5 µs, if the peripheral is

capable of high-speed, it sets XCVRSELECT[1:0] = 00b (high-speed) and

OPMODE[1:0] = 10b (chirp). The peripheral immediately follows this with a

TXCMD (NOPID), transmitting a Chirp K for no less than 1 ms and ending no more

than 7 ms after reset time T₀. If the peripheral is in low-power mode, it must wake

up its clock within 5.6 ms, leaving 200 µs for the link to start transmitting the

Chirp K, and 1.2 ms for the Chirp K to complete (worst case with 10 % slow clock).

b. Host chirp: If the host does not detect the peripheral chirp, it must continue

asserting SE0 until the end of reset. If the host detects the peripheral Chirp K for

no less than 2.5 µs, then no more than 100 µs after the bus leaves the Chirp K

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state, the host sends a TXCMD (NOPID) with an alternating sequence of Chirp Ks

and Js. Each Chirp K or Chirp J must last no less than 40 µs and no longer than

60 µs.

c. High-speed idle: The peripheral must detect a minimum of Chirp K-J-K-J-K-J. Each

Chirp K and Chirp J must be detected for at least 2.5 µs. After seeing that

minimum sequence, the peripheral sets TERMSELECT = 0b and

OPMODE[1:0] = 00b. The peripheral is now in high-speed mode and sees !squelch

(01b on LINESTATE). When the peripheral sees squelch (10b on LINESTATE), it

knows that the host has completed chirp and waits for high-speed USB trafﬁc to

begin. After transmitting the chirp sequence, the host changes OPMODE[1:0] to

00b and begins sending USB packets.

For more information, refer to UTMI+ Low Pin Interface (ULPI) Speciﬁcation Rev. 1.1.

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ULPI HS USB OTG transceiver

USB reset

high-speed detection handshake (chirp)

T

0

peripheral chirp

host chirp

HS idle

TXCMD

(REGW)

TXCMD

(REGW)

TXCMD

NOPID

SE0

K

00

K

...

J

K

J

DATA

[

]

7:0

DIR

STP

NXT

00 (HS)

01 (FS)

XCVR

SELECT

TERM

SELECT

00 (normal)

J (01b)

01 (chirp)

OP

MODE

squelch

(00b)

SE0 (00b)

host chirp K (10b) or chirp J (01b)

peripheral chirp K (10b)

squelch (00b)

LINE

STATE

RXCMDs

TXCMD

(REGW)

TXCMD

NOPID

(REGW)

00

K

J

K

J

00

SE0

K

...

K

J

DATA

[

]

7:0

DIR

STP

NXT

01 (FS)

00 (HS)

XCVR

SELECT

TERM

SELECT

00 (normal)

10 (chirp)

00 (normal)

OP

MODE

squelch

(00b)

!squelch

(01b)

squelch (00b)

peripheral chirp K (10b)

J (01b)

SE0 (00b)

host chirp K or J (10b or 01b)

LINE

STATE

DP

DM

004aaa711

Timing is not to scale.

Fig 13. USB reset and high-speed detection handshake (chirp) sequence

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9.8 USB packet transmit and receive

An example of a packet transmit and receive is shown in Figure 14. For details on USB

packets, refer to UTMI+ Low Pin Interface (ULPI) Speciﬁcation Rev. 1.1.

ISP1504

asserts DIR, ISP1504

causing

ISP1504

deasserts

DIR, causing

link sends

ISP1504 the next data;

ISP1504

sends

link sends

TXCMD

accepts

TXCMD

ISP1504 link signals

accepts end of data

ULPI bus turnaround

RXCMD

(NXT LOW) (NXT HIGH)

USB data turnaround

is idle

cycle

CLOCK

turnaround

DATA

turnaround RXCMD

DATA

[

]

TXCMD

DATA 7:0

DIR

STP

NXT

004aaa626

Fig 14. Example of using the ISP1504 to transmit and receive USB data

9.8.1 USB packet timing

9.8.1.1 ISP1504 pipeline delays

The ISP1504 delays are shown in Table 15. For detailed description, refer to UTMI+ Low

Pin Interface (ULPI) Speciﬁcation Rev. 1.1, Section 3.8.2.6.2.

Table 15. PHY pipeline delays

Parameter name

RXCMD delay (J and K)

RXCMD delay (SE0)

TX start delay

High-speed PHY delay

Full-speed PHY delay

4

Low-speed PHY delay

4

4 to 6

16 to 18

1 to 2

3 to 4

6 to 9

5 to 6

6 to 10

74 to 75

TX end delay (packets)

TX end delay (SOF)

RX start delay

not applicable

17 to 18

not applicable

122 to 123

RX end delay

9.8.1.2 Allowed link decision time

The amount of clock cycles allocated to the link to respond to a received packet and

correctly receive back-to-back packets is given in Table 16. Link designs must follow

values given in Table 16 for correct USB system operation. Examples of high-speed

packet sequences and timing are shown in Figure 15 and Figure 16. For details, refer to

UTMI+ Low Pin Interface (ULPI) Speciﬁcation Rev. 1.1, Section 3.8.2.6.3.

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Table 16. Link decision times

Packet sequence High-speed Full-speed Low-speed Deﬁnition

link delay

Transmit-Transmit 15 to 24

(host only)

7 to 18

77 to 247

Number of clocks a host link must wait before driving the

TXCMD for the second packet.

In high-speed, the link starts counting from the assertion of

STP for the ﬁrst packet.

In full-speed, the link starts counting from the RXCMD,

indicating LINESTATE has changed from SE0 to J for the

ﬁrst packet. The timing given ensures inter-packet delays of

2 bit times to 6.5 bit times.

Receive-Transmit 1 to 14

(host or

7 to 18

77 to 247

Number of clocks the link must wait before driving the

TXCMD for the transmit packet.

peripheral)

In high-speed, the link starts counting from the end of the

receive packet; de-assertion of DIR or an RXCMD

indicating RxActive is LOW.

In full-speed or low-speed, the link starts counting from the

RXCMD, indicating LINESTATE has changed from SE0 to J

for the receive packet. The timing given ensures

inter-packet delays of 2 bit times to 6.5 bit times.

Receive-Receive

(peripheral only)

1

Minimum number of clocks between consecutive receive

packets. The link must be able to receive both packets.

Transmit-Receive 92

(host or

peripheral)

80

718

Host or peripheral transmits a packet and will time-out after

this amount of clock cycles if a response is not received.

Any subsequent transmission can occur after this time.

USB interpacket delay (88 to 192 high-speed bit times)

DP or

DM

IDLE

EOP

SYNC

D0

DATA

CLOCK

D

N−1

D

N

D1

TXCMD

DATA

[7:0]

DIR

STP

NXT

link decision time (15 to 24 clocks)

TX start delay

TX end delay (two to five clocks)

(one to two clocks)

004aaa712

Fig 15. High-speed transmit-to-transmit packet timing

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USB interpacket delay (8 to 192 high-speed bit times)

DP or

DM

IDLE

EOP

SYNC

DATA

CLOCK

D

N

D

N−4

D

N−2

D0

D1

TXCMD

DATA

[7:0]

turnaround

D

N−3

D

N−1

DIR

STP

NXT

link decision time (1 to 14 clocks)

RX end delay

(three to eight clocks)

TX start delay

(one to two clocks)

004aaa713

Fig 16. High-speed receive-to-transmit packet timing

9.9 Preamble

Preamble packets are headers to low-speed packets that must travel over a full-speed

bus, between a host and a hub. To enter preamble mode, the link sets

XCVRSELECT[1:0] = 11b in the Function Control register. When in preamble mode, the

ISP1504 operates just as in full-speed mode, and sends all data with the full-speed rise

and fall times. Whenever the link transmits a USB packet in preamble mode, the ISP1504

will automatically send a preamble header at full-speed bit rate before sending the link

packet at low-speed bit rate. The ISP1504 will ensure a minimum gap of four full-speed bit

times between the last bit of the full-speed PRE PID and the ﬁrst bit of the low-speed

packet SYNC. The ISP1504 will drive a J for at least one full-speed bit time after sending

the PRE PID, after which the pull-up resistor can hold the J state on the bus. An example

transmit packet is shown in Figure 17.

In preamble mode, the ISP1504 can also receive low-speed packets from the full-speed

bus.

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CLOCK

D1

D0

TXCMD (low-speed packet ID)

DATA[7:0]

DIR

STP

NXT

FS

PRE ID

IDLE (min

4 FS bits)

LS D0

LS D1

LS SYNC

LS PID

FS SYNC

DP or DM

004aaa714

DP and DM timing is not to scale.

Fig 17. Preamble sequence

9.10 USB suspend and resume

9.10.1 Full-speed or low-speed host-initiated suspend and resume

Figure 18 illustrates how a host or a hub places a full-speed or low-speed peripheral into

suspend and sometime later initiates resume signaling to wake up the downstream

peripheral. Note that Figure 18 timing is not to scale, and does not show all RXCMD

LINESTATE updates.

The sequence of events for a host and a peripheral, both with ISP1504, is as follows:

1. Idle: Initially, the host and the peripheral are idle. The host has its 15 kΩ pull-down

resistors enabled (DP_PULLDOWN and DM_PULLDOWN are set to 1b) and 45 Ω

terminations disabled (TERMSELECT is set to 1b). The peripheral has the 1.5 kΩ

pull-up resistor connected to DP for full-speed or DM for low-speed (TERMSELECT is

set to 1b).

2. Suspend: When the peripheral sees no bus activity for 3 ms, it enters the suspend

state. The peripheral link places the PHY into low-power mode by setting the

SUSPENDM bit in the Function Control register, causing the PHY to draw only

suspend current. The host may or may not be powered down.

3. Resume K: When the host wants to wake up the peripheral, it sets OPMODE[1:0] to

10b and transmits a K for at least 20 ms. The peripheral link sees the resume K on

LINESTATE, and asserts STP to wake up the PHY.

4. EOP: When STP is asserted, the ISP1504 on the host side automatically appends an

EOP of two bits of SE0 at low-speed bit rate, followed by one bit of J. The ISP1504 on

the host side knows to add the EOP because DP_PULLDOWN and DM_PULLDOWN

are set to 1b for a host. After the EOP is completed, the host link sets OPMODE[1:0]

to 00b for normal operation. The peripheral link sees the EOP and also resumes

normal operation.

ISP1504A_ISP1504C_1

Product data sheet

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37 of 84

ISP1504A; ISP1504C

NXP Semiconductors

ULPI HS USB OTG transceiver

EOP

IDLE

SUSPEND

RESUME K

IDLE

TXCMD

(REGW)

TXCMD

NOPID

K

...

K

TXCMD

K

DATA

[

]

7:0

DIR

STP

NXT

OPMODE

10b

00b

LINE

STATE

K

SE0

J

CLK

TXCMD

(REGW)

LINESTATE J

LINE STATE K

SE0

J

DATA

[

]

7:0

DIR

STP

NXT

00b

OPMODE

10b

00b

SUSPEND

M

LINE

STATE

K

SE0

J

DP

DM

004aaa715

Timing is not to scale.

Fig 18. Full-speed suspend and resume

9.10.2 High-speed suspend and resume

Figure 19 illustrates how a host or a hub places a high-speed enabled peripheral into

suspend and then initiates resume signaling. The high-speed peripheral will wake up and

return to high-speed operations. Note that Figure 19 timing is not to scale, and does not

show all RXCMD LINESTATE updates.

ISP1504A_ISP1504C_1

Product data sheet

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38 of 84

ISP1504A; ISP1504C

NXP Semiconductors

ULPI HS USB OTG transceiver

The sequence of events related to a host and a peripheral, both with ISP1504, is as

follows:

1. High-speed idle: Initially, the host and the peripheral are idle. The host has its 15 kΩ

pull-down resistors enabled (DP_PULLDOWN and DM_PULLDOWN are set to 1b)

and 45 Ω terminations enabled (TERMSELECT is set to 0b). The peripheral has its

45 Ω terminations enabled (TERMSELECT is set to 0b).

2. Full-speed suspend: When the peripheral sees no bus activity for 3 ms, it enters the

suspend state. The peripheral link places the ISP1504 into full-speed mode

(XCVRSELECT is set to 01b), removes 45 Ω terminations, and enables the 1.5 kΩ

pull-up resistor on DP (TERMSELECT is set to 1b). The peripheral link then places

the ISP1504 into low-power mode by setting SUSPENDM, causing the ISP1504 to

draw only suspend current. The host also changes the ISP1504 to full-speed

(XCVRSELECT is set to 01b), removes 45 Ω terminations (TERMSELECT is set to

1b), and then may or may not be powered down.

3. Resume K: When the host wants to wake up the peripheral, it sets OPMODE to 10b

and transmits a full-speed K for at least 20 ms. The peripheral link sees the resume K

(10b) on LINESTATE, and asserts STP to wake up the ISP1504.

4. High-speed trafﬁc: The host link sets high-speed (XCVRSELECT is set to 00b) and

enables its 45 Ω terminations (TERMSELECT is set to 0b). The peripheral link sees

SE0 on LINESTATE and also sets high-speed (XCVRSELECT is set to 00b), and

enables its 45 Ω terminations (TERMSELECT is set to 0b). The host link sets

OPMODE to 00b for normal high-speed operation.

ISP1504A_ISP1504C_1

Product data sheet

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39 of 84

ISP1504A; ISP1504C

NXP Semiconductors

ULPI HS USB OTG transceiver

FS SUSPEND

RESUME K

HS IDLE

TXCMD

(REGW)

TXCMD

(REGW)

TXCMD

(REGW)

TXCMD

NOPID

K

...

K

DATA

[

]

7:0

DIR

STP

NXT

XCVR

01b

00b

SELECT

TERM

SELECT

OP

10b

00b

MODE

!SQUELCH

(01b)

!SQUELCH SQUELCH

FS J (01b)

FS K (10b)

SQUELCH (00b)

(01b)

(00b)

LINE

STATE

CLK

TXCMD

(REGW)

TXCMD

(REGW)

LINESTATE K

LINESTATE J

SE0

DATA

[

]

7:0

DIR

STP

NXT

XCVR

SELECT

01b

00b

TERM

SELECT

OP

MODE

00b

10b

00b

SUSPEND

M

!SQUELCH

(01b)

!SQUELCH

(01b)

SQUELCH

(00b)

FS K (10b)

SQUELCH (00b)

FS J (01b)

LINE

STATE

DP

DM

004aaa717

Timing is not to scale.

Fig 19. High-speed suspend and resume

ISP1504A_ISP1504C_1

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ISP1504A; ISP1504C

NXP Semiconductors

ULPI HS USB OTG transceiver

9.10.3 Remote wake-up

The ISP1504 supports peripherals that initiate remote wake-up resume. When placed into

USB suspend, the peripheral link remembers at what speed it was originally operating.

Depending on the original speed, the link follows one of the protocols detailed here. In

Figure 20, timing is not to scale, and not all RXCMD LINESTATE updates are shown.

The sequence of events related to a host and a peripheral, both with ISP1504, is as

follows:

1. Both the host and the peripheral are assumed to be in low-power mode.

2. The peripheral begins remote wake-up by re-enabling its clock and setting its

SUSPENDM bit to 1b.

3. The peripheral begins driving K on the bus to signal resume. Note that the peripheral

link must assume that LINESTATE is K (01b) while transmitting because it will not

receive any RXCMDs.

4. The host recognizes the resume, re-enables its clock and sets its SUSPENDM bit.

5. The host takes over resume driving within 1 ms of detecting the remote wake-up.

6. The peripheral stops driving resume.

7. The peripheral sees the host continuing to drive the resume.

8. The host stops driving resume and the ISP1504 automatically adds the EOP to the

end of the resume. The peripheral recognizes the EOP as the end of resume.

9. Both the host and the peripheral revert to normal operation by writing 00b to

OPMODE. If the host or the peripheral was previously in high-speed mode, it must

revert to high-speed before the SE0 of the EOP is completed. This can be achieved

by writing XCVRSELECT = 00b and TERMSELECT = 0b after LINESTATE indicates

SE0.

ISP1504A_ISP1504C_1

Product data sheet

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41 of 84

ISP1504A; ISP1504C

NXP Semiconductors

ULPI HS USB OTG transceiver

TXCMD

NOPID

TXCMD

REGW

TXCMD

REGW

00h

LINESTATE

DATA

[

]

7:0

DIR

STP

NXT

XCVR

SELECT

01b (FS), 10b (LS)

00b (HS only)

TERM

SELECT

0b (HS only)

00b

OP

MODE

10b

TXCMD

REGW

TXCMD

REGW

TXCMD

NOPID

LINESTATE

00h

RXCMD

DATA

[

]

7:0

DIR

STP

NXT

00b (HS only)

0b (HS only)

XCVR

SELECT

00b (HS), 01b (FS), 10b (LS)

TERM

SELECT

OP

MODE

10b

00b

004aaa718

Timing is not to scale.

Fig 20. Remote wake-up from low-power mode

9.11 No automatic SYNC and EOP generation (optional)

This setting allows the link to turn off the automatic SYNC and EOP generation, and must

be used for high-speed packets only. It is provided for backward compatibility with legacy

controllers that include SYNC and EOP bytes in the data payload when transmitting

packets. The ISP1504 will not automatically generate the SYNC and EOP patterns when

OPMODE[1:0] is set to 11b. The ISP1504 will still NRZI encode data and perform bit

stufﬁng. An example of a sequence is shown in Figure 21. The link must always send

packets using the TXCMD (NOPID) type. The ISP1504 does not provide a mechanism to

control bit stufﬁng in individual bytes, but will automatically turn off bit stufﬁng for EOP

when STP is asserted with data set to FEh. If data is set to 00h when STP is asserted, the

ISP1504A_ISP1504C_1

Product data sheet

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42 of 84

ISP1504A; ISP1504C

NXP Semiconductors

ULPI HS USB OTG transceiver

PHY will not transmit any EOP. The ISP1504 will also detect if the PID byte is A5h,

indicating an SOF packet, and automatically send a long EOP when STP is asserted. To

transmit chirp and resume signaling, the link must set OPMODE to 10b.

CLOCK

D

N − 1

DATA

[7:0]

... ...

80h

D

N

00h

00h 00h

PID D1 D2 D3

FEh

TXCMD

DIR

STP

NXT

TX

VALID

TX

READY

TXBIT

STUFF

ENABLE

DP,

DM

SYNC

DATA PAYLOAD

IDLE

PID

EOP

004aaa719

Fig 21. Transmitting USB packets without automatic SYNC and EOP generation

9.12 On-The-Go operations

On-The-Go (OTG) is a supplement to Universal Serial Bus Speciﬁcation Rev. 2.0 that

allows a portable USB device to assume the role of a limited USB host by deﬁning

improvements, such as a small connector and low power. Non-portable devices, such as

standard hosts and embedded hosts, can also beneﬁt from OTG features.

The ISP1504 OTG PHY is designed to support all the tasks speciﬁed in the OTG

supplement. The ISP1504 provides the front-end analog support for Host Negotiation

Protocol (HNP) and Session Request Protocol (SRP) for dual-role devices. The

supporting components include:

• Built-in 5 V charge pump

• Voltage comparators

– A_VBUS_VLD

– SESS_VLD (session valid, can be used for both A-session and B-session valid)

– SESS_END (session end)

• Pull-up and pull-down resistors on DP and DM

• ID detector indicates if mini-A or mini-B plug is inserted

• Charge and discharge resistors on V_BUS

The following subsections describe how to use the ISP1504 OTG components.

ISP1504A_ISP1504C_1

Product data sheet

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43 of 84

ISP1504A; ISP1504C

NXP Semiconductors

ULPI HS USB OTG transceiver

9.12.1 OTG charge pump

A description of the charge pump is given in Section 7.6.4. When the controller is

conﬁgured as an A-device, it can provide the V_BUSpower by turning on the charge pump.

Control of the charge pump is described in Section 9.4.1 and Section 10.1.4.

9.12.2 OTG comparators

The ISP1504 provides comparators that conform to On-The-Go Supplement to the

USB 2.0 Speciﬁcation Rev. 1.2 requirements of V_{A_VBUS_VLD}, V_{A_SESS_VLD}, V_{B_SESS_VLD}

and V_{B_SESS_END}. In this data sheet, V_{A_SESS_VLD}and V_{B_SESS_VLD}are combined into

V_{B_SESS_VLD}. Comparators are described in Section 7.6.2. Changes in comparator values

are communicated to the link by RXCMDs as described in Section 9.5.2.2. Control over

comparators is described in Section 10.1.5 to Section 10.1.8.

9.12.3 Pull-up and pull-down resistors

The USB resistors on DP and DM can be used to initiate data-line pulsing SRP. The link

must set the required bus state using mode settings in Table 8.

9.12.4 ID detection

The ISP1504 provides an internal pull-up resistor to sense the value of the ID pin. The

pull-up resistor must ﬁrst be enabled by setting the ID_PULLUP register bit to logic 1. If

the value on ID has changed, the ISP1504 will send an RXCMD or interrupt to the link by

time t_ID. If the link does not receive any RXCMD or interrupt by t_ID, then the ID value has

not changed.

9.12.5 V_BUScharge and discharge resistors

A pull-up resistor, R_UP(VBUS), is provided to perform V_BUSpulsing SRP. A B-device is

allowed to charge V_BUSabove the session valid threshold to request the host to turn on

the V_BUSpower.

A pull-down resistor, R_DN(VBUS), is provided for a B-device to discharge V_BUS. This is done

whenever the A-device turns off the V_BUSpower; the B-device can use the pull-down

resistor to ensure V_BUSis below V_{B_SESS_END}before starting a session.

For details, refer to On-The-Go Supplement to the USB 2.0 Speciﬁcation Rev. 1.2.

9.13 Serial modes

The ISP1504 supports both 6-pin serial mode and 3-pin serial mode, controlled by

bits 6PIN_FSLS_SERIAL and 3PIN_FSLS_SERIAL of the Interface Control register. For

details, refer to UTMI+ Low Pin Interface (ULPI) Speciﬁcation Rev. 1.1, Section 3.10.

Figure 22 and Figure 23 provide examples of 6-pin serial mode and 3-pin serial mode,

respectively.

ISP1504A_ISP1504C_1

Product data sheet

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44 of 84

ISP1504A; ISP1504C

NXP Semiconductors

ULPI HS USB OTG transceiver

TRANSMIT

DATA

RECEIVE

SYNC

DATA

EOP

DATA0

(TX_ENABLE)

DATA1

(TX_DAT)

DATA2

(TX_SE0)

DATA4

(RX_DP)

DATA5

(RX_DM)

DATA6

(RX_RCV)

DP

DM

004aaa692

Fig 22. Example of transmit followed by receive in 6-pin serial mode

TRANSMIT

RECEIVE

DATA

SYNC

EOP

DATA0

(TX_ENABLE)

DATA1

(TX_DAT/

RX_RCV)

DATA2

(TX_SE0/

RX_SE0)

DP

DM

004aaa693

Fig 23. Example of transmit followed by receive in 3-pin serial mode

ISP1504A_ISP1504C_1

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45 of 84

ISP1504A; ISP1504C

NXP Semiconductors

ULPI HS USB OTG transceiver

9.14 Aborting transfers

The ISP1504 supports aborting transfers on the ULPI bus. For details, refer to UTMI+ Low

Pin Interface (ULPI) Speciﬁcation Rev. 1.1, Section 3.8.4.

9.15 Avoiding contention on the ULPI data bus

Because the ULPI data bus is bidirectional, avoid situations in which both the link and the

PHY simultaneously drive the data bus.

The following points must be considered while implementing the data bus drive control on

the link.

After power-up and clock stabilization, default states are as follows:

• The ISP1504 drives DIR is LOW.

• The data bus is input to the ISP1504.

• The ULPI link data bus is output, with all data bus lines driven to LOW.

When the ISP1504 wants to take control of the data bus to initiate a data transfer, it

changes the DIR value from LOW to HIGH.

At this point, the link must disable its output buffers. This needs to be as fast as possible

so the link must use a combinational path from DIR.

The ISP1504 will not immediately enable its output buffers, but will delay the enabling of

its buffers until the next clock edge, avoiding bus contention.

When the data transfer is no longer required by the ISP1504, it changes DIR from HIGH to

LOW and starts to immediately turn off its output drivers. The link senses the change of

DIR from HIGH to LOW, but delays enabling its output buffers for one CLOCK cycle,

avoiding data bus contention.

ISP1504A_ISP1504C_1

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ISP1504A; ISP1504C

NXP Semiconductors

ULPI HS USB OTG transceiver

10. Register map

Table 17. Register map overview

Field name

Size Address (6 bits)

(bits

References

C^[4]

R^[1]

W^[2]

S^[3]

Immediate register set

Vendor ID Low register

Vendor ID High register

Product ID Low register

Product ID High register

Function Control register

Interface Control register

OTG Control register

8

00h

01h

02h

03h

-

Section 10.1.1 on page 47

-

04h to 06h 04h

07h to 09h 07h

0Ah to 0Ch 0Ah

0Dh to 0Fh 0Dh

05h

08h

0Bh

0Eh

06h

09h

0Ch

0Fh

Section 10.1.2 on page 48

Section 10.1.3 on page 49

Section 10.1.4 on page 50

Section 10.1.5 on page 51

USB Interrupt Enable Rising Edge

register

USB Interrupt Enable Falling Edge

register

8

10h to 12h 10h

11h

12h

Section 10.1.6 on page 52

USB Interrupt Status register

USB Interrupt Latch register

Debug register

8

-

13h

14h

15h

-

Section 10.1.7 on page 52

Section 10.1.8 on page 53

Section 10.1.9 on page 54

Section 10.1.10 on page 54

Section 10.1.11 on page 54

Section 10.1.12 on page 54

Section 10.1.13 on page 54

Section 10.1.14 on page 54

Section 10.2 on page 55

-

Scratch register

16h to 18h 16h

17h

18h

Reserved (do not use)

Access extended register set

Vendor-speciﬁc registers

Power Control register

Extended register set

19h to 2Eh

8

-

2Fh

-

30h to 3Ch

3D to 3Fh

-

Address (8 bits)

00h to 3Fh

40h to FFh

Maps to immediate register set above 8

Reserved (do not use)

8

[1] Read (R): A register can be read. Read-only if this is the only mode given.

[2] Write (W): The pattern on the data bus will be written over all bits of a register.

[3] Set (S): The pattern on the data bus is OR-ed with and written to a register.

[4] Clear (C): The pattern on the data bus is a mask. If a bit in the mask is set, then the corresponding register bit will be set to zero

(cleared).

10.1 Immediate register set

10.1.1 Vendor ID and Product ID registers

10.1.1.1 Vendor ID Low register

Table 18 shows the bit description of the register.

Table 18. Vendor ID Low register (address R = 00h) bit description

Bit

Symbol

Access Value Description

7 to 0

VENDOR_ID_

LOW[7:0]

R

CCh

Vendor ID Low: Lower byte of the NXP vendor ID supplied by USB-IF;

has a ﬁxed value of CCh

ISP1504A_ISP1504C_1

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ISP1504A; ISP1504C

NXP Semiconductors

ULPI HS USB OTG transceiver

10.1.1.2 Vendor ID High register

The bit description of the register is given in Table 19.

Table 19. Vendor ID High register (address R = 01h) bit description

Bit

Symbol

Access Value

04h

Description

7 to 0

VENDOR_ID_

HIGH[7:0]

R

Vendor ID High: Upper byte of the NXP vendor ID supplied by USB-IF;

has a ﬁxed value of 04h

10.1.1.3 Product ID Low register

The bit description of the Product ID Low register is given in Table 20.

Table 20. Product ID Low register (address R = 02h) bit description

Bit

Symbol

Access Value

04h

Description

7 to 0

PRODUCT_ID_ R

LOW[7:0]

Product ID Low: Lower byte of the NXP product ID number; has a ﬁxed

value of 04h

10.1.1.4 Product ID High register

The bit description of the register is given in Table 21.

Table 21. Product ID High register (address R = 03h) bit description

Bit

Symbol

Access

Value

Description

7 to 0

PRODUCT_ID_ R

HIGH[7:0]

15h

Product ID High: Upper byte of the NXP product ID number; has a ﬁxed

value of 15h

10.1.2 Function Control register

This register controls UTMI function settings of the PHY. The bit allocation of the register

is given in Table 22.

Table 22. Function Control register (address R = 04h to 06h, W = 04h, S = 05h, C = 06h) bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

reserved

SUSPENDM

RESET

OPMODE[1:0]

TERM

XCVRSELECT[1:0]

SELECT

Reset

0

1

0

1

Access

R/W/S/C

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ISP1504A; ISP1504C

NXP Semiconductors

ULPI HS USB OTG transceiver

Table 23. Function Control register (address R = 04h to 06h, W = 04h, S = 05h, C = 06h) bit description

Bit

7

Symbol

Description

-

reserved

6

SUSPENDM

Suspend LOW: Active LOW PHY suspend.

Places the PHY into low-power mode. The PHY will power down all blocks, except the

full-speed receiver, OTG comparators and ULPI interface pins.

To come out of low-power mode, the link must assert STP. The PHY will automatically clear

this bit when it exits low-power mode.

0b — Low-power mode

1b — Powered (default)

5

RESET

Reset: Active HIGH transceiver reset.

After the link sets this bit, the PHY will assert DIR and reset the digital core. This does not

reset the ULPI interface or the ULPI register set.

When reset is completed, the PHY will de-assert DIR and automatically clear this bit, followed

by an RXCMD update to the link.

0b — Do not reset (default)

1b — Reset

The link must wait for DIR to de-assert before using the ULPI bus. Does not reset the ULPI

interface or the ULPI register set.

4 to 3

OPMODE[1:0] Operation Mode: Selects the required bit-encoding style during transmit.

00b — Normal operation (default)

01b — Non-driving

10b — Disable bit-stufﬁng and NRZI encoding

11b — Do not automatically add SYNC and EOP when transmitting; must be used only for

high-speed packets

2

TERMSELECT Termination Select: Controls the internal 1.5 kΩ full-speed pull-up resistor and 45 Ω

high-speed terminations. Control over bus resistors changes, depending on

XCVRSELECT[1:0], OPMODE[1:0], DP_PULLDOWN and DM_PULLDOWN, as shown in

Table 8.

1 to 0

XCVRSELECT Transceiver Select: Selects the required transceiver speed.

[1:0]

00b — Enable the high-speed transceiver

01b — Enable the full-speed transceiver (default)

10b — Enable the low-speed transceiver

11b — Enable the full-speed transceiver for low-speed packets (full-speed preamble is

automatically preﬁxed)

10.1.3 Interface Control register

The Interface Control register enables alternative interfaces. All of these modes are

optional features provided for legacy link cores. Setting more than one of these ﬁelds

results in undeﬁned behavior. Table 24 provides the bit allocation of the register.

Table 24. Interface Control register (address R = 07h to 09h, W = 07h, S = 08h, C = 09h) bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

INTF_

PROT_DIS

IND_PASS

THRU

IND_

COMPL

reserved

CLOCK_

SUSPENDM

reserved

3PIN_

FSLS_

SERIAL

6PIN_

FSLS_

SERIAL

Reset

0

Access

R/W/S/C

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ISP1504A; ISP1504C

NXP Semiconductors

ULPI HS USB OTG transceiver

Table 25. Interface Control register (address R = 07h to 09h, W = 07h, S = 08h, C = 09h) bit description

Bit

Symbol

Description

7

INTF_PROT_DIS

Interface Protect Disable: Controls circuitry built into the ISP1504 to protect the ULPI

interface when the link 3-states STP and DATA[7:0]. When this bit is enabled, the ISP1504

will automatically detect when the link stops driving STP.

0b — Enables the interface protect circuit (default). The ISP1504 attaches a weak pull-up

resistor on STP. If STP is unexpectedly HIGH, the ISP1504 attaches weak pull-down

resistors on DATA[7:0], protecting data inputs.

1b — Disables the interface protect circuit, detaches weak pull-down resistors on

DATA[7:0], and a weak pull-up resistor on STP.

6

5

IND_PASSTHRU

Indicator Pass-through: Controls whether the complement output is qualiﬁed with the

internal A_VBUS_VLD comparator before being used in the V_BUSstate in RXCMD. For

details, see Section 9.5.2.2.

0b — The complement output signal is qualiﬁed with the internal A_VBUS_VLD

comparator (default).

1b — The complement output signal is not qualiﬁed with the internal A_VBUS_VLD

comparator.

IND_COMPL

Indicator Complement: Informs the PHY to invert the FAULT input signal, generating the

complement output. For details, see Section 9.5.2.2.

0b — The ISP1504 will not invert the FAULT signal (default).

1b — The ISP1504 will invert the FAULT signal.

reserved

4

3

-

CLOCK_SUSPENDM Clock Suspend LOW: Active LOW clock suspend.

Powers down the internal clock circuitry only. By default, the clock will not be powered in

6-pin serial mode or 3-pin serial mode.

Valid only in 6-pin serial mode and 3-pin serial mode. Valid only when SUSPENDM is set

to logic 1, otherwise this bit is ignored.

0b — Clock will not be powered in 3-pin or 6-pin serial mode (default).

1b — Clock will be powered in 3-pin and 6-pin serial mode.

reserved

2

1

-

3PIN_FSLS_SERIAL

3-Pin Full-Speed Low-Speed Serial Mode: Changes the ULPI interface to a 3-bit serial

interface. The PHY will automatically clear this bit when 3-pin serial mode is exited.

0b — Full-speed or low-speed packets are sent using the parallel interface (default).

1b — Full-speed or low-speed packets are sent using the 3-pin serial interface.

0

6PIN_FSLS_SERIAL

6-Pin Full-Speed Low-Speed Serial Mode: Changes the ULPI interface to a 6-bit serial

interface. The PHY will automatically clear this bit when 6-pin serial mode is exited.

0b — Full-speed or low-speed packets are sent using the parallel interface (default).

1b — Full-speed or low-speed packets are sent using the 6-pin serial interface.

10.1.4 OTG Control register

This register controls various OTG functions of the ISP1504. The bit allocation of the OTG

Control register is given in Table 26.

Table 26. OTG Control register (address R = 0Ah to 0Ch, W = 0Ah, S = 0Bh, C = 0Ch) bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

USE_EXT_

VBUS_IND VBUS_EXT

DRV_

VBUS

CHRG_

VBUS

DISCHRG_ DM_PULL

DP_PULL

DOWN

ID_PULL

UP

VBUS

DOWN

Reset

0

1

0

Access

R/W/S/C

ISP1504A_ISP1504C_1

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ISP1504A; ISP1504C

NXP Semiconductors

ULPI HS USB OTG transceiver

Table 27. OTG Control register (address R = 0Ah to 0Ch, W = 0Ah, S = 0Bh, C = 0Ch) bit description

Bit

Symbol

Description

7

USE_EXT_VBUS_

IND

Use External V_BUSIndicator: Informs the PHY to use an external V_BUSovercurrent indicator.

0b — Use the internal OTG comparator (default).

1b — Use the external V_BUSvalid indicator signal input from the FAULT pin.

6

DRV_VBUS_EXT

Drive V_BUSExternal: Selects between the internal and external 5 V V_BUSsupply. Using an

external charge pump or a 5 V supply is optional.

0b — Drive V_BUSusing the internal charge pump. Also ensures PSW_N is not driven to LOW

(default).

1b — Drive V_BUSusing the external charge pump or the 5 V supply. Drives PSW_N to LOW.

5

4

DRV_VBUS

Drive V_BUS: Signals the ISP1504 to drive 5 V on V_BUS. If DRV_VBUS_EXT is set to logic 1,

then setting DRV_VBUS is optional.

0b — Do not drive V_BUS(default).

1b — Drive 5 V on V_BUS

.

CHRG_VBUS

Charge V_BUS: Charges V_BUSthrough a resistor. Used for the V_BUSpulsing SRP. The link must

ﬁrst check that V_BUSis discharged (see bit DISCHRG_VBUS), and that both the DP and DM

data lines have been LOW (SE0) for 2 ms.

0b — Do not charge V_BUS(default).

1b — Charge V_BUS

.

3

DISCHRG_VBUS

Discharge V_BUS: Discharges V_BUSthrough a resistor. If the link sets this bit to logic 1, it waits

for an RXCMD indicating that SESS_END has changed from 0 to 1, and then resets this bit to

0 to stop the discharge.

0b — Do not discharge V_BUS(default).

1b — Discharge V_BUS

.

2

1

0

DM_PULLDOWN

DP_PULLDOWN

ID_PULLUP

DM Pull Down: Enables the 15 kΩ pull-down resistor on DM.

0b — Pull-down resistor is not connected to DM.

1b — Pull-down resistor is connected to DM (default).

DP Pull Down: Enables the 15 kΩ pull-down resistor on DP.

0b — Pull-down resistor is not connected to DP.

1b — Pull-down resistor is connected to DP (default).

ID Pull Up: Connects a pull-up to the ID line and enables sampling of the ID level. Disabling

the ID line sampler will reduce PHY power consumption.

0b — Disables sampling of the ID line (default).

1b — Enables sampling of the ID line.

10.1.5 USB Interrupt Enable Rising Edge register

The bits in this register enable interrupts and RXCMDs to be sent when the corresponding

bits in the USB Interrupt Status register change from logic 0 to logic 1. By default, all

transitions are enabled. Table 28 shows the bit allocation of the register.

Table 28. USB Interrupt Enable Rising Edge register (address R = 0Dh to 0Fh, W = 0Dh, S = 0Eh, C = 0Fh) bit

allocation

Bit

7

6

5

4

3

2

1

0

Symbol

reserved

ID_GND_R

SESS_

END_R

SESS_

VALID_R

VBUS_

VALID_R DISCON_R

HOST_

Reset

0

1

Access

R/W/S/C

ISP1504A_ISP1504C_1

Product data sheet

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51 of 84

ISP1504A; ISP1504C

NXP Semiconductors

ULPI HS USB OTG transceiver

Table 29. USB Interrupt Enable Rising Edge register (address R = 0Dh to 0Fh, W = 0Dh, S = 0Eh, C = 0Fh) bit

description

Bit

7 to 5

4

Symbol

-

Description

reserved

ID_GND_R

SESS_END_R

ID Ground Rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on ID_GND.

3

Session End Rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on

SESS_END.

2

1

SESS_VALID_R

VBUS_VALID_R

Session Valid Rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on

SESS_VLD.

V_BUSValid Rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on

A_VBUS_VLD.

0

HOST_DISCON_ Host Disconnect Rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on

R

HOST_DISCON.

10.1.6 USB Interrupt Enable Falling Edge register

The bits in this register enable interrupts and RXCMDs to be sent when the corresponding

bits in the USB Interrupt Status register change from logic 1 to logic 0. By default, all

transitions are enabled. See Table 30.

Table 30. USB Interrupt Enable Falling Edge register (address R = 10h to 12h, W = 10h, S = 11h, C = 12h) bit

allocation

Bit

7

6

5

4

3

2

1

0

Symbol

reserved

ID_GND_F

SESS_

END_F

SESS_

VALID_F

VBUS_

VALID_F

HOST_

DISCON_F

Reset

0

1

Access

R/W/S/C

Table 31. USB Interrupt Enable Falling Edge register (address R = 10h to 12h, W = 10h, S = 11h, C = 12h) bit

description

Bit

7 to 5

4

Symbol

Description

-

reserved

ID_GND_F

ID Ground Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on

ID_GND.

3

2

1

SESS_END_F

SESS_VALID_F

VBUS_VALID_F

Session End Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on

SESS_END.

Session Valid Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on

SESS_VLD.

V_BUSValid Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on

A_VBUS_VLD.

0

HOST_DISCON_F Host Disconnect Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on

HOST_DISCON.

10.1.7 USB Interrupt Status register

This register (see Table 32) indicates the current value of the interrupt source signal.

ISP1504A_ISP1504C_1

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52 of 84

ISP1504A; ISP1504C

NXP Semiconductors

ULPI HS USB OTG transceiver

Table 32. USB Interrupt Status register (address R = 13h) bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

reserved

ID_GND

SESS_

END

SESS_

VALID

VBUS_

VALID

HOST_

DISCON

Reset

X

R

X

R

X

R

0

Access

R

Table 33. USB Interrupt Status register (address R = 13h) bit description

Bit

Symbol

Description

7 to 5

-

reserved

4

3

2

1

0

ID_GND

ID Ground: Reﬂects the current value of the ID detector circuit.

SESS_END

SESS_VALID

VBUS_VALID

HOST_DISCON

Session End: Reﬂects the current value of the session end voltage comparator.

Session Valid: Reﬂects the current value of the session valid voltage comparator.

V_BUSValid: Reﬂects the current value of the V_BUSvalid voltage comparator.

Host Disconnect: Reﬂects the current value of the host disconnect detector.

10.1.8 USB Interrupt Latch register

The bits of the USB Interrupt Latch register are automatically set by the ISP1504 when an

unmasked change occurs on the corresponding interrupt source signal. The ISP1504 will

automatically clear all bits when the link reads this register, or when the PHY enters

low-power mode.

Remark: It is optional for the link to read this register when the clock is running because

all signal information will automatically be sent to the link through the RXCMD byte.

The bit allocation of this register is given in Table 34.

Table 34. USB Interrupt Latch register (address R = 14h) bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

reserved

ID_GND_L

SESS_

END_L

SESS_

VALID_L

VBUS_

VALID_L

HOST_

DISCON_L

Reset

0

Access

R

Table 35. USB Interrupt Latch register (address R = 14h) bit description

Bit

7 to 5

4

Symbol

Description

-

reserved

ID_GND_L

ID Ground Latch: Automatically set when an unmasked event occurs on ID_GND. Cleared

when this register is read.

3

2

1

SESS_END_L

SESS_VALID_L

VBUS_VALID_L

Session End Latch: Automatically set when an unmasked event occurs on SESS_END.

Cleared when this register is read.

Session Valid Latch: Automatically set when an unmasked event occurs on SESS_VLD.

Cleared when this register is read.

V_BUSValid Latch: Automatically set when an unmasked event occurs on A_VBUS_VLD.

Cleared when this register is read.

0

HOST_DISCON_L Host Disconnect Latch: Automatically set when an unmasked event occurs on

HOST_DISCON. Cleared when this register is read.

ISP1504A_ISP1504C_1

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53 of 84

ISP1504A; ISP1504C

NXP Semiconductors

ULPI HS USB OTG transceiver

10.1.9 Debug register

The bit allocation of the Debug register is given in Table 36. This register indicates the

current value of signals useful for debugging.

Table 36. Debug register (address R = 15h) bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

reserved

LINE

STATE1

STATE0

Reset

0

Access

R

Table 37. Debug register (address R = 15h) bit description

Bit

7 to 2

1

Symbol

-

Description

reserved

LINESTATE1

LINESTATE0

Line State 1: Contains the current value of LINESTATE 1.

Line State 0: Contains the current value of LINESTATE 0.

0

10.1.10 Scratch register

This is an empty register for testing purposes; see Table 38.

Table 38. Scratch register (address R = 16h to 18h, W = 16h, S = 17h, C = 18h) bit description

Bit

Symbol

Access

Value

Description

7 to 0

SCRATCH[7:0] R/W/S/C

00h

Scratch: This is an empty register byte for testing purposes.

Software can read, write, set and clear this register; and the

functionality of the PHY will not be affected.

10.1.11 Reserved

Registers 19h to 2Eh are not implemented. Operating on these addresses will have no

effect on the PHY.

10.1.12 Access extended register set

Address 2Fh does not contain register data. Instead it links to the extended register set.

The immediate register set maps to the lower end of the extended register set.

10.1.13 Vendor-speciﬁc registers

Addresses 30h to 3Fh contains vendor-speciﬁc registers.

10.1.14 Power Control register

This register controls various aspects of the ISP1504. Table 39 shows the bit allocation of

the register.

Table 39. Power Control register (address R = 3Dh to 3Fh, W = 3Dh, S = 3Eh, C = 3Fh) bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

reserved

BVALID_

FALL

BVALID_

RISE

reserved

Reset

0

Access

R/W/S/C

ISP1504A_ISP1504C_1

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ISP1504A; ISP1504C

NXP Semiconductors

ULPI HS USB OTG transceiver

Table 40. Power Control register (address R = 3Dh to 3Fh, W = 3Dh, S = 3Eh, C = 3Fh) bit description

Bit

7 to 4

3

Symbol

Description

-

reserved; the link must never write logic 1 to these bits.

BVALID_FALL

BValid Fall: Enables RXCMDs for HIGH-to-LOW transitions on BVALID. When BVALID

changes from HIGH to LOW, the ISP1504 will send an RXCMD to the link with the ALT_INT bit

set to logic 1.

This bit is optional and is not necessary for OTG devices. The session valid comparator should

be used instead.

2

BVALID_RISE

BValid Rise: Enables RXCMDs for LOW-to-HIGH transitions on BVALID. When BVALID

changes from LOW to HIGH, the ISP1504 will send an RXCMD to the link with the ALT_INT bit

set to logic 1.

This bit is optional and is not necessary for OTG devices. The session valid comparator should

be used instead.

1 to 0

-

reserved; the link must never write logic 1 to this bit.

10.2 Extended register set

Addresses 00h to 3Fh of the extended register set directly map to the immediate set. This

means a read, write, set or clear operation to these extended addresses will operate on

the immediate register set.

Addresses 40h to FFh are not implemented. Operating on these addresses will have no

effect on the PHY.

ISP1504A_ISP1504C_1

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ISP1504A; ISP1504C

NXP Semiconductors

ULPI HS USB OTG transceiver

11. ElectroStatic Discharge (ESD)

11.1 ESD protection

The pins that are connected to the USB connector (DP, DM, ID, V_BUSand GND) have a

minimum of ±4 kV ESD protection. Capacitors 0.1 µF and 1 µF must be connected in

parallel from V_BUSto GND to achieve this ±4 kV ESD protection (see Figure 24).

Remark: Capacitors 0.1 µF and 1 µF are also required by Universal Serial Bus

Speciﬁcation Rev. 2.0. For details on the requirements for C_VBUS, see Section 16.

R

1 MΩ

R

D

1500 Ω

C

charge current

limit resistor

discharge

resistance

DEVICE UNDER

TEST

V

BUS

A

B

HIGH VOLTAGE

DC SOURCE

storage

capacitor

0.1 µF

1 µF

C

S

100 pF

GND

004aaa881

Fig 24. Human body ESD test model

11.2 ESD test conditions

A detailed report on test setup and results is available on request.

ISP1504A_ISP1504C_1

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56 of 84

ISP1504A; ISP1504C

NXP Semiconductors

ULPI HS USB OTG transceiver

12. Limiting values

Table 41. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_CC

Parameter

Conditions

Min

−0.5

Max

Unit

V

supply voltage

+4.6

V_CC(I/O)

V_I

input/output supply voltage

input voltage

+4.6

V

on pins CLOCK, STP, DATA[7:0],

RESET_N and CHIP_SELECT_N

V_CC(I/O)+ 0.5 V

V

on pins V_BUS, FAULT and PSW_N

on pin XTAL1

−0.5

−4

+6.0

+2.5

+4.6

+4

V

on pin ID

V

[1]

V_ESD

electrostatic discharge

voltage

pins DP, DM, ID, V_BUSand GND;

kV

I_LI< 1 µA

all other pins; I_LI< 1 µA

−1.5

-

+1.5

100

kV

mA

°C

I_lu

latch-up current

−0.5 × V_CC< V < +1.5 × V_CC

T_stg

T_j

storage temperature

junction temperature

−40

+125

[1] Equivalent to discharging a 100 pF capacitor through a 1.5 kΩ resistor (Human Body Model JESD22-A114D).

13. Recommended operating conditions

Table 42. Recommended operating conditions

Symbol

V_CC

Parameter

Conditions

Min

3.0

1.65

0

Typ

Max

3.6

Unit

supply voltage

3.3

V

[1]

V_CC(I/O)

V_I

input/output supply voltage

input voltage

-

3.6

on pins CLOCK, STP, DATA[7:0],

RESET_N and CHIP_SELECT_N

V_CC(I/O)

on pins V_BUS, FAULT and PSW_N

on pins DP, DM and ID

on pin XTAL1

0

-

5.5

V

0

-

3.6

V

0

-

1.95

+85

V

T_amb

ambient temperature

−40

+25

°C

[1] V_CC(I/O)should be less than or equal to V_CC

.

ISP1504A_ISP1504C_1

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57 of 84

ISP1504A; ISP1504C

NXP Semiconductors

ULPI HS USB OTG transceiver

14. Static characteristics

Table 43. Static characteristics: supply pins

V_CC= 3.0 V to 3.6 V; V_CC(I/O)= 1.65 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Typical values are at V_CC= 3.3 V; V_CC(I/O)= 3.3 V; T_amb= +25 °C; unless otherwise speciﬁed.

Symbol Parameter

Conditions

Min

3.0

Typ

3.3

1.8

-

Max

3.6

Unit

V

V_(REG3V3)voltage on pin REG3V3

V_(REG1V8)voltage on pin REG1V8

V_POR(trip)power-on reset trip voltage

1.65

1.0

1.95

1.5

V

I_CC

supply current

charge pump disabled

low-power mode; V_BUSvalid detector

disabled; 1.5 kΩ pull-up resistor on

pin DP disconnected

-

35

85

µA

low-power mode; V_BUSvalid detector

disabled; 1.5 kΩ pull-up resistor on

pin DP connected

215

280

full-speed idle; no USB activity

high-speed idle; no USB activity

-

10

19

15

-

mA

[1]

full-speed continuous data transmit,

50 pF load on pins DP and DM

[1]

full-speed continuous data receive

-

11

48

-

mA

high-speed continuous data transmit,

45 Ω load on pins DP and DM to ground

[1]

high-speed continuous data receive

charge pump enabled

-

28

-

mA

I_O(VBUS)= 8 mA; charge pump supply

current only

-

20

300

-

23

-

mA

µA

I_O(VBUS)= 0 mA; charge pump supply

current only

I_CC(I/O)

supply current on

pin V_CC(I/O)

ULPI interface pins are static

1

[1] A continuous stream of 1 kB packets with minimum inter-packet gap and all data bits set to logic 0 for continuous toggling.

Table 44. Static characteristics: digital pins (CLOCK, DIR, STP, NXT, DATA[7:0], RESET_N, CHIP_SELECT_N)

V_CC= 3.0 V to 3.6 V; V_CC(I/O)= 1.65 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Typical values are at V_CC= 3.3 V; V_CC(I/O)= 3.3 V; T_amb= +25 °C; unless otherwise speciﬁed.

Symbol Parameter

Input levels

Conditions

Min

Typ

Max

Unit

V_IL

V_IH

I_IL

LOW-level input voltage

-

0.3 × V_CC(I/O)

V

HIGH-level input voltage

LOW-level input current

HIGH-level input current

input leakage current

0.7 × V_CC(I/O)

-

V

V_I= 0 V

-

1

µA

I_IH

I_LI

V_I= V_CC(I/O)

-

1

−1

+0.1

+1

Output levels

V_OL

V_OH

LOW-level output voltage I_OL= −2 mA

-

0.4

-

V

HIGH-level output voltage I_OH= +2 mA

V_CC(I/O)− 0.4 V

ISP1504A_ISP1504C_1

Product data sheet

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58 of 84

ISP1504A; ISP1504C

NXP Semiconductors

ULPI HS USB OTG transceiver

Table 44. Static characteristics: digital pins (CLOCK, DIR, STP, NXT, DATA[7:0], RESET_N, CHIP_SELECT_N)

…continued

V_CC= 3.0 V to 3.6 V; V_CC(I/O)= 1.65 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol Parameter

Conditions

Min

−4.8

4.2

-

Typ

Max

Unit

mA

µA

I_OH

HIGH-level output current V_O= V_CC(I/O)− 0.4 V

-

I_OL

LOW-level output current V_O= 0.4 V

-

I_OZ

off-state output current

0 V < V_O< V_CC(I/O)

1

Impedance

Z_L

load impedance

45

25

-

65

90

Ω

Pull-up and pull-down

I_pdpull-down current

interface protect enabled;

DATA[7:0] pins only;

V_I= V_CC(I/O)

50

µA

I_pu

pull-up current

interface protect enabled;

STP pin only; V_I= 0 V

−30

−50

−80

µA

Capacitance

C_ininput capacitance

pins STP, RESET_N,

CLOCK, DATA[7:0],

CHIP_SELECT_N

-

3.5

pF

Table 45. Static characteristics: digital pin FAULT

V_CC= 3.0 V to 3.6 V; V_CC(I/O)= 1.65 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Typical values are at V_CC= 3.3 V; V_CC(I/O)= 3.3 V; T_amb= +25 °C; unless otherwise speciﬁed.

Symbol Parameter

Input levels

Conditions

Min

Typ

Max

Unit

V_IL

V_IH

I_IL

LOW-level input voltage

-

0.8

-

V

HIGH-level input voltage

LOW-level input current

HIGH-level input current

2.0

V

V_I= 0 V

-

1

µA

I_IH

V_I= V_CC(I/O)

1

Table 46. Static characteristics: digital pin PSW_N

V_CC= 3.0 V to 3.6 V; V_CC(I/O)= 1.65 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Typical values are at V_CC= 3.3 V; V_CC(I/O)= 3.3 V; T_amb= +25 °C; unless otherwise speciﬁed.

Symbol Parameter

Output levels

Conditions

Min

Typ

Max

Unit

V_OH

HIGH-level output voltage external pull-up resistor

connected

-

5.5

V

V_OL

I_OH

LOW-level output voltage

HIGH-level output current

I_OL= −4 mA

-

0.4

1

V

external pull-up resistor

connected

µA

I_OL

LOW-level output current

V_O= 0.4 V

4.0

-

mA

ISP1504A_ISP1504C_1

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ISP1504A; ISP1504C

NXP Semiconductors

ULPI HS USB OTG transceiver

Table 47. Static characteristics: analog I/O pins (DP, DM)

V_CC= 3.0 V to 3.6 V; V_CC(I/O)= 1.65 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Typical values are at V_CC= 3.3 V; V_CC(I/O)= 3.3 V; T_amb= +25 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Original USB transceiver (low-speed and full-speed)

Input levels (differential receiver)

V_DI

differential input sensitivity

|V_DP− V_DM

|

0.2

0.8

-

V

V_CM

differential common mode voltage

range

includes V_DIrange

2.5

Input levels (single-ended receivers)

V_IL

LOW-level input voltage

HIGH-level input voltage

-

0.8

-

V

V_IH

2.0

Output levels

V_OL

LOW-level output voltage

HIGH-level output voltage

pull-up on pin DP;

R_L= 1.5 kΩ to 3.6 V

0.0

2.8

0.18

3.2

0.3

3.6

V

V_OH

pull-down on

pins DP and DM;

R_L= 15 kΩ to GND

Termination

V_TERM

termination voltage

for 1.5 kΩ pull-up

3.0

-

3.6

V

resistor

Resistance

R_UP(DP)

pull-up resistance on pin DP

1425

1500

1575

Ω

High-speed USB transceiver

Input levels (differential receiver)

V_HSSQ

high-speed squelch detection

threshold voltage (differential signal

amplitude)

100

525

-

150

625

mV

V_HSDSC

high-speed disconnect detection

threshold voltage (differential signal

amplitude)

V_HSDI

high-speed differential input sensitivity |V_DP− V_DM

|

300

-

mV

V_HSCM

high-speed data signaling

includes V_DIrange

−50

+500

common-mode voltage range

V_HSOI

high-speed idle level

−10

-

+10

mV

V_HSOL

high-speed data signaling low

Output levels

V_HSOH

high-speed data signaling high

Chirp J level (differential voltage)

Chirp K level (differential voltage)

360

-

440

mV

V_CHIRPJ

V_CHIRPK

Leakage current

700

1100

−500

−900

I_LZ

off-state leakage current

−1

-

+1

5

µA

Capacitance

C_in

input capacitance

pin to GND

-

pF

ISP1504A_ISP1504C_1

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Rev. 01 — 19 October 2006

60 of 84

ISP1504A; ISP1504C

NXP Semiconductors

ULPI HS USB OTG transceiver

Table 47. Static characteristics: analog I/O pins (DP, DM) …continued

V_CC= 3.0 V to 3.6 V; V_CC(I/O)= 1.65 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Typical values are at V_CC= 3.3 V; V_CC(I/O)= 3.3 V; T_amb= +25 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Resistance

R_DN(DP)

pull-down resistance on pin DP

pull-down resistance on pin DM

14.25

15

15.75

kΩ

R_DN(DM)

Termination

[1]

Z_O(drv)(DP)driver output impedance on pin DP

Z_O(drv)(DM)driver output impedance on pin DM

steady-state drive

40.5

10

45

-

49.5

-

Ω

Z_INP

input impedance

MΩ

[1] For high-speed USB and full-speed USB.

Table 48. Static characteristics: charge pump

V_CC= 3.0 V to 3.6 V; V_CC(I/O)= 1.65 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Typical values are at V_CC= 3.3 V; V_CC(I/O)= 3.3 V; T_amb= +25 °C; unless otherwise speciﬁed.

Symbol

Voltage

V_O(VBUS)

Parameter

Conditions

Min

Typ

Max

Unit

output voltage on pin V_BUS

I_O(VBUS)= 50 mA;

4.65

-

5.0

-

5.25

0.2

V

C

_{cp(C_A)-(C_B)}= 270 nF

V_L(VBUS)

Current

I_O(VBUS)

Efﬁciency

η_cp

leakage voltage on pin V_BUScharge pump disabled

output current on pin V_BUS

charge pump efﬁciency

C_{cp(C_A)-(C_B)}= 270 nF

45

60

75

72

-

mA

%

I_O(VBUS)= 50 mA

78

Table 49. Static characteristics: V_BUScomparators

V_CC= 3.0 V to 3.6 V; V_CC(I/O)= 1.65 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Typical values are at V_CC= 3.3 V; V_CC(I/O)= 3.3 V; T_amb= +25 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

4.4

0.8

Typ

4.5

1.6

Max

4.65

2.0

Unit

V_{A_VBUS_VLD}

V_{B_SESS_VLD}

A-device V_BUSvalid voltage

B-device session valid voltage

V

for A-device and

B-device

V_{hys(B_SESS_VLD)}B-device session valid hysteresis voltage

70

90

110

0.8

mV

V

V_{B_SESS_END}

B-device session end voltage

0.2

0.5

ISP1504A_ISP1504C_1

Product data sheet

Rev. 01 — 19 October 2006

61 of 84

ISP1504A; ISP1504C

NXP Semiconductors

ULPI HS USB OTG transceiver

Table 50. Static characteristics: V_BUSresistors

V_CC= 3.0 V to 3.6 V; V_CC(I/O)= 1.65 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Typical values are at V_CC= 3.3 V; V_CC(I/O)= 3.3 V; T_amb= +25 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

R_UP(VBUS)

pull-up resistance on pin V_BUS

connect to pin REG3V3

when CHRG_VBUS is

logic 1

281

680

-

Ω

R_DN(VBUS)

pull-down resistance on pin V_BUSconnect to GND when

656

1100

-

Ω

DISCHRG_VBUS is

logic 1

R_{I(idle)(VBUS)(A)}

R_{I(idle)(VBUS)(B)}

idle input resistance on pin V_BUSID pin LOW and charge

40

57

80

kΩ

(A-device)

idle input resistance on pin V_BUSID pin HIGH or charge

(B-device) pump enabled

pump disabled

170

240

310

Table 51. Static characteristics: ID detection circuit

V_CC= 3.0 V to 3.6 V; V_CC(I/O)= 1.65 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Typical values are at V_CC= 3.3 V; V_CC(I/O)= 3.3 V; T_amb= +25 °C; unless otherwise speciﬁed.

Symbol Parameter

Conditions

Min

50

Typ

-

Max

Unit

ms

V

t_ID

ID detection time

-

V_th(ID)

R_UP(ID)

ID detector threshold voltage

ID pull-up resistance

0.8

40

1.2

50

2.0

60

ID_PULLUP is logic 1

kΩ

Table 52. Static characteristics: resistor reference

V_CC= 3.0 V to 3.6 V; V_CC(I/O)= 1.65 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Typical values are at V_CC= 3.3 V; V_CC(I/O)= 3.3 V; T_amb= +25 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_O(RREF)

output voltage on pin RREF SUSPENDM is logic 1

-

1.22

-

V

ISP1504A_ISP1504C_1

Product data sheet

Rev. 01 — 19 October 2006

62 of 84

ISP1504A; ISP1504C

NXP Semiconductors

ULPI HS USB OTG transceiver

004aaa876

004aaa877

5.50

120

I

CC(cp)

(mA)

=

3.6 V

3.3 V

3.0 V

V

CC

V

O(VBUS)

(V)

100

=

3.6 V

3.3 V

3.0 V

V

CC

5.00

4.50

4.00

80

60

40

20

0

10

20

30

40

O(VBUS)

50

(mA)

0

10

20

30

40

O(VBUS)

50

I

(mA)

I

I_CC(cp)denotes charge pump supply current.

Fig 25. Charge pump supply current vs. V_BUSoutput

current

Fig 26. V_BUSoutput voltage vs. V_BUSoutput current

004aaa879

004aaa878

108

5.50

I

= 0 mA

8 mA

O(VBUS)

I

CC(cp)

(mA)

V

O(VBUS)

(V)

50 mA

106

5.00

4.50

4.00

I

= 50 mA

O(VBUS)

104

102

100

−40

−20

0

+20

+40 +60 +80 +100

(°C)

3

3.1

3.2

3.3

3.4

3.5

CC(cp)

3.6

(V)

T

V

amb

V_CC(cp)denotes charge pump supply voltage.

I_CC(cp)denotes charge pump supply current.

Fig 27. V_BUSoutput voltage vs. charge pump supply

voltage

Fig 28. Charge pump supply current vs. temperature

ISP1504A_ISP1504C_1

Product data sheet

Rev. 01 — 19 October 2006

63 of 84

ISP1504A; ISP1504C

NXP Semiconductors

ULPI HS USB OTG transceiver

15. Dynamic characteristics

Table 53. Dynamic characteristics: reset and clock

V_CC= 3.0 V to 3.6 V; V_CC(I/O)= 1.65 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Typical values are at V_CC= 3.3 V; V_CC(I/O)= 3.3 V; T_amb= +25 °C; unless otherwise speciﬁed.

Symbol

Reset

Parameter

Conditions

Min

Typ

Max

Unit

t_W(POR)

internal power-on reset pulse

width

0.2

-

µs

t_{w(REG1V8_H)}

t_{w(REG1V8_L)}

t_{W(RESET_N)}

t_PWRUP

REG1V8 HIGH pulse width

REG1V8 LOW pulse width

external RESET_N pulse width

regulator start-up time

2

-

µs

ns

ms

11

200

-

4.7 µF ± 20 %

1

capacitor each on pins

REG1V8 and REG3V3

Crystal or clock applied to XTAL1

f_i(XTAL1)

input frequency on pin XTAL1

ISP1504ABS

ISP1504CBS

ISP1504ABS

ISP1504CBS

-

19.2

26

-

MHz

ps

-

[1]

t_{jit(i)(XTAL1)RMS}

RMS input jitter on pin XTAL1

200

300

200

-

ps

∆f_i(XTAL1)

t_r(XTAL1)

input frequency tolerance on

pin XTAL1

50

ppm

rise time on pin XTAL1

only for square wave

input

-

5

ns

V

t_f(XTAL1)

fall time on pin XTAL1

only for square wave

input

-

5

V_(XTAL1)(p-p)

peak-to-peak voltage on

pin XTAL1

only for square wave

input

0.566

1.95

External clock input on CLOCK

f_i(CLOCK)

input frequency on pin CLOCK

-

60

-

MHz

ps

[1]

t_{jit(i)(CLOCK)RMS}

∆f_i(CLOCK)

RMS input jitter on pin CLOCK

200

input frequency tolerance on

pin CLOCK

50

ppm

δ_i(CLOCK)

input clock duty cycle on

pin CLOCK

45

-

50

60

55

-

%

Output CLOCK characteristics

f_o(CLOCK)

output frequency on pin CLOCK active only when a

crystal or clock is input

MHz

on pin XTAL1

[1]

t_{jit(o)(CLOCK)RMS}RMS output jitter on pin CLOCK

-

500

55

ps

%

δ_o(CLOCK)

output clock duty cycle on

pin CLOCK

45

50

t_startup(PLL)

PLL startup time

-

650

-

µs

t_{startup(o)(CLOCK)}output CLOCK start-up time

measured from power

good or assertion of

pin STP

450

900

[1] RMS = Root Mean Square.

ISP1504A_ISP1504C_1

Product data sheet

Rev. 01 — 19 October 2006

64 of 84

ISP1504A; ISP1504C

NXP Semiconductors

ULPI HS USB OTG transceiver

Table 54. Dynamic characteristics: digital I/O pins

V_CC= 3.0 V to 3.6 V; V_CC(I/O)= 1.65 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Typical values are at V_CC= 3.3 V; T_amb= +25 °C; unless otherwise speciﬁed.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

Output 60 MHz CLOCK, V_CC(I/O)= 1.65 V to 1.95 V

t_su(DATA)

t_h(DATA)

t_d(DATA)

t_su(STP)

t_h(STP)

t_d(DIR)

DATA set-up time with respect to 20 pF total external load

5.7

0

-

ns

the rising edge of pin CLOCK

per pin

DATA hold time with respect to

the rising edge of pin CLOCK

20 pF total external load

per pin

-

DATA output delay with respect 20 pF total external load

to the rising edge of pin CLOCK per pin

-

7.8

-

STP set-up time with respect to 20 pF total external load

4.5

0

the rising edge of pin CLOCK

per pin

STP hold time with respect to

the rising edge of pin CLOCK

20 pF total external load

per pin

-

DIR output delay with respect to 20 pF total external load

the rising edge of pin CLOCK per pin

-

8.9

t_d(NXT)

NXT output delay with respect to 20 pF total external load

the rising edge of pin CLOCK per pin

-

Output 60 MHz CLOCK, V_CC(I/O)= 3.0 V to 3.6 V

t_su(DATA)

t_h(DATA)

t_d(DATA)

t_su(STP)

t_h(STP)

t_d(DIR)

DATA set-up time with respect to 30 pF total external load

3.3

0.8

-

ns

the rising edge of pin CLOCK

per pin

DATA hold time with respect to

the rising edge of pin CLOCK

30 pF total external load

per pin

-

DATA output delay with respect 30 pF total external load

to the rising edge of pin CLOCK per pin

5.5

-

STP set-up time with respect to 30 pF total external load

3.4

0.8

-

the rising edge of pin CLOCK

per pin

STP hold time with respect to

the rising edge of pin CLOCK

30 pF total external load

per pin

-

DIR output delay with respect to 30 pF total external load

the rising edge of pin CLOCK per pin

6.6

t_d(NXT)

NXT output delay with respect to 30 pF total external load

the rising edge of pin CLOCK per pin

-

Input 60 MHz CLOCK, V_CC(I/O)= 1.65 V to 1.95 V

t_su(DATA)

t_h(DATA)

t_d(DATA)

t_su(STP)

t_h(STP)

t_d(DIR)

DATA set-up time with respect to 10 pF total external load

4.9

0

4.4

-

ns

the rising edge of pin CLOCK

per pin

DATA hold time with respect to

the rising edge of pin CLOCK

10 pF total external load

per pin

-

DATA output delay with respect 10 pF total external load

to the rising edge of pin CLOCK per pin

9.2

3.5

0

5.2

3.4

-

STP set-up time with respect to 10 pF total external load

-

the rising edge of pin CLOCK

per pin

STP hold time with respect to

the rising edge of pin CLOCK

10 pF total external load

per pin

-

DIR output delay with respect to 10 pF total external load

the rising edge of pin CLOCK per pin

-

4.9

9.3

t_d(NXT)

NXT output delay with respect to 10 pF total external load

the rising edge of pin CLOCK per pin

-

ISP1504A_ISP1504C_1

Product data sheet

Rev. 01 — 19 October 2006

65 of 84

ISP1504A; ISP1504C

NXP Semiconductors

ULPI HS USB OTG transceiver

Table 54. Dynamic characteristics: digital I/O pins …continued

V_CC= 3.0 V to 3.6 V; V_CC(I/O)= 1.65 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Typical values are at V_CC= 3.3 V; T_amb= +25 °C; unless otherwise speciﬁed.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

Input 60 MHz CLOCK, V_CC(I/O)= 3.0 V to 3.6 V

t_su(DATA)

t_h(DATA)

t_d(DATA)

t_su(STP)

t_h(STP)

t_d(DIR)

DATA set-up time with respect to 20 pF total external load

3.4

0

3.0

-

ns

the rising edge of pin CLOCK

per pin

DATA hold time with respect to

the rising edge of pin CLOCK

20 pF total external load

per pin

DATA output delay with respect 20 pF total external load

to the rising edge of pin CLOCK per pin

7.7

3.1

0

4.1

2.7

-

STP set-up time with respect to 20 pF total external load

the rising edge of pin CLOCK

per pin

STP hold time with respect to

the rising edge of pin CLOCK

20 pF total external load

per pin

DIR output delay with respect to 20 pF total external load

the rising edge of pin CLOCK per pin

7.3

3.8

t_d(NXT)

NXT output delay with respect to 20 pF total external load

the rising edge of pin CLOCK per pin

Table 55. Dynamic characteristics: analog I/O pins (DP and DM)

V_CC= 3.0 V to 3.6 V; V_CC(I/O)= 1.65 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Typical values are at V_CC= 3.3 V; V_CC(I/O)= 3.3 V; T_amb= +25 °C; unless otherwise speciﬁed.

Symbol Parameter

High-speed driver

Conditions

Min

Typ

Max

Unit

t_HSR

t_HSF

Full-speed driver

rise time (10 % to 90 %)

500

-

ps

fall time (10 % to 90 %)

t_FR

rise time

C_L= 50 pF; 10 % to 90 % of

4

-

20

ns

%

V

|V_OH− V_OL

C_L= 50 pF; 10 % to 90 % of

|V_OH− V_OL

|

t_FF

fall time

4

20

|

t_FRFM

V_CRS

differential rise and fall

time matching

excluding the ﬁrst transition

from the idle state

90

1.3

111.1

2.0

output signal crossover

voltage

excluding the ﬁrst transition

from the idle state

Low-speed driver

t_LR

transition time: rise time

C_L= 200 pF to 600 pF;

1.5 kΩ pull-up on pin DM

enabled; 10 % to 90 % of

75

80

-

300

125

ns

%

|V_OH− V_OL

|

t_LF

transition time: fall time

C_L= 200 pF to 600 pF;

1.5 kΩ pull-up on pin DM

enabled; 10 % to 90 % of

|V_OH− V_OL

|

t_LRFM

rise and fall time matching t_LR/t_LF; excluding the ﬁrst

transition from the idle state

ISP1504A_ISP1504C_1

Product data sheet

Rev. 01 — 19 October 2006

66 of 84

ISP1504A; ISP1504C

NXP Semiconductors

ULPI HS USB OTG transceiver

Table 55. Dynamic characteristics: analog I/O pins (DP and DM) …continued

V_CC= 3.0 V to 3.6 V; V_CC(I/O)= 1.65 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Typical values are at V_CC= 3.3 V; V_CC(I/O)= 3.3 V; T_amb= +25 °C; unless otherwise speciﬁed.

Symbol Parameter

Driver timing

Conditions

Min

Typ

Max

Unit

t_PLH(drv)

t_PHL(drv)

t_PHZ

driver propagation delay

(LOW to HIGH)

TX_DAT, TX_SE0 to DP, DM;

see Figure 30

-

11

12

20

ns

driver propagation delay

(HIGH to LOW)

TX_DAT, TX_SE0 to DP, DM;

see Figure 30

driver disable delay from

HIGH level

TX_ENABLE to DP, DM;

see Figure 31

t_PLZ

driver disable delay from

LOW level

TX_ENABLE to DP, DM;

see Figure 31

t_PZH

driver enable delay to

HIGH level

TX_ENABLE to DP, DM;

see Figure 31

t_PZL

driver enable delay to

LOW level

TX_ENABLE to DP, DM;

see Figure 31

Receiver timing

Differential receiver

t_PLH(rcv)

receiver propagation

delay (LOW to HIGH)

DP, DM to RX_RCV, RX_DP

and RX_DM; see Figure 32

-

17

ns

t_PHL(rcv)

receiver propagation

delay (HIGH to LOW)

DP, DM to RX_RCV, RX_DP

and RX_DM; see Figure 32

Single-ended receiver

t_PLH(se)single-ended propagation DP, DM to RX_RCV, RX_DP

delay (LOW to HIGH) and RX_DM; see Figure 32

single-ended propagation DP, DM to RX_RCV, RX_DP

delay (HIGH to LOW) and RX_DM; see Figure 32

-

17

ns

t_PHL(se)

ISP1504A_ISP1504C_1

Product data sheet

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67 of 84

ISP1504A; ISP1504C

NXP Semiconductors

ULPI HS USB OTG transceiver

1.8 V

logic input 0.9 V

0 V

0.9 V

t

, t , t

HSF FF LF

t

, t , t

HSR FR LR

V

t

PHL(drv)

OH

PLH(drv)

90 %

V

OH

differential

data lines

V

CRS

10 %

V

OL

V

OL

004aaa573

004aaa861

Fig 29. Rise time and fall time

Fig 30. Timing of TX_DAT and TX_SE0 to DP and DM

2.0 V

1.8 V

differential

data lines

V

CRS

logic

input

0.9 V

0.8 V

0 V

t

PLH(rcv)

PHL(rcv)

t

PHZ

PZH

t

PHL(se)

t

PLH(se)

t

PLZ

PZL

V

OH

V

OH

V

− 0.3 V

OH

0.9 V

logic output

differential

data lines

V

CRS

V

+ 0.3 V

OL

V

OL

V

004aaa574

004aaa575

OL

Fig 31. Timing of TX_ENABLE to DP and DM

Fig 32. Timing of DP and DM to RX_RCV, RX_DP and

RX_DM

15.1 ULPI timing

ULPI interface timing requirements are given in Figure 33. This timing applies to

synchronous mode only. All timing is measured with respect to the ISP1504 CLOCK pin.

All signals are clocked on the rising edge of CLOCK.

CLOCK

t

su(STP) h(STP)

CONTROL IN

(STP)

t

su(DATA)

h(DATA)

DATA IN

(8-BIT)

t

,

d(DIR)

t

d(NXT)

CONTROL OUT

(DIR, NXT)

t

,

d(DIR)

t

d(NXT)

d(DATA)

DATA OUT

(8-BIT)

004aaa722

Fig 33. ULPI timing interface

ISP1504A_ISP1504C_1

Product data sheet

Rev. 01 — 19 October 2006

68 of 84

ISP1504A; ISP1504C

NXP Semiconductors

ULPI HS USB OTG transceiver

16. Application information

Table 56. Recommended bill of materials

Designator^[1]

Application

Value

Comment

C_bypass

highly recommended for

all applications

0.1 µF

-

C_{cp(C_A)-(C_B)}

C_ﬁlter

charge pump is used

22 nF (8 mA), 270 nF (50 mA);

up to 470 nF (50 mA)

-

highly recommended for

all applications

4.7 µF ± 20 %; use a LOW

ESR capacitor (0.2 Ω to 2 Ω)

for best performance

C_VBUS

mandatory for peripherals 0.1 µF and 1 µF to 10 µF in

-

parallel

mandatory for host

mandatory for OTG

0.1 µF and 120 µF ± 20 %

(min) in parallel

0.1 µF and 1 µF to 6.5 µF in

parallel

D_ESD

recommended for all

ESD-sensitive

applications

IP4059CX5/LF

Wafer-Level Chip-Scale Package (WLCSP);

1.34 mm × 0.96 mm × 0.41 mm; ESD

IEC 61000-4-2 level 4; ±8 kV contact; ±15 kV

air discharge

R_pullup

recommended; for

applications with an

external V_BUSsupply

controlled by PSW_N

4.7 kΩ to 100 kΩ (10 kΩ

recommended)

maximum value is determined by the voltage

drop on PSW_N caused by leakage into

PSW_N and the external supply control pin

R_RREF

R_VBUS

mandatory in all

applications

12 kΩ ± 1 %

-

strongly recommended for 1 kΩ ± 5 %

peripheral or external 5 V

applications only

R_XTAL

required only for

applications driving a

square wave into the

XTAL1 pin

47 kΩ ± 5 %

used to avoid ﬂoating input on the XTAL1 pin

XTAL

crystal is used

19.2 MHz

26 MHz

100 pF

C_L= 10 pF; R_S< 220 Ω; C_XTAL= 18 pF

C_L= 10 pF; R_S< 130 Ω; C_XTAL= 18 pF

C_(XTAL)SQ

required only for

applications driving a

square wave into the

XTAL1 pin that has a DC

offset

used to AC couple the input square wave to

the XTAL1 pin

[1] For detailed information and alternative interface options, refer to the Interfacing to the ISP1504/5/6 (AN10048) application note.

ISP1504A_ISP1504C_1

Product data sheet

Rev. 01 — 19 October 2006

69 of 84

ISP1504A; ISP1504C

NXP Semiconductors

ULPI HS USB OTG transceiver

17. Package outline

HVQFN32: plastic thermal enhanced very thin quad flat package; no leads;

32 terminals; body 5 x 5 x 0.85 mm

SOT617-1

B

A

D

terminal 1

index area

A

1

E

c

detail X

C

e

1

y

e

1/2 e

v

M

b

C

A B

C

1

w M

9

16

L

17

8

e

2

E

h

1/2 e

1

24

terminal 1

index area

32

25

X

D

h

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

A

(1)

UNIT

A

b

c

E

e

2

y

D

E

L

v

w

y

1

h

1

h

max.

0.05 0.30

0.00 0.18

5.1

4.9

3.25

2.95

5.1

4.9

3.25

2.95

0.5

0.3

mm

0.05 0.1

1

0.2

0.5

3.5

0.1

0.05

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

01-08-08

02-10-18

SOT617-1

- - -

MO-220

- - -

Fig 38. Package outline SOT617-1 (HVQFN32)

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ULPI HS USB OTG transceiver

18. Soldering

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reﬂow

soldering description”.

18.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

18.2 Wave and reﬂow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reﬂow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature proﬁle. Leaded packages,

packages with solder balls, and leadless packages are all reﬂow solderable.

Key characteristics in both wave and reﬂow soldering are:

• Board speciﬁcations, including the board ﬁnish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus PbSn soldering

18.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and ﬂux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath speciﬁcations, including temperature and impurities

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ISP1504A; ISP1504C

NXP Semiconductors

ULPI HS USB OTG transceiver

18.4 Reﬂow soldering

Key characteristics in reﬂow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 39) than a PbSn process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classiﬁed in accordance with

Table 57 and 58

Table 57. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

235

≥ 350

220

< 2.5

≥ 2.5

220

Table 58. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reﬂow

soldering, see Figure 39.

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ULPI HS USB OTG transceiver

maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 39. Temperature proﬁles for large and small components

For further information on temperature proﬁles, refer to Application Note AN10365

“Surface mount reﬂow soldering description”.

19. Abbreviations

Table 59. Abbreviations

Acronym

ATX

Description

Analog USB Transceiver

End-Of-Packet

EOP

ESD

FS

ElectroStatic Discharge

Full-Speed

HBM

HNP

HS

Human Body Model

Host Negotiation Protocol

High-Speed

ID

Identiﬁcation

LS

Low-Speed

NRZI

OTG

PHY

PID

Non-Return-to-Zero Inverted

On-The-Go

Physical Layer^[1]

Packet Identiﬁer

POR

RXCMD

SE0

Power-On Reset

Receive Command

Single-Ended Zero

Start-Of-Frame

SOF

SRP

SYNC

Session Request Protocol

Synchronous

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NXP Semiconductors

ULPI HS USB OTG transceiver

Table 59. Abbreviations …continued

Acronym

Description

TTL

Transistor-Transistor Logic

Transmit Command

TXCMD

USB

Universal Serial Bus

USB Implementers Forum

UTMI+ Low Pin Interface

USB-IF

ULPI

UTMI

UTMI+

USB 2.0 Transceiver Macrocell Interface

USB 2.0 Transceiver Macrocell Interface Plus

[1] Physical layer containing the USB transceiver. The ISP1504 is a PHY.

20. References

[1] Universal Serial Bus Speciﬁcation Rev. 2.0

[2] On-The-Go Supplement to the USB 2.0 Speciﬁcation Rev. 1.2

[3] UTMI+ Low Pin Interface (ULPI) Speciﬁcation Rev. 1.1

[4] UTMI+ Speciﬁcation Rev. 1.0

[5] USB 2.0 Transceiver Macrocell Interface (UTMI) Speciﬁcation Ver. 1.05

[6] Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM)

(JESD22-A114D)

[7] Interfacing to the ISP1504/5/6 (AN10048)

21. Revision history

Table 60. Revision history

Document ID

Release date

Data sheet status

Change notice

Supersedes

ISP1504A_ISP1504C_1 20061019

Product data sheet

-

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ISP1504A; ISP1504C

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ULPI HS USB OTG transceiver

22. Legal information

22.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

malfunction of a NXP Semiconductors product can reasonably be expected to

22.2 Deﬁnitions

result in personal injury, death or severe property or environmental damage.

NXP Semiconductors accepts no liability for inclusion and/or use of NXP

Semiconductors products in such equipment or applications and therefore

such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

22.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

22.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

23. Contact information

For additional information, please visit: http://www.nxp.com

For sales ofﬁce addresses, send an email to: salesaddresses@nxp.com

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NXP Semiconductors

ULPI HS USB OTG transceiver

24. Tables

Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .3

Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5

Table 3. Recommended charge pump capacitor value .12

Table 4. ULPI signal description . . . . . . . . . . . . . . . . . .15

Table 5. Signal mapping during low-power mode . . . . .16

Table 6. Signal mapping for 6-pin serial mode . . . . . . .17

Table 7. Signal mapping for 3-pin serial mode . . . . . . .18

Table 8. Operating states and their corresponding resistor

settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Table 9. OTG Control register power control bits . . . . .25

Table 10. TXCMD byte format . . . . . . . . . . . . . . . . . . . . .26

Table 11. RXCMD byte format . . . . . . . . . . . . . . . . . . . . .27

Table 12. LINESTATE[1:0] encoding for upstream facing

ports: peripheral . . . . . . . . . . . . . . . . . . . . . . . .28

Table 13. LINESTATE[1:0] encoding for downstream facing

ports: host . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Table 14. V_BUSindicators in RXCMD required for typical

applications . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Table 15. PHY pipeline delays . . . . . . . . . . . . . . . . . . . . .34

Table 16. Link decision times . . . . . . . . . . . . . . . . . . . . .35

Table 17. Register map overview . . . . . . . . . . . . . . . . . .47

Table 18. Vendor ID Low register (address R = 00h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Table 19. Vendor ID High register (address R = 01h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Table 20. Product ID Low register (address R = 02h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Table 21. Product ID High register (address R = 03h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Table 22. Function Control register (address R =

04h to 06h, W = 04h, S = 05h, C = 06h) bit

Table 29. USB Interrupt Enable Rising Edge register

(address R = 0Dh to 0Fh, W = 0Dh, S = 0Eh, C =

0Fh) bit description . . . . . . . . . . . . . . . . . . . . . 52

Table 30. USB Interrupt Enable Falling Edge register

(address R = 10h to 12h, W = 10h, S = 11h, C =

12h) bit allocation . . . . . . . . . . . . . . . . . . . . . . 52

Table 31. USB Interrupt Enable Falling Edge register

(address R = 10h to 12h, W = 10h, S = 11h, C =

12h) bit description . . . . . . . . . . . . . . . . . . . . . 52

Table 32. USB Interrupt Status register (address R = 13h)

bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 33. USB Interrupt Status register (address R = 13h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 34. USB Interrupt Latch register (address R = 14h) bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 35. USB Interrupt Latch register (address R = 14h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 36. Debug register (address R = 15h) bit allocation .

54

Table 37. Debug register (address R = 15h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 38. Scratch register (address R = 16h to 18h, W =

16h, S = 17h, C = 18h) bit description . . . . . . . 54

Table 39. Power Control register (address R = 3Dh to 3Fh,

W = 3Dh, S = 3Eh, C = 3Fh) bit allocation . . . 54

Table 40. Power Control register (address R = 3Dh to 3Fh,

W = 3Dh, S = 3Eh, C = 3Fh) bit description . . 55

Table 41. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 42. Recommended operating conditions . . . . . . . . 57

Table 43. Static characteristics: supply pins . . . . . . . . . . 58

Table 44. Static characteristics: digital pins (CLOCK, DIR,

STP, NXT, DATA[7:0], RESET_N,

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Table 23. Function Control register (address R

CHIP_SELECT_N) . . . . . . . . . . . . . . . . . . . . . 58

Table 45. Static characteristics: digital pin FAULT . . . . . 59

Table 46. Static characteristics: digital pin PSW_N . . . . 59

Table 47. Static characteristics: analog I/O pins

= 04h to 06h, W = 04h, S = 05h, C = 06h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Table 24. Interface Control register (address R =

07h to 09h, W = 07h, S = 08h, C = 09h) bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Table 25. Interface Control register (address R =

07h to 09h, W = 07h, S = 08h, C = 09h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Table 26. OTG Control register (address R = 0Ah to 0Ch,

W = 0Ah, S = 0Bh, C = 0Ch) bit allocation . . .50

Table 27. OTG Control register (address R = 0Ah to 0Ch,

W = 0Ah, S = 0Bh, C = 0Ch) bit description . .51

Table 28. USB Interrupt Enable Rising Edge register

(address R = 0Dh to 0Fh, W = 0Dh, S = 0Eh, C =

0Fh) bit allocation . . . . . . . . . . . . . . . . . . . . . .51

(DP, DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 48. Static characteristics: charge pump . . . . . . . . 61

Table 49. Static characteristics: V_BUScomparators . . . . 61

Table 50. Static characteristics: V_BUSresistors . . . . . . . . 62

Table 51. Static characteristics: ID detection circuit . . . . 62

Table 52. Static characteristics: resistor reference . . . . . 62

Table 53. Dynamic characteristics: reset and clock . . . . 64

Table 54. Dynamic characteristics: digital I/O pins . . . . . 65

Table 55. Dynamic characteristics: analog I/O pins (DP and

DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 56. Recommended bill of materials . . . . . . . . . . . . 69

Table 57. SnPb eutectic process (from J-STD-020C) . . . 76

continued >>

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ULPI HS USB OTG transceiver

Table 58. Lead-free process (from J-STD-020C) . . . . . .76

Table 59. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .77

Table 60. Revision history . . . . . . . . . . . . . . . . . . . . . . . .78

continued >>

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ISP1504A; ISP1504C

NXP Semiconductors

ULPI HS USB OTG transceiver

25. Figures

Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Fig 2. Pin conﬁguration HVQFN32; top view . . . . . . . . . .5

Fig 3. External capacitors connection . . . . . . . . . . . . . .10

Fig 4. Charge pump capacitor . . . . . . . . . . . . . . . . . . . .12

Fig 5. Internal power-on reset timing . . . . . . . . . . . . . . .20

Fig 6. Power-up and reset sequence required before the

ULPI bus is ready for use. . . . . . . . . . . . . . . . . . .22

Fig 7. Interface behavior with respect to RESET_N. . . .23

Fig 8. Entering and exiting 3-state in normal mode . . . .24

Fig 9. Entering and exiting 3-state in suspend mode. . .25

Fig 10. Single and back-to-back RXCMDs from the

ISP1504 to the link. . . . . . . . . . . . . . . . . . . . . . . .27

and external 60 MHz input on CLOCK . . . . . . . . 71

Fig 36. Using the ISP1504 with a standard USB Host

Controller; external 5 V source with built-in FAULT

and external square wave input on XTAL1 . . . . . 72

Fig 37. Using the ISP1504 with a standard USB Peripheral

Controller; external crystal . . . . . . . . . . . . . . . . . 73

Fig 38. Package outline SOT617-1 (HVQFN32) . . . . . . . 74

Fig 39. Temperature proﬁles for large and small

components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Fig 11. RXCMD A_VBUS_VLD indicator source . . . . . . .29

Fig 12. Example of register write, register read, extended

register write and extended register read . . . . . .31

Fig 13. USB reset and high-speed detection handshake

(chirp) sequence . . . . . . . . . . . . . . . . . . . . . . . . .33

Fig 14. Example of using the ISP1504 to transmit and

receive USB data. . . . . . . . . . . . . . . . . . . . . . . . .34

Fig 15. High-speed transmit-to-transmit packet timing. . .35

Fig 16. High-speed receive-to-transmit packet timing . . .36

Fig 17. Preamble sequence. . . . . . . . . . . . . . . . . . . . . . .37

Fig 18. Full-speed suspend and resume . . . . . . . . . . . . .38

Fig 19. High-speed suspend and resume . . . . . . . . . . . .40

Fig 20. Remote wake-up from low-power mode . . . . . . .42

Fig 21. Transmitting USB packets without automatic SYNC

and EOP generation . . . . . . . . . . . . . . . . . . . . . .43

Fig 22. Example of transmit followed by receive in 6-pin

serial mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Fig 23. Example of transmit followed by receive in 3-pin

serial mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Fig 24. Human body ESD test model. . . . . . . . . . . . . . . .56

Fig 25. Charge pump supply current vs. V_BUSoutput

current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

Fig 26. V_BUSoutput voltage vs. V_BUSoutput current . . . .63

Fig 27. V_BUSoutput voltage vs. charge pump supply

voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

Fig 28. Charge pump supply current vs. temperature . . .63

Fig 29. Rise time and fall time . . . . . . . . . . . . . . . . . . . . .68

Fig 30. Timing of TX_DAT and TX_SE0 to DP and DM. .68

Fig 31. Timing of TX_ENABLE to DP and DM. . . . . . . . .68

Fig 32. Timing of DP and DM to RX_RCV, RX_DP and

RX_DM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

Fig 33. ULPI timing interface . . . . . . . . . . . . . . . . . . . . . .68

Fig 34. Using the ISP1504 with an OTG Controller; internal

charge pump is utilized and crystal is attached . .70

Fig 35. Using the ISP1504 with an OTG Controller; external

charge pump using the ISP1504 internal V_BUSvalid

continued >>

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Product data sheet

Rev. 01 — 19 October 2006

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NXP Semiconductors

ULPI HS USB OTG transceiver

26. Contents

1

2

3

4

5

General description . . . . . . . . . . . . . . . . . . . . . . 1

8.1

ULPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Synchronous mode . . . . . . . . . . . . . . . . . . . . 15

Low-power mode . . . . . . . . . . . . . . . . . . . . . . 16

6-pin full-speed or low-speed serial mode . . . 17

3-pin full-speed or low-speed serial mode . . . 17

USB and OTG state transitions . . . . . . . . . . . 18

8.1.1

8.1.2

8.1.3

8.1.4

8.2

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . 3

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

9

9.1

9.2

9.3

9.3.1

9.3.2

9.3.3

Protocol description . . . . . . . . . . . . . . . . . . . . 20

ULPI references . . . . . . . . . . . . . . . . . . . . . . . 20

Power-On Reset (POR) . . . . . . . . . . . . . . . . . 20

Power-up, reset and bus idle sequence . . . . . 20

Interface protection. . . . . . . . . . . . . . . . . . . . . 23

Interface behavior with respect to RESET_N. 23

Interface behavior with respect to

7

7.1

7.2

7.3

7.4

7.5

7.6

7.6.1

7.6.2

7.6.2.1

7.6.2.2

7.6.2.3

7.6.3

7.6.4

7.7

Functional description . . . . . . . . . . . . . . . . . . . 7

ULPI interface controller . . . . . . . . . . . . . . . . . . 7

USB data serializer and deserializer. . . . . . . . . 7

Hi-Speed USB (USB 2.0) ATX . . . . . . . . . . . . . 7

Voltage regulator. . . . . . . . . . . . . . . . . . . . . . . . 8

Crystal oscillator and PLL. . . . . . . . . . . . . . . . . 8

OTG module . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

ID detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

V_BUScomparators. . . . . . . . . . . . . . . . . . . . . . . 9

CHIP_SELECT_N . . . . . . . . . . . . . . . . . . . . . 23

V_BUSpower and fault detection . . . . . . . . . . . 25

9.4

9.4.1

9.4.2

9.5

9.5.1

9.5.2

9.5.2.1

9.5.2.2

9.5.2.3

9.6

Driving 5 V on V_BUS. . . . . . . . . . . . . . . . . . . . 25

Fault detection . . . . . . . . . . . . . . . . . . . . . . . . 25

TXCMD and RXCMD . . . . . . . . . . . . . . . . . . . 26

TXCMD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

RXCMD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Linestate encoding. . . . . . . . . . . . . . . . . . . . . 27

V_BUSvalid comparator . . . . . . . . . . . . . . . . . . . 9

Session valid comparator . . . . . . . . . . . . . . . . . 9

Session end comparator. . . . . . . . . . . . . . . . . . 9

SRP charge and discharge resistors . . . . . . . . 9

Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . 10

Band gap reference voltage . . . . . . . . . . . . . . 10

Power-On Reset (POR) . . . . . . . . . . . . . . . . . 10

Detailed description of pins . . . . . . . . . . . . . . 10

DATA[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

V_CC(I/O). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

RREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

DP and DM . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

FAULT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

CPGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

C_A and C_B . . . . . . . . . . . . . . . . . . . . . . . . . 12

V_BUSstate encoding. . . . . . . . . . . . . . . . . . . . 28

RxEvent encoding . . . . . . . . . . . . . . . . . . . . . 30

Register read and write operations . . . . . . . . 30

USB reset and high-speed detection handshake

(chirp). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

USB packet transmit and receive . . . . . . . . . . 34

USB packet timing . . . . . . . . . . . . . . . . . . . . . 34

ISP1504 pipeline delays. . . . . . . . . . . . . . . . . 34

Allowed link decision time . . . . . . . . . . . . . . . 34

Preamble . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

USB suspend and resume . . . . . . . . . . . . . . . 37

Full-speed or low-speed host-initiated suspend

and resume . . . . . . . . . . . . . . . . . . . . . . . . . . 37

High-speed suspend and resume . . . . . . . . . 38

Remote wake-up . . . . . . . . . . . . . . . . . . . . . . 41

No automatic SYNC and EOP generation

7.8

7.9

9.7

7.9.1

7.9.2

7.9.3

7.9.4

7.9.5

7.9.6

7.9.7

7.9.8

7.9.9

7.9.10

7.9.11

7.9.12

7.9.13

7.9.14

7.9.15

7.9.16

7.9.17

7.9.18

7.9.19

7.9.20

9.8

9.8.1

9.8.1.1

9.8.1.2

9.9

9.10

9.10.1

V_CC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

9.10.2

9.10.3

9.11

PSW_N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

V_BUS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

REG3V3 and REG1V8 . . . . . . . . . . . . . . . . . . 13

XTAL1 and XTAL2. . . . . . . . . . . . . . . . . . . . . . 13

RESET_N . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

DIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

STP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

NXT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

CHIP_SELECT_N. . . . . . . . . . . . . . . . . . . . . . 14

GND (die pad). . . . . . . . . . . . . . . . . . . . . . . . . 14

(optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

On-The-Go operations . . . . . . . . . . . . . . . . . . 43

OTG charge pump . . . . . . . . . . . . . . . . . . . . . 44

OTG comparators. . . . . . . . . . . . . . . . . . . . . . 44

Pull-up and pull-down resistors . . . . . . . . . . . 44

ID detection . . . . . . . . . . . . . . . . . . . . . . . . . . 44

9.12

9.12.1

9.12.2

9.12.3

9.12.4

9.12.5

9.13

V_BUScharge and discharge resistors . . . . . . . 44

Serial modes . . . . . . . . . . . . . . . . . . . . . . . . . 44

Aborting transfers. . . . . . . . . . . . . . . . . . . . . . 46

Avoiding contention on the ULPI data bus . . . 46

9.14

9.15

8

Modes of operation . . . . . . . . . . . . . . . . . . . . . 15

10

Register map . . . . . . . . . . . . . . . . . . . . . . . . . . 47

continued >>

ISP1504A_ISP1504C_1

Product data sheet

Rev. 01 — 19 October 2006

83 of 84

ISP1504A; ISP1504C

NXP Semiconductors

ULPI HS USB OTG transceiver

10.1

10.1.1

Immediate register set . . . . . . . . . . . . . . . . . . 47

Vendor ID and Product ID registers . . . . . . . . 47

10.1.1.1 Vendor ID Low register . . . . . . . . . . . . . . . . . . 47

10.1.1.2 Vendor ID High register . . . . . . . . . . . . . . . . . 48

10.1.1.3 Product ID Low register . . . . . . . . . . . . . . . . . 48

10.1.1.4 Product ID High register . . . . . . . . . . . . . . . . . 48

10.1.2

10.1.3

10.1.4

10.1.5

10.1.6

10.1.7

10.1.8

10.1.9

Function Control register . . . . . . . . . . . . . . . . 48

Interface Control register . . . . . . . . . . . . . . . . 49

OTG Control register . . . . . . . . . . . . . . . . . . . 50

USB Interrupt Enable Rising Edge register . . 51

USB Interrupt Enable Falling Edge register . . 52

USB Interrupt Status register . . . . . . . . . . . . . 52

USB Interrupt Latch register. . . . . . . . . . . . . . 53

Debug register . . . . . . . . . . . . . . . . . . . . . . . . 54

10.1.10 Scratch register. . . . . . . . . . . . . . . . . . . . . . . . 54

10.1.11 Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

10.1.12 Access extended register set . . . . . . . . . . . . . 54

10.1.13 Vendor-speciﬁc registers . . . . . . . . . . . . . . . . 54

10.1.14 Power Control register . . . . . . . . . . . . . . . . . . 54

10.2

Extended register set . . . . . . . . . . . . . . . . . . . 55

11

11.1

11.2

ElectroStatic Discharge (ESD) . . . . . . . . . . . . 56

ESD protection . . . . . . . . . . . . . . . . . . . . . . . . 56

ESD test conditions . . . . . . . . . . . . . . . . . . . . 56

12

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 57

Recommended operating conditions. . . . . . . 57

Static characteristics. . . . . . . . . . . . . . . . . . . . 58

Dynamic characteristics . . . . . . . . . . . . . . . . . 64

ULPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Application information. . . . . . . . . . . . . . . . . . 69

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 74

13

14

15

15.1

16

17

18

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Introduction to soldering . . . . . . . . . . . . . . . . . 75

Wave and reﬂow soldering . . . . . . . . . . . . . . . 75

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 75

Reﬂow soldering . . . . . . . . . . . . . . . . . . . . . . . 76

18.1

18.2

18.3

18.4

19

20

21

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 77

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 78

22

Legal information. . . . . . . . . . . . . . . . . . . . . . . 79

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 79

Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 79

22.1

22.2

22.3

22.4

23

24

25

26

Contact information. . . . . . . . . . . . . . . . . . . . . 79

Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 19 October 2006

Document identifier: ISP1504A_ISP1504C_1


型号：	ISP1504ABS
厂家：	NXP
描述：	ULPI Hi-Speed Universal Serial Bus On-The-Go transceiver ULPI高速通用串行总线的On-the - Go收发器线路驱动器或接收器驱动程序和接口接口集成电路
文件：	总84页 (文件大小：415K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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