ISP1505CBS,551 [NXP]

IC LINE TRANSCEIVER, PQCC24, 4 X 4 MM, 0.85 MM HEIGHT, ROHS COMPLIANT, PLASTIC, MO-220, SOT-616-1, HVQFN-24, Line Driver or Receiver;
ISP1505CBS,551
型号: ISP1505CBS,551
厂家: NXP    NXP
描述:

IC LINE TRANSCEIVER, PQCC24, 4 X 4 MM, 0.85 MM HEIGHT, ROHS COMPLIANT, PLASTIC, MO-220, SOT-616-1, HVQFN-24, Line Driver or Receiver

驱动 接口集成电路 驱动器
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中文:  中文翻译
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3
4
.80 7IRELESS  
IMPORTANT NOTICE  
Dear customer,  
As from August 2nd 2008, the wireless operations of NXP have moved to a new company,  
ST-NXP Wireless.  
As a result, the following changes are applicable to the attached document.  
Company name - NXP B.V. is replaced with ST-NXP Wireless.  
Copyright - the copyright notice at the bottom of each page “© NXP B.V. 200x. All  
rights reserved”, shall now read: “© ST-NXP Wireless 200x - All rights reserved”.  
Web site - http://www.nxp.com is replaced with http://www.stnwireless.com  
Contact information - the list of sales offices previously obtained by sending  
an email to salesaddresses@nxp.com , is now found at http://www.stnwireless.com  
under Contacts.  
If you have any questions related to the document, please contact our nearest sales office.  
Thank you for your cooperation and understanding.  
ST-NXP Wireless  
34.80 7IRELESS  
www.stnwireless.com  
ISP1505A; ISP1505C  
ULPI Hi-Speed USB host and peripheral transceiver  
Rev. 03 — 26 August 2008  
Product data sheet  
1. General description  
The ISP1505 is a Universal Serial Bus (USB) high-speed host and peripheral transceiver  
that is fully compliant with Universal Serial Bus Specification Rev. 2.0 and UTMI+ Low Pin  
Interface (ULPI) Specification Rev. 1.1.  
The ISP1505 can transmit and receive USB data at high-speed (480 Mbit/s), full-speed  
(12 Mbit/s) and low-speed (1.5 Mbit/s), and provides a pin-optimized, physical layer  
front-end attachment to USB host, peripheral and OTG devices.  
It is ideal for use in portable electronic devices, such as mobile phones, digital still  
cameras, digital video cameras, Personal Digital Assistants (PDAs) and digital audio  
players. It allows USB Application-Specific Integrated Circuits (ASICs), Programmable  
Logic Devices (PLDs) and any system chip set to interface with the physical layer of the  
USB through a 12-pin interface.  
The ISP1505 can interface to the link with digital I/O voltages in the range of 1.65 V to  
3.6 V.  
The ISP1505 is available in HVQFN24 package.  
2. Features  
I Fully complies with:  
N Universal Serial Bus Specification Rev. 2.0  
N UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1  
I Interfaces to host and peripheral cores; optimized for stand-alone and embedded host  
applications with an external VBUS supply; stand-alone peripheral cores, and Session  
Request Protocol (SRP)-capable peripheral cores  
I Complete Hi-Speed USB physical front-end solution that supports high-speed  
(480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s)  
N Integrated 45 Ω ± 10 % high-speed termination resistors, 1.5 kΩ ± 5 % full-speed  
device pull-up resistor, and 15 kΩ ± 5 % host termination resistors  
N Integrated parallel-to-serial and serial-to-parallel converters to transmit and receive  
N USB clock and data recovery to receive USB data up to ±500 ppm  
N Insertion of stuff bits during transmit and discarding of stuff bits during receive  
N Non-Return-to-Zero Inverted (NRZI) encoding and decoding  
N Supports bus reset, suspend, resume and high-speed detection handshake (chirp)  
I Supports SRP for reduced power consumption  
N Complete control over bus resistors  
N Data line and VBUS pulsing session request methods  
N Integrated VBUS voltage comparators  
ISP1505A; ISP1505C  
NXP Semiconductors  
ULPI HS USB host and peripheral transceiver  
I Highly optimized ULPI compliant  
N 60 MHz, 8-bit interface between the core and the transceiver  
N Supports 60 MHz output clock configuration  
N Integrated Phase-Locked Loop (PLL) supporting one crystal or clock frequency:  
19.2 MHz (ISP1505ABS) and 26 MHz (ISP1505CBS)  
N Fully programmable ULPI-compliant register set  
N Internal Power-On Reset (POR) circuit  
I Flexible system integration and very low current consumption, optimized for portable  
devices  
N Power-supply input range is 3.0 V to 3.6 V  
N Internal voltage regulator supplies 3.3 V and 1.8 V  
N Supports external VBUS charge pump  
N External VBUS source is controlled using the PSW_N pin; open-drain PSW_N  
allows per-port or ganged power control  
N FAULT input pin to monitor the external VBUS supply status  
N Supports wide range interfacing I/O voltage of 1.65 V to 3.6 V; separate I/O voltage  
pins minimize crosstalk  
N Typical operating current of 10 mA to 48 mA, depending on the USB speed and  
bus utilization  
N Typical suspend current of 35 µA  
I Full industrial grade operating temperature range from 40 °C to +85 °C  
I 4 kV ElectroStatic Discharge (ESD) protection on pins DP, DM, VBUS and GND  
I Available in a small HVQFN24 (4 mm × 4 mm) Restriction of Hazardous Substances  
(RoHS) compliant, halogen-free and lead-free package  
3. Applications  
I Digital still camera  
I Digital TV  
I Digital Video Disc (DVD) recorder  
I External storage device, for example:  
N Magneto-Optical (MO) drive  
N Optical drive: CD-ROM, CD-RW, DVD  
N Zip drive  
I Mobile phone  
I MP3 player  
I PDA  
I Printer  
I Scanner  
I Set-Top Box (STB)  
I Video camera  
ISP1505A_ISP1505C_3  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 03 — 26 August 2008  
2 of 75  
ISP1505A; ISP1505C  
NXP Semiconductors  
ULPI HS USB host and peripheral transceiver  
4. Ordering information  
Table 1.  
Part  
Ordering information  
Package  
Name  
Type number Marking Crystal or  
Description  
Version  
clock  
frequency  
ISP1505ABS  
ISP1505CBS  
05A[1]  
05C[1]  
19.2 MHz  
HVQFN24 plastic thermal enhanced very thin quad flat package; SOT616-3  
no leads; 24 terminals; body 4 × 4 × 0.85 mm  
26 MHz  
HVQFN24 plastic thermal enhanced very thin quad flat package; SOT616-3  
no leads; 24 terminals; body 4 × 4 × 0.85 mm  
[1] The package marking is the first line of text on the IC package and can be used for IC identification.  
ISP1505A_ISP1505C_3  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 03 — 26 August 2008  
3 of 75  
ISP1505A; ISP1505C  
NXP Semiconductors  
ULPI HS USB host and peripheral transceiver  
5. Block diagram  
21  
15  
14  
16  
CLOCK  
STP  
USB DATA  
SERIALIZER  
6
DP  
HIGH-SPEED  
USB ATX  
DIR  
ULPI  
INTERFACE  
CONTROLLER  
NXT  
TERMINATION  
RESISTORS  
ULPI  
INTERFACE  
5
USB DATA  
DESERIALIZER  
1, 2,  
17 to 20,  
22, 24  
DM  
8
DATA  
[7:0]  
V
VALID EXTERNAL  
BUS  
USB  
CABLE  
REGISTER  
MAP  
DRIVE V  
EXTERNAL  
BUS  
12  
RESET_N/  
PSW_N  
GLOBAL  
RESET  
V
POWER-ON  
RESET  
BUS  
COMPARATORS  
8
V
/
BUS  
PLL  
FAULT  
GLOBAL  
CLOCKS  
SRP CHARGE  
AND DISCHARGE  
RESISTORS  
10  
11  
XTAL1  
XTAL2  
CRYSTAL  
OSCILLATOR  
3, 23  
V
interface voltage  
internal power  
ISP1505  
CC(I/O)  
BAND GAP  
REFERENCE  
VOLTAGE  
9
4
REG3V3  
REG1V8  
V
REF  
RREF  
13  
7
VOLTAGE  
REGULATOR  
V
CC  
004aaa587  
Fig 1. Block diagram  
ISP1505A_ISP1505C_3  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 03 — 26 August 2008  
4 of 75  
ISP1505A; ISP1505C  
NXP Semiconductors  
ULPI HS USB host and peripheral transceiver  
6. Pinning information  
6.1 Pinning  
terminal 1  
index area  
1
2
3
4
5
6
18  
17  
16  
15  
14  
13  
DATA1  
DATA0  
DATA6  
DATA7  
NXT  
V
CC(I/O)  
ISP1505  
RREF  
STP  
DM  
DP  
DIR  
REG1V8  
004aaa689  
Transparent top view  
Fig 2. Pin configuration HVQFN24; top view  
6.2 Pin description  
Table 2.  
Pin description  
Symbol[1][2]  
Pin  
Type[3] Description[4]  
DATA1  
1
I/O  
pin 1 of the bidirectional ULPI data bus  
slew-rate controlled output (1 ns); plain input; programmable pull down  
pin 0 of the bidirectional ULPI data bus  
slew-rate controlled output (1 ns); plain input; programmable pull down  
I/O supply rail  
DATA0  
2
I/O  
VCC(I/O)  
RREF  
DM  
3
4
5
6
7
8
P
AI/O  
AI/O  
AI/O  
P
resistor reference  
data minus (D) pin of the USB cable  
DP  
data plus (D+) pin of the USB cable  
VCC  
input supply voltage or battery source  
VBUS/FAULT  
AI/O  
This pin has two possible functions:  
VBUS (analog input and output) — VBUS pin of the USB cable.  
FAULT (input) — Input pin for the external VBUS digital overcurrent or fault detector  
signal.  
If this pin is not used as either VBUS or FAULT, it must be connected to ground.  
5 V tolerant  
REG3V3  
XTAL1  
9
P
3.3 V regulator output  
crystal oscillator or clock input  
crystal oscillator output  
10  
11  
AI  
AO  
XTAL2  
ISP1505A_ISP1505C_3  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 03 — 26 August 2008  
5 of 75  
ISP1505A; ISP1505C  
NXP Semiconductors  
ULPI HS USB host and peripheral transceiver  
Table 2.  
Pin description …continued  
Symbol[1][2]  
Pin  
Type[3] Description[4]  
RESET_N/PSW_N 12  
I/O  
This pin has two possible functions:  
RESET_N (input) — Active LOW, asynchronous reset input.  
3.3 V tolerant; plain input  
PSW_N (output) — Active LOW external VBUS power switch or external charge  
pump enable.  
open-drain; 3.3 V tolerant  
If not used, this pin must be connected to VCC(I/O)  
1.8 V regulator output  
.
REG1V8  
DIR  
13  
14  
P
O
ULPI direction signal  
slew-rate controlled output (1 ns)  
ULPI stop signal  
STP  
15  
16  
17  
18  
19  
20  
21  
22  
I
plain input; programmable pull up  
ULPI next signal  
NXT  
O
slew-rate controlled output (1 ns)  
pin 7 of the bidirectional ULPI data bus  
DATA7  
DATA6  
DATA5  
DATA4  
CLOCK  
DATA3  
I/O  
I/O  
I/O  
I/O  
O
slew-rate controlled output (1 ns); plain input; programmable pull down  
pin 6 of the bidirectional ULPI data bus  
slew-rate controlled output (1 ns); plain input; programmable pull down  
pin 5 of the bidirectional ULPI data bus  
slew-rate controlled output (1 ns); plain input; programmable pull down  
pin 4 of the bidirectional ULPI data bus  
slew-rate controlled output (1 ns); plain input; programmable pull down  
60 MHz clock output  
slew-rate controlled output (1 ns)  
I/O  
pin 3 of the bidirectional ULPI data bus  
slew-rate controlled output (1 ns); plain input; programmable pull down  
I/O supply rail  
VCC(I/O)  
DATA2  
23  
24  
P
I/O  
pin 2 of the bidirectional ULPI data bus  
slew-rate controlled output (1 ns); plain input; programmable pull down  
GND  
die  
pad  
P
ground supply; down bonded to the exposed die pad (heat sink); to be connected to  
the PCB ground  
[1] Symbol names ending with underscore N, for example, NAME_N, indicate active LOW signals.  
[2] For details on external components required on each pin, see bill of materials and application diagrams in Section 16.  
[3] I = input; O = output; I/O = digital input/output; AI = analog input; AO = analog output; AI/O = analog input/output; P = power or ground  
pin.  
[4] A detailed description of these pins can be found in Section 7.10.  
ISP1505A_ISP1505C_3  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 03 — 26 August 2008  
6 of 75  
ISP1505A; ISP1505C  
NXP Semiconductors  
ULPI HS USB host and peripheral transceiver  
7. Functional description  
7.1 ULPI interface controller  
The ISP1505 provides a 12-pin interface that is compliant with UTMI+ Low Pin Interface  
(ULPI) Specification Rev. 1.1. This interface must be connected to the USB link.  
The ULPI interface controller provides the following functions:  
ULPI-compliant interface and register set  
Allows full control over the USB peripheral, host and SRP functionality  
Parses the USB transmit and receive data  
Prioritizes the USB receive data, USB transmit data, interrupts and register operations  
Low-power mode  
External VBUS source control  
VBUS monitoring, charging and discharging  
6-pin serial mode and 3-pin serial mode  
Generates RXCMDs; status updates  
Maskable interrupts  
For more information on the ULPI protocol, see Section 9.  
7.2 USB data serializer and deserializer  
The USB data serializer prepares data to transmit on the USB bus. To transmit data, the  
USB link sends a transmit command and data on the ULPI bus. The serializer performs  
parallel-to-serial conversion, bit stuffing and NRZI encoding. For packets with a PID, the  
serializer adds a SYNC pattern to the start of the packet, and an EOP pattern to the end  
of the packet. When the serializer is busy and cannot accept any more data, the ULPI  
interface controller deasserts NXT.  
The USB data deserializer decodes data received from the USB bus. When data is  
received, the deserializer strips the SYNC and EOP patterns, and then performs  
serial-to-parallel conversion, NRZI decoding and discarding of stuff bits on the data  
payload. The ULPI interface controller sends data to the USB link by asserting DIR, and  
then asserting NXT whenever a byte is ready. The deserializer also detects various  
receive errors, including bit stuff errors, elasticity buffer underrun or overrun, and  
byte-alignment errors.  
7.3 Hi-Speed USB (USB 2.0) ATX  
The Hi-Speed USB ATX block is an analog front-end containing the circuitry needed to  
transmit, receive and terminate the USB bus in high-speed, full-speed and low-speed, for  
USB peripheral, host and OTG implementations. The following circuitry is included:  
Differential drivers to transmit data at high-speed, full-speed and low-speed  
Differential and single-ended receivers to receive data at high-speed, full-speed and  
low-speed  
Squelch circuit to detect high-speed bus activity  
ISP1505A_ISP1505C_3  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 03 — 26 August 2008  
7 of 75  
ISP1505A; ISP1505C  
NXP Semiconductors  
ULPI HS USB host and peripheral transceiver  
High-speed disconnect detector  
45 high-speed bus terminations on DP and DM for peripheral and host modes  
1.5 kpull-up resistor on DP for full-speed peripheral mode  
15 kbus terminations on DP and DM for host and OTG modes  
For details on controlling resistor settings, see Table 7.  
7.4 Voltage regulator  
The ISP1505 contains a built-in voltage regulator that conditions the VCC supply for use  
inside the ISP1505. The voltage regulator:  
Supports input supply range of 3.0 V < VCC < 3.6 V  
Supplies internal circuitry with 1.8 V and 3.3 V  
Remark: The REG1V8 and REG3V3 pins require external decoupling capacitors. For  
details, see Section 16.  
7.5 Crystal oscillator and PLL  
The ISP1505 has a built-in crystal oscillator and a Phase-Locked Loop (PLL) for clock  
generation.  
The crystal oscillator takes a sine-wave input from an external crystal on the XTAL1 pin,  
and converts it to a square wave clock for internal use. Alternatively, a square wave clock  
of the same frequency can also be directly driven into the XTAL1 pin. Using an existing  
square wave clock can save the cost of the crystal and also reduce the board size.  
The PLL takes the square wave clock from the crystal oscillator, and multiplies or divides it  
into various frequencies for internal use.  
The PLL produces the following frequencies, irrespective of the clock source:  
60 MHz clock for the ULPI interface controller  
1.5 MHz for the low-speed USB data  
12 MHz for the full-speed USB data  
480 MHz for the high-speed USB data  
Other internal frequencies for data conversion and data recovery  
7.6 VBUS comparators  
The ISP1505 provides three comparators, VBUS valid comparator, session valid  
comparator and session end comparator, to detect the VBUS voltage level.  
7.6.1 VBUS valid comparator  
This comparator is used by hosts and A-devices to determine whether the voltage on  
VBUS is at a valid level for operation. The ISP1505 minimum threshold for the VBUS valid  
comparator is VA_VBUS_VLD. Any voltage on VBUS below VA_VBUS_VLD is considered a fault.  
During power-up, it is expected that the comparator output will be ignored.  
ISP1505A_ISP1505C_3  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 03 — 26 August 2008  
8 of 75  
ISP1505A; ISP1505C  
NXP Semiconductors  
ULPI HS USB host and peripheral transceiver  
While it is possible for the external 5 V supply to use the ISP1505 internal A_VBUS_VLD  
comparator, typical 5 V supplies must provide their own power fault indicator that can be  
connected as an input to the ISP1505 FAULT pin.  
7.6.2 Session valid comparator  
The session valid comparator is a TTL-level input that determines when VBUS is high  
enough for a session to start. Peripherals, A-devices and B-devices use this comparator to  
detect when a session is started. The A-device also uses this comparator to determine  
when a session is completed. The session valid threshold of the ISP1505 is VB_SESS_VLD  
,
with a hysteresis of Vhys(B_SESS_VLD)  
.
7.6.3 Session end comparator  
The ISP1505 session end comparator determines when VBUS is below the B-device  
session end threshold. The B-device uses this threshold to determine when a session has  
ended. The session end threshold of the ISP1505 is VB_SESS_END  
.
7.7 SRP charge and discharge resistors  
The ISP1505 provides on-chip resistors for short-term charging and discharging of VBUS  
These are used by the B-device to request a session, prompting the A-device to restore  
the VBUS power. First, the B-device makes sure that VBUS is fully discharged from the  
previous session by setting the DISCHRG_VBUS register bit to logic 1 and waiting for  
SESS_END to be logic 1. Then the B-device charges VBUS by setting the CHRG_VBUS  
register bit to logic 1. The A-device sees that VBUS is charged above the session valid  
threshold and starts a session by turning on the VBUS power.  
.
7.8 Band gap reference voltage  
The band gap circuit provides a stable internal voltage reference to bias the analog  
circuitry. The band gap requires an accurate external reference resistor RRREF connected  
between the RREF and GND pins. For details, see Section 16.  
7.9 Power-on reset  
The ISP1505 has an internal power-on reset circuit that resets all internal logic on  
power-up. The ULPI interface is also reset at power-up.  
Remark: When CLOCK starts toggling after power-up, the USB link must issue a reset  
command over the ULPI bus to ensure correct operation of the ISP1505.  
7.10 Detailed description of pins  
7.10.1 DATA[7:0]  
The ISP1505 is a Physical layer (PHY) containing a USB transceiver. DATA[7:0] is a  
bidirectional data bus. The USB link must drive DATA[7:0] to LOW when the ULPI bus is  
idle. When the link has data to transmit to the PHY, it drives a nonzero value.  
Weak pull-down resistors are incorporated into DATA[7:0] pins as part of the interface  
protect feature. For details, see Section 9.3.1.  
The data bus can be reconfigured to carry various data types, as given in Section 8 and  
Section 9.  
ISP1505A_ISP1505C_3  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 03 — 26 August 2008  
9 of 75  
ISP1505A; ISP1505C  
NXP Semiconductors  
7.10.2 VCC(I/O)  
ULPI HS USB host and peripheral transceiver  
The input power pin that sets the I/O voltage level. For details, see Section 12, Section 13  
and Section 16. VCC(I/O) provides power to on-chip pads of the following pins:  
CLOCK  
DATA[7:0]  
DIR  
NXT  
RESET_N  
STP  
7.10.3 RREF  
Resistor reference analog I/O pin. A resistor, RRREF, must be connected between RREF  
and GND, as shown in Section 16. This provides an accurate voltage reference that  
biases internal analog circuitry. Less accurate resistors cannot be used and will render the  
ISP1505 unusable.  
7.10.4 DP and DM  
The DP (data plus) and DM (data minus) are USB differential data pins. These must be  
connected to the D+ and Dpins of the USB receptacle.  
7.10.5 VCC  
VCC is the main input supply voltage for the ISP1505. Decoupling capacitors are  
recommended. For details, see Section 16.  
7.10.6 VBUS/FAULT  
This pin provides two options for VBUS driving and monitoring. If neither function is used,  
this pin must be connected to ground.  
7.10.6.1 VBUS  
By default, this pin acts as an input to VBUS comparators, and also charges and  
discharges VBUS for SRP.  
The VBUS pin requires a capacitive load as shown in Section 16.  
To prevent electrical overstress, it is strongly recommended that you attach a series  
resistor on the VBUS pin (RVBUS). RVBUS must not be attached when using the ISP1505  
internal charge pump. For details, see Section 16.  
7.10.6.2 FAULT (external overcurrent or fault detector)  
If an external VBUS overcurrent or fault circuit is used, the output fault indicator of that  
circuit can be connected to the ISP1505 FAULT input pin. The ISP1505 will inform the link  
of VBUS fault events by sending RXCMDs on the ULPI bus. To use the FAULT pin, the link  
must:  
Set the USE_EXT_VBUS_IND register bit to logic 1.  
Set the polarity of the external fault signal using the IND_COMPL register bit.  
Set the IND_PASSTHRU register bit to logic 1.  
ISP1505A_ISP1505C_3  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 03 — 26 August 2008  
10 of 75  
ISP1505A; ISP1505C  
NXP Semiconductors  
ULPI HS USB host and peripheral transceiver  
7.10.7 REG3V3 and REG1V8  
Regulator output voltage. These supplies are used to power the ISP1505 internal digital  
and analog circuits, and must not be used to power external circuits.  
For correct operation of the regulator, it is recommended that you connect REG3V3 and  
REG1V8 to decoupling capacitors. For an example, see Section 16.  
7.10.8 XTAL1 and XTAL2  
XTAL1 is the crystal input, and XTAL2 is the crystal output. The allowed frequency on the  
XTAL1 pin depends on the ISP1505 product version.  
If the link requires a 60 MHz clock from the ISP1505, then either a crystal must be  
attached, or a clock of the same frequency must be driven into XTAL1, with XTAL2 left  
floating.  
If a crystal is attached, it requires external load capacitors to GND on each terminal of the  
crystal. For details, see Section 16.  
If at any time the system wants to stop the clock on XTAL1, the link must first put the  
ISP1505 into low-power mode. The clock on XTAL1 must be restarted before low-power  
mode is exited.  
7.10.9 RESET_N/PSW_N  
This pin provides two optional functions. If neither function is used, this pin must be  
connected to VCC(I/O)  
.
7.10.9.1 RESET_N  
An active LOW asynchronous reset pin that resets all circuits in the ISP1505. The  
ISP1505 contains an internal power-on reset circuit, and therefore using the RESET_N  
pin is optional. If RESET_N is not used, it must be connected to VCC(I/O)  
.
For details on using RESET_N, see Section 9.3.2.  
7.10.9.2 PSW_N  
PSW_N is an active LOW, open-drain output pin. This pin can be connected to an active  
LOW, external VBUS switch or charge pump enable circuit to control the external VBUS  
power source. An external pull-up resistor, Rpullup, is required when PSW_N is used. This  
pin is open-drain, allowing ganged-mode power control for multiple USB ports. For  
application details, see Section 16.  
To use the PSW_N pin, the link must disable the reset input by setting the  
IGNORE_RESET bit in the Power Control register to logic 1. This will ensure that PSW_N  
is not misinterpreted as a reset.  
If the link is in host mode, it can enable the external VBUS power source by setting the  
DRV_VBUS_EXT bit in the OTG Control register to logic 1. The ISP1505 will drive  
PSW_N to LOW to enable the external VBUS power source. If the link detects an  
overcurrent condition (the VBUS state in RXCMD is not 11b), it must disable the external  
VBUS supply by setting DRV_VBUS_EXT to logic 0.  
ISP1505A_ISP1505C_3  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 03 — 26 August 2008  
11 of 75  
ISP1505A; ISP1505C  
NXP Semiconductors  
7.10.10 DIR  
ULPI HS USB host and peripheral transceiver  
ULPI direction output pin. Controls the direction of the data bus. By default, the ISP1505  
holds DIR at LOW, causing the data bus to be an input. When DIR is LOW, the ISP1505  
listens for data from the link. The ISP1505 pulls DIR to HIGH only when it has data to  
send to the link, which is for one of two reasons:  
To send the USB receive data, RXCMD status updates and register reads data to the  
link.  
To block the link from driving the data bus during power-up, reset and low-power  
mode (suspend).  
For details on DIR usage, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1.  
7.10.11 STP  
ULPI stop input pin. The link must assert STP to signal the end of a USB transmit packet  
or a register write operation. When DIR is asserted, the link can optionally assert STP to  
abort the ISP1505, causing it to deassert DIR in the next clock cycle. A weak pull-up  
resistor is incorporated into the STP pin as part of the interface protect feature. For details,  
see Section 9.3.1.  
For details on STP usage, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1.  
7.10.12 NXT  
ULPI next data output pin. The ISP1505 holds NXT at LOW, by default. When DIR is LOW  
and the link is sending data to the ISP1505, NXT will be asserted to notify the link to  
provide the next data byte. When DIR is at HIGH and the ISP1505 is sending data to the  
link, NXT will be asserted to notify the link that another valid byte is on the bus. NXT is not  
used for the register read data or the RXCMD status update.  
For details on NXT usage, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1.  
7.10.13 CLOCK  
A 60 MHz interface clock to synchronize the ULPI bus. The ISP1505 provides two  
clocking options:  
A crystal is attached between the XTAL1 and XTAL2 pins.  
A clock is driven into the XTAL1 pin, with the XTAL2 pin left floating.  
For details on CLOCK usage, refer to UTMI+ Low Pin Interface (ULPI) Specification  
Rev. 1.1.  
7.10.14 GND (die pad)  
Global ground signal. The die pad is exposed on the underside of the package as a  
ground plate. This acts as a ground to all circuits in the ISP1505. To ensure correct  
operation of the ISP1505, GND must be soldered to the cleanest ground available.  
ISP1505A_ISP1505C_3  
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Product data sheet  
Rev. 03 — 26 August 2008  
12 of 75  
ISP1505A; ISP1505C  
NXP Semiconductors  
ULPI HS USB host and peripheral transceiver  
8. Modes of operation  
8.1 ULPI modes  
The ISP1505 ULPI bus can be programmed to operate in four modes. Each mode  
reconfigures the signals on the data bus as described in the following subsections. Setting  
more than one mode will lead to undefined behavior.  
8.1.1 Synchronous mode  
This is default mode. At power-up, and when CLOCK is stable, the ISP1505 will enter  
synchronous mode. The link must synchronize all ULPI signals to CLOCK, meeting the  
set-up and hold times as defined in Section 15. A description of the ULPI pin behavior in  
synchronous mode is given in Table 3.  
This mode is used by the link to perform the following tasks:  
High-speed detection handshake (chirp)  
Transmit and receive USB packets  
Read and write to registers  
Receive USB status updates (RXCMDs)  
For more information on various synchronous mode protocols, see Section 9.  
Table 3.  
ULPI signal description  
Signal  
name  
Directionon Signal description  
ISP1505  
CLOCK  
O
60 MHz interface clock. If a crystal is attached or a clock is driven into  
the XTAL1 pin, the ISP1505 will drive a 60 MHz output clock.  
DATA[7:0] I/O  
8-bit data bus. In synchronous mode, the link drives DATA[7:0] to LOW  
by default. The link initiates transfers by sending a nonzero data pattern  
called TXCMD (transmit command). In synchronous mode, the direction  
of DATA[7:0] is controlled by DIR. Contents of DATA[7:0] lines must be  
ignored for exactly one clock cycle whenever DIR changes value. This is  
called the turnaround cycle.  
Data lines have fixed direction and different meaning in low-power and  
serial modes.  
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Product data sheet  
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ISP1505A; ISP1505C  
NXP Semiconductors  
ULPI HS USB host and peripheral transceiver  
Table 3.  
ULPI signal description …continued  
Signal  
name  
Directionon Signal description  
ISP1505  
DIR  
O
Direction: Controls the direction of data bus DATA[7:0]. In synchronous  
mode, the ISP1505 drives DIR to LOW by default, making the data bus  
an input so that the ISP1505 can listen for TXCMDs from the link. The  
ISP1505 drives DIR to HIGH only when it has data for the link. When  
DIR and NXT are HIGH, the byte on the data bus contains decoded  
USB data. When DIR is HIGH and NXT is LOW, the byte contains  
status information called RXCMD (receive command). The only  
exception to this rule is when the PHY returns register read data, where  
NXT is also LOW, replacing the usual RXCMD byte. Every change in  
DIR causes a turnaround cycle on the data bus, during which DATA[7:0]  
is not valid and must be ignored by the link.  
DIR is always asserted during low-power and serial modes.  
STP  
NXT  
I
Stop: In synchronous mode, the link drives STP to HIGH for one cycle  
after the last byte of data is sent to the ISP1505. The link can optionally  
assert STP to force DIR to be deasserted.  
In low-power and serial modes, the link holds STP at HIGH to wake up  
the ISP1505, causing the ULPI bus to return to synchronous mode.  
O
Next: In synchronous mode, the ISP1505 drives NXT to HIGH to  
throttle data. If DIR is LOW, the ISP1505 asserts NXT to notify the link  
to place the next data byte on DATA[7:0] in the following clock cycle. If  
DIR is HIGH, the ISP1505 asserts NXT to notify the link that a valid  
USB data byte is on DATA[7:0] in the current cycle. The ISP1505 always  
drives an RXCMD when DIR is HIGH and NXT is LOW, unless register  
read data is to be returned to the link in the current cycle.  
NXT is not used in low-power or serial mode.  
8.1.2 Low-power mode  
When the USB is idle, the link can place the ISP1505 into low-power mode (also called  
suspend mode). In low-power mode, the data bus definition changes to that shown in  
Table 4. To enter low-power mode, the link sets the SUSPENDM bit in the Function  
Control register to logic 0. To exit low-power mode, the link asserts the STP signal. The  
ISP1505 will draw only suspend current from the VCC supply (see Table 44).  
During low-power mode, the clock on XTAL1 may be stopped. The clock must be started  
again before asserting STP to exit low-power mode. After exiting low-power mode, the  
ISP1505 will send an RXCMD to the link if a change was detected in any interrupt source,  
and the change still exists. An RXCMD may not be sent if the interrupt condition is  
removed before exiting.  
For more information on low-power mode enter and exit protocols, refer to UTMI+ Low Pin  
Interface (ULPI) Specification Rev. 1.1.  
Table 4.  
Signal  
Signal mapping during low-power mode  
Maps to  
Direction  
Description  
LINESTATE0 DATA0  
LINESTATE1 DATA1  
O
O
combinatorial LINESTATE0 directly driven by the analog receiver  
combinatorial LINESTATE1 directly driven by the analog receiver  
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ULPI HS USB host and peripheral transceiver  
Table 4.  
Signal  
Reserved  
INT  
Signal mapping during low-power mode …continued  
Maps to  
DATA2  
DATA3  
Direction  
Description  
O
O
reserved; the ISP1505 will drive this pin to LOW  
active HIGH interrupt indication; will be asserted whenever any unmasked  
interrupt occurs  
Reserved  
DATA[7:4]  
O
reserved; the ISP1505 will drive these pins to LOW  
8.1.3 6-pin full-speed or low-speed serial mode  
If the link requires a 6-pin serial interface to transmit and receive full-speed or low-speed  
USB data, it can set the ISP1505 to 6-pin serial mode. In 6-pin serial mode, the DATA[7:0]  
bus definition changes to that shown in Table 5. To enter 6-pin serial mode, the link sets  
the 6PIN_FSLS_SERIAL bit in the Interface Control register to logic 1. To exit 6-pin serial  
mode, the link asserts STP. This is provided primarily for links that contain legacy  
full-speed or low-speed functionality, providing a more cost-effective upgrade path to  
high-speed. An interrupt pin is also provided to inform the link of USB events. If the link  
requires CLOCK to be running during 6-pin serial mode, the CLOCK_SUSPENDM  
register bit must be set to logic 1.  
For more information on 6-pin serial mode enter and exit protocols, refer to UTMI+ Low  
Pin Interface (ULPI) Specification Rev. 1.1.  
Table 5.  
Signal  
Signal mapping for 6-pin serial mode  
Maps to  
DATA0  
DATA1  
DATA2  
DATA3  
Direction  
Description  
TX_ENABLE  
TX_DAT  
TX_SE0  
INT  
I
active HIGH transmit enable  
transmit differential data on DP and DM  
transmit single-ended zero on DP and DM  
I
I
O
active HIGH interrupt indication; will be asserted whenever any  
unmasked interrupt occurs  
RX_DP  
DATA4  
DATA5  
DATA6  
DATA7  
O
O
O
O
single-ended receive data from DP  
RX_DM  
RX_RCV  
Reserved  
single-ended receive data from DM  
differential receive data from DP and DM  
reserved; the ISP1505 will drive this pin to LOW  
8.1.4 3-pin full-speed or low-speed serial mode  
If the link requires a 3-pin serial interface to transmit and receive full-speed or low-speed  
USB data, it can set the ISP1505 to 3-pin serial mode. In 3-pin serial mode, the data bus  
definition changes to that shown in Table 6. To enter 3-pin serial mode, the link sets the  
3PIN_FSLS_SERIAL bit in the Interface Control register to logic 1. To exit 3-pin serial  
mode, the link asserts STP. This is primarily provided for links that contain legacy  
full-speed or low-speed functionality, providing a more cost-effective upgrade path to  
high-speed. An interrupt pin is also provided to inform the link of USB events. If the link  
requires CLOCK to be running during 3-pin serial mode, the CLOCK_SUSPENDM  
register bit must be set to logic 1.  
For more information on 3-pin serial mode enter and exit protocols, refer to UTMI+ Low  
Pin Interface (ULPI) Specification Rev. 1.1.  
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ULPI HS USB host and peripheral transceiver  
Table 6.  
Signal  
Signal mapping for 3-pin serial mode  
Maps to  
DATA0  
DATA1  
Direction  
Description  
TX_ENABLE  
DAT  
I
active HIGH transmit enable  
I/O  
transmit differential data on DP and DM when TX_ENABLE is HIGH  
receive differential data from DP and DM when TX_ENABLE is LOW  
transmit single-ended zero on DP and DM when TX_ENABLE is HIGH  
receive single-ended zero from DP and DM when TX_ENABLE is LOW  
SE0  
DATA2  
I/O  
INT  
DATA3  
O
O
active HIGH interrupt indication; will be asserted whenever any  
unmasked interrupt occurs  
Reserved  
DATA[7:4]  
reserved; the ISP1505 will drive these pins to LOW  
8.2 USB and OTG state transitions  
A Hi-Speed USB peripheral, host or OTG device handles more than one electrical state as  
defined in Universal Serial Bus Specification Rev. 2.0 and On-The-Go Supplement to the  
USB 2.0 Specification Rev. 1.3. The ISP1505 accommodates the various states through  
register bit settings of XCVRSELECT[1:0], TERMSELECT, OPMODE[1:0],  
DP_PULLDOWN and DM_PULLDOWN.  
Table 7 summarizes operating states. The values of register settings in Table 7 will force  
resistor settings as also given in Table 7. Resistor setting signals are defined as follows:  
RPU_DP_EN enables the 1.5 kpull-up resistor on DP  
RPD_DP_EN enables the 15 kpull-down resistor on DP  
RPD_DM_EN enables the 15 kpull-down resistor on DM  
HSTERM_EN enables the 45 termination resistors on DP and DM  
It is up to the link to set the desired register settings.  
Table 7.  
Operating states and their corresponding resistor settings  
Signaling mode  
Register settings  
Internal resistor settings  
OPMODE DP_PULL DM_PULL RPU_ RPD_ RPD_  
DP_EN DP_EN DM_EN _EN  
XCVR TERM  
SELECT SELECT [1:0]  
[1:0]  
HSTERM  
DOWN  
DOWN  
General settings  
3-state drivers  
XXb  
01b  
Xb  
0b  
01b  
00b  
Xb  
1b  
Xb  
1b  
0b  
0b  
0b  
1b  
0b  
1b  
0b  
0b  
Power-up or  
VBUS < VB_SESS_END  
Host settings  
Host chirp  
00b  
00b  
X1b  
01b  
0b  
0b  
1b  
1b  
10b  
00b  
00b  
00b  
1b  
1b  
1b  
1b  
1b  
1b  
1b  
1b  
0b  
0b  
0b  
0b  
1b  
1b  
1b  
1b  
1b  
1b  
1b  
1b  
1b  
1b  
0b  
0b  
Host high-speed  
Host full-speed  
Host high-speed or  
full-speed suspend  
Host high-speed or  
full-speed resume  
01b  
10b  
1b  
1b  
10b  
00b  
1b  
1b  
1b  
1b  
0b  
0b  
1b  
1b  
1b  
1b  
0b  
0b  
Host low-speed  
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ULPI HS USB host and peripheral transceiver  
Table 7.  
Operating states and their corresponding resistor settings …continued  
Signaling mode  
Register settings  
XCVR TERM  
Internal resistor settings  
OPMODE DP_PULL DM_PULL RPU_  
RPD_  
RPD_  
HSTERM  
SELECT SELECT [1:0]  
[1:0]  
DOWN  
DOWN  
DP_EN DP_EN DM_EN _EN  
Host low-speed  
suspend  
10b  
1b  
1b  
0b  
00b  
10b  
10b  
1b  
1b  
0b  
0b  
0b  
1b  
1b  
1b  
1b  
1b  
1b  
0b  
0b  
1b  
Host low-speed  
resume  
10b  
1b  
1b  
Host Test J or Test K 00b  
1b  
1b  
Peripheral settings  
Peripheral chirp  
00b  
00b  
1b  
0b  
10b  
00b  
0b  
0b  
0b  
0b  
1b  
0b  
0b  
0b  
0b  
0b  
0b  
1b  
Peripheral  
high-speed  
Peripheral full-speed 01b  
1b  
1b  
00b  
00b  
0b  
0b  
0b  
0b  
1b  
1b  
0b  
0b  
0b  
0b  
0b  
0b  
Peripheral  
01b  
high-speed or  
full-speed suspend  
Peripheral  
high-speed or  
full-speed resume  
01b  
1b  
0b  
10b  
10b  
0b  
0b  
0b  
0b  
1b  
0b  
0b  
0b  
0b  
0b  
0b  
1b  
Peripheral Test J or 00b  
Test K  
OTG settings  
OTG device  
peripheral chirp  
00b  
00b  
1b  
0b  
10b  
00b  
0b  
0b  
1b  
1b  
1b  
0b  
0b  
0b  
1b  
1b  
0b  
1b  
OTG device  
peripheral  
high-speed  
OTG device  
peripheral full-speed  
01b  
01b  
1b  
1b  
00b  
00b  
0b  
0b  
1b  
1b  
1b  
1b  
0b  
0b  
1b  
1b  
0b  
0b  
OTG device  
peripheral  
high-speed and  
full-speed suspend  
OTG device  
peripheral  
high-speed and  
full-speed resume  
01b  
00b  
1b  
0b  
10b  
10b  
0b  
0b  
1b  
1b  
1b  
0b  
0b  
0b  
1b  
1b  
0b  
1b  
OTG device  
peripheral Test J or  
Test K  
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ISP1505A; ISP1505C  
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ULPI HS USB host and peripheral transceiver  
9. Protocol description  
The following subsections describe the protocol for using the ISP1505.  
9.1 ULPI references  
The ISP1505 provides a 12-pin ULPI interface to communicate with the link. It is highly  
recommended that you read UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 and  
UTMI+ Specification Rev. 1.0.  
9.2 Power-On Reset (POR)  
An internal POR is generated when REG1V8 rises above VPOR(trip), for at least  
tw(REG1V8_H). The internal POR pulse will also be generated whenever REG1V8 drops  
below VPOR(trip) for more than tw(REG1V8_L), and then rises above VPOR(trip) again. The  
voltage on REG1V8 is generated from VCC  
.
To give a better view of the functionality, Figure 3 shows a possible curve of REG1V8. The  
internal POR starts with logic 0 at t0. At t1, the detector will see the passing of the trip  
level so that POR turns to logic 1 and a delay element will add another tPORP before it  
drops to logic 0. If REG1V8 dips from t2 to t3 for > tw(REG1V8_L), another POR pulse is  
generated. If the dip at t4 to t5 is too short, that is, < tw(REG1V8_L), the internal POR pulse  
will not react and will remain LOW.  
REG1V8  
V
POR(trip)  
t4  
t3  
t5  
t0  
t1  
t
t2  
POR  
t
PORP  
PORP  
004aaa751  
Fig 3. Internal power-on reset timing  
9.3 Power-up, reset and bus idle sequence  
Figure 4 shows a typical start-up sequence.  
On power-up, the ISP1505 performs an internal power-on reset and asserts DIR to  
indicate to the link that the ULPI bus cannot be used. When the internal PLL is stable, the  
ISP1505 deasserts DIR. The power-up time depends on the VCC supply rise time, the  
crystal start-up time, and PLL start-up time tstartup(o)(CLOCK). Whenever DIR is asserted,  
the ISP1505 drives the NXT pin to LOW and drives DATA[7:0] with RXCMD values. When  
DIR is deasserted, the link must drive the data bus to a valid level. By default, the link  
must drive data to LOW. When the ISP1505 initially deasserts DIR on power-up, the link  
must ignore all RXCMDs until it resets the ISP1505. Before beginning USB packets, the  
link must set the RESET bit in the Function Control register to reset the ISP1505. After the  
RESET bit is set, the ISP1505 will assert DIR until the internal reset completes. The  
ISP1505 will automatically deassert DIR and clear the RESET bit when reset has  
completed. After every reset, an RXCMD is sent to the link to update USB status  
information. After this sequence, the ULPI bus is ready for use and the link can start USB  
operations.  
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ISP1505A; ISP1505C  
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If a crystal is attached or a clock is driven into the XTAL1 pin, the ISP1505 will drive a  
60 MHz clock out from the CLOCK pin when DIR deasserts. This is shown as CLOCK in  
Figure 4.  
The recommended power-up sequence for the link is as follows:  
1. The link waits for 1 ms, ignoring all the ULPI pin status.  
2. The link may start to detect DIR status level. If DIR is detected as LOW for three clock  
cycles, the link may send a RESET command.  
The ULPI interface is ready for use.  
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ISP1505A; ISP1505C  
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ULPI HS USB host and peripheral transceiver  
V
CC  
V
CC(I/O)  
REG1V8  
t
PWRUP  
internal  
REG1V8  
detector  
internal  
POR  
XTAL1  
bus idle  
internal clocks stable  
RESET command  
t
startup(PLL)  
CLOCK  
DATA[7:0]  
D
TXCMD  
RXCMD  
update  
internal reset  
DIR  
STP  
NXT  
t5  
t2  
t3  
t4  
t1  
004aaa885  
t1 = VCC and VCC(I/O) are applied to the ISP1505. The ISP1505 regulator starts to turn on.  
t2 = ULPI pads detect REG1V8 rising above the REG1V8 regulator threshold and are not in 3-state. These pads may drive  
either LOW or HIGH. It is recommended that the link ignores the ULPI pins status during tPWRUP  
.
t3 = The POR threshold is reached and a POR pulse is generated. After the POR pulse, ULPI pins are driven to a defined level.  
DIR is driven to HIGH and the other pins are driven to LOW.  
t4 = The internal PLL is stabilized after tstartup(PLL). If the 19.2 MHz or 26 MHz clock is started before POR, the internal PLL will  
be stabilized after tstartup(PLL) from POR. The CLOCK pin starts to output 60 MHz. The DIR pin will transition from HIGH to LOW.  
The DIR pin will remain LOW before the link issues a RESET command to the ISP1505.  
t5 = The power-up sequence is completed and the ULPI bus interface is ready for use.  
Fig 4. Power-up and reset sequence required before the ULPI bus is ready for use  
9.3.1 Interface protection  
By default, the ISP1505 enables a weak pull-up resistor on STP. If the STP pin is  
unexpectedly HIGH at any time, the ISP1505 will protect the ULPI interface by enabling  
weak pull-down resistors on DATA[7:0].  
The interface protect feature prevents unwanted activity of the ISP1505 whenever the  
ULPI interface is not correctly driven by the link. For example, when the link powers up  
more slowly than the ISP1505.  
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The interface protect feature can be disabled by setting the INTF_PROT_DIS bit to logic 1.  
9.3.2 Interface behavior with respect to RESET_N  
The use of the RESET_N pin is optional. When RESET_N is asserted (LOW), the  
ISP1505 will assert DIR. All logic in the ISP1505 will be reset, including the analog  
circuitry and ULPI registers. During reset, the link must drive DATA[7:0] and STP to LOW;  
otherwise undefined behavior may result. When RESET_N is deasserted (HIGH), the DIR  
output will deassert (LOW) four or five clock cycles later. Figure 5 shows the ULPI  
interface behavior when RESET_N is asserted (LOW), and subsequently deasserted  
(HIGH). If RESET_N is not used, it must be connected to VCC(I/O)  
.
CLOCK  
RESET_N  
DATA[7:0]  
Hi-Z (input)  
Hi-Z (input)  
Hi-Z (link must drive)  
Hi-Z (link must drive)  
Hi-Z (input)  
DIR  
Hi-Z (input)  
STP  
NXT  
004aaa720  
Fig 5. Interface behavior with respect to RESET_N  
9.4 VBUS power and fault detection  
9.4.1 Driving 5 V on VBUS  
The ISP1505 supports external 5 V supplies. The ISP1505 can control the external supply  
using the active-LOW PSW_N open-drain output pin. To enable the external supply by  
driving PSW_N to LOW, the link must set the DRV_VBUS_EXT bit in the OTG Control  
register to logic 1. When the DRV_VBUS_EXT bit is set, the DRV_VBUS bit can be set to  
any value and will be ignored.  
9.4.2 Fault detection  
The ISP1505 supports external VBUS fault detector circuits. An overcurrent detection  
circuit is required for host applications that supply more than 100 mA on VBUS for voltages  
between 4.75 V to 5.25 V. For low-power applications supplying less than 100 mA, the  
VBUS power line can directly be connected to the VBUS/FAULT pin on the ISP1505 and the  
link can utilize the internal A_VBUS_VLD comparator.  
The ISP1505 supports external VBUS fault detector circuits that output a digital fault  
indicator signal. The indicator signal must be connected to the VBUS/FAULT pin. To enable  
the ISP1505 to monitor the digital fault input, the link must set the USE_EXT_VBUS_IND  
bit in the OTG Control register and the IND_PASSTHRU bit in the Interface Control  
register to logic 1. For details, see Figure 7.  
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ISP1505A; ISP1505C  
NXP Semiconductors  
ULPI HS USB host and peripheral transceiver  
The FAULT input pin is mapped to the A_VBUS_VLD bit in RXCMD. Any changes for the  
FAULT input will trigger RXCMD carrying the FAULT condition with A_VBUS_VLD.  
9.5 TXCMD and RXCMD  
Commands between the ISP1505 and the link are described in the following subsections.  
9.5.1 TXCMD  
By default, the link must drive the ULPI bus to its idle state of 00h. To send commands and  
USB packets, the link drives a nonzero value on DATA[7:0] to the ISP1505 by sending a  
byte called TXCMD. Commands include USB packet transmissions, and register reads  
and writes. Once the TXCMD is interpreted and accepted by the ISP1505, the NXT signal  
is asserted and the link can follow up with the required number of data bytes. The TXCMD  
byte format is given in Table 8. Any values other than those in Table 8 are illegal and may  
result in undefined behavior.  
Various TXCMD packet and register sequences are shown in later sections.  
Table 8.  
TXCMD byte format  
Command Command code Command  
Command Command description  
type name DATA[7:6] payload DATA[5:0] name  
Idle  
00b  
01b  
00 0000b  
00 0000b  
NOOP  
NOPID  
No operation. 00h is the idle value of the data bus. The  
link must drive NOOP by default.  
Packet  
transmit  
Transmit USB data that does not have a PID, such as  
chirp and resume signaling. The ISP1505 starts  
transmitting only after accepting the next data byte.  
00 XXXXb  
10 1111b  
PID  
Transmit USB packet. DATA[3:0] indicates USB packet  
identifier PID[3:0].  
Register  
write  
10b  
11b  
EXTW  
Extended register write command (optional). The 8-bit  
address must be provided after the command is  
accepted.  
XX XXXXb  
10 1111b  
REGW  
EXTR  
Register write command with 6-bit immediate address.  
Register  
read  
Extended register read command (optional). The 8-bit  
address must be provided after the command is  
accepted.  
XX XXXXb  
REGR  
Register read command with 6-bit immediate address.  
9.5.2 RXCMD  
The ISP1505 communicates status information to the link by asserting DIR and sending  
an RXCMD byte on the data bus. The RXCMD data byte format is given in Table 9.  
The ISP1505 will automatically send an RXCMD whenever there is a change in any of the  
RXCMD data fields. The link must be able to accept an RXCMD at any time; including  
single RXCMDs, back-to-back RXCMDs, and RXCMDs at any time during USB receive  
packets when NXT is LOW. An example is shown in Figure 6. For details and diagrams,  
refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1.  
An RXCMD may not be sent when exiting low-power mode or serial mode, if the interrupt  
condition is removed before exiting.  
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Table 9.  
DATA  
RXCMD byte format  
Name Description and value  
1 to 0  
LINESTATE LINESTATE signals: For a definition of LINESTATE, see Section 9.5.2.1.  
DATA0 — LINESTATE[0]  
DATA1 — LINESTATE[1]  
3 to 2  
5 to 4  
6
VBUS state  
RxEvent  
reserved  
ALT_INT  
Encoded VBUS voltage state: For an explanation of the VBUS state, see Section 9.5.2.2.  
Encoded USB event signals: For an explanation of RxEvent, see Section 9.5.2.4.  
-
7
By default, this signal is not used and is not needed in typical designs. Optionally, the link can  
enable the BVALID_RISE and/or BVALID_FALL bits in the Power Control register. Corresponding  
changes in BVALID will cause an RXCMD to be sent to the link with the ALT_INT bit asserted.  
CLOCK  
Single RXCMD  
RXCMD  
Back-to-back RXCMDs  
RXCMD RXCMD  
turnaround  
turnaround  
turnaround  
turnaround  
[
]
DATA 7:0  
DIR  
STP  
NXT  
004aaa695  
Fig 6. Single and back-to-back RXCMDs from the ISP1505 to the link  
9.5.2.1 Linestate encoding  
LINESTATE[1:0] reflects the current state of DP and DM. Whenever the ISP1505 detects  
a change in DP or DM, an RXCMD will be sent to the link with the new LINESTATE[1:0]  
value. The value given on LINESTATE[1:0] depends on the setting of various registers.  
Table 10 shows the LINESTATE[1:0] encoding for upstream facing ports, which applies to  
peripherals. Table 11 shows the LINESTATE[1:0] encoding for downstream facing ports,  
which applies to host controllers. Dual-role devices must choose the correct table,  
depending on whether it is in peripheral or host mode.  
Table 10. LINESTATE[1:0] encoding for upstream facing ports: peripheral  
DP_PULLDOWN = 0.[1]  
Mode  
Full-speed  
01, 11  
1
High-speed  
00  
Chirp  
XCVRSELECT[1:0]  
TERMSELECT  
LINESTATE[1:0]  
00  
0
1
00  
01  
10  
11  
SE0  
squelch  
!squelch  
invalid  
invalid  
squelch  
FS-J  
!squelch and HS_Differential_Receiver_Output  
!squelch and !HS_Differential_Receiver_Output  
invalid  
FS-K  
SE1  
[1] !squelch indicates inactive squelch. !HS_Differential_Receiver_Output indicates inactive HS_Differential_Receiver_Output.  
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Table 11. LINESTATE[1:0] encoding for downstream facing ports: host  
DP_PULLDOWN and DM_PULLDOWN = 1.[1]  
Mode  
Low-speed  
Full-speed High-speed  
Chirp  
XCVRSELECT[1:0]  
TERMSELECT  
OPMODE[1:0]  
LINESTATE[1:0]  
10  
01, 11  
1
00  
00  
1
0
0
X
X
00, 01, 11  
squelch  
!squelch  
invalid  
invalid  
10  
00  
01  
10  
11  
SE0  
LS-K  
LS-J  
SE1  
SE0  
FS-J  
FS-K  
SE1  
squelch  
!squelch and HS_Differential_Receiver_Output  
!squelch and !HS_Differential_Receiver_Output  
invalid  
[1] !squelch indicates inactive squelch. !HS_Differential_Receiver_Output indicates inactive HS_Differential_Receiver_Output.  
9.5.2.2 VBUS state encoding  
USB devices must monitor the VBUS voltage for purposes such as overcurrent detection,  
starting a session and SRP. The VBUS state field in the RXCMD is an encoding of the  
voltage level on VBUS  
.
The A_VBUS_VLD, SESS_VLD and SESS_END indicators in the VBUS state are directly  
taken from internal comparators built-in to the ISP1505, and encoded as shown in Table 9  
and Table 12.  
An RXCMD may not be sent when exiting low-power mode or serial mode, if the interrupt  
condition is removed before exiting.  
Table 12. Encoded VBUS voltage state  
Value  
00  
VBUS voltage  
SESS_END SESS_VLD A_VBUS_VLD  
VBUS < VB_SESS_END  
1
0
X
X
0
0
1
X
0
0
0
1
01  
VB_SESS_END VBUS < VB_SESS_VLD  
VB_SESS_VLD VBUS < VA_VBUS_VLD  
VBUS VA_VBUS_VLD  
10  
11  
Note that VBUS and FAULT share the same pin and cannot be simultaneously used.  
A_VBUS_VLD and FAULT will be interpreted by the ISP1505 as shown in Figure 7.  
A description on how to use and select the VBUS state encoding is given in  
Section 9.5.2.3.  
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ULPI HS USB host and peripheral transceiver  
A_VBUS_VLD comparator  
(V < 4.4 V)  
BUS  
internal A_VBUS_VLD  
V
/FAULT  
BUS  
(0, X)  
(1, 1)  
RXCMD  
A_VBUS_VLD  
complement output  
IND_COMPL  
USE_EXT_VBUS_IND,  
IND_PASSTHRU  
004aaa752  
Fig 7. RXCMD A_VBUS_VLD indicator source  
9.5.2.3 Using and selecting the VBUS state encoding  
The VBUS state encoding is shown in Table 9. The ISP1505 will send an RXCMD to the  
link whenever there is a change in the VBUS state. To receive VBUS state updates, the link  
must first enable the corresponding interrupts in the USB Interrupt Enable Rising Edge  
and USB Interrupt Enable Falling Edge registers.  
The link can use the VBUS state to monitor VBUS and take appropriate action. Table 13  
shows the recommended usage for typical applications.  
Table 13. VBUS indicators in RXCMD required for typical applications  
Application  
A_VBUS_VLD  
SESS_VLD  
SESS_END  
Standard host  
Standard peripheral  
OTG A-device  
OTG B-device  
yes  
no  
no  
no  
no  
no  
yes  
yes  
yes  
yes  
yes  
no  
Standard USB host controllers: For standard hosts, the system must be able to provide  
500 mA on VBUS in the range of 4.75 V to 5.25 V. An external circuit must be used to  
detect overcurrent conditions. If the external overcurrent detector provides a digital fault  
signal, then the fault signal must be connected to the ISP1505 FAULT input pin, and the  
link must do the following:  
1. Set the IND_COMPL bit in the Interface Control register to logic 0 or logic 1,  
depending on the polarity of the external fault signal.  
2. Set the IND_PASSTHRU bit in the Interface Control register to logic 1.  
3. Set the USE_EXT_VBUS_IND bit in the OTG Control register to logic 1.  
Standard USB peripheral controllers: Standard peripherals must be able to detect  
when VBUS is at a sufficient level for operation. SESS_VLD must be enabled to detect the  
start and end of USB peripheral operations. Detection of A_VBUS_VLD and SESS_END  
thresholds is not needed for standard peripherals.  
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OTG devices: The ISP1505 provides partial OTG support. A low-power OTG A-device  
that supplies less than 100 mA on VBUS can connect the VBUS power to the ISP1505 VBUS  
pin. The internal A_VBUS_VLD comparator can be used. If the OTG A-device provides  
more than 100 mA on VBUS, an overcurrent detector must be used and Section “Standard  
USB host controllers” on page 25 applies. The OTG A-device also uses SESS_VLD to  
detect when an OTG B-device is initiating VBUS pulsing SRP.  
When an OTG device is configured as an OTG B-device, SESS_VLD must be used to  
detect when VBUS is at a sufficient level for operation. SESS_END must be used to detect  
when VBUS has dropped to a LOW level, allowing the B-device to safely initiate VBUS  
pulsing SRP.  
9.5.2.4 RxEvent encoding  
The RxEvent field (see Table 14) of the RXCMD informs the link of information related  
packets received on the USB bus. RxActive and RxError are defined in USB 2.0  
Transceiver Macrocell Interface (UTMI) Specification Ver. 1.05. HostDisconnect is defined  
in UTMI+ Specification Rev. 1.0. A short definition is also given in the following  
subsections.  
Table 14. Encoded USB event signals  
Value  
00  
RxActive  
RxError  
HostDisconnect  
0
1
1
X
0
0
1
X
0
0
0
1
01  
11  
10  
RxActive: When the ISP1505 has detected a SYNC pattern on the USB bus, it signals an  
RxActive event to the link. An RxActive event can be communicated using two methods.  
The first method is for the ISP1505 to simultaneously assert DIR and NXT. The second  
method is for the ISP1505 to send an RXCMD to the link with the RxActive field in  
RxEvent bits set to logic 1. The link must be able to detect both methods. RxActive frames  
the receive packet from the first byte to the last byte.  
The link must assume that RxActive is set to logic 0 when indicated in an RXCMD or when  
DIR is deasserted, whichever occurs first.  
The link uses RxActive to time high-speed packets and ensure that bus turnaround times  
are met. For more information on the USB packet timing, see Section 9.8.1.  
RxError: When the ISP1505 has detected an error while receiving a USB packet, it  
deasserts NXT and sends an RXCMD with the RxError field set to logic 1. The received  
packet is no longer valid and must be dropped by the link.  
HostDisconnect: HostDisconnect is encoded into the RxEvent field of the RXCMD.  
HostDisconnect is valid only when the ISP1505 is configured as a host (both  
DP_PULLDOWN and DM_PULLDOWN are set to logic 1), and indicates to the host  
controller when a peripheral is connected or disconnected. The host controller must  
enable HostDisconnect by setting the HOST_DISCON_R and HOST_DISCON_F bits in  
the USB Interrupt Enable Rising Edge and USB Interrupt Enable Falling Edge registers,  
respectively. Changes in HostDisconnect will cause the PHY to send an RXCMD to the  
link with the updated value.  
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ISP1505A; ISP1505C  
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ULPI HS USB host and peripheral transceiver  
9.6 Register read and write operations  
Figure 8 shows register read and write sequences. The ISP1505 supports immediate  
addressing and extended addressing register operations. Extended register addressing is  
optional for links. Note that register operations will be aborted if the ISP1505 unexpectedly  
asserts DIR during the operation. When a register operation is aborted, the link must retry  
until successful. For more information on register operations, refer to UTMI+ Low Pin  
Interface (ULPI) Specification Rev. 1.1.  
CLOCK  
TXCMD  
(REGW) D  
TXCMD  
(REGR)  
TXCMD  
(EXTW) AD  
TXCMD  
(EXTW) AD  
D
D
D
DATA[7:0]  
immediate  
register write  
extended  
register write  
immediate  
register read  
extended  
register read  
DIR  
STP  
NXT  
004aaa710  
AD indicates the address byte, and D indicates the data byte.  
Fig 8. Example of register write, register read, extended register write and extended register read  
9.7 USB reset and high-speed detection handshake (chirp)  
Figure 9 shows the sequence of events for USB reset and high-speed detection  
handshake (chirp). The sequence is shown for hosts and peripherals. Figure 9 does not  
show all RXCMD updates and timing is not to scale. The sequence is as follows:  
1. USB reset: The host detects a peripheral attachment as low-speed if DM is HIGH and  
as full-speed if DP is HIGH. If a host detects a low-speed peripheral, it does not follow  
the remainder of this protocol. If a host detects a full-speed peripheral, it resets the  
peripheral by writing to the Function Control register and setting  
XCVRSELECT[1:0] = 00b (high-speed) and TERMSELECT = 0b, which drives SE0  
on the bus (DP and DM connected to ground through 45 ). The host also sets  
OPMODE[1:0] = 10b for correct chirp transmit and receive. The start of SE0 is labeled  
T0.  
Remark: To receive chirp signaling, the host must also consider the high-speed  
differential receiver output. The host controller must interpret LINESTATE[1:0] as  
shown in Table 11.  
2. High-speed detection handshake (chirp)  
a. Peripheral chirp: After detecting SE0 for no less than 2.5 µs, if the peripheral is  
capable of high-speed, it sets XCVRSELECT[1:0] = 00b (high-speed) and  
OPMODE[1:0] = 10b (chirp). The peripheral immediately follows this with a  
TXCMD (NOPID), transmitting a Chirp K for no less than 1 ms and ending no more  
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than 7 ms after reset time T0. If the peripheral is in low-power mode, it must wake  
up its clock within 5.6 ms, leaving 200 µs for the link to start transmitting the  
Chirp K, and 1.2 ms for the Chirp K to complete (worst case with 10 % slow clock).  
b. Host chirp: If the host does not detect the peripheral chirp, it must continue  
asserting SE0 until the end of reset. If the host detects the peripheral Chirp K for  
no less than 2.5 µs, then no more than 100 µs after the bus leaves the Chirp K  
state, the host sends a TXCMD (NOPID) with an alternating sequence of Chirp Ks  
and Js. Each Chirp K or Chirp J must last for no less than 40 µs and no longer than  
60 µs.  
c. High-speed idle: The peripheral must detect a minimum of Chirp K-J-K-J-K-J. Each  
Chirp K and Chirp J must be detected for at least 2.5 µs. After seeing that  
minimum sequence, the peripheral sets TERMSELECT = 0b and  
OPMODE[1:0] = 00b. The peripheral is now in high-speed mode and sees !squelch  
(01b on LINESTATE). When the peripheral sees squelch (10b on LINESTATE), it  
knows that the host has completed chirp and waits for Hi-Speed USB traffic to  
begin. After transmitting the chirp sequence, the host changes OPMODE[1:0] to  
00b and begins sending USB packets.  
For more information, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1.  
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ISP1505A; ISP1505C  
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ULPI HS USB host and peripheral transceiver  
USB reset  
high-speed detection handshake (chirp)  
T
0
peripheral chirp  
host chirp  
HS idle  
TXCMD  
(REGW)  
TXCMD  
(REGW)  
TXCMD  
NOPID  
SE0  
K
00  
K
...  
J
K
J
DATA  
[
]
7:0  
DIR  
STP  
NXT  
00 (HS)  
01 (FS)  
XCVR  
SELECT  
TERM  
SELECT  
00 (normal)  
00 (normal)  
J (01b)  
01 (chirp)  
OP  
MODE  
squelch  
(00b)  
SE0 (00b)  
host chirp K (10b) or chirp J (01b)  
peripheral chirp K (10b)  
squelch (00b)  
LINE  
STATE  
RXCMDs  
TXCMD  
TXCMD  
(REGW)  
TXCMD  
NOPID  
(REGW)  
00  
K
J
K
J
00  
SE0  
K
K
...  
K
K
J
DATA  
[
]
7:0  
DIR  
STP  
NXT  
01 (FS)  
00 (HS)  
XCVR  
SELECT  
TERM  
SELECT  
00 (normal)  
10 (chirp)  
00 (normal)  
OP  
MODE  
squelch  
(00b)  
!squelch  
(01b)  
squelch (00b)  
peripheral chirp K (10b)  
J (01b)  
SE0 (00b)  
host chirp K or J (10b or 01b)  
LINE  
STATE  
DP  
DM  
004aaa711  
Timing is not to scale.  
Fig 9. USB reset and high-speed detection handshake (chirp) sequence  
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ISP1505A; ISP1505C  
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ULPI HS USB host and peripheral transceiver  
9.8 USB packet transmit and receive  
An example of a packet transmit and receive is shown in Figure 10. For details on USB  
packets, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1.  
ISP1505  
deasserts  
DIR, causing  
ISP1505  
asserts DIR,  
causing  
turnaround  
cycle  
link sends  
the next data;  
ISP1505  
ISP1505  
sends  
RXCMD  
(NXT LOW)  
ISP1505  
sends  
ISP1505  
accepts  
TXCMD  
link sends  
TXCMD  
link signals ULPI bus  
end of data is idle  
USB data turnaround  
(NXT HIGH) cycle  
accepts  
CLOCK  
turnaround RXCMD  
DATA  
turnaround  
[
]
TXCMD  
DATA  
DATA 7:0  
DIR  
STP  
NXT  
004aaa705  
Fig 10. Example of using the ISP1505 to transmit and receive USB data  
9.8.1 USB packet timing  
9.8.1.1 ISP1505 pipeline delays  
The ISP1505 delays are shown in Table 15. For a detailed description, refer to UTMI+ Low  
Pin Interface (ULPI) Specification Rev. 1.1, Section 3.8.2.6.2.  
Table 15. PHY pipeline delays  
Parameter name  
RXCMD delay (J and K)  
RXCMD delay (SE0)  
TX start delay  
High-speed PHY delay  
Full-speed PHY delay  
4
Low-speed PHY delay  
4
4
4
4 to 6  
16 to 18  
1 to 2  
3 to 4  
6 to 9  
5 to 6  
5 to 6  
6 to 10  
74 to 75  
TX end delay (packets)  
TX end delay (SOF)  
RX start delay  
not applicable  
not applicable  
not applicable  
17 to 18  
not applicable  
not applicable  
not applicable  
122 to 123  
RX end delay  
9.8.1.2 Allowed link decision time  
The amount of clock cycles allocated to the link to respond to a received packet and  
correctly receive back-to-back packets is given in Table 16. Link designs must follow  
values given in Table 16 for correct USB system operation. Examples of high-speed  
packet sequences and timing are shown in Figure 11 and Figure 12. For details, refer to  
UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1, Section 3.8.2.6.3.  
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ISP1505A; ISP1505C  
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ULPI HS USB host and peripheral transceiver  
Table 16. Link decision times  
Packet sequence High-speed Full-speed Low-speed Definition  
link delay  
link delay  
link delay  
Transmit-Transmit 15 to 24  
(host only)  
7 to 18  
77 to 247  
Number of clock cycles a host link must wait before driving  
the TXCMD for the second packet.  
In high-speed, the link starts counting from the assertion of  
STP for the first packet.  
In full-speed, the link starts counting from the RXCMD,  
indicating LINESTATE has changed from SE0 to J for the  
first packet. The timing given ensures inter-packet delays of  
2 bit times to 6.5 bit times.  
Receive-Transmit 1 to 14  
(host or  
7 to 18  
77 to 247  
Number of clock cycles the link must wait before driving the  
TXCMD for the transmit packet.  
peripheral)  
In high-speed, the link starts counting from the end of the  
receive packet; deassertion of DIR or an RXCMD, indicating  
RxActive is LOW.  
In full-speed or low-speed, the link starts counting from the  
RXCMD, indicating LINESTATE has changed from SE0 to J  
for the receive packet. The timing given ensures  
inter-packet delays of 2 bit times to 6.5 bit times.  
Receive-Receive  
(peripheral only)  
1
1
1
Minimum number of clock cycles between consecutive  
receive packets. The link must be able to receive both  
packets.  
Transmit-Receive 92  
(host or  
peripheral)  
80  
718  
Host or peripheral transmits a packet and will time-out after  
this number of clock cycles if a response is not received.  
Any subsequent transmission can occur after this time.  
USB interpacket delay (88 to 192 high-speed bit times)  
DP or  
DM  
IDLE  
EOP  
SYNC  
D0  
DATA  
CLOCK  
D
N1  
D
N
D1  
TXCMD  
DATA  
[7:0]  
DIR  
STP  
NXT  
link decision time (15 to 24 clocks)  
TX start delay  
TX end delay (two to five clocks)  
(one to two clocks)  
004aaa712  
Fig 11. High-speed transmit-to-transmit packet timing  
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ISP1505A; ISP1505C  
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ULPI HS USB host and peripheral transceiver  
USB interpacket delay (8 to 192 high-speed bit times)  
DP or  
DM  
IDLE  
EOP  
SYNC  
DATA  
CLOCK  
D
N
D
N4  
D
N2  
D0  
D1  
TXCMD  
DATA  
[7:0]  
turnaround  
D
N3  
D
N1  
DIR  
STP  
NXT  
link decision time (1 to 14 clocks)  
RX end delay  
(three to eight clocks)  
TX start delay  
(one to two clocks)  
004aaa713  
Fig 12. High-speed receive-to-transmit packet timing  
9.9 Preamble  
Preamble packets are headers to low-speed packets that must travel over a full-speed  
bus, between a host and a hub. To enter preamble mode, the link sets  
XCVRSELECT[1:0] = 11b in the Function Control register. When in preamble mode, the  
ISP1505 operates just as in full-speed mode, and sends all data with the full-speed rise  
time and fall time. Whenever the link transmits a USB packet in preamble mode, the  
ISP1505 will automatically send a preamble header at full-speed bit rate before sending  
the link packet at low-speed bit rate. The ISP1505 will ensure a minimum gap of four  
full-speed bit times between the last bit of the full-speed PRE PID and the first bit of the  
low-speed packet SYNC. The ISP1505 will drive a J for at least one full-speed bit time  
after sending the PRE PID, after which the pull-up resistor can hold the J state on the bus.  
An example transmit packet is shown in Figure 13.  
In preamble mode, the ISP1505 can also receive low-speed packets from the full-speed  
bus.  
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Product data sheet  
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32 of 75  
ISP1505A; ISP1505C  
NXP Semiconductors  
ULPI HS USB host and peripheral transceiver  
CLOCK  
D1  
D0  
TXCMD (low-speed packet ID)  
DATA[7:0]  
DIR  
STP  
NXT  
FS  
PRE ID  
IDLE (min  
4 FS bits)  
LS D0  
LS D1  
LS SYNC  
LS PID  
FS SYNC  
DP or DM  
004aaa714  
DP and DM timing is not to scale.  
Fig 13. Preamble sequence  
9.10 USB suspend and resume  
9.10.1 Full-speed and low-speed host-initiated suspend and resume  
Figure 14 illustrates how a host or a hub places a full-speed or low-speed peripheral into  
suspend and sometime later initiates resume signaling to wake up the downstream  
peripheral. Note that Figure 14 timing is not to scale, and does not show all RXCMD  
LINESTATE updates.  
The sequence of events for a host and a peripheral, both with ISP1505, is as follows:  
1. Idle: Initially, the host and the peripheral are idle. The host has its 15 kpull-down  
resistors enabled (DP_PULLDOWN and DM_PULLDOWN are set to 1b) and 45 Ω  
terminations disabled (TERMSELECT is set to 1b). The peripheral has the 1.5 kΩ  
pull-up resistor connected to DP for full-speed or DM for low-speed (TERMSELECT is  
set to 1b).  
2. Suspend: When the peripheral sees no bus activity for 3 ms, it enters the suspend  
state. The peripheral link places the PHY into low-power mode by clearing the  
SUSPENDM bit in the Function Control register, causing the PHY to draw only  
suspend current. The host may or may not be powered down.  
3. Resume K: When the host wants to wake up the peripheral, it sets OPMODE[1:0] to  
10b and transmits a K for at least 20 ms. The peripheral link sees the resume K on  
LINESTATE, and asserts STP to wake up the PHY.  
4. EOP: When STP is asserted, the ISP1505 on the host side automatically appends an  
EOP of two bits of SE0 at low-speed bit rate, followed by one bit of J. The ISP1505 on  
the host side knows to add the EOP because DP_PULLDOWN and DM_PULLDOWN  
are set to 1b for a host. After the EOP is completed, the host link sets OPMODE[1:0]  
to 00b for normal operation. The peripheral link sees the EOP and also resumes  
normal operation.  
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Product data sheet  
Rev. 03 — 26 August 2008  
33 of 75  
ISP1505A; ISP1505C  
NXP Semiconductors  
ULPI HS USB host and peripheral transceiver  
EOP  
idle  
suspend  
resume K  
idle  
TXCMD  
(REGW)  
TXCMD  
NOPID  
K
...  
K
TXCMD  
K
DATA  
[
]
7:0  
DIR  
STP  
NXT  
OPMODE  
10b  
00b  
00b  
LINE  
STATE  
K
SE0  
J
J
CLOCK  
TXCMD  
(REGW)  
LINESTATE J  
LINESTATE K  
SE0  
J
DATA  
[
]
7:0  
DIR  
STP  
NXT  
00b  
OPMODE  
10b  
00b  
SUSPENDM  
LINE  
STATE  
K
SE0  
J
J
DP  
DM  
004aab123  
Timing is not to scale.  
Fig 14. Full-speed suspend and resume  
9.10.2 High-speed suspend and resume  
Figure 15 illustrates how a host or a hub places a high-speed enabled peripheral into  
suspend and then initiates resume signaling. The high-speed peripheral will wake up and  
return to high-speed operations. Note that Figure 15 timing is not to scale, and does not  
show all RXCMD LINESTATE updates.  
ISP1505A_ISP1505C_3  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 03 — 26 August 2008  
34 of 75  
ISP1505A; ISP1505C  
NXP Semiconductors  
ULPI HS USB host and peripheral transceiver  
The sequence of events related to a host and a peripheral, both with ISP1505, is as  
follows:  
1. High-speed idle: Initially, the host and the peripheral are idle. The host has its 15 kΩ  
pull-down resistors enabled (DP_PULLDOWN and DM_PULLDOWN are set to 1b)  
and 45 terminations enabled (TERMSELECT is set to 0b). The peripheral has its  
45 terminations enabled (TERMSELECT is set to 0b).  
2. Full-speed suspend: When the peripheral sees no bus activity for 3 ms, it enters the  
suspend state. The peripheral link places the ISP1505 into full-speed mode  
(XCVRSELECT is set to 01b), removes 45 terminations, and enables the 1.5 kΩ  
pull-up resistor on DP (TERMSELECT is set to 1b). The peripheral link then places  
the ISP1505 into low-power mode by clearing SUSPENDM, causing the ISP1505 to  
draw only suspend current. The host also changes the ISP1505 to full-speed  
(XCVRSELECT is set to 01b), removes 45 terminations (TERMSELECT is set to  
1b), and then may or may not be powered down.  
3. Resume K: When the host wants to wake up the peripheral, it sets OPMODE to 10b  
and transmits a full-speed K for at least 20 ms. The peripheral link sees the resume K  
(10b) on LINESTATE, and asserts STP to wake up the ISP1505.  
4. High-speed traffic: The host link sets high-speed (XCVRSELECT is set to 00b) and  
enables its 45 terminations (TERMSELECT is set to 0b). The peripheral link sees  
SE0 on LINESTATE and also sets high-speed (XCVRSELECT is set to 00b), and  
enables its 45 terminations (TERMSELECT is set to 0b). The host link sets  
OPMODE to 00b for normal high-speed operation.  
ISP1505A_ISP1505C_3  
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Product data sheet  
Rev. 03 — 26 August 2008  
35 of 75  
ISP1505A; ISP1505C  
NXP Semiconductors  
ULPI HS USB host and peripheral transceiver  
FS suspend  
resume K  
HS idle  
HS idle  
TXCMD  
(REGW)  
TXCMD  
(REGW)  
TXCMD  
(REGW)  
TXCMD  
NOPID  
K
K
...  
K
DATA  
[
]
7:0  
DIR  
STP  
NXT  
XCVR  
01b  
00b  
00b  
SELECT  
TERM  
SELECT  
OP  
10b  
00b  
00b  
MODE  
!SQUELCH  
(01b)  
!SQUELCH SQUELCH  
FS J (01b)  
FS K (10b)  
SQUELCH (00b)  
(01b)  
(00b)  
LINE  
STATE  
CLOCK  
TXCMD  
(REGW)  
TXCMD  
(REGW)  
LINESTATE K  
LINESTATE J  
SE0  
DATA  
[
]
7:0  
DIR  
STP  
NXT  
XCVR  
SELECT  
01b  
00b  
00b  
TERM  
SELECT  
OP  
MODE  
00b  
10b  
00b  
SUSPENDM  
!SQUELCH  
(01b)  
!SQUELCH  
(01b)  
SQUELCH  
(00b)  
FS K (10b)  
SQUELCH (00b)  
FS J (01b)  
LINE  
STATE  
DP  
DM  
004aab124  
Timing is not to scale.  
Fig 15. High-speed suspend and resume  
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Product data sheet  
Rev. 03 — 26 August 2008  
36 of 75  
ISP1505A; ISP1505C  
NXP Semiconductors  
ULPI HS USB host and peripheral transceiver  
9.10.3 Remote wake-up  
The ISP1505 supports peripherals that initiate remote wake-up resume. When placed into  
USB suspend, the peripheral link remembers at what speed it was originally operating.  
Depending on the original speed, the link follows one of the protocols detailed here. In  
Figure 16, timing is not to scale, and not all RXCMD LINESTATE updates are shown.  
The sequence of events related to a host and a peripheral, both with ISP1505, is as  
follows:  
1. Both the host and the peripheral are assumed to be in low-power mode.  
2. The peripheral begins remote wake-up by re-enabling its clock and setting its  
SUSPENDM bit to 1b.  
3. The peripheral begins driving K on the bus to signal resume. Note that the peripheral  
link must assume that LINESTATE is K (01b) while transmitting because it will not  
receive any RXCMDs.  
4. The host recognizes the resume, re-enables its clock and sets its SUSPENDM bit.  
5. The host takes over resume driving within 1 ms of detecting the remote wake-up.  
6. The peripheral stops driving resume.  
7. The peripheral sees the host continuing to drive resume.  
8. The host stops driving resume and the ISP1505 automatically adds the EOP to the  
end of resume. The peripheral recognizes the EOP as the end of resume.  
9. Both the host and the peripheral revert to normal operation by writing 00b to  
OPMODE. If the host or the peripheral was previously in high-speed mode, it must  
revert to high-speed before the SE0 of the EOP is completed. This can be achieved  
by writing XCVRSELECT[1:0] = 00b and TERMSELECT = 0b after LINESTATE  
indicates SE0.  
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Product data sheet  
Rev. 03 — 26 August 2008  
37 of 75  
ISP1505A; ISP1505C  
NXP Semiconductors  
ULPI HS USB host and peripheral transceiver  
TXCMD  
NOPID  
TXCMD  
REGW  
TXCMD  
REGW  
00h  
LINESTATE  
DATA  
[
]
7:0  
DIR  
STP  
NXT  
XCVR  
SELECT  
01b (FS), 10b (LS)  
00b (HS only)  
TERM  
SELECT  
0b (HS only)  
00b  
OP  
MODE  
10b  
TXCMD  
REGW  
TXCMD  
REGW  
TXCMD  
NOPID  
LINESTATE  
00h  
RXCMD  
RXCMD  
RXCMD  
DATA  
[
]
7:0  
DIR  
STP  
NXT  
00b (HS only)  
0b (HS only)  
XCVR  
SELECT  
00b (HS), 01b (FS), 10b (LS)  
TERM  
SELECT  
OP  
MODE  
10b  
00b  
004aaa718  
Timing is not to scale.  
Fig 16. Remote wake-up from low-power mode  
9.11 No automatic SYNC and EOP generation (optional)  
This setting allows the link to turn off the automatic SYNC and EOP generation, and must  
be used for high-speed packets only. It is provided for backward compatibility with legacy  
controllers that include SYNC and EOP bytes in the data payload when transmitting  
packets. The ISP1505 will not automatically generate the SYNC and EOP patterns when  
OPMODE[1:0] is set to 11b. The ISP1505 will still NRZI encode data and perform bit  
stuffing. An example of a sequence is shown in Figure 17. The link must always send  
packets using the TXCMD (NOPID) type. The ISP1505 does not provide a mechanism to  
control bit stuffing in individual bytes, but will automatically turn off bit stuffing for EOP  
when STP is asserted with data set to FEh. If data is set to 00h when STP is asserted, the  
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Product data sheet  
Rev. 03 — 26 August 2008  
38 of 75  
ISP1505A; ISP1505C  
NXP Semiconductors  
ULPI HS USB host and peripheral transceiver  
PHY will not transmit any EOP. The ISP1505 will also detect if the PID byte is A5h,  
indicating an SOF packet, and automatically send a long EOP when STP is asserted. To  
transmit chirp and resume signaling, the link must set OPMODE[1:0] to 10b.  
CLOCK  
... ...  
TXCMD  
00h  
00h 00h 80h PID D1 D2 D3  
D
N 1  
D
N
FEh  
DATA  
[7:0]  
DIR  
STP  
NXT  
TXVALID  
TXREADY  
TXBIT  
STUFF  
ENABLE  
IDLE  
SYNC  
PID  
DATA PAYLOAD  
EOP  
IDLE  
DP, DM  
004aab125  
Fig 17. Transmitting USB packets without the automatic SYNC and EOP generation  
9.12 On-The-Go operations  
On-The-Go (OTG) is a supplement to Universal Serial Bus Specification Rev. 2.0 that  
allows a portable USB device to assume the role of a limited USB host by defining  
improvements, such as a small connector and low power. Non-portable devices, such as  
standard hosts and embedded hosts, can also benefit from OTG features.  
The ISP1505 OTG PHY is designed to support all the tasks specified in the OTG  
supplement. The ISP1505 provides the front-end analog support for Host Negotiation  
Protocol (HNP) and Session Request Protocol (SRP) for dual-role devices. The  
supporting components include:  
Voltage comparators  
A_VBUS_VLD  
SESS_VLD (session valid, can be used for both A-session and B-session valid)  
SESS_END (session end)  
Pull-up and pull-down resistors on DP and DM  
Charge and discharge resistors on VBUS  
For complete OTG support, the system designer must add a VBUS power supply and  
detect the value on the ID pin of the USB cable. This is not provided on the ISP1505.  
The following subsections describe how to use the ISP1505 OTG components.  
ISP1505A_ISP1505C_3  
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Product data sheet  
Rev. 03 — 26 August 2008  
39 of 75  
ISP1505A; ISP1505C  
NXP Semiconductors  
ULPI HS USB host and peripheral transceiver  
9.12.1 OTG comparators  
The ISP1505 provides comparators that conform to On-The-Go Supplement to the  
USB 2.0 Specification Rev. 1.3 requirements of VA_VBUS_VLD, VA_SESS_VLD, VB_SESS_VLD  
and VB_SESS_END. In this data sheet, VA_SESS_VLD and VB_SESS_VLD are combined into  
VB_SESS_VLD. Comparators are described in Section 7.6. Changes in comparator values  
are communicated to the link by RXCMDs as described in Section 9.5.2.2. Control over  
comparators is described in Section 10.1.5 to Section 10.1.8.  
9.12.2 Pull-up and pull-down resistors  
The USB resistors on DP and DM can be used to initiate data-line pulsing SRP. The link  
must set the required bus state using mode settings given in Table 7.  
9.12.3 VBUS charge and discharge resistors  
A pull-up resistor, RUP(VBUS), is provided to perform VBUS pulsing SRP. A B-device is  
allowed to charge VBUS above the session valid threshold to request the host to turn on  
the VBUS power.  
A pull-down resistor, RDN(VBUS), is provided for a B-device to discharge VBUS. This is done  
whenever the A-device turns off the VBUS power. The B-device can use the pull-down  
resistor to ensure VBUS is below VB_SESS_END before starting a session.  
For details, refer to On-The-Go Supplement to the USB 2.0 Specification Rev. 1.3.  
9.13 Serial modes  
The ISP1505 supports both 6-pin serial mode and 3-pin serial mode, controlled by  
bits 6PIN_FSLS_SERIAL and 3PIN_FSLS_SERIAL of the Interface Control register. For  
details, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1, Section 3.10.  
Figure 18 and Figure 19 provide examples of 6-pin serial mode and 3-pin serial mode,  
respectively.  
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Product data sheet  
Rev. 03 — 26 August 2008  
40 of 75  
ISP1505A; ISP1505C  
NXP Semiconductors  
ULPI HS USB host and peripheral transceiver  
TRANSMIT  
DATA  
RECEIVE  
SYNC  
SYNC  
DATA  
EOP  
EOP  
DATA0  
(TX_ENABLE)  
DATA1  
(TX_DAT)  
DATA2  
(TX_SE0)  
DATA4  
(RX_DP)  
DATA5  
(RX_DM)  
DATA6  
(RX_RCV)  
DP  
DM  
004aaa692  
Fig 18. Example of transmit followed by receive in 6-pin serial mode  
TRANSMIT  
RECEIVE  
DATA  
DATA  
SYNC  
SYNC  
EOP  
EOP  
DATA0  
(TX_ENABLE)  
DATA1  
(TX_DAT/  
RX_RCV)  
DATA2  
(TX_SE0/  
RX_SE0)  
DP  
DM  
004aaa693  
Fig 19. Example of transmit followed by receive in 3-pin serial mode  
ISP1505A_ISP1505C_3  
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Product data sheet  
Rev. 03 — 26 August 2008  
41 of 75  
ISP1505A; ISP1505C  
NXP Semiconductors  
ULPI HS USB host and peripheral transceiver  
9.14 Aborting transfers  
The ISP1505 supports aborting transfers on the ULPI bus. For details, refer to UTMI+ Low  
Pin Interface (ULPI) Specification Rev. 1.1, Section 3.8.4.  
9.15 Avoiding contention on the ULPI data bus  
Because the ULPI data bus is bidirectional, avoid situations in which both the link and the  
PHY simultaneously drive the data bus.  
The following points must be considered while implementing the data bus drive control on  
the link.  
After power-up and clock stabilization, default states are as follows:  
The ISP1505 drives DIR to LOW.  
The data bus is input to the ISP1505.  
The ULPI link data bus is output, with all data bus lines driven to LOW.  
When the ISP1505 wants to take control of the data bus to initiate a data transfer, it  
changes the DIR value from LOW to HIGH.  
At this point, the link must disable its output buffers. This must be as fast as possible so  
the link must use a combinational path from DIR.  
The ISP1505 will not immediately enable its output buffers, but will delay the enabling of  
its buffers until the next clock edge, avoiding bus contention.  
When the data transfer is no longer required by the ISP1505, it changes DIR from HIGH to  
LOW and starts to immediately turn off its output drivers. The link senses the change of  
DIR from HIGH to LOW, but delays enabling its output buffers for one CLOCK cycle,  
avoiding data bus contention.  
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Product data sheet  
Rev. 03 — 26 August 2008  
42 of 75  
ISP1505A; ISP1505C  
NXP Semiconductors  
ULPI HS USB host and peripheral transceiver  
10. Register map  
Table 17. Immediate register set overview  
Field name  
Size Address (6 bit)  
References  
(bit)  
R[1]  
W[2]  
S[3]  
C[4]  
Immediate register set  
Vendor ID Low register  
Vendor ID High register  
Product ID Low register  
Product ID High register  
Function Control register  
Interface Control register  
OTG Control register  
8
8
8
8
8
8
8
8
00h  
-
-
-
Section 10.1.1 on page 44  
01h  
-
-
-
02h  
-
-
-
03h  
-
-
-
04h to 06h  
07h to 09h  
0Ah to 0Ch  
0Dh to 0Fh  
04h  
07h  
0Ah  
0Dh  
05h  
08h  
0Bh  
0Eh  
06h  
09h  
0Ch  
0Fh  
Section 10.1.2 on page 44  
Section 10.1.3 on page 45  
Section 10.1.4 on page 46  
Section 10.1.5 on page 47  
USB Interrupt Enable Rising Edge  
register  
USB Interrupt Enable Falling Edge  
register  
8
10h to 12h  
10h  
11h  
12h  
Section 10.1.6 on page 48  
USB Interrupt Status register  
USB Interrupt Latch register  
Debug register  
8
8
8
8
-
13h  
-
-
-
Section 10.1.7 on page 48  
Section 10.1.8 on page 49  
Section 10.1.9 on page 49  
Section 10.1.10 on page 50  
Section 10.1.11 on page 50  
Section 10.1.12 on page 50  
Section 10.1.13 on page 50  
Section 10.1.14 on page 50  
14h  
-
-
-
15h  
-
-
-
Scratch register  
16h to 18h  
16h  
17h  
18h  
Reserved (do not use)  
Access extended register set  
Vendor-specific registers  
Power Control register  
19h to 2Eh  
8
8
8
-
2Fh  
-
-
30h to 3Ch  
3Dh to 3Fh  
[1] Read (R): A register can be read. Read-only if this is the only mode given.  
[2] Write (W): The pattern on the data bus will be written over all bits of a register.  
[3] Set (S): The pattern on the data bus is OR-ed with and written to a register.  
[4] Clear (C): The pattern on the data bus is a mask. If a bit in the mask is set, then the corresponding register bit will be set to zero  
(cleared).  
Table 18. Extended register set overview  
Field name  
Size Address (6 bit)  
(bit)  
References  
R[1]  
W[2]  
S[3]  
00h to 3Fh  
40h to FFh  
C[4]  
Maps to immediate register set above 8  
Section 10.2 on page 51  
Reserved (do not use)  
8
[1] Read (R): A register can be read. Read-only if this is the only mode given.  
[2] Write (W): The pattern on the data bus will be written over all bits of a register.  
[3] Set (S): The pattern on the data bus is OR-ed with and written to a register.  
[4] Clear (C): The pattern on the data bus is a mask. If a bit in the mask is set, then the corresponding register bit will be set to zero  
(cleared).  
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Product data sheet  
Rev. 03 — 26 August 2008  
43 of 75  
ISP1505A; ISP1505C  
NXP Semiconductors  
ULPI HS USB host and peripheral transceiver  
10.1 Immediate register set  
10.1.1 Vendor ID and Product ID registers  
10.1.1.1 Vendor ID Low register  
Table 19 shows the bit description of the register.  
Table 19. Vendor ID Low register (address R = 00h) bit description  
Bit  
Symbol  
Access Value Description  
7 to 0  
VENDOR_ID_  
LOW[7:0]  
R
CCh  
Vendor ID Low: Lower byte of the NXP vendor ID supplied by USB-IF; has  
a fixed value of CCh  
10.1.1.2 Vendor ID High register  
The bit description of the register is given in Table 20.  
Table 20. Vendor ID High register (address R = 01h) bit description  
Bit  
Symbol  
Access  
Value  
Description  
7 to 0  
VENDOR_ID_  
HIGH[7:0]  
R
04h  
Vendor ID High: Upper byte of the NXP vendor ID supplied by USB-IF;  
has a fixed value of 04h  
10.1.1.3 Product ID Low register  
The bit description of the Product ID Low register is given in Table 21.  
Table 21. Product ID Low register (address R = 02h) bit description  
Bit  
Symbol  
Access Value  
05h  
Description  
7 to 0  
PRODUCT_ID_ R  
LOW[7:0]  
Product ID Low: Lower byte of the NXP product ID number; has a fixed  
value of 05h  
10.1.1.4 Product ID High register  
The bit description of the register is given in Table 22.  
Table 22. Product ID High register (address R = 03h) bit description  
Bit  
Symbol  
Access  
Value  
Description  
7 to 0  
PRODUCT_ID_ R  
HIGH[7:0]  
15h  
Product ID High: Upper byte of the NXP product ID number; has a fixed  
value of 15h  
10.1.2 Function Control register  
This register controls UTMI function settings of the PHY. The bit allocation of the register  
is given in Table 23.  
Table 23. Function Control register (address R = 04h to 06h, W = 04h, S = 05h, C = 06h) bit allocation  
Bit  
7
6
5
4
3
2
1
0
Symbol  
reserved  
SUSPENDM  
RESET  
OPMODE[1:0]  
TERM  
XCVRSELECT[1:0]  
SELECT  
Reset  
0
1
0
0
0
0
0
1
Access  
R/W/S/C  
R/W/S/C  
R/W/S/C  
R/W/S/C  
R/W/S/C  
R/W/S/C  
R/W/S/C  
R/W/S/C  
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ISP1505A; ISP1505C  
NXP Semiconductors  
ULPI HS USB host and peripheral transceiver  
Table 24. Function Control register (address R = 04h to 06h, W = 04h, S = 05h, C = 06h) bit description  
Bit  
7
Symbol  
Description  
-
reserved  
6
SUSPENDM  
Suspend LOW: Active LOW PHY suspend.  
Places the PHY into low-power mode. The PHY will power down all blocks, except the  
full-speed receiver, OTG comparators and ULPI interface pins.  
To come out of low-power mode, the link must assert STP. The PHY will automatically clear  
this bit when it exits low-power mode.  
0b — Low-power mode  
1b — Powered (default)  
5
RESET  
Reset: Active HIGH transceiver reset.  
After the link sets this bit, the PHY will assert DIR and reset the digital core. This does not  
reset the ULPI interface or the ULPI register set.  
When reset is completed, the PHY will deassert DIR and automatically clear this bit, followed  
by an RXCMD update to the link.  
0b — Do not reset (default)  
1b — Reset  
The link must wait for DIR to deassert before using the ULPI bus. Does not reset the ULPI  
interface or the ULPI register set.  
4 to 3 OPMODE[1:0]  
Operation Mode: Selects the required bit-encoding style during transmit.  
00b — Normal operation (default)  
01b — Non-driving  
10b — Disable bit-stuffing and NRZI encoding  
11b — Do not automatically add SYNC and EOP when transmitting; must be used only for  
high-speed packets  
2
TERMSELECT  
Termination Select: Controls the internal 1.5 kfull-speed pull-up resistor and 45 Ω  
high-speed terminations. Control over bus resistors changes, depending on  
XCVRSELECT[1:0], OPMODE[1:0], DP_PULLDOWN and DM_PULLDOWN, as shown in  
Table 7.  
1 to 0 XCVRSELECT[1:0] Transceiver Select: Selects the required transceiver speed.  
00b — Enable the high-speed transceiver  
01b — Enable the full-speed transceiver  
10b — Enable the low-speed transceiver  
11b — Enable the full-speed transceiver for low-speed packets (full-speed preamble is  
automatically prefixed)  
10.1.3 Interface Control register  
The Interface Control register enables alternative interfaces. All of these modes are  
optional features provided for legacy link cores. Setting more than one of these fields  
results in undefined behavior. Table 25 provides the bit allocation of the register.  
Table 25. Interface Control register (address R = 07h to 09h, W = 07h, S = 08h, C = 09h) bit allocation  
Bit  
7
6
5
4
3
2
1
0
Symbol  
INTF_  
PROT_DIS  
IND_PASS  
THRU  
IND_  
COMPL  
reserved  
CLOCK_  
SUSPENDM  
reserved  
3PIN_FSLS 6PIN_FSLS  
_SERIAL  
_SERIAL  
Reset  
0
0
0
0
0
0
0
0
Access  
R/W/S/C  
R/W/S/C  
R/W/S/C  
R/W/S/C  
R/W/S/C  
R/W/S/C  
R/W/S/C  
R/W/S/C  
ISP1505A_ISP1505C_3  
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Product data sheet  
Rev. 03 — 26 August 2008  
45 of 75  
ISP1505A; ISP1505C  
NXP Semiconductors  
ULPI HS USB host and peripheral transceiver  
Table 26. Interface Control register (address R = 07h to 09h, W = 07h, S = 08h, C = 09h) bit description  
Bit  
Symbol  
Description  
7
INTF_PROT_DIS  
Interface Protect Disable: Controls circuitry built into the ISP1505 to protect the ULPI  
interface when the link 3-states STP and DATA[7:0]. When this bit is enabled, the ISP1505  
will automatically detect when the link stops driving STP.  
0b — Enables the interface protect circuit (default). The ISP1505 attaches a weak pull-up  
resistor on STP. If STP is unexpectedly HIGH, the ISP1505 attaches weak pull-down  
resistors on DATA[7:0], protecting data inputs.  
1b — Disables the interface protect circuit, detaches weak pull-down resistors on  
DATA[7:0], and a weak pull-up resistor on STP.  
6
5
IND_PASSTHRU  
Indicator Pass-through: The ISP1505 does not support the qualification of an external  
FAULT with the internal VA_VBUS_VLD comparator. Either a digital FAULT is input on the  
V
BUS/FAULT pin or the VBUS power is connected to the VBUS/FAULT pin, not both. This bit  
must always be set to logic 1.  
0b — Not supported.  
1b — The complement output signal is not qualified with the internal A_VBUS_VLD  
comparator. The link must always set this bit to logic 1.  
IND_COMPL  
Indicator Complement: Informs the PHY to invert the FAULT input signal, generating the  
complement output. For details, see Section 9.5.2.2.  
0b — The ISP1505 will not invert the FAULT signal (default).  
1b — The ISP1505 will invert the FAULT signal.  
reserved  
4
3
-
CLOCK_SUSPENDM Clock Suspend LOW: Active LOW clock suspend.  
Powers down the internal clock circuitry only. By default, the clock will not be powered in  
6-pin serial mode or 3-pin serial mode.  
Valid only in 6-pin serial mode and 3-pin serial mode. Valid only when SUSPENDM is set to  
logic 1, otherwise this bit is ignored.  
0b — Clock will not be powered in 3-pin or 6-pin serial mode.  
1b — Clock will be powered in 3-pin and 6-pin serial modes.  
reserved  
2
1
-
3PIN_FSLS_SERIAL  
3-Pin Full-Speed Low-Speed Serial Mode: Changes the ULPI interface to a 3-bit serial  
interface. The PHY will automatically clear this bit when 3-pin serial mode is exited.  
0b — Full-speed or low-speed packets are sent using the parallel interface.  
1b — Full-speed or low-speed packets are sent using the 3-pin serial interface.  
0
6PIN_FSLS_SERIAL  
6-Pin Full-Speed Low-Speed Serial Mode: Changes the ULPI interface to a 6-bit serial  
interface. The PHY will automatically clear this bit when 6-pin serial mode is exited.  
0b — Full-speed or low-speed packets are sent using the parallel interface.  
1b — Full-speed or low-speed packets are sent using the 6-pin serial interface.  
10.1.4 OTG Control register  
This register controls various OTG functions of the ISP1505. The bit allocation of the OTG  
Control register is given in Table 27.  
Table 27. OTG Control register (address R = 0Ah to 0Ch, W = 0Ah, S = 0Bh, C = 0Ch) bit allocation  
Bit  
7
6
5
4
3
2
1
0
Symbol  
USE_EXT_  
VBUS_IND VBUS_EXT  
DRV_  
DRV_  
VBUS  
CHRG_  
VBUS  
DISCHRG_ DM_PULL  
DP_PULL  
DOWN  
reserved  
VBUS  
DOWN  
Reset  
0
0
0
0
0
1
1
0
Access  
R/W/S/C  
R/W/S/C  
R/W/S/C  
R/W/S/C  
R/W/S/C  
R/W/S/C  
R/W/S/C  
R/W/S/C  
ISP1505A_ISP1505C_3  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 03 — 26 August 2008  
46 of 75  
ISP1505A; ISP1505C  
NXP Semiconductors  
ULPI HS USB host and peripheral transceiver  
Table 28. OTG Control register (address R = 0Ah to 0Ch, W = 0Ah, S = 0Bh, C = 0Ch) bit description  
Bit  
Symbol  
Description  
7
USE_EXT_VBUS_  
IND  
Use External VBUS Indicator: Informs the PHY to use an external VBUS overcurrent indicator.  
0b — Use the internal OTG comparator.  
1b — Use the external VBUS valid indicator signal input from the FAULT pin.  
6
DRV_VBUS_EXT  
Drive VBUS External: Controls the external VBUS supply through the RESET_N/PSW_N pin.  
0b — Do not drive PSW_N to LOW, disabling VBUS  
.
1b — Drive PSW_N to LOW, enabling VBUS  
.
5
4
DRV_VBUS  
Drive VBUS: Signals the ISP1505 to drive 5 V on VBUS. If DRV_VBUS_EXT is set to logic 1,  
then setting DRV_VBUS is optional.  
CHRG_VBUS  
Charge VBUS: Charges VBUS through a resistor. Used for the VBUS pulsing SRP. The link must  
first check that VBUS is discharged (see the DISCHRG_VBUS bit), and that both the DP and  
DM data lines have been LOW (SE0) for 2 ms.  
0b — Do not charge VBUS  
.
1b — Charge VBUS  
.
3
DISCHRG_VBUS  
Discharge VBUS: Discharges VBUS through a resistor. If the link sets this bit to logic 1, it waits  
for an RXCMD indicating that SESS_END has changed from 0 to 1, and then resets this bit to 0  
to stop the discharge.  
0b — Do not discharge VBUS  
1b — Discharge VBUS  
.
.
2
1
0
DM_PULLDOWN DM Pull Down: Enables the 15 kpull-down resistor on DM.  
0b — Pull-down resistor is not connected to DM.  
1b — Pull-down resistor is connected to DM.  
DP_PULLDOWN  
DP Pull Down: Enables the 15 kpull-down resistor on DP.  
0b — Pull-down resistor is not connected to DP.  
1b — Pull-down resistor is connected to DP.  
-
reserved; writing logic 1 will give undefined results  
10.1.5 USB Interrupt Enable Rising Edge register  
The bits in this register enable interrupts and RXCMDs to be sent when the corresponding  
bits in the USB Interrupt Status register change from logic 0 to logic 1. By default, all  
transitions are enabled. Table 29 shows the bit allocation of the register.  
Table 29. USB Interrupt Enable Rising Edge register (address R = 0Dh to 0Fh, W = 0Dh, S = 0Eh, C = 0Fh) bit  
allocation  
Bit  
7
6
5
4
3
2
1
0
Symbol  
reserved  
SESS_  
END_R  
SESS_  
VALID_R  
VBUS_  
VALID_R DISCON_R  
HOST_  
Reset  
0
0
0
1
1
1
1
1
Access  
R/W/S/C  
R/W/S/C  
R/W/S/C  
R/W/S/C  
R/W/S/C  
R/W/S/C  
R/W/S/C  
R/W/S/C  
ISP1505A_ISP1505C_3  
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Product data sheet  
Rev. 03 — 26 August 2008  
47 of 75  
ISP1505A; ISP1505C  
NXP Semiconductors  
ULPI HS USB host and peripheral transceiver  
Table 30. USB Interrupt Enable Rising Edge register (address R = 0Dh to 0Fh, W = 0Dh, S = 0Eh, C = 0Fh) bit  
description  
Bit  
7 to 4  
3
Symbol  
Description  
-
reserved  
SESS_END_R  
Session End Rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on  
SESS_END.  
2
1
SESS_VALID_R  
VBUS_VALID_R  
Session Valid Rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on  
SESS_VLD.  
VBUS Valid Rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on  
A_VBUS_VLD.  
0
HOST_DISCON_R Host Disconnect Rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on  
HOST_DISCON.  
10.1.6 USB Interrupt Enable Falling Edge register  
The bits in this register enable interrupts and RXCMDs to be sent when the corresponding  
bits in the USB Interrupt Status register change from logic 1 to logic 0. By default, all  
transitions are enabled. See Table 31.  
Table 31. USB Interrupt Enable Falling Edge register (address R = 10h to 12h, W = 10h, S = 11h, C = 12h) bit  
allocation  
Bit  
7
6
5
4
3
2
1
0
Symbol  
reserved  
SESS_  
END_F  
SESS_  
VALID_F  
VBUS_  
VALID_F  
HOST_  
DISCON_F  
Reset  
0
0
0
1
1
1
1
1
Access  
R/W/S/C  
R/W/S/C  
R/W/S/C  
R/W/S/C  
R/W/S/C  
R/W/S/C  
R/W/S/C  
R/W/S/C  
Table 32. USB Interrupt Enable Falling Edge register (address R = 10h to 12h, W = 10h, S = 11h, C = 12h) bit  
description  
Bit  
7 to 4  
3
Symbol  
Description  
-
reserved  
SESS_END_F  
Session End Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on  
SESS_END.  
2
1
SESS_VALID_F  
VBUS_VALID_F  
Session Valid Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on  
SESS_VLD.  
VBUS Valid Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on  
A_VBUS_VLD.  
0
HOST_DISCON_F Host Disconnect Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on  
HOST_DISCON.  
10.1.7 USB Interrupt Status register  
This register (see Table 33) indicates the current value of the interrupt source signal.  
Table 33. USB Interrupt Status register (address R = 13h) bit allocation  
Bit  
7
6
5
4
3
2
1
0
Symbol  
reserved  
SESS_  
END  
SESS_  
VALID  
VBUS_  
VALID  
HOST_  
DISCON  
Reset  
X
R
X
R
X
R
0
0
0
0
0
Access  
R
R
R
R
R
ISP1505A_ISP1505C_3  
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Product data sheet  
Rev. 03 — 26 August 2008  
48 of 75  
ISP1505A; ISP1505C  
NXP Semiconductors  
ULPI HS USB host and peripheral transceiver  
Table 34. USB Interrupt Status register (address R = 13h) bit description  
Bit  
Symbol  
Description  
7 to 4  
-
reserved  
3
2
1
0
SESS_END  
SESS_VALID  
VBUS_VALID  
HOST_DISCON  
Session End: Reflects the current value of the session end voltage comparator.  
Session Valid: Reflects the current value of the session valid voltage comparator.  
VBUS Valid: Reflects the current value of the VBUS valid voltage comparator.  
Host Disconnect: Reflects the current value of the host disconnect detector.  
10.1.8 USB Interrupt Latch register  
The bits of the USB Interrupt Latch register are automatically set by the ISP1505 when an  
unmasked change occurs on the corresponding interrupt source signal. The ISP1505 will  
automatically clear all bits when the link reads this register, or when the PHY enters  
low-power mode.  
Remark: It is optional for the link to read this register when the clock is running because  
all signal information will automatically be sent to the link through the RXCMD byte.  
The bit allocation of this register is given in Table 35.  
Table 35. USB Interrupt Latch register (address R = 14h) bit allocation  
Bit  
7
6
5
4
3
2
1
0
Symbol  
reserved  
SESS_  
END_L  
SESS_  
VALID_L  
VBUS_  
VALID_L  
HOST_  
DISCON_L  
Reset  
0
0
0
0
0
0
0
0
Access  
R
R
R
R
R
R
R
R
Table 36. USB Interrupt Latch register (address R = 14h) bit description  
Bit  
7 to 4  
3
Symbol  
Description  
-
reserved  
SESS_END_L  
Session End Latch: Automatically set when an unmasked event occurs on SESS_END.  
Cleared when this register is read.  
2
1
SESS_VALID_L  
VBUS_VALID_L  
Session Valid Latch: Automatically set when an unmasked event occurs on SESS_VLD.  
Cleared when this register is read.  
VBUS Valid Latch: Automatically set when an unmasked event occurs on A_VBUS_VLD.  
Cleared when this register is read.  
0
HOST_DISCON_L  
Host Disconnect Latch: Automatically set when an unmasked event occurs on  
HOST_DISCON. Cleared when this register is read.  
10.1.9 Debug register  
The bit allocation of the Debug register is given in Table 37. This register indicates the  
current value of signals useful for debugging.  
Table 37. Debug register (address R = 15h) bit allocation  
Bit  
7
6
5
4
3
2
1
0
Symbol  
reserved  
LINE  
LINE  
STATE1  
STATE0  
Reset  
0
0
0
0
0
0
0
0
Access  
R
R
R
R
R
R
R
R
ISP1505A_ISP1505C_3  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 03 — 26 August 2008  
49 of 75  
ISP1505A; ISP1505C  
NXP Semiconductors  
ULPI HS USB host and peripheral transceiver  
Table 38. Debug register (address R = 15h) bit description  
Bit  
7 to 2  
1
Symbol  
-
Description  
reserved  
LINESTATE1  
LINESTATE0  
Line State 1: Contains the current value of LINESTATE 1  
Line State 0: Contains the current value of LINESTATE 0  
0
10.1.10 Scratch register  
Table 39 shows the bit description of the Scratch register. It is an empty register for testing  
purposes.  
Table 39. Scratch register (address R = 16h to 18h, W = 16h, S = 17h, C = 18h) bit description  
Bit  
Symbol  
Access  
Value  
Description  
7 to 0  
SCRATCH  
[7:0]  
R/W/S/C  
00h  
Scratch: This is an empty register byte for testing purposes. Software  
can read, write, set and clear this register. The functionality of the PHY  
will not be affected.  
10.1.11 Reserved  
Registers 19h to 2Eh are not implemented. Operating on these addresses will have no  
effect on the PHY.  
10.1.12 Access extended register set  
Address 2Fh does not contain register data. Instead it links to the extended register set.  
The immediate register set maps to the lower end of the extended register set.  
10.1.13 Vendor-specific registers  
Addresses 30h to 3Fh contain vendor-specific registers.  
10.1.14 Power Control register  
Table 40 provides the bit allocation of the Power Control register.  
Table 40. Power Control register (address R = 3Dh to 3Fh, W = 3Dh, S = 3Eh, C = 3Fh) bit allocation  
Bit  
7
6
5
4
3
2
1
0
Symbol  
reserved  
BVALID_  
FALL  
BVALID_  
RISE  
reserved  
IGNORE_  
RESET  
Reset  
0
0
0
0
0
0
0
0
Access  
R/W/S/C  
R/W/S/C  
R/W/S/C  
R/W/S/C  
R/W/S/C  
R/W/S/C  
R/W/S/C  
R/W/S/C  
ISP1505A_ISP1505C_3  
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Product data sheet  
Rev. 03 — 26 August 2008  
50 of 75  
ISP1505A; ISP1505C  
NXP Semiconductors  
ULPI HS USB host and peripheral transceiver  
Table 41. Power Control register (address R = 3Dh to 3Fh, W = 3Dh, S = 3Eh, C = 3Fh) bit description  
Bit  
7 to 4  
3
Symbol  
Description  
-
reserved; the link must never write logic 1 to these bits.  
BVALID_FALL  
BVALID Fall: Enables RXCMDs for HIGH-to-LOW transitions on BVALID. When BVALID  
changes from HIGH to LOW, the ISP1505 will send an RXCMD to the link with the ALT_INT  
bit set to logic 1.  
This bit is optional and is not necessary for OTG devices. This bit is provided for debugging  
purposes. The session valid comparator should be used instead.  
2
BVALID_RISE  
BVALID Rise: Enables RXCMDs for LOW-to-HIGH transitions on BVALID. When BVALID  
changes from LOW to HIGH, the ISP1505 will send an RXCMD to the link with the ALT_INT  
bit set to logic 1.  
This bit is optional and is not necessary for OTG devices. This bit is provided for debugging  
purposes. The session valid comparator should be used instead.  
1
0
-
reserved  
IGNORE_RESET Ignore Reset: Selects between the RESET_N and PSW_N functions of the  
RESET_N/PSW_N pin. The link must set this bit to logic 1, if PSW_N is used in a ganged  
mode configuration.  
0b — The RESET_N/PSW_N pin behaves as an active-LOW reset input (RESET_N). This is  
the default setting.  
1b — The RESET_N/PSW_N pin behaves as an active-LOW power switch output (PSW_N).  
10.2 Extended register set  
Addresses 00h to 3Fh of the extended register set directly map to the immediate set. This  
means a read, write, set or clear operation to these extended addresses will operate on  
the immediate register set.  
Addresses 40h to FFh are not implemented. Operating on these addresses may result in  
undefined behavior of the PHY.  
ISP1505A_ISP1505C_3  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 03 — 26 August 2008  
51 of 75  
ISP1505A; ISP1505C  
NXP Semiconductors  
ULPI HS USB host and peripheral transceiver  
11. ElectroStatic Discharge (ESD)  
11.1 ESD protection  
The pins that are connected to the USB connector (DP, DM, VBUS and GND) have a  
minimum of ±4 kV ESD protection. Capacitors 0.1 µF and 1 µF must be connected in  
parallel from VBUS to GND to achieve this ±4 kV ESD protection (see Figure 20).  
Remark: Capacitors 0.1 µF and 1 µF are also required by Universal Serial Bus  
Specification Rev. 2.0. For details on the requirements for CVBUS, see Section 16.  
R
1 MΩ  
R
D
1500 Ω  
C
charge current  
limit resistor  
discharge  
resistance  
DEVICE UNDER  
TEST  
V
BUS  
A
B
HIGH VOLTAGE  
DC SOURCE  
storage  
capacitor  
0.1 µF  
1 µF  
C
S
100 pF  
GND  
004aaa881  
Fig 20. Human body ESD test model  
11.2 ESD test conditions  
A detailed report on test setup and results is available on request.  
ISP1505A_ISP1505C_3  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 03 — 26 August 2008  
52 of 75  
ISP1505A; ISP1505C  
NXP Semiconductors  
ULPI HS USB host and peripheral transceiver  
12. Limiting values  
Table 42. Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134).  
Symbol Parameter  
Conditions  
Min  
0.5  
0.5  
0.5  
Max  
Unit  
V
VCC  
supply voltage  
+4.6  
VCC(I/O)  
VI  
input/output supply voltage  
input voltage  
+4.6  
V
on pins STP, DATA[7:0] and  
RESET_N/PSW_N  
VCC(I/O) + 0.5  
V
on pin VBUS/FAULT  
0.5  
0.5  
0.5  
4  
+6.0  
+2.5  
+4.6  
+4  
V
on pin XTAL1  
V
[1]  
[2]  
on pins DP and DM  
on pins DP, DM, VBUS and GND;  
V
VESD  
electrostatic discharge  
voltage  
kV  
ILI < 1 µA  
on all other pins; ILI < 1 µA  
2  
+2  
kV  
mA  
V
Ilu  
latch-up current  
100  
-
+100  
4.6  
Vlu  
Tstg  
latch-up voltage  
storage temperature  
40  
+125  
°C  
[1] The ISP1505 has been tested according to the additional requirements listed in Universal Serial Bus Specification Rev. 2.0,  
Section 7.1.1. The short circuit withstand test and the AC stress test were performed for 24 hours, and the ISP1505 was found to be fully  
operational after the test completed.  
[2] Equivalent to discharging a 100 pF capacitor through a 1.5 kresistor (Human Body Model JESD22-A114D).  
13. Recommended operating conditions  
Table 43. Recommended operating conditions  
Symbol  
VCC  
Parameter  
Conditions  
Min  
3.0  
1.65  
0
Typ  
Max  
3.6  
Unit  
V
supply voltage  
3.3  
[1]  
VCC(I/O)  
VI  
input/output supply voltage  
input voltage  
-
-
3.6  
V
on pins STP, DATA[7:0] and  
RESET_N/PSW_N  
VCC(I/O)  
V
on pin VBUS/FAULT  
on pins DP and DM  
on pin XTAL1  
0
-
5.5  
V
0
-
3.6  
V
0
-
1.95  
+85  
+125  
V
Tamb  
Tj  
ambient temperature  
junction temperature  
40  
40  
+25  
-
°C  
°C  
[1] VCC(I/O) must be less than or equal to VCC  
.
ISP1505A_ISP1505C_3  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 03 — 26 August 2008  
53 of 75  
ISP1505A; ISP1505C  
NXP Semiconductors  
ULPI HS USB host and peripheral transceiver  
14. Static characteristics  
Table 44. Static characteristics: supply pins  
VCC = 3.0 V to 3.6 V; VCC(I/O) = 1.65 V to 3.6 V; Tamb = 40 °C to +85 °C; unless otherwise specified.  
Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 °C; unless otherwise specified.  
Symbol  
Parameter  
Conditions  
Min  
3.0  
Typ  
3.3  
1.8  
-
Max  
3.6  
Unit  
V
V(REG3V3) voltage on pin REG3V3  
V(REG1V8) voltage on pin REG1V8  
1.65  
1.0  
1.95  
1.5  
V
VPOR(trip) power-on reset trip  
voltage  
V
ICC  
supply current  
low-power mode; VBUS valid detector  
disabled; 1.5 kpull-up resistor on  
pin DP disconnected  
-
-
30  
85  
µA  
µA  
low-power mode; VBUS valid detector  
disabled; 1.5 kpull-up resistor on  
pin DP connected  
215  
280  
full-speed idle; no USB activity  
high-speed idle; no USB activity  
-
-
-
10  
19  
15  
-
-
-
mA  
mA  
mA  
[1]  
full-speed continuous data transmit;  
50 pF load on pins DP and DM  
[1]  
[1]  
full-speed continuous data receive  
-
-
11  
48  
-
-
mA  
mA  
high-speed continuous data transmit;  
45 load on pins DP and DM to ground  
[1]  
high-speed continuous data receive  
static current; I/O pins are idle  
-
-
28  
-
-
mA  
ICC(I/O)  
supply current on  
pin VCC(I/O)  
1
µA  
[1] A continuous stream of 1 kB packets with minimum inter-packet gap and all data bits set to logic 0 for continuous toggling.  
Table 45. Static characteristics: digital pins (CLOCK, DIR, STP, NXT, DATA[7:0], RESET_N/PSW_N)  
VCC = 3.0 V to 3.6 V; VCC(I/O) = 1.65 V to 3.6 V; Tamb = 40 °C to +85 °C; unless otherwise specified.  
Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 °C; unless otherwise specified.  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
Input levels  
VIL  
VIH  
IIL  
LOW-level input voltage  
HIGH-level input voltage  
LOW-level input current  
HIGH-level input current  
input leakage current  
-
-
0.3 × VCC(I/O)  
V
0.7 × VCC(I/O)  
-
-
V
VI = 0 V  
-
-
1
µA  
µA  
µA  
IIH  
ILI  
VI = VCC(I/O)  
-
-
1
1  
+0.1  
+1  
Output levels  
VOL  
VOH  
IOH  
IOL  
LOW-level output voltage  
IOL = +2 mA  
-
-
-
-
-
-
0.4  
V
HIGH-level output voltage  
HIGH-level output current  
LOW-level output current  
off-state output current  
IOH = 2 mA  
V
CC(I/O) 0.4  
-
V
VO = VCC(I/O) 0.4 V  
VO = 0.4 V  
4.8  
4.2  
-
-
mA  
mA  
µA  
-
IOZ  
0 V < VO < VCC(I/O)  
1
ISP1505A_ISP1505C_3  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 03 — 26 August 2008  
54 of 75  
ISP1505A; ISP1505C  
NXP Semiconductors  
ULPI HS USB host and peripheral transceiver  
Table 45. Static characteristics: digital pins (CLOCK, DIR, STP, NXT, DATA[7:0], RESET_N/PSW_N) …continued  
VCC = 3.0 V to 3.6 V; VCC(I/O) = 1.65 V to 3.6 V; Tamb = 40 °C to +85 °C; unless otherwise specified.  
Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 °C; unless otherwise specified.  
Symbol  
Impedance  
ZL  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
load impedance  
45  
-
65  
Pull-up and pull-down  
Ipd pull-down current  
interface protect  
25  
50  
90  
µA  
enabled; DATA[7:0]  
pins only; VI = VCC(I/O)  
Ipu  
pull-up current  
interface protect  
enabled; STP pin only;  
VI = 0 V  
30  
50  
80  
µA  
Capacitance  
Cin  
input capacitance  
pins STP, RESET_N,  
DATA[7:0]  
-
-
3.5  
pF  
Table 46. Static characteristics: pin VBUS/FAULT  
VCC = 3.0 V to 3.6 V; VCC(I/O) = 1.65 V to 3.6 V; Tamb = 40 °C to +85 °C; unless otherwise specified.  
Applicable only when pin VBUS/FAULT is used as FAULT.  
Symbol Parameter  
Input levels  
Conditions  
Min  
Typ  
Max  
Unit  
VIL  
VIH  
IIL  
LOW-level input voltage  
-
-
-
-
-
0.8  
-
V
HIGH-level input voltage  
LOW-level input current  
HIGH-level input current  
2.0  
V
VI = 0 V  
-
-
1
µA  
µA  
IIH  
VI = VCC(I/O)  
1
Table 47. Static characteristics: analog I/O pins (DP, DM)  
VCC = 3.0 V to 3.6 V; VCC(I/O) = 1.65 V to 3.6 V; Tamb = 40 °C to +85 °C; unless otherwise specified.  
Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 °C; unless otherwise specified.  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
Original USB transceiver (low-speed and full-speed)  
Input levels (differential receiver)  
VDI  
differential input sensitivity voltage |VDP VDM  
|
0.2  
0.8  
-
-
-
V
V
VCM  
differential common mode voltage includes VDI range  
range  
2.5  
Input levels (single-ended receivers)  
VIL  
LOW-level input voltage  
HIGH-level input voltage  
-
-
-
0.8  
-
V
V
VIH  
2.0  
Output levels  
VOL  
LOW-level output voltage  
HIGH-level output voltage  
pull-up on pin DP;  
RL = 1.5 kto 3.6 V  
0.0  
2.8  
0.18  
3.2  
0.3  
3.6  
V
V
VOH  
pull-down on pins DP and  
DM; RL = 15 kto GND  
ISP1505A_ISP1505C_3  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 03 — 26 August 2008  
55 of 75  
ISP1505A; ISP1505C  
NXP Semiconductors  
ULPI HS USB host and peripheral transceiver  
Table 47. Static characteristics: analog I/O pins (DP, DM) …continued  
VCC = 3.0 V to 3.6 V; VCC(I/O) = 1.65 V to 3.6 V; Tamb = 40 °C to +85 °C; unless otherwise specified.  
Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 °C; unless otherwise specified.  
Symbol  
Termination  
VTERM  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
termination voltage for upstream  
facing port pull-up  
for 1.5 kpull-up resistor  
3.0  
-
3.6  
V
Resistance  
RUP(DP)  
pull-up resistance on pin DP  
1425  
1500  
1575  
High-speed USB transceiver  
Input levels (differential receiver)  
VHSSQ  
high-speed squelch detection  
threshold voltage (differential  
signal amplitude)  
100  
525  
-
-
150  
625  
mV  
mV  
VHSDSC  
high-speed disconnect detection  
threshold voltage (differential  
signal amplitude)  
VHSDI  
high-speed differential input  
sensitivity  
|VDP VDM  
|
300  
-
-
-
mV  
mV  
VHSCM  
high-speed data signaling  
common mode voltage range  
(guideline for receiver)  
includes VDI range  
50  
+500  
VHSOI  
VHSOL  
high-speed idle level voltage  
10  
10  
-
-
+10  
+10  
mV  
mV  
high-speed data signaling  
LOW-level voltage  
Output levels  
VHSOH  
high-speed data signaling  
HIGH-level voltage  
360  
-
440  
mV  
VCHIRPJ  
VCHIRPK  
Chirp J level (differential voltage)  
Chirp K level (differential voltage)  
700  
-
-
1100  
mV  
mV  
900  
500  
Leakage current  
ILZ  
off-state leakage current  
1  
-
-
+1  
5
µA  
Capacitance  
Cin  
input capacitance  
pin to GND  
-
pF  
Resistance  
RDN(DP)  
pull-down resistance on pin DP  
pull-down resistance on pin DM  
14.25  
14.25  
15  
15  
15.75  
15.75  
kΩ  
kΩ  
RDN(DM)  
Termination  
[1]  
[1]  
ZO(drv)(DP) driver output impedance on pin DP steady-state drive  
40.5  
40.5  
45  
45  
49.5  
49.5  
ZO(drv)(DM) driver output impedance on  
pin DM  
steady-state drive  
ZINP  
input impedance exclusive of  
pull-up/pull-down (for  
low-/full-speed)  
10  
-
-
MΩ  
[1] For high-speed USB and full-speed USB.  
ISP1505A_ISP1505C_3  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 03 — 26 August 2008  
56 of 75  
ISP1505A; ISP1505C  
NXP Semiconductors  
ULPI HS USB host and peripheral transceiver  
Table 48. Static characteristics: VBUS comparators  
VCC = 3.0 V to 3.6 V; VCC(I/O) = 1.65 V to 3.6 V; Tamb = 40 °C to +85 °C; unless otherwise specified.  
Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 °C; unless otherwise specified.  
Symbol  
Parameter  
Conditions  
Min  
4.4  
0.8  
Typ  
4.5  
1.6  
Max  
4.65  
2.0  
Unit  
V
VA_VBUS_VLD  
VB_SESS_VLD  
A-device VBUS valid voltage  
B-device session valid voltage  
for A-device and  
B-device  
V
Vhys(B_SESS_VLD) B-device session valid hysteresis  
voltage  
70  
140  
0.5  
200  
0.8  
mV  
V
VB_SESS_END  
B-device session end voltage  
0.2  
Table 49. Static characteristics: VBUS resistors  
VCC = 3.0 V to 3.6 V; VCC(I/O) = 1.65 V to 3.6 V; Tamb = 40 °C to +85 °C; unless otherwise specified.  
Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 °C; unless otherwise specified.  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
RUP(VBUS)  
pull-up resistance on  
pin VBUS  
connect to pin REG3V3 when  
CHRG_VBUS is logic 1  
281  
680  
-
RDN(VBUS)  
pull-down resistance on  
pin VBUS  
connect to GND when  
DISCHRG_VBUS is logic 1  
656  
40  
850  
57  
-
RI(idle)(VBUS) idle input resistance on  
pin VBUS  
80  
kΩ  
Table 50. Static characteristics: resistor reference  
VCC = 3.0 V to 3.6 V; VCC(I/O) = 1.65 V to 3.6 V; Tamb = 40 °C to +85 °C; unless otherwise specified.  
Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 °C; unless otherwise specified.  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
VO(RREF)  
output voltage on pin RREF  
SUSPENDM is logic 1  
-
1.22  
-
V
ISP1505A_ISP1505C_3  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 03 — 26 August 2008  
57 of 75  
ISP1505A; ISP1505C  
NXP Semiconductors  
ULPI HS USB host and peripheral transceiver  
15. Dynamic characteristics  
Table 51. Dynamic characteristics: reset and clock  
VCC = 3.0 V to 3.6 V; VCC(I/O) = 1.65 V to 3.6 V; Tamb = 40 °C to +85 °C; unless otherwise specified.  
Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 °C; unless otherwise specified.  
Symbol  
Reset  
Parameter  
Conditions  
Min  
Typ  
Max Unit  
tW(POR)  
internal power-on reset pulse  
width  
0.2  
-
-
µs  
tw(REG1V8_H)  
tw(REG1V8_L)  
tW(RESET_N)  
tPWRUP  
REG1V8 HIGH pulse width  
REG1V8 LOW pulse width  
external RESET_N pulse width  
regulator start-up time  
2
-
-
-
-
-
µs  
µs  
ns  
ms  
11  
200  
-
-
-
4.7 µF ± 20 % capacitor each on  
1
pins REG1V8 and REG3V3  
Crystal or clock applied to XTAL1  
fi(XTAL1)  
input frequency on pin XTAL1  
ISP1505ABS  
ISP1505CBS  
ISP1505ABS  
ISP1505CBS  
-
-
-
-
-
19.2  
26  
-
-
-
MHz  
MHz  
tjit(i)(XTAL1)RMS  
RMS input jitter on pin XTAL1  
input duty cycle on pin XTAL1  
200 ps  
300 ps  
-
[1]  
δi(XTAL1)  
applicable only when clock is  
applied on pin XTAL1  
50  
-
%
fi(XTAL1)  
input frequency tolerance on  
pin XTAL1  
-
50  
200 ppm  
tr(XTAL1)  
rise time on pin XTAL1  
fall time on pin XTAL1  
only for square wave input  
only for square wave input  
only for square wave input  
-
-
-
-
5
ns  
ns  
V
tf(XTAL1)  
-
5
V(XTAL1)(p-p)  
peak-to-peak voltage on  
pin XTAL1  
0.566  
1.95  
Output CLOCK characteristics  
fo(CLOCK)  
output frequency on pin CLOCK  
-
60  
-
-
MHz  
tjit(o)(CLOCK)RMS RMS output jitter on pin CLOCK  
-
500 ps  
δo(CLOCK)  
output clock duty cycle on  
pin CLOCK  
45  
50  
55  
%
tstartup(PLL)  
PLL startup time  
-
650  
650  
-
µs  
tstartup(o)(CLOCK) output CLOCK start-up time  
measured from power good or  
assertion of pin STP  
450  
900 µs  
[1] The internal PLL is triggered only on the positive edge from the crystal oscillator. Therefore, the duty cycle is not critical.  
Table 52. Dynamic characteristics: digital I/O pins  
VCC = 3.0 V to 3.6 V; Tamb = 40 °C to +85 °C; unless otherwise specified.  
Symbol Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
VCC(I/O) = 1.65 V to 1.95 V  
tsu(DATA)  
DATA set-up time with respect to 20 pF total external load  
5.7  
0
-
-
-
-
ns  
ns  
the rising edge of pin CLOCK  
per pin  
th(DATA)  
DATA hold time with respect to  
the rising edge of pin CLOCK  
20 pF total external load  
per pin  
ISP1505A_ISP1505C_3  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 03 — 26 August 2008  
58 of 75  
ISP1505A; ISP1505C  
NXP Semiconductors  
ULPI HS USB host and peripheral transceiver  
Table 52. Dynamic characteristics: digital I/O pins …continued  
VCC = 3.0 V to 3.6 V; Tamb = 40 °C to +85 °C; unless otherwise specified.  
Symbol Parameter Conditions  
Min  
Typ  
Max  
Unit  
td(DATA)  
tsu(STP)  
th(STP)  
td(DIR)  
DATA output delay with respect 20 pF total external load  
to the rising edge of pin CLOCK per pin  
-
-
7.8  
ns  
STP set-up time with respect to 20 pF total external load  
4.5  
-
-
-
-
-
ns  
ns  
ns  
ns  
the rising edge of pin CLOCK  
per pin  
STP hold time with respect to  
the rising edge of pin CLOCK  
20 pF total external load  
per pin  
0
-
-
DIR output delay with respect to 20 pF total external load  
the rising edge of pin CLOCK per pin  
8.9  
8.9  
td(NXT)  
NXT output delay with respect to 20 pF total external load  
the rising edge of pin CLOCK per pin  
-
VCC(I/O) = 3.0 V to 3.6 V  
tsu(DATA)  
th(DATA)  
td(DATA)  
tsu(STP)  
th(STP)  
td(DIR)  
DATA set-up time with respect to 30 pF total external load  
3.3  
0.8  
-
-
-
-
-
-
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
the rising edge of pin CLOCK  
per pin  
DATA hold time with respect to  
the rising edge of pin CLOCK  
30 pF total external load  
per pin  
-
DATA output delay with respect 30 pF total external load  
to the rising edge of pin CLOCK per pin  
5.5  
-
STP set-up time with respect to 30 pF total external load  
3.4  
0.8  
-
the rising edge of pin CLOCK  
per pin  
STP hold time with respect to  
the rising edge of pin CLOCK  
30 pF total external load  
per pin  
-
DIR output delay with respect to 30 pF total external load  
the rising edge of pin CLOCK per pin  
6.6  
6.6  
td(NXT)  
NXT output delay with respect to 30 pF total external load  
the rising edge of pin CLOCK per pin  
-
Table 53. Dynamic characteristics: analog I/O pins (DP, DM)  
VCC = 3.0 V to 3.6 V; VCC(I/O) = 1.65 V to 3.6 V; Tamb = 40 °C to +85 °C; unless otherwise specified.  
Symbol Parameter  
High-speed driver  
Conditions  
Min  
Typ  
Max  
Unit  
tHSR  
tHSF  
Full-speed driver  
rise time (10 % to 90 %)  
500  
500  
-
-
-
-
ps  
ps  
fall time (10 % to 90 %)  
tFR  
rise time  
CL = 50 pF; 10 % to 90 % of  
4
-
-
-
-
20  
ns  
ns  
%
V
|VOH VOL  
CL = 50 pF; 10 % to 90 % of  
|VOH VOL  
differential rise and fall time excluding the first transition  
|
tFF  
fall time  
4
20  
|
tFRFM  
VCRS  
90  
1.3  
111.1  
2.0  
matching  
from the idle state  
output signal crossover  
voltage  
excluding the first transition  
from the idle state  
Low-speed driver  
tLR  
transition time: rise time  
CL = 200 pF to 600 pF;  
1.5 kpull-up on pin DM  
enabled; 10 % to 90 % of  
75  
-
300  
ns  
|VOH VOL  
|
ISP1505A_ISP1505C_3  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 03 — 26 August 2008  
59 of 75  
ISP1505A; ISP1505C  
NXP Semiconductors  
ULPI HS USB host and peripheral transceiver  
Table 53. Dynamic characteristics: analog I/O pins (DP, DM) …continued  
VCC = 3.0 V to 3.6 V; VCC(I/O) = 1.65 V to 3.6 V; Tamb = 40 °C to +85 °C; unless otherwise specified.  
Symbol Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
tLF  
transition time: fall time  
CL = 200 pF to 600 pF;  
1.5 kpull-up on pin DM  
enabled; 10 % to 90 % of  
75  
-
300  
ns  
|VOH VOL  
|
tLRFM  
rise and fall time matching tLR/tLF; excluding the first  
transition from the idle state  
80  
-
125  
%
Driver timing  
tPLH(drv)  
tPHL(drv)  
tPHZ  
driver propagation delay  
(LOW to HIGH)  
TX_DAT, TX_SE0 to DP, DM;  
see Figure 22  
-
-
-
-
-
-
-
-
-
-
-
-
11  
11  
12  
12  
20  
20  
ns  
ns  
ns  
ns  
ns  
ns  
driver propagation delay  
(HIGH to LOW)  
TX_DAT, TX_SE0 to DP, DM;  
see Figure 22  
driver disable delay from  
HIGH level  
TX_ENABLE to DP, DM;  
see Figure 23  
tPLZ  
driver disable delay from  
LOW level  
TX_ENABLE to DP, DM;  
see Figure 23  
tPZH  
driver enable delay to HIGH TX_ENABLE to DP, DM;  
level see Figure 23  
tPZL  
driver enable delay to LOW TX_ENABLE to DP, DM;  
level see Figure 23  
Receiver timing  
Differential receiver  
tPLH(rcv)  
receiver propagation delay DP, DM to RX_RCV, RX_DP  
(LOW to HIGH) and RX_DM; see Figure 24  
-
-
-
-
17  
17  
ns  
ns  
tPHL(rcv)  
receiver propagation delay DP, DM to RX_RCV, RX_DP  
(HIGH to LOW)  
Single-ended receiver  
tPLH(se) single-ended propagation  
and RX_DM; see Figure 24  
DP, DM to RX_RCV, RX_DP  
and RX_DM; see Figure 24  
-
-
-
-
17  
17  
ns  
ns  
delay (LOW to HIGH)  
tPHL(se)  
single-ended propagation  
delay (HIGH to LOW)  
DP, DM to RX_RCV, RX_DP  
and RX_DM; see Figure 24  
ISP1505A_ISP1505C_3  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 03 — 26 August 2008  
60 of 75  
ISP1505A; ISP1505C  
NXP Semiconductors  
ULPI HS USB host and peripheral transceiver  
1.8 V  
logic input 0.9 V  
0 V  
0.9 V  
t
, t , t  
HSF FF LF  
t
, t , t  
HSR FR LR  
V
t
t
PHL(drv)  
OH  
PLH(drv)  
90 %  
90 %  
V
OH  
differential  
data lines  
V
V
CRS  
CRS  
10 %  
10 %  
V
OL  
V
OL  
004aaa861  
004aaa573  
Fig 21. Rise time and fall time  
Fig 22. Timing of TX_DAT and TX_SE0 to DP and DM  
2.0 V  
1.8 V  
differential  
data lines  
V
V
CRS  
CRS  
logic  
input  
0.9 V  
0.9 V  
0.8 V  
0 V  
t
t
PLH(rcv)  
PHL(rcv)  
t
t
t
PHZ  
PZH  
t
PHL(se)  
t
PLH(se)  
t
PLZ  
PZL  
V
OH  
V
OH  
V
0.3 V  
OH  
0.9 V  
0.9 V  
logic output  
differential  
data lines  
V
CRS  
V
+ 0.3 V  
OL  
V
OL  
V
004aaa574  
004aaa575  
OL  
Fig 23. Timing of TX_ENABLE to DP and DM  
Fig 24. Timing of DP and DM to RX_RCV, RX_DP and  
RX_DM  
15.1 ULPI timing  
ULPI interface timing requirements are given in Figure 25. This timing applies to  
synchronous mode only. All timing is measured with respect to the ISP1505 CLOCK pin.  
All signals are clocked on the rising edge of CLOCK.  
CLOCK  
t
t
su(STP) h(STP)  
CONTROL IN  
(STP)  
t
t
su(DATA)  
h(DATA)  
DATA IN  
(8-BIT)  
t
,
d(DIR)  
t
d(NXT)  
CONTROL OUT  
(DIR, NXT)  
t
,
d(DIR)  
t
t
d(NXT)  
d(DATA)  
DATA OUT  
(8-BIT)  
004aaa722  
Fig 25. ULPI interface timing  
ISP1505A_ISP1505C_3  
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Product data sheet  
Rev. 03 — 26 August 2008  
61 of 75  
ISP1505A; ISP1505C  
NXP Semiconductors  
ULPI HS USB host and peripheral transceiver  
16. Application information  
Table 54. Recommended bill of materials  
Designator[1] Application  
Value  
Comment  
Cbypass  
highly recommended for all  
applications  
0.1 µF  
-
Cfilter  
highly recommended for all  
applications  
4.7 µF ± 20 %; use a LOW  
ESR capacitor (0.2 to  
2 ) for best performance  
-
CVBUS  
mandatory for peripherals  
mandatory for host  
0.1 µF and 1 µF to 10 µF in -  
parallel  
0.1 µF and 120 µF ± 20 %  
(min) in parallel  
-
-
mandatory for OTG  
0.1 µF and 1 µF to 6.5 µF  
in parallel  
DESD  
recommended for all  
ESD-sensitive applications  
-
IP4359CX4/LF; Wafer-Level Chip-Scale  
Package (WLCSP); ESD IEC 61000-4-2  
level 4; ±15 kV contact; ±15 kV air discharge  
compliant protection  
Rpullup  
recommended; for applications 4.7 k(recommended)  
with an external VBUS supply  
controlled by PSW_N  
maximum value is determined by the voltage  
drop on PSW_N caused by leakage into  
PSW_N and the external supply control pin  
RRREF  
RVBUS  
mandatory in all applications  
12 kΩ ± 1 %  
1 kΩ ± 5 %  
-
-
strongly recommended for  
peripheral or external 5 V  
applications only  
RXTAL  
XTAL  
required only for applications  
driving a square wave into the  
XTAL1 pin  
47 kΩ ± 5 %  
used to avoid floating input on the XTAL1 pin  
crystal is used  
19.2 MHz  
26 MHz  
-
CL = 10 pF; RS < 220 ; CXTAL = 18 pF  
CL = 10 pF; RS < 130 ; CXTAL = 18 pF  
CSTCE26M0XK2***-R0[2]  
CXTAL is not required  
C(XTAL)SQ  
required only for applications  
driving a square wave into the  
XTAL1 pin that has a DC offset  
100 pF  
used to AC couple the input square wave to  
the XTAL1 pin  
[1] For detailed information and alternative interface options, refer to the Interfacing to the ISP1504/5/6 (AN10048) application note.  
[2] For more information, contact Murata.  
ISP1505A_ISP1505C_3  
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Product data sheet  
Rev. 03 — 26 August 2008  
62 of 75  
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V
V
CC(I/O)  
CC  
C
C
bypass  
bypass  
+5 V  
IN  
FAULT  
OUT  
R
pullup  
V
BUS  
C
bypass  
DATA1  
DATA0  
DATA2  
SWITCH  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
ON  
DATA0  
DATA1  
DATA2  
DATA3  
DATA4  
DATA5  
V
CC(I/O)  
2
V
CC(I/O)  
RREF  
DM  
DATA3  
CLOCK  
DATA4  
DATA5  
DATA6  
DATA7  
NXT  
3
R
RREF  
V
BUS  
1
2
3
4
5
6
7
8
4
D−  
5
D+  
DP  
6
HOST  
CONTROLLER  
ISP1505  
GND  
V
CC  
USB  
STANDARD-A  
RECEPTACLE  
7
DATA6  
SHIELD  
SHIELD  
SHIELD  
SHIELD  
V
/FAULT  
BUS  
C
VBUS  
8
DATA7  
NXT  
A1  
A2  
REG3V3  
XTAL1  
XTAL2  
9
IP4359CX4/LF  
B1  
B2  
STP  
STP  
10  
11  
12  
D
ESD  
DIR  
DIR  
RESET_N/  
PSW_N  
CLOCK  
REG1V8  
(1)  
XTAL  
XTAL  
GND (die pad)  
C
bypass  
C
XTAL  
C
filter  
C
C
filter  
C
bypass  
004aaa589  
(1) Frequency is version dependent: ISP1505ABS: 19.2 MHz; ISP1505CBS: 26 MHz.  
Fig 26. Using the ISP1505 with a USB host controller; external 5 V source with built-in FAULT and external crystal  
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx  
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x  
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx  
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx  
V
CC(I/O)  
C
C
bypass  
bypass  
V
CC  
DATA0  
DATA1  
DATA2  
DATA3  
CLOCK  
DATA4  
C
bypass  
DATA1  
DATA0  
DATA2  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
1
V
CC(I/O)  
2
3
4
V
CC(I/O)  
RREF  
DATA3  
CLOCK  
DATA4  
DATA5  
DATA6  
DATA7  
NXT  
R
RREF  
R
VBUS  
V
BUS  
1
2
3
4
_
DM  
DP  
D
5
D+  
GND  
PERIPHERAL  
CONTROLLER  
6
7
DATA5  
DATA6  
ISP1505  
USB  
STANDARD-B  
RECEPTACLE  
V
CC  
A1  
A2  
SHIELD  
SHIELD  
SHIELD  
SHIELD  
V
/FAULT  
BUS  
5
8
DATA7  
NXT  
IP4359CX4/LF  
B1  
B2  
6
7
REG3V3  
XTAL1  
XTAL2  
9
D
ESD  
10  
11  
STP  
STP  
C
VBUS  
C
bypass  
C
filter  
8
DIR  
DIR  
RESET_N/  
PSW_N  
REG1V8  
12  
GND (die pad)  
C
C
filter  
bypass  
C
(XTAL)SQ  
R
XTAL  
(1)  
f
i(XTAL1)  
004aaa896  
(1) Frequency is version dependent: ISP1505ABS: 19.2 MHz; ISP1505CBS: 26 MHz.  
Fig 27. Using the ISP1505 with a peripheral controller; external square wave input on pin XTAL1  
ISP1505A; ISP1505C  
NXP Semiconductors  
ULPI HS USB host and peripheral transceiver  
17. Package outline  
HVQFN24: plastic thermal enhanced very thin quad flat package; no leads;  
24 terminals; body 4 x 4 x 0.85 mm  
SOT616-3  
B
A
D
terminal 1  
index area  
A
A
1
E
c
detail X  
e
1
C
1/2 e  
y
y
C
1
e
v
M
M
C
C
A
B
b
7
12  
w
L
13  
6
e
e
E
h
2
1/2 e  
1
18  
terminal 1  
index area  
24  
19  
X
D
h
0
2.5  
5 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
(1)  
A
(1)  
(1)  
UNIT  
mm  
A
b
c
E
e
e
e
2
y
D
D
E
L
v
w
y
1
1
h
1
h
max.  
0.05 0.30  
0.00 0.18  
4.1  
3.9  
2.75  
2.45  
4.1  
3.9  
2.75  
2.45  
0.5  
0.3  
0.05  
0.1  
1
0.2  
0.5  
2.5  
2.5  
0.1 0.05  
Note  
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
04-11-19  
05-03-10  
SOT616-3  
- - -  
MO-220  
- - -  
Fig 28. Package outline SOT616-3 (HVQFN24)  
ISP1505A_ISP1505C_3  
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Product data sheet  
Rev. 03 — 26 August 2008  
65 of 75  
ISP1505A; ISP1505C  
NXP Semiconductors  
ULPI HS USB host and peripheral transceiver  
18. Soldering of SMD packages  
This text provides a very brief insight into a complex technology. A more in-depth account  
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow  
soldering description”.  
18.1 Introduction to soldering  
Soldering is one of the most common methods through which packages are attached to  
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both  
the mechanical and the electrical connection. There is no single soldering method that is  
ideal for all IC packages. Wave soldering is often preferred when through-hole and  
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not  
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high  
densities that come with increased miniaturization.  
18.2 Wave and reflow soldering  
Wave soldering is a joining technology in which the joints are made by solder coming from  
a standing wave of liquid solder. The wave soldering process is suitable for the following:  
Through-hole components  
Leaded or leadless SMDs, which are glued to the surface of the printed circuit board  
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless  
packages which have solder lands underneath the body, cannot be wave soldered. Also,  
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,  
due to an increased probability of bridging.  
The reflow soldering process involves applying solder paste to a board, followed by  
component placement and exposure to a temperature profile. Leaded packages,  
packages with solder balls, and leadless packages are all reflow solderable.  
Key characteristics in both wave and reflow soldering are:  
Board specifications, including the board finish, solder masks and vias  
Package footprints, including solder thieves and orientation  
The moisture sensitivity level of the packages  
Package placement  
Inspection and repair  
Lead-free soldering versus SnPb soldering  
18.3 Wave soldering  
Key characteristics in wave soldering are:  
Process issues, such as application of adhesive and flux, clinching of leads, board  
transport, the solder wave parameters, and the time during which components are  
exposed to the wave  
Solder bath specifications, including temperature and impurities  
ISP1505A_ISP1505C_3  
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Product data sheet  
Rev. 03 — 26 August 2008  
66 of 75  
ISP1505A; ISP1505C  
NXP Semiconductors  
ULPI HS USB host and peripheral transceiver  
18.4 Reflow soldering  
Key characteristics in reflow soldering are:  
Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to  
higher minimum peak temperatures (see Figure 29) than a SnPb process, thus  
reducing the process window  
Solder paste printing issues including smearing, release, and adjusting the process  
window for a mix of large and small components on one board  
Reflow temperature profile; this profile includes preheat, reflow (in which the board is  
heated to the peak temperature) and cooling down. It is imperative that the peak  
temperature is high enough for the solder to make reliable solder joints (a solder paste  
characteristic). In addition, the peak temperature must be low enough that the  
packages and/or boards are not damaged. The peak temperature of the package  
depends on package thickness and volume and is classified in accordance with  
Table 55 and 56  
Table 55. SnPb eutectic process (from J-STD-020C)  
Package thickness (mm) Package reflow temperature (°C)  
Volume (mm3)  
< 350  
235  
350  
220  
< 2.5  
2.5  
220  
220  
Table 56. Lead-free process (from J-STD-020C)  
Package thickness (mm) Package reflow temperature (°C)  
Volume (mm3)  
< 350  
260  
350 to 2000  
> 2000  
260  
< 1.6  
260  
250  
245  
1.6 to 2.5  
> 2.5  
260  
245  
250  
245  
Moisture sensitivity precautions, as indicated on the packing, must be respected at all  
times.  
Studies have shown that small packages reach higher temperatures during reflow  
soldering, see Figure 29.  
ISP1505A_ISP1505C_3  
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Product data sheet  
Rev. 03 — 26 August 2008  
67 of 75  
ISP1505A; ISP1505C  
NXP Semiconductors  
ULPI HS USB host and peripheral transceiver  
maximum peak temperature  
= MSL limit, damage level  
temperature  
minimum peak temperature  
= minimum soldering temperature  
peak  
temperature  
time  
001aac844  
MSL: Moisture Sensitivity Level  
Fig 29. Temperature profiles for large and small components  
For further information on temperature profiles, refer to Application Note AN10365  
“Surface mount reflow soldering description”.  
19. Abbreviations  
Table 57. Abbreviations  
Acronym  
ASIC  
ATX  
Description  
Application-Specific Integrated Circuit  
Analog USB Transceiver  
Compact Disc-ReWritable  
End-Of-Packet  
CD-RW  
EOP  
ESD  
ESR  
FS  
ElectroStatic Discharge  
Effective Series Resistance  
Full-Speed  
HBM  
HNP  
HS  
Human Body Model  
Host Negotiation Protocol  
High-Speed  
ID  
Identification  
IEC  
International Electrotechnical Commission  
Low-Speed  
LS  
MO  
Magneto-Optical  
NRZI  
OTG  
PCB  
PDA  
PHY  
Non-Return-to-Zero Inverted  
On-The-Go  
Printed-Circuit Board  
Personal Digital Assistant  
Physical Layer  
ISP1505A_ISP1505C_3  
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Product data sheet  
Rev. 03 — 26 August 2008  
68 of 75  
ISP1505A; ISP1505C  
NXP Semiconductors  
ULPI HS USB host and peripheral transceiver  
Table 57. Abbreviations …continued  
Acronym  
Description  
PID  
Packet Identifier  
PLD  
Programmable Logic Device  
Phase-Locked Loop  
PLL  
POR  
Power-On Reset  
RoHS  
RXCMD  
SE0  
Restriction of Hazardous Substances  
Receive Command  
Single-Ended Zero  
SOF  
Start-Of-Frame  
SRP  
Session Request Protocol  
Set-Top Box  
STB  
SYNC  
TTL  
Synchronous  
Transistor-Transistor Logic  
Transmit Command  
TXCMD  
USB  
Universal Serial Bus  
USB-IF  
ULPI  
UTMI  
UTMI+  
USB Implementers Forum  
UTMI+ Low Pin Interface  
USB 2.0 Transceiver Macrocell Interface  
USB 2.0 Transceiver Macrocell Interface Plus  
20. References  
[1] Universal Serial Bus Specification Rev. 2.0  
[2] On-The-Go Supplement to the USB 2.0 Specification Rev. 1.3  
[3] UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1  
[4] UTMI+ Specification Rev. 1.0  
[5] USB 2.0 Transceiver Macrocell Interface (UTMI) Specification Ver. 1.05  
[6] Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM)  
(JESD22-A114D)  
[7] Interfacing to the ISP1504/5/6 (AN10048)  
ISP1505A_ISP1505C_3  
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Product data sheet  
Rev. 03 — 26 August 2008  
69 of 75  
ISP1505A; ISP1505C  
NXP Semiconductors  
ULPI HS USB host and peripheral transceiver  
21. Revision history  
Table 58. Revision history  
Document ID  
Release date  
Data sheet status  
Change notice  
Supersedes  
ISP1505A_ISP1505C_3 20080826  
Product data sheet  
-
ISP1505A_ISP1505C_2  
Modifications:  
Changed On-The-Go Supplement to the USB 2.0 Specification from Rev. 1.2 to Rev. 1.3.  
Section 2 “Features”: updated.  
Section 8.2 “USB and OTG state transitions”: updated the first sentence.  
Section “OTG devices”: updated the last sentence.  
Section 9.10.1 “Full-speed and low-speed host-initiated suspend and resume”: updated the  
second list item.  
Section 9.10.2 “High-speed suspend and resume”: updated the second list item.  
Table 41 “Power Control register (address R = 3Dh to 3Fh, W = 3Dh, S = 3Eh, C = 3Fh) bit  
description”: updated description for bits 3 and 2.  
Removed reference to input clock mode from the following sections:  
Section 2 “Features”  
Section 5 “Block diagram”  
Table 2 “Pin description”  
Section 7.5 “Crystal oscillator and PLL”  
Section 7.10.2 “VCC(I/O)  
Section 7.10.8 “XTAL1 and XTAL2”  
Section 7.10.13 “CLOCK”  
Table 3 “ULPI signal description”  
Section 9.3 “Power-up, reset and bus idle sequence”  
Table 42 “Limiting values”  
Table 43 “Recommended operating conditions”  
Table 45 “Static characteristics: digital pins (CLOCK, DIR, STP, NXT, DATA[7:0],  
RESET_N/PSW_N)”  
Table 51 “Dynamic characteristics: reset and clock”  
Table 52 “Dynamic characteristics: digital I/O pins”  
Section 16 “Application information”  
ISP1505A_ISP1505C_2 20070913  
Product data sheet  
-
ISP1505A_ISP1505C_1  
Modifications: Section 9.4.2 “Fault detection”: updated.  
Section “Standard USB host controllers”: updated the first list item.  
Section 10.2 “Extended register set”: updated the second paragraph.  
Table 42 “Limiting values”: added VI on the DP and DM pins, and added Table note 1.  
Table 51 “Dynamic characteristics: reset and clock”: added δi(XTAL1) and Table note 1.  
Table 52 “Dynamic characteristics: digital I/O pins”: updated.  
Section 16 “Application information”: updated.  
ISP1505A_ISP1505C_1 20061019  
Product data sheet  
-
-
ISP1505A_ISP1505C_3  
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Product data sheet  
Rev. 03 — 26 August 2008  
70 of 75  
ISP1505A; ISP1505C  
NXP Semiconductors  
ULPI HS USB host and peripheral transceiver  
22. Legal information  
22.1 Data sheet status  
Document status[1][2]  
Product status[3]  
Development  
Definition  
Objective [short] data sheet  
This document contains data from the objective specification for product development.  
This document contains data from the preliminary specification.  
This document contains the product specification.  
Preliminary [short] data sheet Qualification  
Product [short] data sheet Production  
[1]  
[2]  
[3]  
Please consult the most recently issued document before initiating or completing a design.  
The term ‘short data sheet’ is explained in section “Definitions”.  
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status  
information is available on the Internet at URL http://www.nxp.com.  
malfunction of an NXP Semiconductors product can reasonably be expected  
22.2 Definitions  
to result in personal injury, death or severe property or environmental  
damage. NXP Semiconductors accepts no liability for inclusion and/or use of  
NXP Semiconductors products in such equipment or applications and  
therefore such inclusion and/or use is at the customer’s own risk.  
Draft — The document is a draft version only. The content is still under  
internal review and subject to formal approval, which may result in  
modifications or additions. NXP Semiconductors does not give any  
representations or warranties as to the accuracy or completeness of  
information included herein and shall have no liability for the consequences of  
use of such information.  
Applications — Applications that are described herein for any of these  
products are for illustrative purposes only. NXP Semiconductors makes no  
representation or warranty that such applications will be suitable for the  
specified use without further testing or modification.  
Short data sheet — A short data sheet is an extract from a full data sheet  
with the same product type number(s) and title. A short data sheet is intended  
for quick reference only and should not be relied upon to contain detailed and  
full information. For detailed and full information see the relevant full data  
sheet, which is available on request via the local NXP Semiconductors sales  
office. In case of any inconsistency or conflict with the short data sheet, the  
full data sheet shall prevail.  
Limiting values — Stress above one or more limiting values (as defined in  
the Absolute Maximum Ratings System of IEC 60134) may cause permanent  
damage to the device. Limiting values are stress ratings only and operation of  
the device at these or any other conditions above those given in the  
Characteristics sections of this document is not implied. Exposure to limiting  
values for extended periods may affect device reliability.  
Terms and conditions of sale — NXP Semiconductors products are sold  
subject to the general terms and conditions of commercial sale, as published  
at http://www.nxp.com/profile/terms, including those pertaining to warranty,  
intellectual property rights infringement and limitation of liability, unless  
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of  
any inconsistency or conflict between information in this document and such  
terms and conditions, the latter will prevail.  
22.3 Disclaimers  
General — Information in this document is believed to be accurate and  
reliable. However, NXP Semiconductors does not give any representations or  
warranties, expressed or implied, as to the accuracy or completeness of such  
information and shall have no liability for the consequences of use of such  
information.  
No offer to sell or license — Nothing in this document may be interpreted  
or construed as an offer to sell products that is open for acceptance or the  
grant, conveyance or implication of any license under any copyrights, patents  
or other industrial or intellectual property rights.  
Right to make changes — NXP Semiconductors reserves the right to make  
changes to information published in this document, including without  
limitation specifications and product descriptions, at any time and without  
notice. This document supersedes and replaces all information supplied prior  
to the publication hereof.  
22.4 Trademarks  
Notice: All referenced brands, product names, service names and trademarks  
are the property of their respective owners.  
Suitability for use — NXP Semiconductors products are not designed,  
authorized or warranted to be suitable for use in medical, military, aircraft,  
space or life support equipment, nor in applications where failure or  
23. Contact information  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
ISP1505A_ISP1505C_3  
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Product data sheet  
Rev. 03 — 26 August 2008  
71 of 75  
ISP1505A; ISP1505C  
NXP Semiconductors  
ULPI HS USB host and peripheral transceiver  
24. Tables  
Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .3  
Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5  
Table 3. ULPI signal description . . . . . . . . . . . . . . . . . .13  
Table 4. Signal mapping during low-power mode . . . . .14  
Table 5. Signal mapping for 6-pin serial mode . . . . . . .15  
Table 6. Signal mapping for 3-pin serial mode . . . . . . .16  
Table 7. Operating states and their corresponding  
resistor settings . . . . . . . . . . . . . . . . . . . . . . . .16  
Table 8. TXCMD byte format . . . . . . . . . . . . . . . . . . . . .22  
Table 9. RXCMD byte format . . . . . . . . . . . . . . . . . . . . .23  
Table 10. LINESTATE[1:0] encoding for upstream  
facing ports: peripheral . . . . . . . . . . . . . . . . . .23  
Table 11. LINESTATE[1:0] encoding for downstream  
facing ports: host . . . . . . . . . . . . . . . . . . . . . . .24  
Table 12. Encoded VBUS voltage state . . . . . . . . . . . . . .24  
Table 13. VBUS indicators in RXCMD required for  
typical applications . . . . . . . . . . . . . . . . . . . . . .25  
Table 14. Encoded USB event signals . . . . . . . . . . . . . .26  
Table 15. PHY pipeline delays . . . . . . . . . . . . . . . . . . . . .30  
Table 16. Link decision times . . . . . . . . . . . . . . . . . . . . .31  
Table 17. Immediate register set overview . . . . . . . . . . .43  
Table 18. Extended register set overview . . . . . . . . . . . .43  
Table 19. Vendor ID Low register (address R = 00h)  
bit description . . . . . . . . . . . . . . . . . . . . . . . . .44  
Table 20. Vendor ID High register (address R = 01h)  
bit description . . . . . . . . . . . . . . . . . . . . . . . . .44  
Table 21. Product ID Low register (address R = 02h)  
bit description . . . . . . . . . . . . . . . . . . . . . . . . .44  
Table 22. Product ID High register (address R = 03h)  
bit description . . . . . . . . . . . . . . . . . . . . . . . . .44  
Table 23. Function Control register (address R =  
04h to 06h, W = 04h, S = 05h, C = 06h) bit  
C = 12h) bit allocation . . . . . . . . . . . . . . . . . . . 48  
Table 32. USB Interrupt Enable Falling Edge register  
(address R = 10h to 12h, W = 10h, S = 11h,  
C = 12h) bit description . . . . . . . . . . . . . . . . . . 48  
Table 33. USB Interrupt Status register  
(address R = 13h) bit allocation . . . . . . . . . . . 48  
Table 34. USB Interrupt Status register  
(address R = 13h) bit description . . . . . . . . . . 49  
Table 35. USB Interrupt Latch register  
(address R = 14h) bit allocation . . . . . . . . . . . 49  
Table 36. USB Interrupt Latch register  
(address R = 14h) bit description . . . . . . . . . . 49  
Table 37. Debug register (address R = 15h)  
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 49  
Table 38. Debug register (address R = 15h)  
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 50  
Table 39. Scratch register (address R = 16h to 18h,  
W = 16h, S = 17h, C = 18h) bit description . . . 50  
Table 40. Power Control register  
(address R = 3Dh to 3Fh, W = 3Dh, S = 3Eh,  
C = 3Fh) bit allocation . . . . . . . . . . . . . . . . . . . 50  
Table 41. Power Control register  
(address R = 3Dh to 3Fh, W = 3Dh, S = 3Eh,  
C = 3Fh) bit description . . . . . . . . . . . . . . . . . . 51  
Table 42. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . 53  
Table 43. Recommended operating conditions . . . . . . . . 53  
Table 44. Static characteristics: supply pins . . . . . . . . . . 54  
Table 45. Static characteristics: digital pins  
(CLOCK, DIR, STP, NXT, DATA[7:0],  
RESET_N/PSW_N) . . . . . . . . . . . . . . . . . . . . . 54  
Table 46. Static characteristics: pin VBUS/FAULT . . . . . . 55  
Table 47. Static characteristics: analog I/O pins  
(DP, DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55  
Table 48. Static characteristics: VBUS comparators . . . . 57  
Table 49. Static characteristics: VBUS resistors . . . . . . . . 57  
Table 50. Static characteristics: resistor reference . . . . . 57  
Table 51. Dynamic characteristics: reset and clock . . . . 58  
Table 52. Dynamic characteristics: digital I/O pins . . . . . 58  
Table 53. Dynamic characteristics: analog I/O pins  
(DP, DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59  
Table 54. Recommended bill of materials . . . . . . . . . . . . 62  
Table 55. SnPb eutectic process (from J-STD-020C) . . . 67  
Table 56. Lead-free process (from J-STD-020C) . . . . . . 67  
Table 57. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 68  
Table 58. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 70  
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44  
Table 24. Function Control register (address R =  
04h to 06h, W = 04h, S = 05h, C = 06h) bit  
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .45  
Table 25. Interface Control register (address R =  
07h to 09h, W = 07h, S = 08h, C = 09h) bit  
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45  
Table 26. Interface Control register (address R =  
07h to 09h, W = 07h, S = 08h, C = 09h) bit  
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .46  
Table 27. OTG Control register  
(address R = 0Ah to 0Ch, W = 0Ah, S = 0Bh,  
C = 0Ch) bit allocation . . . . . . . . . . . . . . . . . . .46  
Table 28. OTG Control register  
(address R = 0Ah to 0Ch, W = 0Ah, S = 0Bh,  
C = 0Ch) bit description . . . . . . . . . . . . . . . . . .47  
Table 29. USB Interrupt Enable Rising Edge register  
(address R = 0Dh to 0Fh, W = 0Dh, S = 0Eh,  
C = 0Fh) bit allocation . . . . . . . . . . . . . . . . . . .47  
Table 30. USB Interrupt Enable Rising Edge register  
(address R = 0Dh to 0Fh, W = 0Dh, S = 0Eh,  
C = 0Fh) bit description . . . . . . . . . . . . . . . . . .48  
Table 31. USB Interrupt Enable Falling Edge register  
(address R = 10h to 12h, W = 10h, S = 11h,  
ISP1505A_ISP1505C_3  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 03 — 26 August 2008  
72 of 75  
ISP1505A; ISP1505C  
NXP Semiconductors  
ULPI HS USB host and peripheral transceiver  
25. Figures  
Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .4  
Fig 2. Pin configuration HVQFN24; top view . . . . . . . . . .5  
Fig 3. Internal power-on reset timing . . . . . . . . . . . . . . .18  
Fig 4. Power-up and reset sequence required  
before the ULPI bus is ready for use . . . . . . . . . .20  
Fig 5. Interface behavior with respect to RESET_N. . . .21  
Fig 6. Single and back-to-back RXCMDs from the  
ISP1505 to the link. . . . . . . . . . . . . . . . . . . . . . . .23  
Fig 7. RXCMD A_VBUS_VLD indicator source . . . . . . .25  
Fig 8. Example of register write, register read,  
extended register write and extended  
register read. . . . . . . . . . . . . . . . . . . . . . . . . . . . .27  
Fig 9. USB reset and high-speed detection  
handshake (chirp) sequence . . . . . . . . . . . . . . . .29  
Fig 10. Example of using the ISP1505 to transmit and  
receive USB data. . . . . . . . . . . . . . . . . . . . . . . . .30  
Fig 11. High-speed transmit-to-transmit packet timing. . .31  
Fig 12. High-speed receive-to-transmit packet timing . . .32  
Fig 13. Preamble sequence. . . . . . . . . . . . . . . . . . . . . . .33  
Fig 14. Full-speed suspend and resume . . . . . . . . . . . . .34  
Fig 15. High-speed suspend and resume . . . . . . . . . . . .36  
Fig 16. Remote wake-up from low-power mode . . . . . . .38  
Fig 17. Transmitting USB packets without  
the automatic SYNC and EOP generation. . . . . .39  
Fig 18. Example of transmit followed by receive in  
6-pin serial mode . . . . . . . . . . . . . . . . . . . . . . . . .41  
Fig 19. Example of transmit followed by receive in  
3-pin serial mode . . . . . . . . . . . . . . . . . . . . . . . . .41  
Fig 20. Human body ESD test model. . . . . . . . . . . . . . . .52  
Fig 21. Rise time and fall time . . . . . . . . . . . . . . . . . . . . .61  
Fig 22. Timing of TX_DAT and TX_SE0 to DP and DM. .61  
Fig 23. Timing of TX_ENABLE to DP and DM. . . . . . . . .61  
Fig 24. Timing of DP and DM to RX_RCV, RX_DP  
and RX_DM . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61  
Fig 25. ULPI interface timing . . . . . . . . . . . . . . . . . . . . . .61  
Fig 26. Using the ISP1505 with a USB host controller;  
external 5 V source with built-in FAULT and  
external crystal. . . . . . . . . . . . . . . . . . . . . . . . . . .63  
Fig 27. Using the ISP1505 with a peripheral controller;  
external square wave input on pin XTAL1 . . . . . .64  
Fig 28. Package outline SOT616-3 (HVQFN24) . . . . . . .65  
Fig 29. Temperature profiles for large and small  
components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68  
ISP1505A_ISP1505C_3  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 03 — 26 August 2008  
73 of 75  
ISP1505A; ISP1505C  
NXP Semiconductors  
ULPI HS USB host and peripheral transceiver  
26. Contents  
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1  
8.1.4  
8.2  
3-pin full-speed or low-speed serial mode . . . 15  
USB and OTG state transitions . . . . . . . . . . . 16  
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2  
Ordering information. . . . . . . . . . . . . . . . . . . . . 3  
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
9
Protocol description . . . . . . . . . . . . . . . . . . . . 18  
ULPI references . . . . . . . . . . . . . . . . . . . . . . . 18  
Power-On Reset (POR) . . . . . . . . . . . . . . . . . 18  
Power-up, reset and bus idle sequence . . . . . 18  
Interface protection. . . . . . . . . . . . . . . . . . . . . 20  
Interface behavior with respect to  
9.1  
9.2  
9.3  
9.3.1  
9.3.2  
6
6.1  
6.2  
Pinning information. . . . . . . . . . . . . . . . . . . . . . 5  
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5  
RESET_N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
7
7.1  
7.2  
7.3  
7.4  
7.5  
7.6  
7.6.1  
7.6.2  
7.6.3  
7.7  
7.8  
7.9  
7.10  
7.10.1  
7.10.2  
7.10.3  
7.10.4  
7.10.5  
7.10.6  
Functional description . . . . . . . . . . . . . . . . . . . 7  
ULPI interface controller . . . . . . . . . . . . . . . . . . 7  
USB data serializer and deserializer. . . . . . . . . 7  
Hi-Speed USB (USB 2.0) ATX . . . . . . . . . . . . . 7  
Voltage regulator. . . . . . . . . . . . . . . . . . . . . . . . 8  
Crystal oscillator and PLL. . . . . . . . . . . . . . . . . 8  
VBUS comparators. . . . . . . . . . . . . . . . . . . . . . . 8  
9.4  
VBUS power and fault detection . . . . . . . . . . . 21  
9.4.1  
9.4.2  
9.5  
9.5.1  
9.5.2  
9.5.2.1  
9.5.2.2  
9.5.2.3  
9.5.2.4  
9.6  
Driving 5 V on VBUS . . . . . . . . . . . . . . . . . . . . 21  
Fault detection . . . . . . . . . . . . . . . . . . . . . . . . 21  
TXCMD and RXCMD . . . . . . . . . . . . . . . . . . . 22  
TXCMD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
RXCMD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
Linestate encoding. . . . . . . . . . . . . . . . . . . . . 23  
VBUS valid comparator . . . . . . . . . . . . . . . . . . . 8  
VBUS state encoding. . . . . . . . . . . . . . . . . . . . 24  
Session valid comparator . . . . . . . . . . . . . . . . . 9  
Session end comparator. . . . . . . . . . . . . . . . . . 9  
SRP charge and discharge resistors . . . . . . . . 9  
Band gap reference voltage . . . . . . . . . . . . . . . 9  
Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 9  
Detailed description of pins . . . . . . . . . . . . . . . 9  
DATA[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
VCC(I/O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
RREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
DP and DM . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
Using and selecting the VBUS state encoding. 25  
RxEvent encoding . . . . . . . . . . . . . . . . . . . . . 26  
Register read and write operations . . . . . . . . 27  
USB reset and high-speed detection  
handshake (chirp) . . . . . . . . . . . . . . . . . . . . . 27  
USB packet transmit and receive . . . . . . . . . . 30  
USB packet timing . . . . . . . . . . . . . . . . . . . . . 30  
ISP1505 pipeline delays. . . . . . . . . . . . . . . . . 30  
Allowed link decision time . . . . . . . . . . . . . . . 30  
Preamble . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32  
USB suspend and resume . . . . . . . . . . . . . . . 33  
Full-speed and low-speed host-initiated  
9.7  
9.8  
9.8.1  
9.8.1.1  
9.8.1.2  
9.9  
9.10  
9.10.1  
V
V
CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
BUS/FAULT . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
7.10.6.1 VBUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
7.10.6.2 FAULT (external overcurrent or  
suspend and resume . . . . . . . . . . . . . . . . . . . 33  
High-speed suspend and resume . . . . . . . . . 34  
Remote wake-up . . . . . . . . . . . . . . . . . . . . . . 37  
No automatic SYNC and EOP generation  
(optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38  
On-The-Go operations . . . . . . . . . . . . . . . . . . 39  
OTG comparators. . . . . . . . . . . . . . . . . . . . . . 40  
Pull-up and pull-down resistors . . . . . . . . . . . 40  
9.10.2  
9.10.3  
9.11  
fault detector) . . . . . . . . . . . . . . . . . . . . . . . . . 10  
7.10.7  
7.10.8  
7.10.9  
REG3V3 and REG1V8 . . . . . . . . . . . . . . . . . . 11  
XTAL1 and XTAL2. . . . . . . . . . . . . . . . . . . . . . 11  
RESET_N/PSW_N . . . . . . . . . . . . . . . . . . . . . 11  
9.12  
7.10.9.1 RESET_N . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
7.10.9.2 PSW_N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
7.10.10 DIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
7.10.11 STP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
7.10.12 NXT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
7.10.13 CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
7.10.14 GND (die pad). . . . . . . . . . . . . . . . . . . . . . . . . 12  
9.12.1  
9.12.2  
9.12.3  
9.13  
9.14  
9.15  
VBUS charge and discharge resistors . . . . . . . 40  
Serial modes . . . . . . . . . . . . . . . . . . . . . . . . . 40  
Aborting transfers. . . . . . . . . . . . . . . . . . . . . . 42  
Avoiding contention on the ULPI data bus . . . 42  
10  
10.1  
10.1.1  
Register map . . . . . . . . . . . . . . . . . . . . . . . . . . 43  
Immediate register set . . . . . . . . . . . . . . . . . . 44  
Vendor ID and Product ID registers . . . . . . . . 44  
8
8.1  
8.1.1  
8.1.2  
8.1.3  
Modes of operation . . . . . . . . . . . . . . . . . . . . . 13  
ULPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Synchronous mode. . . . . . . . . . . . . . . . . . . . . 13  
Low-power mode . . . . . . . . . . . . . . . . . . . . . . 14  
6-pin full-speed or low-speed serial mode . . . 15  
10.1.1.1 Vendor ID Low register. . . . . . . . . . . . . . . . . . 44  
10.1.1.2 Vendor ID High register . . . . . . . . . . . . . . . . . 44  
10.1.1.3 Product ID Low register . . . . . . . . . . . . . . . . . 44  
continued >>  
ISP1505A_ISP1505C_3  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 03 — 26 August 2008  
74 of 75  
ISP1505A; ISP1505C  
NXP Semiconductors  
ULPI HS USB host and peripheral transceiver  
10.1.1.4 Product ID High register . . . . . . . . . . . . . . . . . 44  
10.1.2  
10.1.3  
10.1.4  
10.1.5  
10.1.6  
10.1.7  
10.1.8  
10.1.9  
Function Control register . . . . . . . . . . . . . . . . 44  
Interface Control register . . . . . . . . . . . . . . . . 45  
OTG Control register . . . . . . . . . . . . . . . . . . . 46  
USB Interrupt Enable Rising Edge register . . 47  
USB Interrupt Enable Falling Edge register . . 48  
USB Interrupt Status register . . . . . . . . . . . . . 48  
USB Interrupt Latch register. . . . . . . . . . . . . . 49  
Debug register . . . . . . . . . . . . . . . . . . . . . . . . 49  
10.1.10 Scratch register. . . . . . . . . . . . . . . . . . . . . . . . 50  
10.1.11 Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50  
10.1.12 Access extended register set . . . . . . . . . . . . . 50  
10.1.13 Vendor-specific registers . . . . . . . . . . . . . . . . 50  
10.1.14 Power Control register . . . . . . . . . . . . . . . . . . 50  
10.2  
Extended register set . . . . . . . . . . . . . . . . . . . 51  
11  
11.1  
11.2  
ElectroStatic Discharge (ESD) . . . . . . . . . . . . 52  
ESD protection . . . . . . . . . . . . . . . . . . . . . . . . 52  
ESD test conditions . . . . . . . . . . . . . . . . . . . . 52  
12  
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 53  
Recommended operating conditions. . . . . . . 53  
Static characteristics. . . . . . . . . . . . . . . . . . . . 54  
Dynamic characteristics . . . . . . . . . . . . . . . . . 58  
ULPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 61  
Application information. . . . . . . . . . . . . . . . . . 62  
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 65  
13  
14  
15  
15.1  
16  
17  
18  
Soldering of SMD packages . . . . . . . . . . . . . . 66  
Introduction to soldering . . . . . . . . . . . . . . . . . 66  
Wave and reflow soldering . . . . . . . . . . . . . . . 66  
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 66  
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 67  
18.1  
18.2  
18.3  
18.4  
19  
20  
21  
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 68  
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69  
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 70  
22  
Legal information. . . . . . . . . . . . . . . . . . . . . . . 71  
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 71  
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 71  
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 71  
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 71  
22.1  
22.2  
22.3  
22.4  
23  
24  
25  
26  
Contact information. . . . . . . . . . . . . . . . . . . . . 71  
Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72  
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73  
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74  
Please be aware that important notices concerning this document and the product(s)  
described herein, have been included in section ‘Legal information’.  
© NXP B.V. 2008.  
All rights reserved.  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
Date of release: 26 August 2008  
Document identifier: ISP1505A_ISP1505C_3  

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NXP

ISP1506ABS,518

IC LINE TRANSCEIVER, PQCC24, 4 X 4 MM, 0.85 MM HEIGHT, ROHS COMPLIANT, PLASTIC, MO-220, SOT-616-1, HVQFN-24, Line Driver or Receiver
NXP

ISP1506ABS,551

IC LINE TRANSCEIVER, PQCC24, 4 X 4 MM, 0.85 MM HEIGHT, ROHS COMPLIANT, PLASTIC, MO-220, SOT-616-1, HVQFN-24, Line Driver or Receiver
NXP

ISP1506A_08

ULPI Hi-Speed USB OTG transceiver
NXP

ISP1506B

ULPI Hi-Speed Universal Serial Bus On-The-Go transceiver
NXP

ISP1506BBS

ULPI Hi-Speed Universal Serial Bus On-The-Go transceiver
NXP

ISP1506BBS,518

IC LINE TRANSCEIVER, PQCC24, 4 X 4 MM, 0.85 MM HEIGHT, ROHS COMPLIANT, PLASTIC, MO-220, SOT-616-1, HVQFN-24, Line Driver or Receiver
NXP

ISP1506BBS,557

LINE TRANSCEIVER, PQCC24, 4 X 4 MM, 0.85 MM HEIGHT, ROHS COMPLIANT, PLASTIC, MO-220, SOT-616-1, HVQFN-24
NXP

ISP1506C

ISP1506C
NXP

ISP1507A

ULPI Hi-Speed Universal Serial Bus On-The-Go transceiver
NXP