ISP1761ET,551_技术文档

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ISP1761

Hi-Speed Universal Serial Bus On-The-Go controller

Rev. 05 — 13 March 2008

Product data sheet

1. General description

The ISP1761 is a single-chip Hi-Speed Universal Serial Bus (USB) On-The-Go (OTG)

Controller integrated with advanced NXP slave host controller and the NXP ISP1582

peripheral controller.

The Hi-Speed USB host controller and peripheral controller comply to Ref. 1 “Universal

Serial Bus Speciﬁcation Rev. 2.0” and support data transfer speeds of up to 480 Mbit/s.

The Enhanced Host Controller Interface (EHCI) core implemented in the host controller is

adapted from Ref. 2 “Enhanced Host Controller Interface Speciﬁcation for Universal Serial

Bus Rev. 1.0”. The OTG controller adheres to Ref. 3 “On-The-Go Supplement to the USB

Speciﬁcation Rev. 1.3”.

The ISP1761 has three USB ports. Port 1 can be conﬁgured to function as a downstream

port, an upstream port or an OTG port; ports 2 and 3 are always conﬁgured as

downstream ports. The OTG port can switch its role from host to peripheral, and

peripheral to host. The OTG port can become a host through the Host Negotiation

Protocol (HNP) as speciﬁed in the OTG supplement.

2. Features

I Compliant with Ref. 1 “Universal Serial Bus Speciﬁcation Rev. 2.0”; supporting data

transfer at high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s)

I Integrated Transaction Translator (TT) for Original USB (full-speed and low-speed)

peripheral support

I Three USB ports that support three operational modes:

N Mode 1: Port 1 is an OTG controller port, and ports 2 and 3 are host controller

ports

N Mode 2: Ports 1, 2 and 3 are host controller ports

N Mode 3: Port 1 is a peripheral controller port, and ports 2 and 3 are host controller

ports

I Supports OTG Host Negotiation Protocol (HNP) and Session Request Protocol (SRP)

I Multitasking support with virtual segmentation feature (up to four banks)

I High-speed memory controller (variable latency and SRAM external interface)

I Directly addressable memory architecture

I Generic processor interface to most CPUs, such as Hitachi SH-3 and SH-4, NXP XA,

Intel StrongARM, NEC and Toshiba MIPS, Freescale DragonBall and PowerPC

Reduced Instruction Set Computer (RISC) processors

I Conﬁgurable 32-bit and 16-bit external memory data bus

I Supports Programmed I/O (PIO) and Direct Memory Access (DMA)

I Slave DMA implementation on CPU interface to reduce the host system’s CPU load

ISP1761

NXP Semiconductors

Hi-Speed USB OTG controller

I Separate IRQ, DREQ and DACK lines for the host controller and the peripheral

controller

I Integrated multi-conﬁguration FIFO

I Double-buffering scheme increases throughput and facilitates real-time data transfer

I Integrated Phase-Locked Loop (PLL) with external 12 MHz crystal for low EMI

I Tolerant I/O for low voltage CPU interface (1.65 V to 3.3 V)

I 3.3 V-to-5.0 V external power supply input

I Integrated 5.0 V-to-1.8 V or 3.3 V-to-1.8 V voltage regulator (internal 1.8 V for

low-power core)

I Internal power-on reset or low-voltage reset and block-dedicated software reset

I Supports suspend and remote wake-up

I Built-in overcurrent circuitry (analog overcurrent protection)

I Hybrid-power mode: V_CC(5V0)(can be switched off), V_CC(I/O)(permanent)

I Target total current consumption:

N Normal operation; one port in high-speed active: I_CC< 100 mA when the internal

charge pump is not used

N Suspend mode: I_CC(susp)< 150 µA at ambient temperature of +25 °C

I Available in LQFP128 and TFBGA128 packages

I Host controller-speciﬁc features

N High performance USB host with integrated Hi-Speed USB transceivers; supports

high-speed, full-speed and low-speed

N EHCI core is adapted from Ref. 2 “Enhanced Host Controller Interface

Speciﬁcation for Universal Serial Bus Rev. 1.0”

N Conﬁgurable power management

N Integrated TT for Original USB peripheral support on all three ports

N Integrated 64 kB high-speed memory (internally organized as 8 k × 64 bit)

N Additional 2.5 kB separate memory for TT

N Individual or global overcurrent protection with built-in sense circuits

N Built-in overcurrent circuitry (digital or analog overcurrent protection)

I OTG controller-speciﬁc features

N OTG transceiver: fully integrated; adheres to Ref. 3 “On-The-Go Supplement to the

USB Speciﬁcation Rev. 1.3”

N Supports HNP and SRP for OTG dual-role devices

N HNP: status and control registers for software implementation

N SRP: status and control registers for software implementation

N Programmable timers with high resolution (0.01 ms to 80 ms) for HNP and SRP

N Supports external source of V_BUS

I Peripheral controller-speciﬁc features

N High-performance USB peripheral controller with integrated Serial Interface Engine

(SIE), FIFO memory and transceiver

N Complies with Ref. 1 “Universal Serial Bus Speciﬁcation Rev. 2.0” and most device

class speciﬁcations

N Supports auto Hi-Speed USB mode discovery and Original USB fallback

capabilities

N Supports high-speed and full-speed on the peripheral controller

N Bus-powered or self-powered capability with suspend mode

ISP1761_5

Product data sheet

Rev. 05 — 13 March 2008

2 of 163

ISP1761

NXP Semiconductors

Hi-Speed USB OTG controller

N Slave DMA, fully autonomous and supports multiple conﬁgurations

N Seven IN endpoints, seven OUT endpoints and one ﬁxed control IN and OUT

endpoint

N Integrated 8 kB memory

N Software-controllable connection to the USB bus, SoftConnect

3. Applications

The ISP1761 can be used to implement a dual-role USB device in any application, USB

host or USB peripheral, depending on the cable connection. If the dual-role device is

connected to a typical USB peripheral, it behaves like a typical USB host. The dual-role

device can also be connected to a PC or any other USB host and behave like a typical

USB peripheral.

3.1 Host/peripheral roles

I Mobile phone to/from:

N Mobile phone: exchange contact information

N Digital still camera: e-mail pictures or upload pictures to the web

N MP3 player: upload/download/broadcast music

N Mass storage: upload/download ﬁles

N Scanner: scan business cards

I Digital still camera to/from:

N Digital still camera: exchange pictures

N Mobile phone: e-mail pictures, upload pictures to the web

N Printer: print pictures

N Mass storage: store pictures

I Printer to/from:

N Digital still camera: print pictures

N Scanner: print scanned image

N Mass storage: print ﬁles stored in a device

I MP3 player to/from:

N MP3 player: exchange songs

N Mass storage: upload/download songs

I Oscilloscope to/from:

N Printer: print screen image

I Personal digital assistant to/from:

N Personal digital assistant: exchange ﬁles

N Printer: print ﬁles

N Mobile phone: upload/download ﬁles

N MP3 player: upload/download songs

N Scanner: scan pictures

N Mass storage: upload/download ﬁles

N Global Positioning System (GPS): obtain directions, mapping information

N Digital still camera: upload pictures

N Oscilloscope: conﬁgure oscilloscope

ISP1761_5

Product data sheet

Rev. 05 — 13 March 2008

3 of 163

ISP1761

NXP Semiconductors

Hi-Speed USB OTG controller

4. Ordering information

Table 1.

Ordering information

Type number Package

Name

Description

plastic low proﬁle quad ﬂat package; 128 leads; body 14 × 20 × 1.4 mm

Version

ISP1761BE

ISP1761ET

LQFP128

SOT425-1

TFBGA128 plastic thin ﬁne-pitch ball grid array package; 128 balls; body 9 × 9 × 0.8 mm SOT857-1

ISP1761_5

Product data sheet

Rev. 05 — 13 March 2008

4 of 163

ISP1761

NXP Semiconductors

Hi-Speed USB OTG controller

5. Block diagram

V

CC(I/O)

10, 40, 48, 59, 67,

75, 83, 94, 104, 115

37 to 39, 41 to 43,

45 to 47, 49, 51,

52, 54, 56 to 58,

60 to 62, 64 to 66,

68 to 70, 72 to 74,

76 to 78, 80

11

XTAL1

ISP1761BE

12

PLL

XTAL2

CLKIN

30 MHz

60 MHz

13

SEL16/32

DATA[15:0]/DATA[31:0]

82, 84, 86, 87,

89, 91 to 93,

95 to 98,

HC PTD

MEMORY

(3 kB)

122

119

BUS INTERFACE:

RESET_N

100 to 103, 105

17

HC PAYLOAD

MEMORY

(60 kB)

DC BUFFER

MEMORY

8 KBYTES

GLOBAL CONTROL

AND POWER

MANAGEMENT

MEMORY

MANAGEMENT

UNIT

A[17:1]

106

107

108

111

112

113

114

116

117

HC_SUSPEND/

WAKEUP_N

CS_N

120

RD_N

DC_SUSPEND/

WAKEUP_N

+

WR_N

SLAVE DMA

CONTROLLER

DC_IRQ

HC_IRQ

DC_DREQ

HC_DREQ

HC_DACK

DC_DACK

+

POWER-ON

RESET AND

110

MEMORY ARBITER

AND FIFO

INTERRUPT

CONTROL

BAT_ON_N

V

BAT

ON

5, 50,

85, 118

REGISTERS

SUPPORT

REG1V8

5 V-TO-1.8 V

VOLTAGE

REGULATOR

ADVANCED

PERIPHERAL

CONTROLLER

6, 7

NXP

SLAVE HOST

CONTROLLER

V

CC(5V0)

124

C_B

C_A

TRANSACTION

TRANSLATOR

(TT) AND RAM

125

126

CHARGE

PUMP

5 V-TO-3.3 V

VOLTAGE

REGULATOR

V

CC(C_IN)

9

REG3V3

DIGITAL

OTG CONTROLLER

2

AND ANALOG

OVERCURRENT

PROTECTION

REF5V

ID

DYNAMIC PORT ROUTING AND PORT CONTROL LOGIC

8

3

GND(OSC)

4, 17, 24,

31, 123

HI-SPEED

USB ATX3

HI-SPEED

USB ATX2

HI-SPEED

USB ATX1

GNDA

GNDC

53, 88, 121

14, 36, 44, 55, 63,

71, 79, 90, 99, 109

16 15 20 19 18 21 127 23 22 27 26 25 28 128 30 29 34 33 32 35

1

004aaa450

GNDD

RREF1 DP1

DM1

RREF2 DP2

DM2

RREF3 DP3

DM3

GND GNDA

(RREF1)

OC1_N/

GND GNDA

(RREF2)

OC2_N

GND GNDA

(RREF3)

OC3_N

V

BUS

PSW1_N

PSW2_N

PSW3_N

This ﬁgure shows the LQFP pinout. For the TFBGA ballout, see Table 2.

All ground pins should normally be connected to a common ground plane.

Fig 1. Block diagram

ISP1761_5

Product data sheet

Rev. 05 — 13 March 2008

5 of 163

ISP1761

NXP Semiconductors

Hi-Speed USB OTG controller

6. Pinning information

6.1 Pinning

1

102

ISP1761BE

38

65

004aaa506

Fig 2. Pin conﬁguration (LQFP128); top view

ball A1

index area

2

4

6

8

10 12 14 16

9 11 13 15

1

3

5

7

A

B

C

D

E

F

G

H

J

ISP1761ET

K

L

M

N

P

R

T

004aaa551

Fig 3. Pin conﬁguration (TFBGA128); top view

ISP1761_5

Product data sheet

Rev. 05 — 13 March 2008

6 of 163

ISP1761

NXP Semiconductors

Hi-Speed USB OTG controller

6.2 Pin description

Table 2.

Pin description

Symbol^[1][2]

Type^[3]

Description

LQFP128 TFBGA128

OC3_N

1

C2

AI/I

port 3 analog (5 V input) and digital overcurrent input; if not used,

connect to V_CC(I/O)through a 10 kΩ resistor

input, 5 V tolerant

REF5V

ID

2

3

A2

B2

AI

I

5 V reference input for analog OC detector; connect a 100 nF

decoupling capacitor

ID input to detect the default host or peripheral setting when port 1

is in OTG mode; pull-up to 3.3 V through a 4.7 kΩ resistor

input, 3.3 V tolerant

analog ground

GNDA

4

5

A1

B1

-

REG1V8

P

core power output (1.8 V); internal 1.8 V for the digital core; used for

decoupling; connect a 100 nF capacitor; for details on additional

capacitor placement, see Section 7.7

V_CC(5V0)

6

7

C1

D2

P

input to internal regulators (3.0 V-to-5.5 V); connect a 100 nF

decoupling capacitor; see Section 7.7

input to internal regulators (3.0 V-to-5.5 V); connect a 100 nF

decoupling capacitor; see Section 7.7

GND(OSC)

REG3V3

8

9

E3

D1

-

oscillator ground

P

regulator output (3.3 V); for decoupling only; connect a 100 nF

capacitor and a 4.7 µF-to-10 µF capacitor; see Section 7.7

V_CC(I/O)

XTAL1

10

11

E2

E1

P

digital supply voltage; 1.65 V to 3.6 V; connect a 100 nF decoupling

capacitor; see Section 7.7

AI

12 MHz crystal connection input; connect to ground if an external

clock is used

XTAL2

12

13

14

15

16

F2

F1

G3

G2

G1

AO

12 MHz crystal connection output

CLKIN

I

12 MHz oscillator or clock input; when not in use, connect to V_CC(I/O)

GNDD

-

digital ground

GND(RREF1)

RREF1

-

RREF1 ground

AI

reference resistor connection; connect a 12 kΩ ± 1 % resistor

between this pin and the RREF1 ground

GNDA^[4]

DM1

17

18

19

20

21

H2

H1

J3

J2

J1

-

analog ground

AI/O

-

downstream data minus port 1

analog ground

GNDA

DP1

AI/O

OD

downstream data plus port 1

power switch port 1, active LOW

output pad, push-pull open-drain, 8 mA output drive, 5 V tolerant

RREF2 ground

PSW1_N

GND(RREF2)

RREF2

22

23

K2

K1

-

AI

reference resistor connection; connect a 12 kΩ ± 1 % resistor

between this pin and the RREF2 ground

GNDA^[5]

DM2

24

25

26

27

L3

L1

L2

M2

-

analog ground

AI/O

-

downstream data minus port 2

analog ground

GNDA

DP2

AI/O

downstream data plus port 2

ISP1761_5

Product data sheet

Rev. 05 — 13 March 2008

7 of 163

ISP1761

NXP Semiconductors

Hi-Speed USB OTG controller

Table 2.

Pin description …continued

Symbol^[1][2]

Type^[3]

Description

LQFP128 TFBGA128

PSW2_N

28

M1

OD

power switch port 2, active LOW

output pad, push-pull open-drain, 8 mA output drive, 5 V tolerant

RREF3 ground

GND(RREF3)

RREF3

29

30

N2

N1

-

AI

reference resistor connection; connect a 12 kΩ ± 1 % resistor

between this pin and the RREF3 ground

GNDA^[6]

DM3

31

32

33

34

35

P2

P1

R2

R1

T1

-

analog ground

AI/O

-

downstream data minus port 3

analog ground

GNDA

DP3

AI/O

OD

downstream data plus port 3

power switch port 3, active LOW

output pad, push-pull open-drain, 8 mA output drive, 5 V tolerant

digital ground

PSW3_N

GNDD

DATA0

36

37

T2

R3

-

I/O

data bit 0 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

DATA1

DATA2

38

39

T3

R4

I/O

data bit 1 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

data bit 2 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

V_CC(I/O)

DATA3

40

41

T4

P5

P

digital supply voltage; 1.65 V to 3.6 V; connect a 100 nF decoupling

capacitor; see Section 7.7

I/O

data bit 3 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

DATA4

DATA5

42

43

T5

R5

I/O

data bit 4 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

data bit 5 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

GNDD

DATA6

44

45

T6

R6

-

digital ground

I/O

data bit 6 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

DATA7

DATA8

V_CC(I/O)

46

47

48

P7

T7

R7

I/O

P

data bit 7 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

data bit 8 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

digital supply voltage; 1.65 V to 3.6 V; connect a 100 nF decoupling

capacitor; see Section 7.7

ISP1761_5

Product data sheet

Rev. 05 — 13 March 2008

8 of 163

ISP1761

NXP Semiconductors

Hi-Speed USB OTG controller

Table 2.

Pin description …continued

Symbol^[1][2]

Type^[3]

Description

LQFP128 TFBGA128

DATA9

49

T8

I/O

data bit 9 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

REG1V8

DATA10

50

51

R8

P9

P

core power output (1.8 V); internal 1.8 V for the digital core; used for

decoupling; connect a 100 nF capacitor; for details on additional

capacitor placement, see Section 7.7

I/O

data bit 10 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

DATA11

52

T9

I/O

data bit 11 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

GNDC

53

54

R9

-

core ground

DATA12

T10

I/O

data bit 12 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

GNDD

55

56

R10

P11

-

digital ground

DATA13

I/O

data bit 13 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

DATA14

DATA15

57

58

T11

R11

I/O

data bit 14 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

data bit 15 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

V_CC(I/O)

DATA16

59

60

T12

R12

P

digital supply voltage; 1.65 V to 3.6 V; connect a 100 nF decoupling

capacitor; see Section 7.7

I/O

data bit 16 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

DATA17

DATA18

61

62

T13

R13

I/O

data bit 17 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

data bit 18 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

GNDD

63

64

R14

T14

-

digital ground

DATA19

I/O

data bit 19 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

DATA20

65

T15

I/O

data bit 20 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

ISP1761_5

Product data sheet

Rev. 05 — 13 March 2008

9 of 163

ISP1761

NXP Semiconductors

Hi-Speed USB OTG controller

Table 2.

Pin description …continued

Symbol^[1][2]

Type^[3]

Description

LQFP128 TFBGA128

DATA21

66

R15

I/O

data bit 21 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

V_CC(I/O)

DATA22

67

68

P15

T16

P

digital supply voltage; 1.65 V to 3.6 V; connect a 100 nF decoupling

capacitor; see Section 7.7

I/O

data bit 22 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

DATA23

DATA24

69

70

R16

P16

I/O

data bit 23 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

data bit 24 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

GNDD

71

72

N16

N15

-

digital ground

DATA25

I/O

data bit 25 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

DATA26

DATA27

73

74

M15

M16

I/O

data bit 26 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

data bit 27 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

V_CC(I/O)

DATA28

75

76

M14

L16

P

digital supply voltage; 1.65 V to 3.6 V; connect a 100 nF decoupling

capacitor; see Section 7.7

I/O

data bit 28 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

DATA29

DATA30

77

78

L15

K16

I/O

data bit 29 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

data bit 30 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

GNDD

79

80

K15

K14

-

digital ground

DATA31

I/O

data bit 31 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

TEST

A1

81

82

J16

-

I

connect to ground

address pin 1

H16

input, 3.3 V tolerant

V_CC(I/O)

83

J15

P

digital supply voltage; 1.65 V to 3.6 V; connect a 100 nF decoupling

capacitor; see Section 7.7

ISP1761_5

Product data sheet

Rev. 05 — 13 March 2008

10 of 163

ISP1761

NXP Semiconductors

Hi-Speed USB OTG controller

Table 2.

Pin description …continued

Symbol^[1][2]

Type^[3]

Description

LQFP128 TFBGA128

A2

84

H15

I

address pin 2

input, 3.3 V tolerant

REG1V8

85

G16

P

core power output (1.8 V); internal 1.8 V for the digital core; used for

decoupling; connect a 100 nF capacitor and a 4.7 µF-to-10 µF

capacitor; see Section 7.7

A3

A4

86

87

H14

F16

I

address pin 3

input, 3.3 V tolerant

address pin 4

input, 3.3 V tolerant

core ground

GNDC

A5

88

89

G15

F15

-

I

address pin 5

input, 3.3 V tolerant

digital ground

GNDD

A6

90

91

E16

F14

-

I

address pin 6

input, 3.3 V tolerant

address pin 7

A7

A8

92

93

E15

D16

I

input, 3.3 V tolerant

address pin 8

input, 3.3 V tolerant

V_CC(I/O)

A9

94

95

D15

C16

P

I

digital supply voltage; 1.65 V to 3.6 V; connect a 100 nF decoupling

capacitor; see Section 7.7

address pin 9

input, 3.3 V tolerant

address pin 10

A10

A11

A12

96

97

98

C15

B16

B15

I

input, 3.3 V tolerant

address pin 11

input, 3.3 V tolerant

address pin 12

input, 3.3 V tolerant

digital ground

GNDD

A13

99

A16

A15

-

I

100

address pin 13

input, 3.3 V tolerant

address pin 14

A14

A15

A16

101

102

103

B14

A14

A13

I

input, 3.3 V tolerant

address pin 15

input, 3.3 V tolerant

address pin 16

input, 3.3 V tolerant

V_CC(I/O)

A17

104

105

B13

C12

P

I

digital voltage; 1.65 V to 3.6 V; connect a 100 nF decoupling

capacitor; see Section 7.7

address pin 17

input, 3.3 V tolerant

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Table 2.

Pin description …continued

Symbol^[1][2]

Type^[3]

Description

LQFP128 TFBGA128

CS_N

106

A12

I

chip select assertion indicates the ISP1761 being accessed; active

LOW

input, 3.3 V tolerant

read enable; active LOW

input, 3.3 V tolerant

write enable; active LOW

input, 3.3 V tolerant

digital ground

RD_N

WR_N

107

108

B12

B11

I

GNDD

109

110

A11

C10

-

BAT_ON_N

OD

to indicate the presence of a minimum 3.3 V on pins 6 and 7

(open-drain); connect to V_CC(I/O)through a 10 kΩ pull-up resistor

output pad, push-pull open-drain, 8 mA output drive, 5 V tolerant

peripheral controller interrupt signal

output 4 mA drive, 3.3 V tolerant

DC_IRQ

111

112

113

114

A10

B10

A9

O

HC_IRQ

host controller interrupt signal

output 4 mA drive, 3.3 V tolerant

DC_DREQ

HC_DREQ

DMA controller request for the peripheral controller

output 4 mA drive, 3.3 V tolerant

B9

DMA controller request for host controller

output 4 mA drive, 3.3 V tolerant

V_CC(I/O)

115

116

C8

A8

P

I

digital voltage; 1.65 V to 3.6 V; connect a 100 nF decoupling

capacitor; see Section 7.7

HC_DACK

host controller DMA request acknowledgment; when not in use,

connect to V_CC(I/O)through a 10 kΩ pull-up resistor

input, 3.3 V tolerant

DC_DACK

REG1V8

117

118

B8

I

peripheral controller DMA request acknowledgment; when not in

use, connect to V_CC(I/O)through a 10 kΩ pull-up resistor

input, 3.3 V tolerant

B7

A7

P

core power output (1.8 V); internal 1.8 V for the digital core; used for

decoupling; connect a 100 nF capacitor; for details on additional

capacitor placement, see Section 7.7

HC_SUSPEND 119

/WAKEUP_N

I/OD

host controller suspend and wake-up; 3-state suspend output

(active LOW) and wake-up input circuits are connected together

• HIGH = output is 3-state; the ISP1761 is in suspend mode

• LOW = output is LOW; the ISP1761 is not in suspend mode

connect to V_CC(I/O)through an external 10 kΩ pull-up resistor

output pad, open-drain, 4 mA output drive, 3.3 V tolerant

DC_SUSPEND 120

/WAKEUP_N

C6

A6

I/OD

peripheral controller suspend and wake-up; 3-state suspend output

(active LOW) and wake-up input circuits are connected together

• HIGH = output is 3-state; the ISP1761 is in suspend mode

• LOW = output is LOW; the ISP1761 is not in suspend mode

connect to V_CC(I/O)through an external 10 kΩ pull-up resistor

output pad, open-drain, 4 mA output drive, 3.3 V tolerant

core ground

GNDC

121

-

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Hi-Speed USB OTG controller

Table 2.

Pin description …continued

Symbol^[1][2]

Type^[3]

Description

LQFP128 TFBGA128

RESET_N

122

B6

I

external power-up reset; active LOW; when reset is asserted, it is

expected that bus signals are idle, that is, not toggling

input, 3.3 V tolerant

Remark: During reset, ensure that all the input pins to the ISP1761

are not toggling and are in their inactive states.

GNDA

C_B

123

124

B5

A5

-

analog ground

AI/O

charge pump capacitor input; connect a 220 nF capacitor between

this pin and pin 125

C_A

125

B4

AI/O

P

charge pump capacitor input; connect a 220 nF capacitor between

this pin and pin 124

V_{CC(C_IN)}

126

127

A4

B3

charge pump input; connect to 3.3 V

OC1_N/V_BUS

(AI/O)(I) This pin has multiple functions:

• Input: Port 1 OC1_N detection when port 1 is conﬁgured for

host functionality and an external power switch is used; if not

used, connect to V_CC(I/O)through a 10 kΩ resistor; the 10 kΩ

resistor is usually required by the open-drain output of the

power-switch ﬂag pin

• Output: V_BUSout when internal charge pump is used and port 1

is conﬁgured for the OTG functionality; maximum 50 mA

current capability; the overcurrent protection in this case is

ensured by the internal charge pump current limitation; only for

port 1

• Input: V_BUSinput detection when port 1 is deﬁned for the

peripheral functionality

5 V tolerant

OC2_N

128

A3

AI/I

port 2 analog (5 V input) and digital overcurrent input; if not used,

connect to V_CC(I/O)through a 10 kΩ resistor

input, 5 V tolerant

[1] Symbol names ending with underscore N, for example, NAME_N, represent active LOW signals.

[2] All ground pins should normally be connected to a common ground plane.

[3] I = input only; O = output only; I/O = digital input/output; OD = open-drain output; AI/O = analog input/output; AI = analog input; P =

power; (AI/O)(I) = analog input/output digital input; AI/I = analog input digital input.

[4] For port 1.

[5] For port 2.

[6] For port 3.

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7. Functional description

7.1 ISP1761 internal architecture: advanced NXP slave host controller

and hub

The EHCI block and the Hi-Speed USB hub block are the main components of the

advanced NXP slave host controller.

The EHCI is the latest generation design, with improved data bandwidth. The EHCI in the

ISP1761 is adapted from Ref. 2 “Enhanced Host Controller Interface Speciﬁcation for

Universal Serial Bus Rev. 1.0”.

The internal Hi-Speed USB hub block replaces the companion host controller block used

in the original architecture of a Peripheral Component Interconnect (PCI) Hi-Speed USB

host controller to handle full-speed and low-speed modes. The hardware architecture in

the ISP1761 is simpliﬁed to help reduce cost and development time, by eliminating the

additional work involved in implementing the OHCI software required to support full-speed

and low-speed modes.

Figure 4 shows the internal architecture of the ISP1761. The ISP1761 implements an

EHCI that has an internal port, the root hub port (not available externally), on which the

internal hub is connected. The three external ports are always routed to the internal hub.

The internal hub is a Hi-Speed USB hub including the TT.

Remark: The root hub must be enabled and the internal hub must be enumerated.

Enumerate the internal hub as if it is externally connected. For details, refer to Ref. 5

“Interfacing the ISP176x to the Intel PXA25x processor (AN10037)”.

At the host controller reset and initialization, the internal root hub port will be polled until a

new connection is detected, showing the connection of the internal hub.

The internal Hi-Speed USB hub is enumerated using a sequence similar to a standard

Hi-Speed USB hub enumeration sequence, and the polling on the root hub is stopped

because the internal Hi-Speed USB hub will never be disconnected. When enumerated,

the internal hub will report the three externally available ports.

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EHCI

ROOT HUB

PORTSC1

ENUMERATION

AND POLLING USING

ACTUAL PTDs

INTERNAL HUB (TT)

PORT2

PORT1

PORT3

EXTERNAL

PORTS

004aaa513

Fig 4. Internal hub

7.1.1 Internal clock scheme and port selection

Figure 5 shows the internal clock scheme of the ISP1761. The ISP1761 has three ports.

DIGITAL

CORE

host clock:

48 MHz,

30 MHz,

60 MHz

PORT 2

HOST

ATX

CORE

peripheral clock:

48 MHz,

30 MHz,

60 MHz

PERIPHERAL

PORT 1

ATX

CORE

XOSC

004aaa538

PORT 3

ATX

PLL 12 MHz IN

Fig 5. ISP1761 clock scheme

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Port 2 does not need to be enabled using software if only port 1 or port 3 is used. No port

needs to be disabled by external pull-up resistors, if not used. The DP and DM of the

unused ports need not be externally pulled HIGH because there are internal pull-down

resistors on each port that are enabled by default.

Table 3 lists the various port connection scenarios.

Table 3.

Port connection scenarios

Port conﬁguration Port 1

Port 2

DP and DM are routed to USB DP and DM are not connected

connector (left open)

DP and DM are not connected DP and DM are routed to USB

(left open) connector

DP and DM are not connected DP and DM are not connected

(left open) (left open)

DP and DM are routed to USB DP and DM are routed to USB

connector connector

DP and DM are not connected DP and DM are routed to USB

(left open) connector

DP and DM are routed to USB DP and DM are not connected

connector (left open)

Port 3

One port (port 1)

One port (port 2)

One port (port 3)

DP and DM are not connected

(left open)

DP and DM are not connected

(left open)

DP and DM are routed to USB

connector

Two ports (ports 1

and 2)

DP and DM are not connected

(left open)

Two ports (ports 2

and 3)

DP and DM are routed to USB

connector

Two ports (ports 1

and 3)

DP and DM are routed to USB

connector

Three ports (ports 1, DP and DM are routed to USB DP and DM are routed to USB

DP and DM are routed to USB

connector

2 and 3)

connector

7.2 Host controller buffer memory block

7.2.1 General considerations

The internal addressable host controller buffer memory is 63 kB. The 63 kB effective

memory size is the result of subtracting the size of the registers (1 kB) from the total

addressable memory space deﬁned by the ISP1761 (64 kB). This is an optimized value to

achieve the highest performance with minimal cost.

The ISP1761 is a slave host controller. This means that it does not need access to the

local bus of the system to transfer data from the system memory to the ISP1761 internal

memory, unlike the case of the original PCI Hi-Speed USB host controllers. Therefore,

correct data must be transferred to both the Philips Transfer Descriptor (PTD) area and

the payload area by PIO (using CPU access) or programmed DMA.

The ‘slave-host’ architecture ensures better compatibility with most of the processors

present in the market today because not all processors allow a ‘bus-master’ on the local

bus. It also allows better load balancing of the processor’s local bus because only the

internal bus arbiter of the processor controls the transfer of data dedicated to USB. This

prevents the local bus from being busy when other more important transfers may be in the

queue; and therefore achieving a ‘linear’ system data ﬂow that has less impact on other

processes running at the same time.

The considerations mentioned are also the main reason for implementing the pre-fetching

technique, instead of using a READY signal. The resulting architecture avoids ‘freezing’ of

the local bus, by asserting READY, enhancing the ISP1761 memory access time, and

avoiding introduction of programmed additional wait states. For details, see Section 7.3.

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The total amount of memory allocated to the payload determines the maximum transfer

size speciﬁed by a PTD, a larger internal memory size results in less CPU interruption for

transfer programming. This means less time spent in context switching, resulting in better

CPU usage.

A larger buffer also implies that a larger amount of data can be transferred. This transfer,

however, can be done over a longer period of time, to maintain the overall system

performance. Each transfer of the USB data on the USB bus can span up to a few

milliseconds before requiring further CPU intervention for data movement.

The internal architecture of the ISP1761 allows a ﬂexible deﬁnition of the memory buffer

for optimization of the data transfer on the CPU extension bus and the USB. It is possible

to implement different data transfer schemes, depending on the number and type of USB

devices present. For example: push-pull; data can be written to half of the memory while

data in the other half is being accessed by the host controller and sent on the USB bus.

This is useful especially when a high-bandwidth ‘continuous or periodic’ data ﬂow is

required.

Through an analysis of the hardware and software environment regarding the usual data

ﬂow and performance requirements of most embedded systems, NXP has determined the

optimal size for the internal buffer as approximately 64 kB.

7.2.2 Structure of the ISP1761 host controller memory

The 63 kB of internal memory consists of the PTD area and the payload area.

The PTD memory zone is divided into three dedicated areas for each main type of USB

transfer: Isochronous (ISO), Interrupt (INT) and Asynchronous Transfer List (ATL). As

shown in Table 4, the PTD areas for ISO, INT and ATL are grouped at the beginning of the

memory, occupying the address range 0400h to 0FFFh, following the register address

space. The payload or data area occupies the next memory address range 1000h to

FFFFh, meaning that 60 kB of memory are allocated for the payload data.

A maximum of 32 PTD areas and their allocated payload areas can be deﬁned for each

type of transfer. The structure of a PTD is similar for every transfer type and consists of

eight Double Words (DWs) that must be correctly programmed for a correct USB data

transfer. The reserved bits of a PTD must be set to logic 0. A detailed description of the

PTD structure can be found in Section 8.5.

The transfer size speciﬁed by the PTD determines the contiguous USB data transfer that

can be performed without any CPU intervention. The respective payload memory area

must be equal to the transfer size deﬁned. The maximum transfer size is ﬂexible and can

be optimized, depending on the number and nature of USB devices or PTDs deﬁned and

their respective MaxPacketSize.

The CPU will program the DMA to transfer the necessary data in the payload memory.

The next CPU intervention will be required only when the current transfer is completed

and DMA programming is necessary to transfer the next data payload. This is normally

signaled by the IRQ that is generated by the ISP1761 on completing the current PTD,

meaning all the data in the payload area was sent on the USB bus. The external IRQ

signal is asserted according to the settings in the IRQ Mask OR or IRQ MASK AND

registers, see Section 8.4.

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The RAM is structured in blocks of PTDs and payloads so that while the USB is executing

on an active transfer-based PTD, the processor can simultaneously ﬁll up another block

area in the RAM. A PTD and its payload can then be updated on-the-ﬂy without stopping

or delaying any other USB transaction or corrupting the RAM data.

Some of the design features are:

• The address range of the internal RAM buffer is from 0400h to FFFFh.

• The internal memory contains isochronous, interrupt and asynchronous PTDs, and

respective deﬁned payloads.

• All accesses to the internal memory are double-word aligned.

• Internal memory address range calculation:

Memory address = (CPU address − 0400h) (shift right >> 3). Base address is 0400h.

Table 4.

Memory address

Memory map

ISO

CPU address

Memory address

0000h to 007Fh

0080h to 00FFh

0100h to 017Fh

0180h to 1FFFh

0400h to 07FFh

0800h to 0BFFh

0C00h to 0FFFh

1000h to FFFFh

INT

ATL

Payload

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Hi-Speed USB OTG controller

PTD1

PTD2

63 kB

ISOCHRONOUS

PTD32

PTD1

PTD2

INTERRUPT

PTD32

PTD1

PTD2

REGISTERS

ASYNC

D[15:0]/D[31:0]

A[17:1]

PTD32

PAYLOAD

USB HIGH-SPEED

CS_N

RD_N

USB BUS

HOST AND

TRANSACTION

TRANSLATOR

(FULL-SPEED

MEMORY MAPPED

INPUT/OUTPUT,

MEMORY

MANAGEMENT

UNIT,

PAYLOAD

WR_N

AND LOW-SPEED)

MICRO-

PROCESSOR

SLAVE DMA

CONTROLLER

AND

INTERRUPT

CONTROL

DC_IRQ

HC_IRQ

PAYLOAD

address

data (64 bits)

240 MB/s

DC_DREQ

HC_DREQ

HC_DACK

DC_DACK

ARBITER

control signals

004aaa568

Fig 6. Memory segmentation and access block diagram

Both the CPU interface logic and the USB host controller require access to the internal

ISP1761 RAM at the same time. The internal arbiter controls these accesses to the

internal memory, organized internally on a 64-bit data bus width, allowing a maximum

bandwidth of 240 MB/s. This bandwidth avoids any bottleneck on accesses both from the

CPU interface and the internal USB host controller.

7.3 Accessing the ISP1761 host controller memory: PIO and DMA

The CPU interface of the ISP1761 can be conﬁgured for a 16-bit or 32-bit data bus width.

When the ISP1761 is conﬁgured for a 16-bit data bus width, the upper unused 16 data

lines must be pulled up to V_CC(I/O). This can be achieved by connecting DATA[31:16] lines

together to a single 10 kΩ pull-up resistor. The 16-bit or 32-bit data bus width

conﬁguration is done by programming bit 8 of the HW Mode Control register. This will

determine the register and memory access types in both PIO and DMA modes to all

internal blocks: host controller, peripheral controller and OTG controller. All accesses must

be word-aligned for 16-bit mode and double-word aligned for 32-bit mode, where one

word = 16 bits. When accessing the host controller registers in 16-bit mode, the register

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access must always be completed using two subsequent accesses. In the case of a DMA

transfer, the 16-bit or 32-bit data bus width conﬁguration will determine the number of

bursts that will complete a certain transfer length.

In PIO mode, CS_N, WR_N and RD_N are used to access registers and memory. In DMA

mode, the data validation is performed by DACK, instead of CS_N, together with the

WR_N and RD_N signals. The DREQ signal will always be asserted as soon as the

ISP1761 DMA is enabled.

7.3.1 PIO mode access, memory read cycle

The following method is implemented to reduce the read access timing in a memory read:

• The Memory register contains the starting address and the bank selection to read

from the memory. Before every new read cycle of the same or different banks, an

appropriate value is written to this register.

• Once a value is written to this register, the address is stored in the FIFO of that bank

and is then used to pre-fetch data for the memory read of that bank.

For every subsequent read operation executed at a contiguous address, the address

pointer corresponding to that bank is automatically incremented to pre-fetch the next

data to be sent to the CPU.

Memory read accesses for multiple banks can be interleaved. In this case, the FIFO

block handles the multiplexing of appropriate data to the CPU.

• The address written to the Memory register is incremented and used to successively

pre-fetch data from the memory irrespective of the value on the address bus for each

bank, until a new value for a bank is written to the Memory register. This is valid only

when the address refers to the memory space (400h to FFFFh).

For example, consider the following sequence of operations:

– Write the starting (read) address 4000h and bank1 = 01 to the Memory register.

When RD_N is asserted for three cycles with A[17:16] = 01, the returned data

corresponds to addresses 4000h, 4004h and 4008h.

Remark: Once 4000h is written to the Memory register for bank1, the bank select

value determines the successive incremental addresses used to fetch data. That

is, the fetching of data is independent of the address on A[15:0] lines.

– Write the starting (read) address 4100h and bank2 = 10 to the Memory register.

When RD_N is asserted for four cycles with A[17:16] = 10, the returned data

corresponds to addresses 4100h, 4104h, 4108h and 410Ch.

Consequently, the RD_N assertion with A[17:16] = 01 will return data from 400Ch

because the bank1 read stopped there in the previous cycle. Also, RD_N

assertions with A[17:16] = 10 will now return data from 4110h because the bank2

read stopped there in the previous cycle.

7.3.2 PIO mode access, memory write cycle

The PIO memory write access is similar to a normal memory access. It is not necessary

to set the pre-fetching address before a write cycle to memory.

The ISP1761 internal write address will not automatically be incremented during

consecutive write accesses, unlike in a series of ISP1761 memory read cycles. The

memory write address must be incremented before every access.

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7.3.3 PIO mode access, register read cycle

The PIO register read access is similar to a general register access. It is not necessary to

set a pre-fetching address before a register read.

The ISP1761 register read address will not automatically be incremented during

consecutive read accesses, unlike in a series of ISP1761 memory read cycles. The

ISP1761 register read address must be correctly speciﬁed before every access.

7.3.4 PIO mode access, register write cycle

The PIO register write access is similar to a general register access. It is not necessary to

set a pre-fetching address before a register write.

The ISP1761 register write address will not automatically be incremented during

consecutive write accesses, unlike in a series of ISP1761 memory read cycles. The

ISP1761 register write address must be correctly speciﬁed before every access.

7.3.5 DMA mode, read and write operations

The internal ISP1761 host controller DMA is a slave DMA. The host system processor or

DMA must ensure the data transfer to or from the ISP1761 memory.

The ISP1761 DMA supports a DMA burst length of 1, 4, 8 and 16 cycles for both the 16-bit

and 32-bit data bus width. DREQ will be asserted at the beginning of the ﬁrst burst of a

DMA transfer and will be de-asserted on the last cycle, RD_N or WR_N active pulse, of

that burst. It will be reasserted shortly after the DACK de-assertion, as long as the DMA

transfer counter was not reached. DREQ will be de-asserted on the last cycle when the

DMA transfer counter is reached and will not be reasserted until the DMA reprogramming

is performed. Both the DREQ and DACK signals are programmable as active LOW or

active HIGH, according to system requirements.

The DMA start address must be initialized in the respective register, and the subsequent

transfers will automatically increment the internal ISP1761 memory address. A register or

memory access or access to other system memory can occur in between DMA bursts,

whenever the bus is released because DACK is de-asserted, without affecting the DMA

transfer counter or the current address.

Any memory area can be accessed by the system’s DMA at any starting address because

there are no predeﬁned memory blocks. The DMA transfer must start on a word or double

word address, depending on whether the data bus width is set to 16-bit or 32-bit. DMA is

the most efﬁcient method to initialize the payload area, to reduce the CPU usage and

overall system loading.

The ISP1761 does not implement EOT to signal the end of a DMA transfer. If

programmed, an interrupt may be generated by the ISP1761 at the end of the DMA

transfer.

The slave DMA of the ISP1761 will issue a DREQ to the DMA controller of the system to

indicate that it is programmed for transfer and data is ready. The system DMA controller

may also start a transfer without the need of the DREQ, if the ISP1761 memory is

available for the data transfer and the ISP1761 DMA programming is completed.

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It is also possible that the system’s DMA will perform a memory-to-memory type of

transfer between the system memory and the ISP1761 memory. The ISP1761 will be

accessed in PIO mode. Consequently, memory read operations must be preceded by

initializing the Memory register (address 033Ch), as described in Section 7.3.1. No IRQ

will be generated by the ISP1761 on completing the DMA transfer but an internal

processor interrupt may be generated to signal that the DMA transfer is completed. This is

mainly useful in implementing the double-buffering scheme for data transfer to optimize

the USB bandwidth.

The ISP1761 DMA programming involves:

• Set the active levels of signals DREQ and DACK in the HW Mode Control register.

• The DMA Start Address register contains the ﬁrst memory address at which the data

transfer will start. It must be word-aligned in 16-bit data bus mode and double word

aligned in 32-bit data bus mode.

• The programming of the HcDMAConﬁguration register speciﬁes:

– The type of transfer that will be performed: read or write.

– The burst size, expressed in bytes, is speciﬁed, regardless of the data bus width.

For the same burst size, a double number of cycles will be generated in 16-bit

mode data bus width as compared to 32-bit mode.

– The transfer length, expressed in number of bytes, deﬁnes the number of bursts.

The DREQ will be de-asserted and asserted to generate the next burst, as long as

there are bytes to be transferred. At the end of a transfer, the DREQ will be

de-asserted and an IRQ can be generated if DMAEOTINT (bit 3 in the HcInterrupt

register) is set. The maximum DMA transfer size is equal to the maximum memory

size. The transfer size can be an odd or even number of bytes, as required. If the

transfer size is an odd number of bytes, the number of bytes transferred by the

system’s DMA is equal to the next multiple of two for the 16-bit data bus width or

four for the 32-bit data bus width. For a write operation, however, only the speciﬁed

odd number of bytes in the ISP1761 memory will be affected.

– Enable ENABLE_DMA (bit 1) of the HcDMAConﬁguration register to determine the

assertion of DREQ immediately after setting the bit.

After programming the preceding parameters, the system’s DMA may be enabled, waiting

for the DREQ to start the transfer or immediate transfer may be started.

The programming of the system’s DMA must match the programming of the ISP1761

DMA parameters. Only one DMA transfer may take place at a time. A PIO mode data

transfer may occur simultaneously with a DMA data transfer, in the same or a different

memory area.

7.4 Interrupts

The ISP1761 will assert the IRQ according to the source or event in the HcInterrupt

register. The main steps to enable the IRQ assertion are:

1. Set GLOBAL_INTR_EN (bit 0) in the HW Mode Control register.

2. Deﬁne the IRQ active as level or edge in INTR_LEVEL (bit 1) of the HW Mode Control

register.

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3. Deﬁne the IRQ polarity as active LOW or active HIGH in INTR_POL (bit 2) of the HW

Mode Control register. These settings must match IRQ settings of the host processor.

By default, interrupt is level-triggered and active LOW.

4. Program the individual Interrupt Enable bits in the HcInterruptEnable register. The

software will need to clear the Interrupt Status bits in the HcInterrupt register before

enabling individual interrupt enable bits.

Additional IRQ characteristics can be adjusted in the Edge Interrupt Count register, as

necessary, applicable only when IRQ is set to be edge-active; a pulse of a deﬁned width is

generated every time IRQ is active.

Bits 15 to 0 of the Edge Interrupt Count register deﬁne the IRQ pulse width. The maximum

pulse width that can be programmed is FFFFh, corresponding to a 1 ms pulse width. This

setting is necessary for certain processors that may require a different minimum IRQ

pulse width from the default value. The default IRQ pulse width set at power-on is

approximately 500 ns.

Bits 31 to 24 of the Edge Interrupt Count register deﬁne the minimum interval between two

interrupts to avoid frequent interrupts to the CPU. The default value of 00h attributed to

these bits determines the normal IRQ generation, without any delay. When a delay is

programmed and the IRQ becomes active after the respective delay, several IRQ events

may have already occurred.

All the interrupt events are represented by the respective bits allocated in the HcInterrupt

register. There is no mechanism to show the order or the moment occurrence of an

interrupt.

The asserted bits in the HcInterrupt register can be cleared by writing back the same

value to the HcInterrupt register. This means that writing logic 1 to each of the set bits will

reset that corresponding bits to the initial inactive state.

The IRQ generation rules that apply according to the preceding settings are:

• If an event of interrupt occurs but the respective bit in the Interrupt Enable register is

not set, then the respective HcInterrupt register bit is set but the interrupt signal is not

asserted.

An interrupt will be generated when interrupt is enabled and the respective bit in the

Interrupt Enable register is set.

• For a level trigger, an interrupt signal remains asserted until the processor clears the

HcInterrupt register by writing logic 1 to clear the HcInterrupt register bits that are set.

• If an interrupt is made edge-sensitive and is asserted, writing to clear the HcInterrupt

register will not have any effect because the interrupt will be asserted for a prescribed

amount of clock cycles.

• The clock stopping mechanism does not affect the generation of an interrupt. This is

useful during the suspend and resume cycles, when an interrupt is generated to

signal a wake-up event.

The IRQ generation can also be conditioned by programming the IRQ Mask OR and IRQ

Mask AND registers.

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With the help of the IRQ Mask AND and IRQ Mask OR registers for each type of transfer

(ISO, INT and bulk), software can determine which PTDs get priority and an interrupt will

be generated when the AND or OR conditions are met. The PTDs that are set will wait

until the respective bits of the remaining PTDs are set and then all PTDs generate an

interrupt request to the CPU together.

The registers deﬁnition shows that the AND or OR conditions are applicable to the same

category of PTDs: ISO, INT and ATL.

When an IRQ is generated, the PTD Done Map registers and the respective V bits will

show which PTDs were completed.

The rules that apply to the IRQ Mask AND or IRQ Mask OR settings are:

• The OR mask has a higher priority over the AND mask. An IRQ is generated if bit n of

done map is set and the corresponding bit n of the OR mask register is set.

• If the OR mask for any done bit is not set, then the AND mask comes into picture. An

IRQ is generated if all the corresponding done bits of the AND Mask register are set.

For example: If bits 2, 4 and 10 are set in the AND Mask register, an IRQ is generated

only if bits 2, 4, 10 of the done map are set.

• If using the IRQ interval setting for the bulk PTD, an interrupt will only occur at the

regular time interval as programmed in the ATL Done Timeout register. Even if an

interrupt event occurs before the time-out of the register, no IRQ will be generated

until the time is up.

For an example on using the IRQ Mask AND or IRQ Mask OR registers, without the ATL

Done Timeout register, see Table 5.

The AND function: activate the IRQ only if PTDs 1, 2 and 4 are done.

The OR function: if any of the PTDs 7, 8 or 9 are done, an IRQ for each of the PTD will be

raised.

Table 5.

Using the IRQ Mask AND or IRQ Mask OR registers

PTD

1

AND register OR register

Time

1 ms

-

PTD done

IRQ

1

0

1

0

1

-

2

-

3

-

4

3 ms

-

1

-

active because of AND

5

-

6

-

7

5 ms

6 ms

7 ms

1

active because of OR

8

9

7.5 Phase-Locked Loop (PLL) clock multiplier

The internal PLL requires a 12 MHz input, which can be a 12 MHz crystal or a 12 MHz

clock already existing in the system with a precision better than 50 ppm. This allows the

use of a low-cost 12 MHz crystal that also minimizes ElectroMagnetic Interference (EMI).

When an external crystal is used, make sure the CLKIN pin is connected to V_CC(I/O)

.

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The PLL block generates all the main internal clocks required for normal functionality of

various blocks: 30 MHz, 48 MHz and 60 MHz.

No external components are required for the PLL operation.

7.6 Power management

The ISP1761 implements a ﬂexible power management scheme, allowing various power

saving stages.

The usual powering scheme implies programming EHCI registers and the internal

Hi-Speed USB (USB 2.0) hub in the same way it is done in a PCI Hi-Speed USB host

controller with a Hi-Speed USB hub attached.

While the ISP1761 is set in suspend mode, main internal clocks will be stopped to ensure

minimum power consumption. An internal LazyClock of 100 kHz ± 40 % will continue

running. This allows initiating a resume on one of these events:

• External USB device connect or disconnect

• CS_N signal asserted when the ISP1761 is accessed

• Driving the HC_SUSPEND/WAKEUP_N pin to a LOW logical level will wake up the

host controller, and driving the DC_SUSPEND/WAKEUP_N pin to a LOW logical level

will wake up the peripheral controller

The HC_SUSPEND/WAKEUP_N and DC_SUSPEND/WAKEUP_N pins are bidirectional.

These pins must be connected to the GPIO pins of a processor.

The awake state can be veriﬁed by reading the LOW level of this pin. If the level is HIGH,

it means that the ISP1761 is in the suspend state.

HC_SUSPEND/WAKEUP_N and DC_SUSPEND/WAKEUP_N require pull-up resistors

because in the ISP1761 suspended state these pins become 3-state and can be pulled

down, driving them externally by switching the processor’s GPIO lines to output mode to

generate the ISP1761 wake-up.

The HC_SUSPEND/WAKEUP_N and DC_SUSPEND/WAKEUP_N pins are 3-state

output and also input to the internal wake-up logic.

When in suspend mode, the ISP1761 internal wake-up circuitry will sense the status of

the HC_SUSPEND/WAKEUP_N and DC_SUSPEND/WAKEUP_N pins:

• If the pins remain pulled-up, no wake-up will be generated because a HIGH is sensed

by the internal wake-up circuit.

• If the pins are externally pulled LOW, for example, by the GPIO lines or just a test by

jumpers, the input to the wake-up circuitry becomes LOW and the wake-up is

internally initiated.

The resume state has a clock-off count timer deﬁned by bits 31 to 16 of the Power Down

Control register. The default value of this timer is 10 ms, meaning that the resume state

will be maintained for 10 ms. If during this time, the RUN/STOP bit in the USBCMD

register is set to logic 1, the host controller will go into a permanent resume; the normal

functional state. If the RUN/STOP bit is not set during the time determined by the clock-off

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count, the ISP1761 will switch back to suspend mode after the speciﬁed time. The

maximum delay that can be programmed in the clock-off count ﬁeld is approximately

500 ms.

Additionally, the Power Down Control register allows ISP1761 internal blocks to disable for

lower power consumption as deﬁned in Section 8.3.11.

The lowest suspend current, I_CC(susp), that can be achieved is approximately 150 µA at

ambient temperature of +25 °C. The suspend current will increase with the increase in

temperature, with approximately 300 µA at 40 °C and up to a typical 1 mA at 85 °C. The

system is not in suspend mode when its temperature increases above 40 °C. Therefore,

even a 1 mA current consumption by the ISP1761 in suspend mode can be considered

negligible. In normal environmental conditions, when the system is in suspend mode, the

maximum ISP1761 temperature is approximately 40 °C, determined by the ambient

temperature. Therefore, the ISP1761 maximum suspend current will be below 300 µA. An

alternative solution to achieve a very low suspend current is to completely switch off the

V_CC(5V0)power input by using an external PMOS transistor, controlled by one of the GPIO

pins of the processor. This is possible because the ISP1761 can be used in hybrid mode,

which allows only the V_CC(I/O)powered on to avoid loading of the system bus.

When the ISP1761 power is always on, the time from wake-up to suspend will be

approximately 100 ms.

It is necessary to wait for the CLKREADY interrupt assertion before programming the

ISP1761 because internal clocks are stopped during deep sleep suspend and restarted

after the ﬁrst wake-up event. The occurrence of the CLKREADY interrupt means that

internal clocks are running and the normal functionality is achieved.

It is estimated that the CLKREADY interrupt will be generated less than 100 µs after the

wake-up event, if the power to the ISP1761 was on during suspend.

If the ISP1761 is used in hybrid mode and V_CC(5V0)is off during suspend, a 2 ms reset

pulse is required when the power is switched back on, before the resume programming

sequence starts. This will ensure that the internal clocks are running and all logics reach a

stable initial state.

7.7 Power supply

Figure 7 shows the ISP1761 power supply connection.

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V

3.3 V to 5 V

100 nF

CC(5V0)

CC(I/O)

6, 7

10, 40, 48,

59, 67, 75,

83, 94,

1.65 V to 3.6 V

100 nF

104, 115

REG1V8

85

10 µF

100 nF

ISP1761BE

REG1V8

REG3V3

5, 50, 118

100 nF

9

10 µF

100 nF

V

3.3 V

CC(C_IN)

126

100 nF

004aaa539

This ﬁgure shows the LQFP pinout. For the TFBGA ballout, see Table 2.

A 4.7 µF-to-10 µF electrolytic or tantalum capacitor is required on any one of the pins 5, 50 or 118.

All the electrolytic or tantalum capacitors must be of LOW ESR type (0.2 Ω to 2 Ω).

Fig 7. ISP1761 power supply connection

Figure 8 shows the most commonly used power supply connection.

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ISP1761BE

6, 7, 10, 40,

48, 59, 67,

V

,

CC(5V0) CC(I/O) CC(C_IN)

,

3.3 V

75, 83, 94,

100 nF

104, 115, 126

REG1V8

85

10 µF

100 nF

REG1V8

REG3V3

5, 50, 118

100 nF

9

100 nF

10 µF

004aaa540

This ﬁgure shows the LQFP pinout. For the TFBGA ballout, see Table 2.

A 4.7 µF-to-10 µF electrolytic or tantalum capacitor is required on any one of the pins 5, 50 or 118.

All the electrolytic or tantalum capacitors must be of LOW ESR type (0.2 Ω to 2 Ω).

Fig 8. Most commonly used power supply connection

7.7.1 Hybrid mode

Table 6 shows the description of hybrid mode.

Table 6.

Voltage

V_CC(5V0)

V_CC(I/O)

Hybrid mode

Status

off

on

In hybrid mode (see Figure 9), V_CC(5V0)can be switched off using an external PMOS

transistor, controlled using one of the GPIO pins of the processor. This helps to reduce the

suspend current, I_CC(I/O), below 100 µA. If the ISP1761 is used in hybrid mode and

V_CC(5V0)is off during suspend, a 2 ms reset pulse is required when power is switched

back on, before the resume programming sequence starts.

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controlled by the CPU

V

3.3 V to 5 V

100 nF

CC(5V0)

CC(I/O)

6, 7

10, 40, 48,

59, 67, 75,

83, 94,

1.65 V to 3.6 V

100 nF

104, 115

REG1V8

85

10 µF

100 nF

ISP1761BE

REG1V8

REG3V3

5, 50, 118

100 nF

9

100 nF

10 µF

V

3.3 V

CC(C_IN)

126

100 nF

004aaa676

This ﬁgure shows the LQFP pinout. For the TFBGA ballout, see Table 2.

A 4.7 µF-to-10 µF electrolytic or tantalum capacitor is required on any one of the pins 5, 50 or 118.

All the electrolytic or tantalum capacitors must be of LOW ESR type (0.2 Ω to 2 Ω).

Fig 9. Hybrid mode

Table 7 shows the status of output pins during hybrid mode.

Table 7.

Pins

Pin status during hybrid mode

V_CC(I/O)

on

V_CC(5V0)

Status

normal

high-Z

DATA[31:0], A[17:1], TEST, HC_IRQ, DC_IRQ,

HC_DREQ, DC_DREQ, HC_DACK, DC_DACK,

HC_SUSPEND/WAKEUP_N,

on

off

X

on

off

undeﬁned

DC_SUSPEND/WAKEUP_N

CS_N, RESET_N, RD_N, WR_N

on

off

X

input

undeﬁned

7.8 Overcurrent detection

The ISP1761 can implement a digital or analog overcurrent detection scheme. Bit 15 of

the HW Mode Control register can be programmed to select the analog or digital

overcurrent detection. An analog overcurrent detection circuit is integrated on-chip. The

main features of this circuit are self reporting, automatic resetting, low-trip time and low

cost. This circuit offers an easy solution at no extra hardware cost on the board. The port

power will automatically be disabled by the ISP1761 on an overcurrent event occurrence,

by de-asserting the PSWn_N signal without any software intervention.

When using the integrated analog overcurrent detection, the range of the overcurrent

detection voltage for the ISP1761 is 45 mV to 100 mV. Calculation of the external

components must be based on the 45 mV value, with the actual overcurrent detection

threshold usually positioned in the middle of the interval.

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For an overcurrent limit of 500 mA per port, a PMOS transistor with R_DSONof

approximately 100 mΩ is required. If a PMOS transistor with a lower R_DSONis used, the

analog overcurrent detection can be adjusted using a series resistor; see Figure 10.

∆V_PMOS= ∆V_OC(TRIP)= ∆V_{TRIP(intrinsic)}− (I_OC(nom)× R_td), where:

∆V_PMOS= voltage drop on PMOS

I_OC(nom)= 1 µA

5 V

I

OC

(1)

R

td

PSWn_N

OCn_N

REF5V

ISP1761

004aaa662

(1) R_tdis optional.

Fig 10. Adjusting analog overcurrent detection limit (optional)

The digital overcurrent scheme requires using an external power switch with integrated

overcurrent detection, such as LM3526, MIC2526 (2 ports) or LM3544 (4 ports). These

devices are controlled by PSWn_N signals corresponding to each port. In the case of

overcurrent occurrence, these devices will assert OCn_N signals. On OCn_N assertion,

the ISP1761 cuts off the port power by de-asserting PSWn_N. The external integrated

power switch will also automatically cut off the port power in the case of an overcurrent

event, by implementing a thermal shutdown. An internal delay ﬁlter will prevent false

overcurrent reporting because of in-rush currents when plugging a USB device. Because

of this internal delay, as soon as OCn_N is asserted, PSWn_N will switch off the external

PMOS in less than 15 ms.

Remark: If port 1 is used in OTG mode or as a dual-role device, the analog overcurrent

detection must be used, same on all three ports, because the same bit (bit 15 of the HW

Mode Control register) determines the overcurrent detection type.

7.9 Power-On Reset (POR)

When V_CC(I/O)is directly connected to the RESET_N pin, the internal POR pulse width,

t_PORP, will typically be 800 ns. The pulse is started when V_CC(5V0)rises above V_TRIPof

1.2 V.

To give a better view of the functionality, Figure 11 shows a possible curve of V_CC(5V0)with

dips at t2 to t3 and t4 to t5. If the dip at t4 to t5 is too short, that is, < 11 µs, the internal

POR pulse will not react and will remain LOW. The internal POR starts with a 1 at t0. At t1,

the detector will see the passing of the trip level and a delay element will add another

t_PORPbefore it drops to 0.

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The internal POR pulse will be generated whenever V_CC(5V0)drops below V_TRIPfor more

than 11 µs.

V

CC(5V0)

TRIP

t4

t0

t1

t

t3

t5

t2

(1)

PORP

t

PORP

004aaa584

(1) PORP = Power-On Reset Pulse.

Fig 11. Internal power-on reset timing

The recommended RESET input pulse length at power-on must be at least 2 ms to ensure

that internal clocks are stable.

The RESET_N pin can be either connected to V_CC(I/O), using the internal POR circuit or

externally controlled by the microcontroller, ASIC, and so on. Figure 12 shows the

availability of the clock with respect to the external POR.

RESET_N

EXTERNAL CLOCK

004aaa583

A

Stable external clock is available at A.

Fig 12. Clock with respect to the external power-on reset

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8. Host controller

Table 8 shows the bit description of the registers.

• All registers range from 0000h to 03FFh. These registers can be read or written as

double word, that is 32-bit data.

• Operational registers range from 0000h to 01FFh. Host controller-speciﬁc and OTG

controller-speciﬁc registers range from 0300h to 03FFh. Peripheral controller-speciﬁc

registers range from 0200h to 02FFh.

• 17 address lines (15/14 addresses, necessary to address up to 64 kB range on a

16-bit/32-bit data bus conﬁguration + additional 2 addresses for bank select/virtual

segmentation for memory address access time improvement). A0 is not deﬁned

because 8-bit access is not implemented.

Table 8.

Address

Host controller-speciﬁc register overview

Register Reset value

References

EHCI capability registers

0000h

0002h

0004h

0008h

CAPLENGTH

HCIVERSION

HCSPARAMS

HCCPARAMS

20h

Section 8.1.1 on page 33

Section 8.1.2 on page 33

Section 8.1.3 on page 33

Section 8.1.4 on page 34

0100h

0000 0011h

0000 0086h

EHCI operational registers

0020h

0024h

0028h

002Ch

0060h

0064h

0130h

0134h

0138h

0140h

0144h

0148h

0150h

0154h

0158h

USBCMD

0008 0B00h

0000 0000h

0000 2000h

0000 0000h

FFFF FFFFh

0000 0000h

FFFF FFFFh

0000 0000h

FFFF FFFFh

0000 0000h

Section 8.2.1 on page 35

Section 8.2.2 on page 36

Section 8.2.3 on page 37

Section 8.2.4 on page 37

Section 8.2.5 on page 38

Section 8.2.6 on page 39

Section 8.2.7 on page 40

Section 8.2.8 on page 41

Section 8.2.9 on page 41

Section 8.2.10 on page 41

Section 8.2.11 on page 41

Section 8.2.12 on page 42

Section 8.2.13 on page 42

Section 8.2.14 on page 42

Section 8.2.15 on page 43

USBSTS

USBINTR

FRINDEX

CONFIGFLAG

PORTSC1

ISO PTD Done Map

ISO PTD Skip Map

ISO PTD Last PTD

INT PTD Done Map

INT PTD Skip Map

INT PTD Last PTD

ATL PTD Done Map

ATL PTD Skip Map

ATL PTD Last PTD

Conﬁguration registers

0300h

0304h

0308h

030Ch

0330h

0334h

0338h

HW Mode Control

0000 0100h

0001 1761h

0000 0000h

Section 8.3.1 on page 43

Section 8.3.2 on page 45

Section 8.3.3 on page 45

Section 8.3.4 on page 45

Section 8.3.5 on page 46

Section 8.3.6 on page 47

Section 8.3.7 on page 48

HcChipID

HcScratch

SW Reset

HcDMAConﬁguration

HcBufferStatus

ATL Done Timeout

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Table 8.

Host controller-speciﬁc register overview …continued

Address

033Ch

0340h

0344h

0354h

Register

Reset value

0000 0000h

0000 000Fh

0000 0000h

03E8 1BA0h

References

Memory

Section 8.3.8 on page 48

Section 8.3.9 on page 49

Section 8.3.10 on page 50

Section 8.3.11 on page 51

Edge Interrupt Count

DMA Start address

Power Down Control

Interrupt registers

0310h

0314h

0318h

031Ch

0320h

0324h

0328h

032Ch

HcInterrupt

0000 0000h

Section 8.4.1 on page 53

Section 8.4.2 on page 55

Section 8.4.3 on page 57

Section 8.4.4 on page 57

Section 8.4.5 on page 57

Section 8.4.6 on page 58

Section 8.4.7 on page 58

Section 8.4.8 on page 58

HcInterruptEnable

ISO IRQ Mask OR

INT IRQ Mask OR

ATL IRQ Mask OR

ISO IRQ Mask AND

INT IRQ Mask AND

ATL IRQ Mask AND

8.1 EHCI capability registers

8.1.1 CAPLENGTH register

The bit description of the Capability Length (CAPLENGTH) register is given in Table 9.

Table 9.

Bit

CAPLENGTH - Capability Length register (address 0000h) bit description

Symbol

Access

Value

Description

7 to 0

CAPLENGTH R

[7:0]

20h

Capability Length: This is used as an offset. It is added to the register

base to ﬁnd the beginning of the operational register space.

8.1.2 HCIVERSION register

Table 10 shows the bit description of the Host Controller Interface Version Number

(HCIVERSION) register.

Table 10. HCIVERSION - Host Controller Interface Version Number register (address 0002h) bit description

Bit Symbol Access Value Description

15 to 0 HCIVERSION R

[15:0]

0100h Host Controller Interface Version Number: It contains a BCD encoding of the

version number of the interface to which the host controller interface conforms.

8.1.3 HCSPARAMS register

The Host Controller Structural Parameters (HCSPARAMS) register is a set of ﬁelds that

are structural parameters. The bit allocation is given in Table 11.

Table 11. HCSPARAMS - Host Controller Structural Parameters register (address 0004h) bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

reserved

0

R

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Bit

23

22

21

20

19

18

17

16

Symbol

DPN[3:0]

reserved

P_INDICAT

OR

Reset

Access

Bit

0

R

0

R

0

R

0

R

0

R

0

R

0

R

9

0

R

8

15

14

13

12

11

10

Symbol

Reset

Access

Bit

N_CC[3:0]

reserved

N_PCC[3:0]

0

R

0

R

6

0

R

5

0

R

0

R

3

0

R

2

0

R

1

0

R

0

7

4

Symbol

Reset

Access

PRR

0

PPC

1

N_PORTS[3:0]

0

1

R

Table 12. HCSPARAMS - Host Controller Structural Parameters register (address 0004h) bit

description

Bit

Symbol

Description^[1]

31 to 24

-

reserved; write logic 0

23 to 20 DPN[3:0]

Debug Port Number: This ﬁeld identiﬁes which of the host controller

ports is the debug port.

19 to 17

16

-

reserved; write logic 0

P_INDICATOR Port Indicators: This bit indicates whether the ports support port

indicator control.

15 to 12 N_CC[3:0]

Number of Companion Controller: This ﬁeld indicates the number

of companion controllers associated with this Hi-Speed USB host

controller.

11 to 8

7

N_PCC[3:0]

PRR

Number of Ports per Companion Controller: This ﬁeld indicates the

number of ports supported per companion host controller.

Port Routing Rules: This ﬁeld indicates the method used to map

ports to the companion controllers.

6 to 5

4

-

reserved; write logic 0

PPC

Port Power Control: This ﬁeld indicates whether the host controller

implementation includes port power control.

3 to 0

N_PORTS[3:0] N_Ports: This ﬁeld speciﬁes the number of physical downstream

ports implemented on this host controller.

[1] For details on register bit description, refer to Ref. 2 “Enhanced Host Controller Interface Speciﬁcation for

Universal Serial Bus Rev. 1.0”.

8.1.4 HCCPARAMS register

The Host Controller Capability Parameters (HCCPARAMS) register is a 4 bytes register,

and the bit allocation is given in Table 13.

Table 13. HCCPARAMS - Host Controller Capability Parameters register (address 0008h) bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

reserved

0

R

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Bit

23

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

reserved

0

R

0

R

0

R

0

R

0

R

0

R

0

R

9

0

R

8

15

14

13

12

11

10

Symbol

Reset

Access

Bit

EECP[7:0]

0

R

7

0

R

6

0

R

5

0

R

4

0

R

3

0

R

0

R

2

ASPC

1

0

Symbol

Reset

Access

IST[3:0]

reserved

PFLF

1

reserved

1

0

R

Table 14. HCCPARAMS - Host Controller Capability Parameters register (address 0008h) bit

description

Bit

Symbol

Description^[1]

31 to 16 -

reserved; write logic 0

15 to 8 EECP[7:0] EHCI Extended Capabilities Pointer: Default = implementation

dependent. This optional ﬁeld indicates the existence of a capabilities list.

7 to 4

IST[3:0]

Isochronous Scheduling Threshold: Default = implementation

dependent. This ﬁeld indicates, relative to the current position of the

executing host controller, where software can reliably update the

isochronous schedule.

3

2

-

reserved; write logic 0

ASPC

Asynchronous Scheduling Park Capability: Default = implementation

dependent. If this bit is set to logic 1, the host controller supports the park

feature for high-speed Transfer Descriptors in the asynchronous schedule.

1

PFLF

Programmable Frame List Flag: Default = implementation dependent. If

this bit is cleared, the system software must use a frame list length of 1024

elements with this host controller.

If PFLF is set, the system software can specify and use a smaller frame

list and conﬁgure the host through the USBCMD register FLS ﬁeld.

0

-

reserved; write logic 0

[1] For details on register bit description, refer to Ref. 2 “Enhanced Host Controller Interface Speciﬁcation for

Universal Serial Bus Rev. 1.0”.

8.2 EHCI operational registers

8.2.1 USBCMD register

The USB Command (USBCMD) register indicates the command to be executed by the

serial host controller. Writing to this register causes a command to be executed. Table 15

shows the USBCMD register bit allocation.

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Hi-Speed USB OTG controller

Table 15. USBCMD - USB Command register (address 0020h) bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

23

R/W

22

R/W

21

R/W

19

R/W

18

R/W

17

R/W

16

20

Symbol

Reset

Access

Bit

reserved^[1]

0

1

0

R/W

9

0

R/W

8

R/W

15

R/W

14

R/W

13

R/W

12

R/W

11

R/W

10

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

7

0

R/W

6

0

R/W

5

0

1

R/W

3

0

R/W

2

1

R/W

0

R/W

4

reserved^[1]

0

1

HCRESET

0

Symbol

Reset

Access

LHCR

0

RS

0

R/W

[1] The reserved bits should always be written with the reset value.

Table 16. USBCMD - USB Command register (address 0020h) bit description

Bit

Symbol

-

Description^[1]

31 to 8

7

reserved

LHCR

Light Host Controller Reset (optional): If implemented, it allows the

driver software to reset the EHCI controller without affecting the state of

the ports or the relationship to the companion host controllers. If not

implemented, a read of this ﬁeld will always return logic 0.

6 to 2

1

-

reserved

HCRESET Host Controller Reset: This control bit is used by the software to reset

the host controller.

0

RS

Run/Stop: 1 = Run, 0 = Stop. When set, the host controller executes the

schedule.

[1] For details on register bit description, refer to Ref. 2 “Enhanced Host Controller Interface Speciﬁcation for

Universal Serial Bus Rev. 1.0”.

8.2.2 USBSTS register

The USB Status (USBSTS) register indicates pending interrupts and various states of the

host controller. The status resulting from a transaction on the serial bus is not indicated in

this register. Software clears the register bits by writing ones to them. The bit allocation is

given in Table 17.

Table 17. USBSTS - USB Status register (address 0024h) bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

reserved^[1]

0

R/W

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Hi-Speed USB OTG controller

Bit

23

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

9

0

R/W

8

R/W

15

R/W

14

R/W

13

R/W

11

R/W

10

12

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

7

0

R/W

6

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

Symbol

Reset

Access

reserved^[1]

FLR

0

PCD

0

reserved^[1]

0

R/W

[1] The reserved bits should always be written with the reset value.

Table 18. USBSTS - USB Status register (address 0024h) bit description

Bit

Symbol Description^[1]

31 to 4

3

-

reserved; write logic 0

FLR

Frame List Rollover: The host controller sets this bit to logic 1 when the

frame list index rolls over from its maximum value to zero.

2

PCD

Port Change Detect: The host controller sets this bit to logic 1 when any port,

where the PO bit is cleared, has a change to a one or a FPR bit changes to a

one as a result of a J-K transition detected on a suspended port.

1 to 0

-

reserved

[1] For details on register bit description, refer to Ref. 2 “Enhanced Host Controller Interface Speciﬁcation for

Universal Serial Bus Rev. 1.0”.

8.2.3 USBINTR register

The USB Interrupt (USBINTR) register is a read or write register located at 0028h. All the

bits in this register are reserved.

8.2.4 FRINDEX register

The Frame Index (FRINDEX) register is used by the host controller to index into the

periodic frame list. The register updates every 125 µs (once each microframe). Bits n to 3

are used to select a particular entry in the periodic frame list during periodic schedule

execution. The number of bits used for the index depends on the size of the frame list as

set by the system software in the FLS (Frame List Size) ﬁeld of the USBCMD register.

This register must be written as a double word. A word-only write (16-bit mode) produces

undeﬁned results. A write to this register while the RS (Run/Stop) bit is set produces

undeﬁned results. Writes to this register also affect the SOF value. The bit allocation is

given in Table 19.

Table 19. FRINDEX - Frame Index register (address: 002Ch) bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

reserved^[1]

0

R/W

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Hi-Speed USB OTG controller

Bit

23

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

9

0

R/W

8

R/W

15

R/W

14

R/W

13

R/W

11

R/W

10

12

Symbol

Reset

Access

Bit

reserved^[1]

FRINDEX[13:8]

0

R/W

7

0

R/W

6

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

Symbol

Reset

Access

FRINDEX[7:0]

0

R/W

[1] The reserved bits should always be written with the reset value.

Table 20. FRINDEX - Frame Index register (address: 002Ch) bit description

Bit

Symbol

Description^[1]

31 to 14 -

reserved

13 to 0 FRINDEX Frame Index: Bits in this register are used for the frame number in the SOF

[13:0]

packet and as the index into the frame list. The value in this register

increments at the end of each time frame. For example, microframe.

[1] For details on register bit description, refer to Ref. 2 “Enhanced Host Controller Interface Speciﬁcation for

Universal Serial Bus Rev. 1.0”.

8.2.5 CONFIGFLAG register

The bit allocation of the Conﬁgure Flag (CONFIGFLAG) register is given in Table 21.

Table 21. CONFIGFLAG - Conﬁgure Flag register (address 0060h) bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

23

R/W

22

R/W

21

R/W

19

R/W

18

R/W

17

R/W

16

20

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

9

0

R/W

8

R/W

15

R/W

14

R/W

13

R/W

12

R/W

11

R/W

10

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

7

0

R/W

6

0

R/W

5

0

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

R/W

4

reserved^[1]

0

Symbol

Reset

Access

CF

0

R/W

[1] The reserved bits should always be written with the reset value.

ISP1761_5

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Hi-Speed USB OTG controller

Table 22. CONFIGFLAG - Conﬁgure Flag register (address 0060h) bit description

Bit

Symbol Description^[1]

31 to 1 - reserved

CF

0

Conﬁgure Flag: The host software sets this bit as the last action when it is

conﬁguring the host controller. This bit controls the default port-routing control

logic.

[1] For details on register bit description, refer to Ref. 2 “Enhanced Host Controller Interface Speciﬁcation for

Universal Serial Bus Rev. 1.0”.

8.2.6 PORTSC1 register

The Port Status and Control (PORTSC) register (bit allocation: Table 23) is in the power

well. It is reset by hardware only when the auxiliary power is initially applied or in response

to a host controller reset. The initial conditions of a port are:

• No peripheral connected

• Port disabled

If the port has power control, software cannot change the state of the port until it sets port

power bits. Software must not attempt to change the state of the port until the power is

stable on the port (maximum delay is 20 ms from the transition).

Table 23. PORTSC1 - Port Status and Control 1 register (address 0064h) bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

23

R/W

22

R/W

21

R/W

19

R/W

18

R/W

17

R/W

16

20

Symbol

Reset

Access

Bit

reserved^[1]

PTC[3:0]

0

R/W

13

0

R/W

9

0

R/W

8

R/W

15

R/W

14

R/W

11

R/W

10

12

Symbol

Reset

Access

Bit

PIC[1:0]

PO

1

PP

LS[1:0]

reserved^[1]

PR

0

R

0

R

0

R/W

3

0

R/W

2

0

R/W

1

R/W

5

R/W

R

7

6

4

reserved^[1]

0

Symbol

Reset

Access

SUSP

0

FPR

0

PED

0

ECSC

0

ECCS

0

R/W

R

[1] The reserved bits should always be written with the reset value.

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Table 24. PORTSC1 - Port Status and Control 1 register (address 0064h) bit description

Bit

Symbol Description^[1]

31 to 20

19 to 16

- reserved

PTC[3:0] Port Test Control: When this ﬁeld is zero, the port is not operating in test

mode. A non-zero value indicates that it is operating in test mode indicated

by the value.

15 to 14

PIC[1:0] Port Indicator Control: Writing to this ﬁeld has no effect if the

P_INDICATOR bit in the HCSPARAMS register is logic 0.

For a description on how these bits are implemented, refer to Ref. 1

“Universal Serial Bus Speciﬁcation Rev. 2.0”.^[2]

13

PO

Port Owner: This bit unconditionally goes to logic 0 when the conﬁgured

bit in the CONFIGFLAG register makes a logic 0 to logic 1 transition. This

bit unconditionally goes to logic 1 whenever the conﬁgured bit is logic 0.

12

PP

Port Power: The function of this bit depends on the value of the PPC (Port

Power Control) ﬁeld in the HCSPARAMS register.

11 to 10

LS[1:0]

Line Status: This ﬁeld reﬂects the current logical levels of the DP (bit 11)

and DM (bit 10) signal lines.

9

8

-

reserved

PR

Port Reset: Logic 1 means the port is in the reset state. Logic 0 means the

port is not in reset.^[2]

7

6

SUSP

FPR

Suspend: Logic 1 means the port is in the suspend state. Logic 0 means

the port is not suspended.^[2]

Force Port Resume: Logic 1 means resume detected or driven on the

port. Logic 0 means no resume (K-state) detected or driven on the port.^[2]

5 to 3

-

reserved

2

1

PED

ECSC

Port Enabled/Disabled: Logic 1 means enable. Logic 0 means disable.^[2]

Connect Status Change: Logic 1 means change in ECCS. Logic 0 means

no change.^[2]

0

ECCS

Current Connect Status: Logic 1 indicates a peripheral is present on the

port. Logic 0 indicates no peripheral is present.^[2]

[1] For details on register bit description, refer to Ref. 2 “Enhanced Host Controller Interface Speciﬁcation for

Universal Serial Bus Rev. 1.0”.

[2] These ﬁelds read logic 0, if the PP (Port Power) bit in register PORTSC 1 is logic 0.

8.2.7 ISO PTD Done Map register

The bit description of the register is given in Table 25.

Table 25. ISO PTD Done Map register (address 0130h) bit description

Bit

Symbol

Access Value

Description

31 to 0 ISO_PTD_DONE

R

0000 0000h ISO PTD Done Map: Done map for each of the 32 PTDs for the ISO

_

transfer

MAP[31:0]

This register represents a direct map of the done status of the 32 PTDs. The bit

corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is

completed. Reading the Done Map register will clear all the bits that are set to logic 1, and

the next reading will reﬂect the updated status of new executed PTDs.

ISP1761_5

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8.2.8 ISO PTD Skip Map register

Table 26 shows the bit description of the register.

Table 26. ISO PTD Skip Map register (address 0134h) bit description

Bit

Symbol

Access Value

Description

31 to 0

ISO_PTD_SKIP R/W

FFFF FFFFh

ISO PTD Skip Map: Skip map for each of the 32 PTDs for the

_

ISO transfer

MAP[31:0]

When a bit in the PTD Skip Map is set to logic 1 that PTD will be skipped although its V bit

may be set. The information in that PTD is not processed. For example, NextPTDPointer

will not affect the order of processing of PTDs. The Skip bit must not normally be set on

the position indicated by NextPTDPointer.

8.2.9 ISO PTD Last PTD register

Table 27 shows the bit description of the ISO PTD Last PTD register.

Table 27. ISO PTD Last PTD register (address 0138h) bit description

Bit

Symbol

Access Value

Description

31 to 0 ISO_PTD_LAST_ R/W

PTD[31:0]

0000 0000h ISO PTD last PTD: Last PTD of the 32 PTDs.

1h — One PTD in ISO

2h — Two PTDs in ISO

4h — Three PTDs in ISO

Once the LastPTD bit corresponding to a PTD is set, this will be the last PTD processed

(checking V = 1) in that PTD category. Subsequently, the process will restart with the ﬁrst

PTD of that group. This is useful to reduce the time in which all the PTDs, the respective

memory space, would be checked, especially if only a few PTDs are deﬁned. The

LastPTD bit must normally be set to a higher position than any other position indicated by

the NextPTDPointer from an active PTD.

8.2.10 INT PTD Done Map register

The bit description of the register is given in Table 28.

Table 28. INT PTD Done Map register (address 0140h) bit description

Bit

Symbol

Access Value

Description

31 to 0 INT_PTD_DONE

R

0000 0000h INT PTD Done Map: Done map for each of the 32 PTDs for the INT

_

transfer

MAP[31:0]

This register represents a direct map of the done status of the 32 PTDs. The bit

corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is

completed. Reading the Done Map register will clear all the bits that are set to logic 1, and

the next reading will reﬂect the updated status of new executed PTDs.

8.2.11 INT PTD Skip Map register

Table 29 shows the bit description of the INT PTD Skip Map register.

ISP1761_5

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Table 29. INT PTD Skip Map register (address 0144h) bit description

Bit

Symbol

Access Value

Description

31 to 0 INT_PTD_SKIP_ R/W

MAP[31:0]

FFFF FFFFh INT PTD Skip Map: Skip map for each of the 32 PTDs for the INT

transfer

When a bit in the PTD Skip map is set to logic 1 that PTD will be skipped although its V bit

may be set. The information in that PTD is not processed. For example, NextPTDPointer

will not affect the order of processing of PTDs. The Skip bit should not normally be set on

the position indicated by NextPTDPointer.

8.2.12 INT PTD Last PTD register

The bit description of the register is given in Table 30.

Table 30. INT PTD Last PTD register (address 0148h) bit description

Bit

Symbol

Access Value

Description

31 to 0 INT_PTD_LAST_ R/W

PTD[31:0]

0000 0000h INT PTD Last PTD: Last PTD of the 32 PTDs.

1h — One PTD in INT

2h — Two PTDs in INT

3h — Three PTDs in INT

Once the LastPTD bit corresponding to a PTD is set, this will be the last PTD processed

(checking V = 1) in that PTD category. Subsequently, the process will restart with the ﬁrst

PTD of that group. This is useful to reduce the time in which all the PTDs, the respective

memory space, would be checked, especially if only a few PTDs are deﬁned. The

LastPTD bit must normally be set to a higher position than any other position indicated by

the NextPTDPointer from an active PTD.

8.2.13 ATL PTD Done Map register

Table 31 shows the bit description of the ATL PTD Done Map register.

Table 31. ATL PTD Done Map register (address 0150h) bit description

Bit

Symbol

Access Value

Description

31 to 0 ATL_PTD_DONE_ R

MAP[31:0]

0000 0000h ATL PTD Done Map: Done map for each of the 32 PTDs for the ATL

transfer

This register represents a direct map of the done status of the 32 PTDs. The bit

corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is

completed. Reading the Done Map register will clear all the bits that are set to logic 1, and

the next reading will reﬂect the updated status of new executed PTDs.

8.2.14 ATL PTD Skip Map register

The bit description of the register is given in Table 32.

Table 32. ATL PTD Skip Map register (address 0154h) bit description

Bit

Symbol

Access Value

Description

31 to 0 ATL_PTD_SKIP_ R/W

MAP[31:0]

FFFF FFFFh ATL PTD Skip Map: Skip map for each of the 32 PTDs for the ATL

transfer

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When a bit in the PTD Skip map is set to logic 1 that PTD will be skipped although its V bit

may be set. The information in that PTD is not processed. For example, NextPTDPointer

will not affect the order of processing of PTDs. The Skip bit should not normally be set on

the position indicated by NextPTDPointer.

8.2.15 ATL PTD Last PTD register

The bit description of the ATL PTD Last PTD register is given in Table 33.

Table 33. ATL PTD Last PTD register (address 0158h) bit description

Bit

Symbol

Access

Value

Description

31 to 0 ATL_PTD_LAST_ R/W

PTD[31:0]

0000 0000h ATL PTD Last PTD: Last PTD of the 32 PTDs.

1h — One PTD in ATL

2h — Two PTDs in ATL

4h — Three PTDs in ATL

Once the LastPTD bit corresponding to a PTD is set, this will be the last PTD processed

(checking V = 1) in that PTD category. Subsequently, the process will restart with the ﬁrst

PTD of that group. This is useful to reduce the time in which all the PTDs, the respective

memory space, would be checked, especially if only a few PTDs are deﬁned. The

LastPTD bit must normally be set to a higher position than any other position indicated by

the NextPTDPointer from an active PTD.

8.3 Conﬁguration registers

8.3.1 HW Mode Control register

Table 34 shows the bit allocation of the register.

Table 34. HW Mode Control - Hardware Mode Control register (address 0300h) bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

ALL_ATX_

RESET

reserved^[1]

Reset

Access

Bit

0

R/W

23

R/W

22

R/W

21

R/W

20

R/W

19

R/W

18

R/W

17

R/W

16

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

0

R/W

11

0

R/W

9

0

R/W

8

R/W

15

R/W

14

R/W

12

R/W

10

13

Symbol

ANA_DIGI_

OC

reserved^[1]

DEV_DMA COMN_IRQ

COMN_

DMA

DATA_BUS

_WIDTH

Reset

Access

Bit

0

R/W

0

R/W

6

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

0

R/W

1

R/W

0

7

2

Symbol

reserved

DACK_

POL

DREQ_

POL

reserved^[1]

INTR_POL

INTR_

LEVEL

GLOBAL_

INTR_EN

Reset

0

Access

R/W

ISP1761_5

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[1] The reserved bits should always be written with the reset value.

Table 35. HW Mode Control - Hardware Mode Control register (address 0300h) bit

description

Bit

Symbol

Description

31

ALL_ATX_RESET

All ATX Reset: For debugging purposes (not used normally).

1 — Enable reset, then write back logic 0

0 — No reset

30 to 16 -

reserved; write logic 0

15

ANA_DIGI_OC

Analog Digital Overcurrent: This bit selects analog or digital

overcurrent detection on pins OC1_N/V_BUS, OC2_N and OC3_N.

0 — Digital overcurrent

1 — Analog overcurrent

14 to 12 -

reserved; write logic 0

11

DEV_DMA

Device DMA: When this bit and bit 9 are set, DC_DREQ and

DC_DACK peripheral signals are selected on the HC_DREQ and

HC_DACK pins.

10

9

COMN_INT

Common IRQ: When this bit is set, DC_IRQ will be generated on

the HC_IRQ pin.

COMN_DMA

Common DMA: When this bit and bit 11 are set, the DC_DREQ

and DC_DACK peripheral signals are routed to the HC_DREQ

and HC_DACK pins.

8

DATA_BUS_WIDTH Data Bus Width:

0 — Deﬁnes a 16-bit data bus width

1 — Sets a 32-bit data bus width

Remark: Setting this bit will affect all the controllers on the chip:

host controller, peripheral controller and OTG controller.

7

6

-

reserved; write logic 0

DACK_POL

DACK Polarity:

1 — Indicates that the DACK input is active HIGH

0 — Indicates active LOW

5

DREQ_POL

DREQ Polarity:

1 — Indicates that the DREQ output is active HIGH

0 — Indicates active LOW

4 to 3

-

reserved; write logic 0

ISP1761_5

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Table 35. HW Mode Control - Hardware Mode Control register (address 0300h) bit

description …continued

Bit

Symbol

Description

2

INTR_POL

Interrupt Polarity:

0 — Active LOW

1 — Active HIGH

1

0

INTR_LEVEL

Interrupt Level:

0 — INT is level triggered.

1 — INT is edge triggered. A pulse of certain width is generated.

GLOBAL_INTR_EN Global Interrupt Enable: This bit must be set to logic 1 to enable

IRQ signal assertion.

0 — IRQ assertion disabled. IRQ will never be asserted,

regardless of other settings or IRQ events.

1 — IRQ assertion enabled. IRQ will be asserted according to the

HcInterruptEnable register, and events setting and occurrence.

8.3.2 HcChipID register

Read this register to get the ID of the ISP1761. This upper word of the register contains

the hardware version number and the lower word contains the chip ID. Table 36 shows the

bit description of the register.

Table 36. HcChipID - Host Controller Chip Identiﬁer register (address 0304h) bit description

Bit

Symbol

Access

Value

Description

31 to 0

CHIPID[31:0]

R

0001 1761h Chip ID: This register represents the hardware version number

(0001h) and the chip ID (1761h) for the host controller.

8.3.3 HcScratch register

This register is for testing and debugging purposes only. The value read back must be the

same as the value that was written. The bit description of this register is given in Table 37.

Table 37. HcScratch - Host Controller Scratch register (address 0308h) bit description

Bit

Symbol

Access

Value

Description

31 to 0

SCRATCH[31:0]

R/W

0000 0000h

Scratch: For testing and debugging purposes

8.3.4 SW Reset register

Table 38 shows the bit allocation of the register.

Table 38. SW Reset - Software Reset register (address 030Ch) bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

23

R/W

22

R/W

21

R/W

19

R/W

18

R/W

17

R/W

16

20

Symbol

Reset

Access

reserved^[1]

0

R/W

ISP1761_5

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Bit

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

7

0

R/W

6

0

R/W

5

0

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

R/W

4

Symbol

reserved^[1]

RESET_

HC

RESET_

ALL

Reset

0

Access

R/W

[1] The reserved bits should always be written with the reset value.

Table 39. SW Reset - Software Reset register (address 030Ch) bit description

Bit

Symbol

Description

31 to 2

1

-

reserved; write logic 0

RESET_HC Reset Host Controller: Reset only host controller-speciﬁc registers

(only registers with address below 300h).

0 — No reset

1 — Enable reset

0

RESET_ALL Reset All: Reset all host controller and CPU interface registers.

0 — No reset

1 — Enable reset

8.3.5 HcDMAConﬁguration register

The bit allocation of the HcDMAConﬁguration register is given in Table 40.

Table 40. HcDMAConﬁguration - Host Controller Direct Memory Access Conﬁguration register (address 0330h) bit

allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

DMA_COUNTER[23:16]

0

R/W

23

R/W

22

R/W

21

R/W

20

R/W

19

R/W

18

R/W

17

R/W

16

Symbol

Reset

Access

Bit

DMA_COUNTER[15:8]

0

R/W

9

0

R/W

8

R/W

15

R/W

14

R/W

13

R/W

12

R/W

11

R/W

10

Symbol

Reset

Access

Bit

DMA_COUNTER[7:0]

0

R/W

7

0

R/W

6

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

Symbol

reserved^[1]

BURST_LEN[1:0]

ENABLE DMA_READ_

_DMA

WRITE_SEL

Reset

0

Access

R/W

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Hi-Speed USB OTG controller

[1] The reserved bits should always be written with the reset value.

Table 41. HcDMAConﬁguration - Host Controller Direct Memory Access Conﬁguration

register (address 0330h) bit description

Bit

Symbol

Description

31 to 8 DMA_COUNTER[23:0] DMA Counter: The number of bytes to be transferred (read or

write).

Remark: Different number of bursts will be generated for the

same transfer length programmed in 16-bit and 32-bit modes

because DMA_COUNTER is in number of bytes.

7 to 4

-

reserved

3 to 2 BURST_LEN[1:0]

DMA Burst Length:

00 — Single DMA burst

01 — 4-cycle DMA burst

10 — 8-cycle DMA burst

11 — 16-cycle DMA burst

1

0

ENABLE_DMA

Enable DMA:

0 — Terminate DMA

1 — Enable DMA

DMA_READ_WRITE_ DMA Read or Write Select: Indicates if the DMA operation is a

SEL

write or read to or from the ISP1761.

0 — DMA write to the ISP1761 internal RAM is set

1 — DMA read from the ISP1761 internal RAM

8.3.6 HcBufferStatus register

The HcBufferStatus register is used to indicate the HC that a particular PTD buffer (that is,

ATL, INT and ISO) contains at least one PTD that must be scheduled. Once software sets

the Buffer Filled bit of a particular transfer in the HcBufferStatus register, the HC will start

traversing through PTD headers that are not marked for skipping and are valid PTDs.

Remark: Software can set these bits during the initialization.

Table 42 shows the bit allocation of the HcBufferStatus register.

Table 42. HcBufferStatus - Host Controller Buffer Status register (address 0334h) bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

23

R/W

22

R/W

21

R/W

19

R/W

18

R/W

17

R/W

16

20

Symbol

Reset

Access

reserved^[1]

0

R/W

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Bit

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

7

0

R/W

6

0

R/W

0

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

R/W

5

4

Symbol

reserved^[1]

ISO_BUF_

FILL

INT_BUF_ ATL_BUF_

FILL

Reset

0

Access

R/W

[1] The reserved bits should always be written with the reset value.

Table 43. HcBufferStatus - Host Controller Buffer Status register (address 0334h) bit

description

Bit

Symbol

Description

31 to 3

2

-

reserved

ISO_BUF_FILL ISO Buffer Filled:

1 — Indicates one of the ISO PTDs is ﬁlled, and the ISO PTD area will

be processed.

0 — Indicates there is no PTD in this area. Therefore, processing of

ISO PTDs will be completely skipped.

1

0

INT_BUF_FILL INT Buffer Filled:

1 — Indicates one of the INT PTDs is ﬁlled, and the INT PTD area will

be processed.

0 — Indicates there is no PTD in this area. Therefore, processing of

INT PTDs will be completely skipped.

ATL_BUF_FILL ATL Buffer Filled:

1 — Indicates one of the ATL PTDs is ﬁlled, and the ATL PTD area will

be processed.

0 — Indicates there is no PTD in this area. Therefore, processing of

ATL PTDs will be completely skipped.

8.3.7 ATL Done Timeout register

The bit description of the ATL Done Timeout register is given in Table 44.

Table 44. ATL Done Timeout register (address 0338h) bit description

Bit

Symbol

Access Value

Description

31 to 0

ATL_DONE_TIME R/W

OUT[31:0]

0000 0000h ATL Done Timeout: This register determines the ATL done

time-out interrupt. This register deﬁnes the time-out in milliseconds

after which the ISP1761 asserts the INT line, if enabled. It is

applicable to ATL done PTDs only.

8.3.8 Memory register

The Memory register contains the base memory read address and the respective bank.

This register needs to be set only before a ﬁrst memory read cycle. Once written, the

address will be latched for the bank and will be incremented for every read of that bank

until a new address for that bank is written to change the address pointer.

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The bit description of the register is given in Table 45.

Table 45. Memory register (address 033Ch) bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

23

R/W

22

R/W

21

R/W

19

R/W

18

R/W

17

R/W

16

20

Symbol

Reset

Access

Bit

reserved^[1]

MEM_BANK_SEL[1:0]

0

R/W

9

0

R/W

8

R/W

15

R/W

14

R/W

13

R/W

12

R/W

11

R/W

10

Symbol

Reset

Access

Bit

START_ADDR_MEM_READ[15:8]

0

R/W

7

0

R/W

6

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

Symbol

Reset

Access

START_ADDR_MEM_READ[7:0]

0

R/W

[1] The reserved bits should always be written with the reset value.

Table 46. Memory register (address 033Ch) bit description

Bit

Symbol

Description

31 to 18 -

reserved

17 to 16 MEM_BANK_

SEL[1:0]

Memory Bank Select: Up to four memory banks can be selected. For

details on internal memory read description, see Section 7.3.1.

Applicable to PIO mode memory read or write data transfers only.

15 to 0 START_ADDR_ Start Address for Memory Read Cycles: The start address for a

MEM_READ

[15:0]

series of memory read cycles at incremental addresses in a

contiguous space. Applicable to PIO mode memory read data

transfers only.

8.3.9 Edge Interrupt Count register

Table 47 shows the bit allocation of the register.

Table 47. Edge Interrupt Count register (address 0340h) bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

MIN_WIDTH[7:0]

0

R/W

23

R/W

22

R/W

21

R/W

20

R/W

19

R/W

18

R/W

17

R/W

16

Symbol

Reset

Access

reserved^[1]

0

R/W

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Bit

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

NO_OF_CLK[15:8]

0

R/W

7

0

R/W

6

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

Symbol

Reset

Access

NO_OF_CLK[7:0]

0

1

R/W

[1] The reserved bits should always be written with the reset value.

Table 48. Edge Interrupt Count register (address 0340h) bit description

Bit

Symbol

Description

31 to 24

MIN_WIDTH[7:0]

Minimum Width: Indicates the minimum width between two edge

interrupts in µSOFs (1 µSOF = 125 µs). This is not valid for level

interrupts. A count of zero means that interrupts occur as and

when an event occurs.

23 to 16

15 to 0

-

reserved

NO_OF_CLK[15:0] Number of Clocks: Count in number of clocks that the edge

interrupt must be kept asserted on the interface. 16 clocks of

60 MHz on POR if this register has a value of 0000h. The default

IRQ pulse width is approximately 500 ns.

8.3.10 DMA Start Address register

This register deﬁnes the start address select for the DMA read and write operations. See

Table 49 for bit allocation.

Table 49. DMA Start Address register (address 0344h) bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved^[1]

0

W

23

W

22

W

21

W

20

W

19

W

18

W

17

W

16

Symbol

Reset

Access

Bit

0

W

9

0

W

8

W

15

W

14

W

13

W

12

W

11

W

10

Symbol

Reset

Access

Bit

START_ADDR_DMA[15:8]

0

W

7

0

W

6

0

W

5

0

W

4

0

W

3

0

W

2

0

W

1

0

W

0

Symbol

Reset

Access

START_ADDR_DMA[7:0]

0

W

[1] The reserved bits should always be written with the reset value.

ISP1761_5

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Table 50. DMA Start Address register (address 0344h) bit description

Bit

Symbol

Description

31 to 16

15 to 0

-

reserved

START_ADDR Start Address for DMA: The start address for DMA read or write

_DMA[15:0] cycles.

8.3.11 Power Down Control register

This register is used to turn off power to internal blocks of the ISP1761 to obtain maximum

power savings. Table 51 shows the bit allocation of the register.

Table 51. Power Down Control register (address 0354h) bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

CLK_OFF_COUNTER[15:8]

0

1

R/W

23

R/W

22

R/W

21

R/W

20

R/W

19

R/W

18

R/W

17

R/W

16

Symbol

Reset

Access

Bit

CLK_OFF_COUNTER[7:0]

1

R/W

1

0

1

0

R/W

9

0

R/W

8

R/W

15

R/W

13

R/W

12

R/W

11

R/W

10

14

Symbol

reserved^[1]

PORT3_

PD

PORT2_

PD

VBATDET_

PWR

reserved^[1]

Reset

Access

Bit

0

R/W

7

0

R/W

6

0

R/W

5

1

R/W

4

1

R/W

3

0

R/W

2

1

R/W

1

R/W

0

Symbol

reserved^[1]

BIASEN

VREG_ON OC3_PWR OC2_PWR OC1_PWR HC_CLK_

EN

Reset

1

0

1

0

Access

R/W

[1] The reserved bits should always be written with the reset value.

ISP1761_5

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Table 52. Power Down Control register (address 0354h) bit description

Bit^[1]

Symbol

Description

31 to 16

CLK_OFF_ Clock Off Counter: Determines the wake-up status duration after any

COUNTER wake-up event before the ISP1761 goes back into suspend mode.

[15:0]

This time-out is applicable only if, during the given interval, the host

controller is not programmed back to normal functionality.

03E8h — The default value. It determines the default wake-up interval

of 10 ms. A value of zero implies that the host controller never wakes

up on any of the events. This may be useful when using the ISP1761

as a peripheral to save power by permanently programming the host

controller in suspend.

FFFFh — The maximum value. It determines a maximum wake-up

time of 500 ms.

The setting of this register is based on the 100 kHz ± 40 % LazyClock

frequency. It is a multiple of 10 µs period.

Remark: In 16-bit mode, the default value is 17E8h. A write operation

to these bits with any value ﬁxes the clock off counter at 1400h. This

value is equivalent to a ﬁxed wake-up time of 50 ms.

15 to 13

12

-

reserved

PORT3_PD Port 3 Pull-Down: Controls port 3 pull-down resistors.

0 — Port 3 internal pull-down resistors are not connected.

1 — Port 3 internal pull-down resistors are connected.

11

10

PORT2_PD Port 2 Pull-Down: Controls port 2 pull-down resistors.

0 — Port 2 internal pull-down resistors are not connected.

1 — Port 2 internal pull-down resistors are connected.

VBATDET_

PWR

V

_BATDetector Powered: Controls the power to the V_BATdetector.

0 — V_BATdetector is powered or enabled in suspend.

1 — V_BATdetector is not powered or disabled in suspend.

9 to 6

5

-

reserved; write reset value

BIASEN

Bias Circuits Powered: Controls the power to internal bias circuits.

0 — Internal bias circuits are not powered in suspend.

1 — Internal bias circuits are powered in suspend.

4

3

VREG_ON

V_REGPowered: Enables or disables the internal 3.3 V and 1.8 V

regulators when the ISP1761 is in suspend.

0 — Internal regulators are normally powered in suspend.

1 — Internal regulators switch to low power mode (in suspend mode).

OC3_PWR OC3_N Powered: Controls the powering of the overcurrent detection

circuitry for port 3.

0 — Overcurrent detection is powered on or enabled during suspend.

1 — Overcurrent detection is powered off or disabled during suspend.

This may be useful when connecting a faulty device while the system

is in standby.

ISP1761_5

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Hi-Speed USB OTG controller

Table 52. Power Down Control register (address 0354h) bit description …continued

Bit^[1]

Symbol

Description

2

OC2_PWR OC2_N Powered: Controls the powering of the overcurrent detection

circuitry for port 2.

0 — Overcurrent detection is powered on or enabled during suspend.

1 — Overcurrent detection is powered off or disabled during suspend.

This may be useful when connecting a faulty device while the system

is in standby.

1

0

OC1_PWR OC1_N Powered: Controls the powering of the overcurrent detection

circuitry for port 1.

0 — Overcurrent detection is powered on or enabled during suspend.

1 — Overcurrent detection is powered off or disabled during suspend.

This may be useful when connecting a faulty device while the system

is in standby.

HC_CLK_

EN

Host Controller Clock Enabled: Controls internal clocks during

suspend.

0 — Clocks are disabled during suspend. This is the default value.

Only the LazyClock of 100 kHz ± 40 % will be left running in suspend if

this bit is logic 0. If clocks are stopped during suspend, CLKREADY

IRQ will be generated when all clocks are running stable.

1 — All clocks are enabled even in suspend.

[1] For a 32-bit operation, the default wake-up counter value is 10 µs. For a 16-bit operation, the wake-up

counter value is 50 ms. In the 16-bit operation, read and write back the same value on initialization.

8.4 Interrupt registers

8.4.1 HcInterrupt register

The bits of this register indicate the interrupt source, deﬁning the events that determined

the INT generation. Clearing the bits that were set because of the events listed is done by

writing back logic 1 to the respective position. All bits must be reset before enabling new

interrupt events. These bits will be set, regardless of the setting of bit GLOBAL_INTR_EN

in the HW Mode Control register. Table 53 shows the bit allocation of the HcInterrupt

register.

Table 53. HcInterrupt - Host Controller Interrupt register (address 0310h) bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

23

R/W

22

R/W

21

R/W

19

R/W

18

R/W

17

R/W

16

20

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

0

R/W

10

0

R/W

9

0

R/W

8

R/W

15

R/W

14

R/W

12

R/W

11

13

Symbol

Reset

Access

reserved^[1]

OTG_IRQ

0

ISO_IRQ

0

ATL_IRQ

0

R/W

ISP1761_5

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Bit

7

6

5

4

3

2

1

0

Symbol

INT_IRQ

CLK

READY

HCSUSP

reserved^[1]DMAEOT

INT

reserved^[1]SOFITLINT reserved^[1]

Reset

0

Access

R/W

[1] The reserved bits should always be written with the reset value.

Table 54. HcInterrupt - Host Controller Interrupt register (address 0310h) bit

description

Bit

31 to 11 -

10 OTG_IRQ

Symbol

Description

reserved; write reset value

OTG_IRQ: Indicates that an OTG event occurred. The IRQ line will be

asserted if the respective enable bit in the HcInterruptEnable register is

set.

0 — No OTG event

1 — OTG event occurred

For details, see Section 7.4.

9

ISO_IRQ

ATL_IRQ

INT_IRQ

CLKREADY

ISO IRQ: Indicates that an ISO PTD was completed, or the PTDs

corresponding to the bits set in the ISO IRQ Mask AND or ISO IRQ

Mask OR register bits combination were completed. The IRQ line will be

asserted if the respective enable bit in the HcInterruptEnable register is

set.

0 — No ISO PTD event occurred

1 — ISO PTD event occurred

For details, see Section 7.4.

8

7

6

ATL IRQ: Indicates that an ATL PTD was completed, or the PTDs

corresponding to the bits set in the ATL IRQ Mask AND or ATL IRQ

Mask OR register bits combination were completed. The IRQ line will be

asserted if the respective enable bit in the HcInterruptEnable register is

set.

0 — No ATL PTD event occurred

1 — ATL PTD event occurred

For details, see Section 7.4.

INT IRQ: Indicates that an INT PTD was completed, or the PTDs

corresponding to the bits set in the INT IRQ Mask AND or INT IRQ

Mask OR register bits combination were completed. The IRQ line will be

asserted if the respective enable bit in the HcInterruptEnable register is

set.

0 — No INT PTD event occurred

1 — INT PTD event occurred

For details, see Section 7.4.

Clock Ready: Indicates that internal clock signals are running stable.

The IRQ line will be asserted if the respective enable bit in the

HcInterruptEnable register is set.

0 — No CLKREADY event has occurred

1 — CLKREADY event occurred

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Table 54. HcInterrupt - Host Controller Interrupt register (address 0310h) bit

description …continued

Bit

Symbol

Description

5

HCSUSP

Host Controller Suspend: Indicates that the host controller has

entered suspend mode. The IRQ line will be asserted if the respective

enable bit in the HcInterruptEnable register is set.

0 — The host controller did not enter suspend mode.

1 — The host controller entered suspend mode.

If the Interrupt Service Routine (ISR) accesses the ISP1761, it will wake

up for the time speciﬁed in bits 31 to 16 of the Power Down Control

register.

4

3

-

reserved; write reset value

DMAEOTINT DMA EOT Interrupt: Indicates the DMA transfer completion. The IRQ

line will be asserted if the respective enable bit in the HcInterruptEnable

register is set.

0 — No DMA transfer is completed

1 — DMA transfer is completed

2

1

-

reserved; write reset value; value is zero just after reset and changes to

one after a short while

SOFITLINT

SOT ITL Interrupt: The IRQ line will be asserted if the respective

enable bit in the HcInterruptEnable register is set.

0 — No SOF event has occurred

1 — An SOF event has occurred

0

-

reserved; write reset value; value is zero just after reset and changes to

one after a short while

8.4.2 HcInterruptEnable register

This register allows enabling or disabling of the IRQ generation because of various events

as described in Table 55.

Table 55. HcInterruptEnable - Host Controller Interrupt Enable register (address 0314h) bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

23

R/W

22

R/W

21

R/W

19

R/W

18

R/W

17

R/W

16

20

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

0

R/W

9

0

R/W

8

R/W

15

R/W

14

R/W

12

R/W

11

R/W

10

13

Symbol

reserved^[1]

OTG_IRQ_ ISO_IRQ_E ATL_IRQ

E

_E

Reset

0

Access

R/W

ISP1761_5

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Bit

7

6

5

4

3

2

1

0

Symbol

INT_IRQ_E CLKREADY HCSUSP_ reserved^[1]DMAEOT

reserved^[1]SOFITLINT reserved^[1]

_E

E

INT _E

Reset

0

Access

R/W

[1] The reserved bits should always be written with the reset value.

Table 56. HcInterruptEnable - Host Controller Interrupt Enable register (address 0314h) bit

description

Bit

31 to 11 -

10 OTG_IRQ_E

Symbol

Description

reserved; write reset value

OTG_IRQ Enable: Controls the IRQ assertion because of events

present in the OTG Interrupt Latch register.

0 — No IRQ will be asserted

1 — IRQ will be asserted

For details, see Section 7.4.

9

ISO_IRQ_E

ATL_IRQ_E

INT_IRQ_E

ISO IRQ Enable: Controls the IRQ assertion when one or more ISO

PTDs matching the ISO IRQ Mask AND or ISO IRQ Mask OR register

bits combination are completed.

0 — No IRQ will be asserted when ISO PTDs are completed

1 — IRQ will be asserted

For details, see Section 7.4.

8

7

ATL IRQ Enable: Controls the IRQ assertion when one or more ATL

PTDs matching the ATL IRQ Mask AND or ATL IRQ Mask OR register

bits combination are completed.

0 — No IRQ will be asserted when ATL PTDs are completed

1 — IRQ will be asserted

For details, see Section 7.4.

INT IRQ Enable: Controls the IRQ assertion when one or more INT

PTDs matching the INT IRQ Mask AND or INT IRQ Mask OR register

bits combination are completed.

0 — No IRQ will be asserted when INT PTDs are completed

1 — IRQ will be asserted

For details, see Section 7.4.

6

5

CLKREADY_E Clock Ready Enable: Enables the IRQ assertion when internal clock

signals are running stable. Useful after wake-up.

0 — No IRQ will be generated after a CLKREADY_E event

1 — IRQ will be generated after a CLKREADY_E event

HCSUSP_E

Host Controller Suspend Enable: Enables the IRQ generation when

the host controller enters suspend mode.

0 — No IRQ will be generated when the host controller enters

suspend mode

1 — IRQ will be generated when the host controller enters suspend

mode

ISP1761_5

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Table 56. HcInterruptEnable - Host Controller Interrupt Enable register (address 0314h) bit

description …continued

Bit

4

Symbol

Description

-

reserved; write reset value

3

DMAEOTINT_E DMA EOT Interrupt Enable: Controls assertion of IRQ on the DMA

transfer completion.

0 — No IRQ will be generated when a DMA transfer is completed

1 — IRQ will be asserted when a DMA transfer is completed

2

1

-

reserved; write reset value

SOFITLINT_E

SOT ITL Interrupt Enable: Controls the IRQ generation at every SOF

occurrence.

0 — No IRQ will be generated on SOF occurrence

1 — IRQ will be asserted at every SOF

0

-

reserved; write reset value

8.4.3 ISO IRQ MASK OR register

Each bit of this register corresponds to one of the 32 ISO PTDs deﬁned, and is a

hardware IRQ mask for each PTD done map. See Table 57 for bit description. For details,

see Section 7.4.

Table 57. ISO IRQ Mask OR register (address 0318h) bit description

Bit

Symbol

Access Value

Description

31 to 0 ISO_IRQ_MASK_ R/W

OR[31:0]

0000 0000h ISO IRQ Mask OR: Represents a direct map for ISO PTDs 31 to 0.

0 — No OR condition deﬁned between ISO PTDs.

1 — The bits corresponding to certain PTDs are set to logic 1 to

deﬁne a certain OR condition.

8.4.4 INT IRQ MASK OR register

Each bit of this register (see Table 58) corresponds to one of the 32 INT PTDs deﬁned,

and is a hardware IRQ mask for each PTD done map. For details, see Section 7.4.

Table 58. INT IRQ Mask OR register (address 031Ch) bit description

Bit

Symbol

Access Value

Description

31 to 0 INT_IRQ_MASK_ R/W

OR[31:0]

0000 0000h INT IRQ Mask OR: Represents a direct map for INT PTDs 31 to 0.

0 — No OR condition deﬁned between INT PTDs 31 to 0.

1 — The bits corresponding to certain PTDs are set to logic 1 to

deﬁne a certain OR condition.

8.4.5 ATL IRQ MASK OR register

Each bit of this register corresponds to one of the 32 ATL PTDs deﬁned, and is a

hardware IRQ mask for each PTD done map. See Table 59 for bit description. For details,

see Section 7.4.

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Table 59. ATL IRQ Mask OR register (address 0320h) bit description

Bit

Symbol

Access Value

Description

31 to 0 ATL_IRQ_MASK_ R/W

OR[31:0]

0000 0000h ATL IRQ Mask OR: Represents a direct map for ATL PTDs 31 to 0.

0 — No OR condition deﬁned between ATL PTDs.

1 — The bits corresponding to certain PTDs are set to logic 1 to

deﬁne a certain OR condition.

8.4.6 ISO IRQ MASK AND register

Each bit of this register corresponds to one of the 32 ISO PTDs deﬁned, and is a

hardware IRQ mask for each PTD done map. For details, see Section 7.4.

Table 60 provides the bit description of the register.

Table 60. ISO IRQ Mask AND register (address 0324h) bit description

Bit

Symbol

Access Value

Description

31 to 0 ISO_IRQ_MASK_ R/W

AND[31:0]

0000 0000h ISO IRQ Mask AND: Represents a direct map for ISO PTDs 31 to 0.

0 — No AND condition deﬁned between ISO PTDs.

1 — The bits corresponding to certain PTDs are set to logic 1 to

deﬁne a certain AND condition between the 32 INT PTDs.

8.4.7 INT IRQ MASK AND register

Each bit of this register (see Table 61) corresponds to one of the 32 INT PTDs deﬁned,

and is a hardware IRQ mask for each PTD done map. For details, see Section 7.4.

Table 61. INT IRQ MASK AND register (address 0328h) bit description

Bit

Symbol

Access Value

Description

31 to 0 INT_IRQ_MASK_ R/W

AND[31:0]

0000 0000h INT IRQ Mask AND: Represents a direct map for INT PTDs 31 to 0.

0 — No OR condition deﬁned between INT PTDs.

1 — The bits corresponding to certain PTDs are set to logic 1 to

deﬁne a certain AND condition between the 32 INT PTDs.

8.4.8 ATL IRQ MASK AND register

Each bit of this register corresponds to one of the 32 ATL PTDs deﬁned, and is a

hardware IRQ mask for each PTD done map. For details, see Section 7.4.

Table 62 shows the bit description of the register.

Table 62. ATL IRQ MASK AND register (address 032Ch) bit description

Bit

Symbol

Access

Value

Description

31 to 0 ATL_IRQ_

MASK_AND

[31:0]

R/W

0000 0000h

ATL IRQ Mask AND: Represents a direct map for ATL PTDs 31 to 0.

0 — No OR condition deﬁned between ATL PTDs.

1 — The bits corresponding to certain PTDs are set to logic 1 to

deﬁne a certain AND condition between the 32 ATL PTDs.

8.5 Philips Transfer Descriptor (PTD)

The standard EHCI data structures as described in Ref. 2 “Enhanced Host Controller

Interface Speciﬁcation for Universal Serial Bus Rev. 1.0” are optimized for the bus master

operation that is managed by the hardware state machine.

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The PTD structures of the ISP1761 are translations of EHCI data structures that are

optimized for the ISP1761. It, however, still follows the basic EHCI architecture. This

optimized form of EHCI data structures is necessary because the ISP1761 is a slave host

controller and has no bus master capability.

EHCI manages schedules in two lists: periodic and asynchronous. Data structures are

designed to provide the maximum ﬂexibility required by USB, minimize memory trafﬁc,

and reduce hardware and software complexity. The ISP1761 controller executes

transactions for devices by using a simple shared-memory schedule. This schedule

consists of data structures organized into three lists.

qISO — Isochronous transfer

qINTL — Interrupt transfer

qATL — Asynchronous transfer; for the control and bulk transfers

The system software maintains two lists for the host controller: periodic and

asynchronous.

The ISP1761 has a maximum of 32 ISO, 32 INTL and 32 ATL PTDs. These PTDs are

used as channels to transfer data from the shared memory to the USB bus. These

channels are allocated and de-allocated on receiving the transfer from the core USB

driver.

Multiple transfers are scheduled to the shared memory for various endpoints by traversing

the next link pointer provided by endpoint data structures, until it reaches the end of the

endpoint list. There are three endpoint lists: one for ISO endpoints, and the other for INTL

and ATL endpoints. If the schedule is enabled, the host controller executes the ISO

schedule, followed by the INTL schedule, and then the ATL schedule.

These lists are traversed and scheduled by the software according to the EHCI traversal

rule. The host controller executes scheduled ISO, INTL and ATL PTDs. The completion of

a transfer is indicated to the software by the interrupt that can be grouped under various

PTDs by using the AND or OR registers that are available for each schedule type: ISO,

INTL and ATL. These registers are simple logic registers to decide the completion status

of group and individual PTDs. When the logical conditions of the Done bit is true in the

shared memory, it means that PTD has completed.

There are four types of interrupts in the ISP1761: ISO, INTL, ATL and SOF. The latency

can be programmed in multiples of µSOF (125 µs).

The NextPTD pointer is a feature that allows the ISP1761 to jump unused and skip PTDs.

This will improve the PTD transversal latency time. The NextPTD pointer is not meant for

same or single endpoint. The NextPTD works only in forward direction.

The NextPTD traversal rules deﬁned by the ISP1761 hardware are:

1. Start the PTD memory vertical traversal, considering the skip and LastPTD

information, as follows.

2. If the current PTD is active and not done, perform the transaction.

3. Follow the NextPTD pointer as speciﬁed in bits 4 to 0 of DW4.

4. If combined with LastPTD, the LastPTD setting must be at a higher address than the

NextPTD speciﬁed. So both are set in a logical manner.

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5. If combined with skip, the skip must not be set (logically) on the same position

corresponding to NextPTD, pointed by the NextPTD pointer.

6. If PTD is set for skip, it will be neglected and the next vertical PTD will be considered.

7. If the skipped PTD already has a setting including a NextPTD pointer that will not be

taken into consideration, the behavior will be just as described in the preceding step.

START PTD

SCHEDULE

no

PTD

yes

SKIPPED?

GO TO

NEXTPTD

VERTICAL

CHECK FOR

VALID AND

ACTIVE BIT

SET?

yes

START PTD

EXECUTION

no

yes

FOLLOW NEXT

PTD POINTED

BY NEXTPTD

POINTER

IS PTD

POINTER

NULL?

no

004aaa883

Fig 13. NextPTD traversal rule

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Hi-Speed USB OTG controller

Table 64. High-speed bulk IN and OUT: bit description

Bit

Symbol

reserved

Access

Value

Description

DW7

63 to 32

DW6

31 to 0

DW5

63 to 32

DW4

31 to 6

5

-

reserved

J

0

not applicable for asynchronous TD.

Jump:

SW — writes -

0 — To increment the PTD pointer.

1 — To enable the next PTD branching.

4 to 0

NextPTDPointer SW — writes -

Next PTD Counter: Next PTD branching assigned by the PTD

[4:0]

pointer.

DW3

63

A

SW — sets

-

Active: Write the same value as that in V.

HW — resets

62

61

H

B

HW — writes -

Halt: This bit corresponds to the Halt bit of the Status ﬁeld of TD.

Babble: This bit corresponds to the Babble Detected bit in the

Status ﬁeld of iTD, siTD or TD.

1 — When babbling is detected, A and V are set to 0.

60

X

HW — writes -

Error: This bit corresponds to the Transaction Error bit in the

Status ﬁeld of iTD, siTD or TD (Exec_Trans, the signal name is

xacterr).

0 — No PID error.

1 — If there are PID errors, this bit is set active. The A and V bits

are also set to inactive. This transaction is retried three times.

SW — writes -

0 — Before scheduling.

59

58

reserved

P

-

SW — writes -

Ping: For high-speed transactions, this bit corresponds to the Ping

state bit in the Status ﬁeld of a TD.

HW —

updates

0 — Ping is not set.

1 — Ping is set.

For the ﬁrst time, software sets the Ping bit to 0. For the successive

asynchronous TD, software sets the bit in asynchronous TD based

on the state of the bit for the previous asynchronous TD of the

same transfer, that is:

• The current asynchronous TD is completed with the Ping bit

set.

• The next asynchronous TD will have its Ping bit set by the

software.

57

DT

HW —

updates

-

Data Toggle: This bit is ﬁlled by software to start a PTD. If

NrBytesToTransfer[14:0] is not complete, software needs to read

this value and then write back the same value to continue.

SW — writes

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Table 64. High-speed bulk IN and OUT: bit description …continued

Bit

Symbol

Access

Value

Description

56 to 55

Cerr[1:0]

HW — writes -

SW — writes

Error Counter: This ﬁeld corresponds to the Cerr[1:0] ﬁeld in TD.

The default value of this ﬁeld is zero for isochronous transactions.

00 — The transaction will not retry.

11 — The transaction will retry three times. Hardware will

decrement these values.

54 to 51

NakCnt[3:0]

reserved

HW — writes -

SW — writes

NAK Counter: This ﬁeld corresponds to the NakCnt ﬁeld in TD.

Software writes for the initial PTD launch. The V bit is reset if

NakCnt decrements to zero and RL is a non-zero value. It reloads

from RL if transaction is ACK-ed.

50 to 47

46 to 32

-

NrBytes

Transferred

[14:0]

HW — writes -

Number of Bytes Transferred: This ﬁeld indicates the number of

bytes sent or received for this transaction. If Mult[1:0] is greater

than one, it is possible to store intermediate results in this ﬁeld.

SW — writes

0000

DW2

31 to 29

28 to 25

reserved

RL[3:0]

-

Set to 0 for asynchronous TD.

SW — writes -

Reload: If RL is set to 0h, hardware ignores the NakCnt value. RL

and NakCnt are set to the same value before a transaction.

24

reserved

-

Always 0 for asynchronous TD.

23 to 8

DataStart

Address[15:0]

SW — writes -

Data Start Address: This is the start address for data that will be

sent or received on or from the USB bus. This is the internal

memory address and not the direct CPU address.

RAM address = (CPU address − 400h) / 8

7 to 0

DW1

63 to 47

46

reserved

-

reserved

S

Always 0 for asynchronous TD.

SW — writes -

This bit indicates whether a split transaction has to be executed:

0 — High-speed transaction

1 — Split transaction

45 to 44

43 to 42

EPType[1:0]

Token[1:0]

Transaction type:

00 — Control

10 — Bulk

Token: Identiﬁes the token Packet Identiﬁer (PID) for this

transaction:

00 — OUT

01 — IN

10 — SETUP

11 — PING (written by hardware only).

41 to 35

34 to 32

DeviceAddress

[6:0]

SW — writes -

Device Address: This is the USB address of the function

containing the endpoint that is referred to by this buffer.

EndPt[3:1]

Endpoint: This is the USB address of the endpoint within the

function.

DW0

31

EndPt[0]

SW — writes -

Endpoint: This is the USB address of the endpoint within the

function.

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Table 64. High-speed bulk IN and OUT: bit description …continued

Bit

Symbol

Access

Value

Description

30 to 29

Mult[1:0]

SW — writes -

Multiplier: This ﬁeld is a multiplier used by the host controller as

the number of successive packets the host controller may submit to

the endpoint in the current execution.

Set this ﬁeld to 01b. You can also set it to 11b and 10b depending

on your application. 00b is undeﬁned.

28 to 18

17 to 3

MaxPacket

Length[10:0]

SW — writes -

Maximum Packet Length: This ﬁeld indicates the maximum

number of bytes that can be sent to or received from an endpoint in

a single data packet. The maximum packet size for a bulk transfer

is 512 bytes. The maximum packet size for the isochronous

transfer is also variable at any whole number.

NrBytesTo

Transfer[14:0]

Number of Bytes to Transfer: This ﬁeld indicates the number of

bytes that can be transferred by this data structure. It is used to

indicate the depth of the DATA ﬁeld (32 kB − 1 B).

2 to 1

0

reserved

V

-

SW — sets

Valid:

HW — resets

0 — This bit is deactivated when the entire PTD is executed, or

when a fatal error is encountered.

1 — Software updates to one when there is payload to be sent or

received. The current PTD is active.

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Table 66. High-speed isochronous IN and OUT: bit description

Bit

Symbol

Access

Value

Description

DW7

63 to 52

ISOIN_7[11:0] HW — writes

ISOIN_6[11:0] HW — writes

ISOIN_5[11:4] HW — writes

-

Bytes received during µSOF7, if µSA[7] is set to 1 and frame

number is correct.

51 to 40

39 to 32

Bytes received during µSOF6, if µSA[6] is set to 1 and frame

number is correct.

Bytes received during µSOF5 (bits 11 to 4), if µSA[5] is set to 1

and frame number is correct.

DW6

31 to 28

ISOIN_5[3:0]

HW — writes

-

Bytes received during µSOF5 (bits 3 to 0), if µSA[5] is set to 1 and

frame number is correct.

27 to 16

15 to 4

3 to 0

ISOIN_4[11:0] HW — writes

ISOIN_3[11:0] HW — writes

ISOIN_2[11:8] HW — writes

Bytes received during µSOF4, if µSA[4] is set to 1 and frame

number is correct.

Bytes received during µSOF3, if µSA[3] is set to 1 and frame

number is correct.

Bytes received during µSOF2 (bits 11 to 8), if µSA[2] is set to 1

and frame number is correct.

DW5

63 to 56

ISOIN_2[7:0]

HW — writes

-

Bytes received during µSOF2 (bits 7 to 0), if µSA[2] is set to 1 and

frame number is correct.

55 to 44

43 to 32

ISOIN_1[11:0] HW — writes

ISOIN_0[11:0] HW — writes

Bytes received during µSOF1, if µSA[1] is set to 1 and frame

number is correct.

Bytes received during µSOF0, if µSA[0] is set to 1 and frame

number is correct.

DW4

31 to 29

Status7[2:0]

Status6[2:0]

Status5[2:0]

Status4[2:0]

Status3[2:0]

Status2[2:0]

Status1[2:0]

Status0[2:0]

HW — writes

-

ISO IN or OUT status at µSOF7

ISO IN or OUT status at µSOF6

ISO IN or OUT status at µSOF5

ISO IN or OUT status at µSOF4

ISO IN or OUT status at µSOF3

ISO IN or OUT status at µSOF2

ISO IN or OUT status at µSOF1

28 to 26

25 to 23

22 to 20

19 to 17

16 to 14

13 to 11

10 to 8

Status of the payload on the USB bus for this µSOF after ISO has

been delivered.

Bit 0 — Transaction error (IN and OUT)

Bit 1 — Babble (IN token only)

Bit 2 — Underrun (OUT token only)

7 to 0

µSA[7:0]

SW — writes

(0 → 1)

-

µSOF Active: When the frame number of bits DW1[7:3] match the

frame number of the USB bus, these bits are checked for 1 before

they are sent for µSOF. For example: If µSA[7:0] = 1, 1, 1, 1, 1, 1,

1, 1: send ISO every µSOF of the entire millisecond. If µSA[7:0] =

0, 1, 0, 1, 0, 1, 0, 1: send ISO only on µSOF0, µSOF2, µSOF4

and µSOF6.

HW — writes

(1 → 0)

After processing

ISP1761_5

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ISP1761

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Hi-Speed USB OTG controller

Table 66. High-speed isochronous IN and OUT: bit description …continued

Bit

Symbol

Access

Value

Description

DW3

63

A

H

SW — sets

-

Active: This bit is the same as the Valid bit.

62

61

HW — writes

Halt: Only one bit for the entire millisecond. When this bit is set,

the Valid bit is reset. The device decides to stall an endpoint.

B

HW — writes

-

Babble: Not applicable here.

60 to 47

46 to 32

reserved

-

0

-

Set to 0 for isochronous.

NrBytes

Transferred

[14:0]

HW — writes

Number of Bytes Transferred: This ﬁeld indicates the number of

bytes sent or received for this transaction. If Mult[1:0] is greater

than one, it is possible to store intermediate results in this ﬁeld.

NrBytesTransferred[14:0] is 32 kB − 1 B per PTD.

DW2

31 to 24

23 to 8

reserved

-

0

-

Set to 0 for isochronous.

DataStart

Address[15:0]

SW — writes

Data Start Address: This is the start address for data that will be

sent or received on or from the USB bus. This is the internal

memory address and not the direct CPU address.

RAM address = (CPU address − 400h) / 8

Bits 2 to 0 — Don’t care

7 to 0

µFrame[7:0]

SW — writes

-

Bits 7 to 3 — Frame number that this PTD will be sent for ISO

OUT or IN

DW1

63 to 47

46

reserved

S

-

SW — writes

This bit indicates whether a split transaction has to be executed.

0 — High-speed transaction

1 — Split transaction

45 to 44

43 to 42

EPType[1:0]

Token[1:0]

SW — writes

-

Endpoint type:

01 — Isochronous

Token: This ﬁeld indicates the token PID for this transaction:

00 — OUT

01 — IN

41 to 35

34 to 32

Device

Address[6:0]

SW — writes

-

Device Address: This is the USB address of the function

containing the endpoint that is referred to by this buffer.

EndPt[3:1]

Endpoint: This is the USB address of the endpoint within the

function.

DW0

31

EndPt[0]

Mult[1:0]

SW — writes

-

Endpoint: This is the USB address of the endpoint within the

function.

30 to 29

This ﬁeld is a multiplier counter used by the host controller as the

number of successive packets the host controller may submit to

the endpoint in the current execution.

For details, refer to Appendix D of Ref. 2 “Enhanced Host

Controller Interface Speciﬁcation for Universal Serial Bus

Rev. 1.0”.

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Table 66. High-speed isochronous IN and OUT: bit description …continued

Bit

Symbol

Access

Value

Description

28 to 18

MaxPacket

Length[10:0]

SW — writes

-

Maximum Packet Length: This ﬁeld indicates the maximum

number of bytes that can be sent to or received from the endpoint

in a single data packet. The maximum packet size for an

isochronous transfer is 1024 bytes. The maximum packet size for

the isochronous transfer is also variable at any whole number.

17 to 3

NrBytesTo

Transfer[14:0]

SW — writes

-

Number of Bytes Transferred: This ﬁeld indicates the number of

bytes that can be transferred by this data structure. It is used to

indicate the depth of the DATA ﬁeld (32 kB − 1 B).

2 to 1

0

reserved

V

-

HW — resets

SW — sets

0 — This bit is deactivated when the entire PTD is executed, or

when a fatal error is encountered.

1 — Software updates to one when there is payload to be sent or

received. The current PTD is active.

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Table 68. High-speed interrupt IN and OUT: bit description

Bit

Symbol

Access

Value Description

DW7

63 to 52 INT_IN_7[11:0] HW — writes

51 to 40 INT_IN_6[11:0] HW — writes

39 to 32 INT_IN_5[11:4] HW — writes

DW6

-

Bytes received during µSOF7, if µSA[7] is set to 1 and frame number

is correct.

Bytes received during µSOF6, if µSA[6] is set to 1 and frame number

is correct.

Bytes received during µSOF5 (bits 11 to 4), if µSA[5] is set to 1 and

frame number is correct.

31 to 28 INT_IN_5[3:0]

HW — writes

-

Bytes received during µSOF5 (bits 3 to 0), if µSA[5] is set to 1 and

frame number is correct.

27 to 16 INT_IN_4[11:0] HW — writes

15 to 4 INT_IN_3[11:0] HW — writes

Bytes received during µSOF4, if µSA[4] is set to 1 and frame number

is correct.

Bytes received during µSOF3, if µSA[3] is set to 1 and frame number

is correct.

3 to 0

INT_IN_2[11:8] HW — writes

Bytes received during µSOF2 (bits 11 to 8), if µSA[2] is set to 1 and

frame number is correct.

DW5

63 to 56 INT_IN_2[7:0]

HW — writes

-

Bytes received during µSOF2 (bits 7 to 0), if µSA[2] is set to 1 and

frame number is correct.

55 to 44 INT_IN_1[11:0] HW — writes

43 to 32 INT_IN_0[11:0] HW — writes

DW4

Bytes received during µSOF1, if µSA[1] is set to 1 and frame number

is correct.

Bytes received during µSOF0, if µSA[0] is set to 1 and frame number

is correct.

31 to 29 Status7[2:0]

28 to 26 Status6[2:0]

25 to 23 Status5[2:0]

22 to 20 Status4[2:0]

19 to 17 Status3[2:0]

16 to 14 Status2[2:0]

13 to 11 Status1[2:0]

10 to 8 Status0[2:0]

HW — writes

-

INT IN or OUT status of µSOF7

INT IN or OUT status of µSOF6

INT IN or OUT status of µSOF5

INT IN or OUT status of µSOF4

INT IN or OUT status of µSOF3

INT IN or OUT status of µSOF2

INT IN or OUT status of µSOF1

Status of the payload on the USB bus for this µSOF after INT has

been delivered.

Bit 0 — Transaction error (IN and OUT)

Bit 1 — Babble (IN token only)

Bit 2 — Underrun (OUT token only)

7 to 0

µSA[7:0]

SW — writes

(0 → 1)

-

When the frame number of bits DW2[7:3] match the frame number of

the USB bus, these bits are checked for 1 before they are sent for

µSOF. For example: When µSA[7:0] = 1, 1, 1, 1, 1, 1, 1, 1: send INT

for every µSOF of the entire millisecond. When µSA[7:0] = 0, 1, 0, 1,

0, 1, 0, 1: send INT for µSOF0, µSOF2, µSOF4 and µSOF6. When

µSA[7:0] = 1, 0, 0, 0, 1, 0, 0, 0 = send INT for every fourth µSOF.

HW — writes

(1 → 0)

After processing

ISP1761_5

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Hi-Speed USB OTG controller

Table 68. High-speed interrupt IN and OUT: bit description …continued

Bit

Symbol

Access

Value Description

DW3

63

A

HW — writes

SW — writes

-

Active: Write the same value as that in V.

62

H

HW — writes

-

Halt: Transaction is halted.

61 to 58 reserved

57 DT

-

HW — writes

SW — writes

Data Toggle: Set the Data Toggle bit to start the PTD. Software

writes the current transaction toggle value. Hardware writes the next

transaction toggle value.

56 to 55 Cerr[1:0]

54 to 47 reserved

HW — writes

SW — writes

-

Error Counter: This ﬁeld corresponds to the Cerr[1:0] ﬁeld in TD. The

default value of this ﬁeld is zero for isochronous transactions.

-

46 to 32 NrBytes

Transferred

[14:0]

HW — writes

Number of Bytes Transferred: This ﬁeld indicates the number of

bytes sent or received for this transaction. If Mult[1:0] is greater than

one, it is possible to store intermediate results in this ﬁeld.

DW2

31 to 24 reserved

-

23 to 8 DataStart

Address[15:0]

SW — writes

Data Start Address: This is the start address for data that will be

sent or received on or from the USB bus. This is the internal memory

address and not the direct CPU address.

RAM address = (CPU address − 400h) / 8

7 to 0

µFrame[7:0]

SW — writes

-

Bits 7 to 3 represent the polling rate in milliseconds.

The INT polling rate is deﬁned as 2^{(b - 1)}µSOF, where b is 1 to 9.

When b is 1, 2, 3 or 4, use µSA to deﬁne polling because the rate is

equal to or less than 1 ms. Bits 7 to 3 are set to 0. Polling checks µSA

bits for µSOF rates. See Table 69.

DW1

63 to 47 reserved

46

-

S

SW — writes

This bit indicates if a split transaction has to be executed:

0 — High-speed transaction

1 — Split transaction

45 to 44 EPType[1:0]

43 to 42 Token[1:0]

SW — writes

-

Endpoint type:

11 — Interrupt

Token: This ﬁeld indicates the token PID for this transaction:

00 — OUT

01 — IN

41 to 35 DeviceAddress SW — writes

-

Device Address: This is the USB address of the function containing

the endpoint that is referred to by the buffer.

[6:0]

34 to 32 EndPt[3:1]

SW — writes

Endpoint: This is the USB address of the endpoint within the

function.

DW0

31

EndPt[0]

-

Endpoint: This is the USB address of the endpoint within the

function.

ISP1761_5

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Rev. 05 — 13 March 2008

71 of 163

ISP1761

NXP Semiconductors

Hi-Speed USB OTG controller

Table 68. High-speed interrupt IN and OUT: bit description …continued

Bit

Symbol

Access

Value Description

30 to 29 Mult[1:0]

SW — writes

-

Multiplier: This ﬁeld is a multiplier counter used by the host controller

as the number of successive packets the host controller may submit

to the endpoint in the current execution.

Set this ﬁeld to 01b. You can also set it to 11b and 10b depending on

your application. 00b is undeﬁned.

28 to 18 MaxPacket

Length[10:0]

SW — writes

-

Maximum Packet Length: This ﬁeld indicates the maximum number

of bytes that can be sent to or received from the endpoint in a single

data packet.

17 to 3 NrBytesTo

Transfer[14:0]

Number of Bytes to Transfer: This ﬁeld indicates the number of

bytes that can be transferred by this data structure. It is used to

indicate the depth of the DATA ﬁeld (32 kB − 1 B).

2 to 1

0

reserved

V

-

SW — sets

Valid:

HW — resets

0 — This bit is deactivated when the entire PTD is executed, or when

a fatal error is encountered.

1 — Software updates to one when there is payload to be sent or

received. The current PTD is active.

Table 69. Microframe description

b

1

2

3

4

5

6

7

8

9

Rate

µFrame[7:3]

0 0000

µSA[7:0]

1 µSOF

2 µSOF

4 µSOF

1 ms

1111 1111

0 0000

1010 1010 or 0101 0101

any 2 bits set

any 1 bit set

0 0000

2 ms

0 0001

4 ms

0 0010 to 0 0011

0 0100 to 0 0111

0 1000 to 0 1111

1 0000 to 1 1111

8 ms

16 ms

32 ms

ISP1761_5

Product data sheet

Rev. 05 — 13 March 2008

72 of 163

ISP1761

NXP Semiconductors

Hi-Speed USB OTG controller

Table 71. Start and complete split for bulk: bit description

Bit

Symbol

reserved

Access

Value Description

DW7

63 to 32

DW6

31 to 0

DW5

63 to 32

DW4

31 to 6

5

-

reserved

J

-

SW — writes

0 — To increment the PTD pointer.

1 — To enable the next PTD branching.

4 to 0

NextPTDPointer[4:0] SW — writes

-

Next PTD Pointer: Next PTD branching assigned by the PTD

pointer.

DW3

63

A

SW — sets

Active: Write the same value as that in V.

HW — resets

62

61

H

B

HW — writes

-

Halt: This bit corresponds to the Halt bit of the Status ﬁeld of

TD.

Babble: This bit corresponds to the Babble Detected bit in the

Status ﬁeld of iTD, siTD or TD.

1 — when babbling is detected, A and V are set to 0.

60

59

X

HW — writes

SW — writes

-

Transaction Error: This bit corresponds to the Transaction

Error bit in the status ﬁeld.

-

0 — Before scheduling

SC

SW — writes 0

HW — updates

Start/Complete:

0 — Start split

1 — Complete split

58

57

reserved

DT

-

HW — writes

SW — writes

Data Toggle: Set the Data Toggle bit to start for the PTD.

56 to 55

Cerr[1:0]

HW — updates

SW — writes

-

Error Counter: This ﬁeld contains the error count for

asynchronous start and complete split (SS/CS) TD. When an

error has no response or bad response, Cerr[1:0] will be

decremented to zero and then Valid will be set to zero. A NAK

or NYET will reset Cerr[1:0]. For details, refer to

Section 4.12.1.2 of Ref. 2 “Enhanced Host Controller Interface

Speciﬁcation for Universal Serial Bus Rev. 1.0”.

If retry has insufﬁcient time at the beginning of a new SOF, the

ﬁrst PTD must be this retry. This can be accomplished if

aperiodic PTD is not advanced.

54 to 51

NakCnt[3:0]

reserved

HW — writes

SW — writes

-

NAK Counter: The V bit is reset if NakCnt decrements to zero

and RL is a non-zero value. Not applicable to isochronous split

transactions.

50 to 47

-

ISP1761_5

Product data sheet

Rev. 05 — 13 March 2008

74 of 163

ISP1761

NXP Semiconductors

Hi-Speed USB OTG controller

Table 71. Start and complete split for bulk: bit description …continued

Bit

Symbol

Access

Value Description

46 to 32

NrBytes

HW — writes

-

Number of Bytes Transferred: This ﬁeld indicates the

Transferred[14:0]

number of bytes sent or received for this transaction.

DW2

31 to 29

28 to 25

reserved

RL[3:0]

-

SW — writes

Reload: If RL is set to 0h, hardware ignores the NakCnt value.

Set RL and NakCnt to the same value before a transaction. For

full-speed and low-speed transactions, set this ﬁeld to 0000b.

Not applicable to isochronous start split and complete split.

24

reserved

-

23 to 8

DataStartAddress

[15:0]

SW — writes

Data Start Address: This is the start address for data that will

be sent or received on or from the USB bus. This is the internal

memory address and not the direct CPU address.

RAM address = (CPU address − 400h) / 8

7 to 0

reserved

-

DW1

63 to 57

HubAddress[6:0]

PortNumber[6:0]

SW — writes

-

Hub Address: This indicates the hub address.

56 to 50

49 to 48

Port Number: This indicates the port number of the hub or

embedded TT.

SE[1:0]

SW — writes

-

This depends on the endpoint type and direction. It is valid

only for split transactions. Table 72 applies to start split and

complete split only.

47

46

reserved

S

-

SW — writes

This bit indicates whether a split transaction has to be

executed:

0 — High-speed transaction

1 — Split transaction

45 to 44

43 to 42

EPType[1:0]

Token[1:0]

SW — writes

-

Endpoint Type:

00 — Control

10 — Bulk

Token: This ﬁeld indicates the PID for this transaction.

00 — OUT

01 — IN

10 — SETUP

41 to 35

34 to 32

DeviceAddress[6:0] SW — writes

-

Device Address: This is the USB address of the function

containing the endpoint that is referred to by this buffer.

EndPt[3:1]

SW — writes

Endpoint: This is the USB address of the endpoint within the

function.

DW0

31

EndPt[0]

reserved

SW — writes

-

Endpoint: This is the USB address of the endpoint within the

function.

30 to 29

-

ISP1761_5

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ISP1761

NXP Semiconductors

Hi-Speed USB OTG controller

Table 71. Start and complete split for bulk: bit description …continued

Bit

Symbol

Access

Value Description

28 to 18

MaximumPacket

Length[10:0]

SW — writes

-

Maximum Packet Length: This ﬁeld indicates the maximum

number of bytes that can be sent to or received from an

endpoint in a single data packet. The maximum packet size for

full-speed is 64 bytes as deﬁned in Ref. 1 “Universal Serial

Bus Speciﬁcation Rev. 2.0”.

17 to 3

NrBytesTo

Transfer[14:0]

SW — writes

-

Number of Bytes to Transfer: This ﬁeld indicates the number

of bytes that can be transferred by this data structure. It is used

to indicate the depth of the DATA ﬁeld.

2 to 1

0

reserved

V

-

SW — sets

Valid:

HW — resets

0 — This bit is deactivated when the entire PTD is executed, or

when a fatal error is encountered.

1 — Software updates to one when there is payload to be sent

or received. The current PTD is active.

Table 72. SE description

Bulk

I/O

Control

I/O

S

1

0

E

0

Remarks

low-speed

full-speed

I/O

ISP1761_5

Product data sheet

Rev. 05 — 13 March 2008

76 of 163

ISP1761

NXP Semiconductors

Hi-Speed USB OTG controller

Table 74. Start and complete split for isochronous: bit description

Bit

Symbol

Access

Value Description

DW7

63 to 40 reserved

-

39 to 32 ISO_IN_7[7:0] HW — writes

Bytes received during µSOF7, if µSA[7] is set to 1 and frame

number is correct.

DW6

31 to 24 ISO_IN_6[7:0] HW — writes

-

Bytes received during µSOF6, if µSA[6] is set to 1 and frame

number is correct.

23 to 16 ISO_IN_5[7:0] HW — writes

Bytes received during µSOF5, if µSA[5] is set to 1 and frame

number is correct.

15 to 8

7 to 0

DW5

ISO_IN_4[7:0] HW — writes

ISO_IN_3[7:0] HW — writes

Bytes received during µSOF4, if µSA[4] is set to 1 and frame

number is correct.

Bytes received during µSOF3, if µSA[3] is set to 1 and frame

number is correct.

63 to 56 ISO_IN_2[7:0] HW — writes

55 to 48 ISO_IN_1[7:0] HW — writes

47 to 40 ISO_IN_0[7:0] HW — writes

-

Bytes received during µSOF2 (bits 7 to 0), if µSA[2] is set to 1

and frame number is correct.

Bytes received during µSOF1, if µSA[1] is set to 1 and frame

number is correct.

Bytes received during µSOF0 if µSA[0] is set to 1 and frame

number is correct.

39 to 32 µSCS[7:0]

SW — writes (0 → 1)

All bits can be set to one for every transfer. It speciﬁes which

µSOF the complete split needs to be sent. Valid only for IN.

Start split and complete split active bits, µSA = 0000 0001 and

µSCS = 0000 0100, will cause SS to execute in µFrame0 and

CS in µFrame2.

HW — writes (1 → 0)

After processing

DW4

31 to 29 Status7[2:0]

HW — writes

-

Isochronous IN or OUT status of µSOF7

Isochronous IN or OUT status of µSOF6

Isochronous IN or OUT status of µSOF5

Isochronous IN or OUT status of µSOF4

Isochronous IN or OUT status of µSOF3

Isochronous IN or OUT status of µSOF2

Isochronous IN or OUT status of µSOF1

28 to 26 Status6[2:0]

25 to 23 Status5[2:0]

22 to 20 Status4[2:0]

19 to 17 Status3[2:0]

16 to 14 Status2[2:0]

13 to 11 Status1[2:0]

10 to 8

Status0[2:0]

Isochronous IN or OUT status of µSOF0

Bit 0 — Transaction error (IN and OUT)

Bit 1 — Babble (IN token only)

Bit 2 — Underrun (OUT token only)

7 to 0

µSA[7:0]

SW — writes (0 → 1)

HW — writes (1 → 0)

After processing

-

Speciﬁes which µSOF the start split needs to be placed.

For OUT token: When the frame number of bits DW2[7:3]

matches the frame number of the USB bus, these bits are

checked for one before they are sent for the µSOF.

For IN token: Only µSOF0, µSOF1, µSOF2 or µSOF3 can be

set to 1. Nothing can be set for µSOF4 and above.

ISP1761_5

Product data sheet

Rev. 05 — 13 March 2008

78 of 163

ISP1761

NXP Semiconductors

Hi-Speed USB OTG controller

Table 74. Start and complete split for isochronous: bit description …continued

Bit

Symbol

Access

Value Description

DW3

63

A

SW — sets

-

Active: Write the same value as that in V.

HW — resets

62

61

60

59

H

HW — writes

-

Halt: The Halt bit is set when any microframe transfer status

has a stalled or halted condition.

B

Babble: This bit corresponds to bit 1 of Status0 to Status7 for

every microframe transfer status.

X

Transaction Error: This bit corresponds to bit 0 of Status0 to

Status7 for every microframe transfer status.

SC

SW — writes 0

HW — updates

Start/Complete:

0 — Start split

1 — Complete split

58

57

reserved

DT

-

HW — writes

SW — writes

Data Toggle: Set the Data Toggle bit to start for the PTD.

56 to 44 reserved

-

43 to 32 NrBytes

Transferred

[11:0]

HW — writes

Number of Bytes Transferred: This ﬁeld indicates the number

of bytes sent or received for this transaction.

DW2

31 to 24 reserved

-

23 to 8

DataStart

SW — writes

Data Start Address: This is the start address for data that will

be sent or received on or from the USB bus. This is the internal

memory address and not the CPU address.

Address[15:0]

7 to 0

µFrame[7:0]

SW — writes

-

Bits 7 to 3 determine which frame to execute.

DW1

63 to 57 HubAddress

[6:0]

SW — writes

-

Hub Address: This indicates the hub address.

56 to 50 PortNumber

[6:0]

Port Number: This indicates the port number of the hub or

embedded TT.

49 to 47 reserved

-

46

S

SW — writes

Split: This bit indicates whether a split transaction has to be

executed:

0 — High-speed transaction

1 — Split transaction

45 to 44 EPType[1:0]

43 to 42 Token[1:0]

SW — writes

-

Transaction type:

01 — Isochronous

Token: Token PID for this transaction:

00 — OUT

01 — IN

ISP1761_5

Product data sheet

Rev. 05 — 13 March 2008

79 of 163

ISP1761

NXP Semiconductors

Hi-Speed USB OTG controller

Table 74. Start and complete split for isochronous: bit description …continued

Bit

41 to 35 Device

Address[6:0]

Symbol

Access

Value Description

SW — writes

-

Device Address: This is the USB address of the function

containing the endpoint that is referred to by this buffer.

34 to 32 EndPt[3:1]

SW — writes

-

Endpoint: This is the USB address of the endpoint within the

function.

DW0

31

EndPt[0]

SW — writes

-

Endpoint: This is the USB address of the endpoint within the

function.

30 to 29 reserved

-

28 to 18 TT_MPS_Len SW — writes

Transaction Translator Maximum Packet Size Length: This

ﬁeld indicates the maximum number of bytes that can be sent

per start split depending on the number of total bytes needed. If

the total bytes to be sent for the entire millisecond is greater

than 188 bytes, this ﬁeld should be set to 188 bytes for an OUT

token and 192 bytes for an IN token. Otherwise, this ﬁeld

should be equal to the total bytes sent.

[10:0]

17 to 3

NrBytesTo

Transfer[14:0]

SW — writes

-

Number of Bytes to Transfer: This ﬁeld indicates the number

of bytes that can be transferred by this data structure. It is used

to indicate the depth of the DATA ﬁeld. This ﬁeld is restricted to

1023 bytes because in siTD the maximum allowable payload for

a full-speed device is 1023 bytes. This ﬁeld indirectly becomes

the maximum packet size of the downstream device.

2 to 1

0

reserved

V

-

SW — sets

0 — This bit is deactivated when the entire PTD is executed, or

when a fatal error is encountered.

HW — resets

1 — Software updates to one when there is payload to be sent

or received. The current PTD is active.

ISP1761_5

Product data sheet

Rev. 05 — 13 March 2008

80 of 163

ISP1761

NXP Semiconductors

Hi-Speed USB OTG controller

Table 76. Start and complete split for interrupt: bit description

Bit

Symbol

Access

Value Description

DW7

63 to 40 reserved

-

39 to 32 INT_IN_7[7:0] HW — writes

Bytes received during µSOF7, if µSA[7] is set to 1 and frame number is

correct. The new value continuously overwrites the old value.

DW6

31 to 24 INT_IN_6[7:0] HW — writes

-

Bytes received during µSOF6, if µSA[6] is set to 1 and frame number is

correct. The new value continuously overwrites the old value.

23 to 16 INT_IN_5[7:0] HW — writes

Bytes received during µSOF5, if µSA[5] is set to 1 and frame number is

correct. The new value continuously overwrites the old value.

15 to 8

7 to 0

DW5

INT_IN_4[7:0] HW — writes

INT_IN_3[7:0] HW — writes

Bytes received during µSOF4, if µSA[4] is set to 1 and frame number is

correct. The new value continuously overwrites the old value.

Bytes received during µSOF3, if µSA[3] is set to 1 and frame number is

correct. The new value continuously overwrites the old value.

63 to 56 INT_IN_2[7:0] HW — writes

-

Bytes received during µSOF2 (bits 7 to 0), if µSA[2] is set to 1 and

frame number is correct. The new value continuously overwrites the

old value.

55 to 48 INT_IN_1[7:0] HW — writes

47 to 40 INT_IN_0[7:0] HW — writes

-

Bytes received during µSOF1, if µSA[1] is set to 1 and frame number is

correct. The new value continuously overwrites the old value.

Bytes received during µSOF0 if µSA[0] is set to 1 and frame number is

correct. The new value continuously overwrites the old value.

39 to 32 µSCS[7:0]

SW — writes

(0 → 1)

All bits can be set to one for every transfer. It speciﬁes which µSOF the

complete split needs to be sent. Valid only for IN. Start split and

complete split active bits, µSA = 0000 0001 and µSCS = 0000 0100,

will cause SS to execute in µFrame0 and CS in µFrame2.

HW — writes

(1 → 0)

After

processing

DW4

31 to 29 Status7[2:0]

HW — writes

-

Interrupt IN or OUT status of µSOF7

Interrupt IN or OUT status of µSOF6

Interrupt IN or OUT status of µSOF5

Interrupt IN or OUT status of µSOF4

Interrupt IN or OUT status of µSOF3

Interrupt IN or OUT status of µSOF2

Interrupt IN or OUT status of µSOF1

28 to 26 Status6[2:0]

25 to 23 Status5[2:0]

22 to 20 Status4[2:0]

19 to 17 Status3[2:0]

16 to 14 Status2[2:0]

13 to 11 Status1[2:0]

10 to 8

Status0[2:0]

Interrupt IN or OUT status of µSOF0

Bit 0 — Transaction error (IN and OUT)

Bit 1 — Babble (IN token only)

Bit 2 — Underrun (OUT token only)

ISP1761_5

Product data sheet

Rev. 05 — 13 March 2008

82 of 163

ISP1761

NXP Semiconductors

Hi-Speed USB OTG controller

Table 76. Start and complete split for interrupt: bit description …continued

Bit

Symbol

Access

Value Description

- Speciﬁes which µSOF the start split needs to be placed.

7 to 0

µSA[7:0]

SW — writes

(0 → 1)

For OUT token: When the frame number of bits DW1[7:3] matches the

frame number of the USB bus, these bits are checked for one before

they are sent for the µSOF.

HW — writes

(1 → 0)

After

processing

For IN token: Only µSOF0, µSOF1, µSOF2 or µSOF3 can be set to 1.

Nothing can be set for µSOF4 and above.

DW3

63

A

SW — sets

-

Active: Write the same value as that in V.

HW — resets

62

61

60

59

H

HW — writes

-

Halt: The Halt bit is set when any microframe transfer status has a

stalled or halted condition.

B

Babble: This bit corresponds to bit 1 of Status0 to Status7 for every

microframe transfer status.

X

Transaction Error: This bit corresponds to bit 0 of Status0 to Status7

for every microframe transfer status.

SC

SW — writes

0

Start/Complete:

0 — Start split

HW —

updates

1 — Complete split

58

57

reserved

DT

-

HW — writes

SW — writes

Data Toggle: For an interrupt transfer, set correct bit to start the PTD.

56 to 55 Cerr[1:0]

HW — writes

SW — writes

-

Error Counter: This ﬁeld corresponds to the Cerr[1:0] ﬁeld in TD.

00 — The transaction will not retry.

11 — The transaction will retry three times. Hardware will decrement

these values.

54 to 44 reserved

-

43 to 32 NrBytes

Transferred

[11:0]

HW — writes

Number of Bytes Transferred: This ﬁeld indicates the number of

bytes sent or received for this transaction.

DW2

31 to 24 reserved

-

23 to 8

7 to 0

DW1

DataStart

Address[15:0]

SW — writes

Data Start Address: This is the start address for data that will be sent

or received on or from the USB bus. This is the internal memory

address and not the CPU address.

µFrame[7:0]

SW — writes

-

Bits 7 to 3 is the polling rate in milliseconds. Polling rate is deﬁned as

2^{(b − 1)}µSOF; where b = 4 to 16. When b is 4, executed every

millisecond. See Table 77.

63 to 57 HubAddress

[6:0]

SW — writes

-

Hub Address: This indicates the hub address.

56 to 50 PortNumber

[6:0]

Port Number: This indicates the port number of the hub or embedded

TT.

49 to 48 SE[1:0]

This depends on the endpoint type and direction. It is valid only for split

transactions. Table 78 applies to start split and complete split only.

ISP1761_5

Product data sheet

Rev. 05 — 13 March 2008

83 of 163

ISP1761

NXP Semiconductors

Hi-Speed USB OTG controller

Table 76. Start and complete split for interrupt: bit description …continued

Bit

47

46

Symbol

reserved

S

Access

Value Description

-

SW — writes

This bit indicates whether a split transaction has to be executed:

0 — High-speed transaction

1 — Split transaction

45 to 44 EPType[1:0]

43 to 42 Token[1:0]

SW — writes

-

Transaction type:

11 — Interrupt

Token PID for this transaction:

00 — OUT

01 — IN

41 to 35 DeviceAddress SW — writes

-

Device Address: This is the USB address of the function containing

the endpoint that is referred to by this buffer.

[6:0]

34 to 32 EndPt[3:1]

SW — writes

Endpoint: This is the USB address of the endpoint within the function.

DW0

31

EndPt[0]

SW — writes

-

Endpoint: This is the USB address of the endpoint within the function.

30 to 29 reserved

-

28 to 18 MaxPacket

Length[10:0]

SW — writes

Maximum Packet Length: This ﬁeld indicates the maximum number

of bytes that can be sent to or received from an endpoint in a single

data packet. The maximum packet size for the full-speed and

low-speed devices is 64 bytes as deﬁned in Ref. 1 “Universal Serial

Bus Speciﬁcation Rev. 2.0”.

17 to 3

NrBytesTo

Transfer[14:0]

SW — writes

-

Number of Bytes to Transfer: This ﬁeld indicates the number of bytes

that can be transferred by this data structure. It is used to indicate the

depth of the DATA ﬁeld. The maximum total number of bytes for this

transaction is 4 kB.

2 to 1

0

reserved

V

-

SW — sets

0 — This bit is deactivated when the entire PTD is executed, or when a

fatal error is encountered.

HW — resets

1 — Software updates to one when there is payload to be sent or

received. The current PTD is active.

Table 77. Microframe description

b

5

6

7

8

9

Rate

2 ms

4 ms

8 ms

16 ms

32 ms

µFrame[7:3]

0 0001

0 0010 or 0 0011

0 0100 or 0 0111

0 1000 or 0 1111

1 0000 or 1 1111

Table 78. SE description

Interrupt

I/O

S

1

0

E

0

Remarks

low-speed

full-speed

I/O

ISP1761_5

Product data sheet

Rev. 05 — 13 March 2008

84 of 163

ISP1761

NXP Semiconductors

Hi-Speed USB OTG controller

9. OTG controller

9.1 Introduction

OTG is a supplement to the Hi-Speed USB speciﬁcation that augments existing USB

peripherals by adding to these peripherals limited host capability to support other targeted

USB peripherals. It is primarily targeted at portable devices because it addresses

concerns related to such devices, such as a small connector and low power. Non-portable

devices, even standard hosts, can also beneﬁt from OTG features.

The ISP1761 OTG controller is designed to perform all the tasks speciﬁed in the OTG

supplement. It supports Host Negotiation Protocol (HNP) and Session Request Protocol

(SRP) for dual-role devices. The ISP1761 uses software implementation of HNP and SRP

for maximum ﬂexibility. A set of OTG registers provides the control and status monitoring

capabilities to support software HNP and SRP.

Besides the normal USB transceiver, timers and analog components required by OTG are

also integrated on-chip. The analog components include:

• Built-in 3.3 V-to-5 V charge pump

• Voltage comparators

• Pull-up or pull-down resistors on data lines

• Charging or discharging resistors for V_BUS

9.2 Dual-role device

When port 1 of the ISP1761 is conﬁgured in OTG mode, it can be used as an OTG

dual-role device. A dual-role device is a USB device that can function either as a host or

as a peripheral.

The default role of the ISP1761 is controlled by the ID pin, which in turn is controlled by

the type of plug connected to the micro-AB receptacle. If ID = LOW (micro-A plug

connected), it becomes an A-device, which is a host by default. If ID = HIGH (micro-B plug

connected), it becomes a B-device, which is a peripheral by default.

Both the A-device and the B-device work on a session base. A session is deﬁned as the

period of time in which devices exchange data. A session starts when V_BUSis driven and

ends when V_BUSis turned off. Both the A-device and the B-device may start a session.

During a session, the role of the host can be transferred back and forth between the

A-device and the B-device any number of times by using HNP.

If the A-device wants to start a session, it turns on V_BUSby enabling the charge pump. The

B-device detects that V_BUShas risen above the B_SESS_VLD level and assumes the role

of a peripheral asserting its pull-up resistor on the DP line. The A-device detects the

remote pull-up resistor and assumes the role of a host. Then, the A-device can

communicate with the B-device as long as it wishes. When the A-device ﬁnishes

communicating with the B-device, the A-device turns off V_BUSand both the devices ﬁnally

go into the idle state. See Figure 15 and Figure 16.

If the B-device wants to start a session, it must initiate SRP by ‘data line pulsing’ and

‘V_BUSpulsing’. When the A-device detects any of these SRP events, it turns on its V_BUS

(Note: only the A-device is allowed to drive V_BUS.) The B-device assumes the role of a

.

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Hi-Speed USB OTG controller

peripheral, and the A-device assumes the role of a host. The A-device detects that the

B-device can support HNP by getting the OTG descriptor from the B-device. The A-device

will then enable the HNP hand-off by using SetFeature (b_hnp_enable) and then go into

the suspend state. The B-device signals claiming the host role by de-asserting its pull-up

resistor. The A-device acknowledges by going into the peripheral state. The B-device then

assumes the role of a host and communicates with the A-device as long as it wishes.

When the B-device ﬁnishes communicating with the A-device, both the devices ﬁnally go

into the idle state. See Figure 15 and Figure 16.

9.3 Session Request Protocol (SRP)

As a dual-role device, the ISP1761 can initiate and respond to SRP. The B-device initiates

SRP by data line pulsing, followed by V_BUSpulsing. The A-device can detect either data

line pulsing or V_BUSpulsing.

9.3.1 B-device initiating SRP

The ISP1761 can initiate SRP by performing the following steps:

1. Detect initial conditions [read B_SESS_END and B_SE0_SRP (bits 7 and 8) of the

OTG Status register].

2. Start data line pulsing [set DP_PULLUP (bit 0) of the OTG Control (set) register to

logic 1].

3. Wait for 5 ms to 10 ms.

4. Stop data line pulsing [set DP_PULLUP (bit 0) of the OTG Control (clear) register to

logic 0].

5. Start V_BUSpulsing [set VBUS_CHRG (bit 6) of the OTG Control (set) register to

logic 1].

6. Wait for 10 ms to 20 ms.

7. Stop V_BUSpulsing [set VBUS_CHRG (bit 6) of the OTG Control (clear) register to

logic 0].

8. Discharge V_BUSfor about 30 ms [by using VBUS_DISCHRG (bit 5) of the OTG

Control (set) register], optional.

The B-device must complete both data line pulsing and V_BUSpulsing within 100 ms.

9.3.2 A-device responding to SRP

The A-device must be able to respond to one of the two SRP events: data line pulsing or

V_BUSpulsing. When data line pulsing is used, the ISP1761 can detect DP pulsing. This

means that the peripheral-only device must initiate data line pulsing through DP. A

dual-role device will always initiate data line pulsing through DP.

To enable the SRP detection through the V_BUSpulsing, set A_B_SESS_VLD (bit 1) in the

OTG Interrupt Enable Fall and OTG Interrupt Enable Rise registers.

To enable the SRP detection through the DP pulsing, set DP_SRP (bit 2) in the OTG

Interrupt Enable Rise register.

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9.4 Host Negotiation Protocol (HNP)

HNP is used to transfer control of the host role between the default host (A-device) and

the default peripheral (B-device) during a session. When the A-device is ready to give up

its role as a host, it will condition the B-device using SetFeature (b_hnp_enable) and will

go into suspend. If the B-device wants to use the bus at that time, it signals a disconnect

to the A-device. Then, the A-device will take the role of a peripheral and the B-device will

take the role of a host.

9.4.1 Sequence of HNP events

The sequence of events for HNP as observed on the USB bus is illustrated in Figure 14.

A-device

1

6

8

3

B-device

5

2

7

4

DP Composite

004aaa079

DP driven

Legend

Pull-up dominates

Pull-down dominates

Normal bus activity

Fig 14. HNP sequence of events

As can be seen in Figure 14:

1. The A-device completes using the bus and stops all bus activity, that is, suspends the

bus.

2. The B-device detects that the bus is idle for more than 5 ms and begins HNP by

turning off the pull-up on DP. This allows the bus to discharge to the SE0 state.

3. The A-device detects SE0 on the bus and recognizes this as a request from the

B-device to become a host. The A-device responds by turning on its DP pull-up within

3 ms of ﬁrst detecting SE0 on the bus.

4. After waiting for 30 µs to ensure that the DP line is not HIGH because of the residual

effect of the B-device pull-up, the B-device notices that the DP line is HIGH and the

DM line is LOW, that is, J state. This indicates that the A-device has recognized the

HNP request from the B-device. At this point, the B-device becomes a host and

asserts bus reset to start using the bus. The B-device must assert the bus reset, that

is, SE0, within 1 ms of the time that the A-device turns on its pull-up.

5. When the B-device completes using the bus, it stops all bus activities. Optionally, the

B-device may turn on its DP pull-up at this time.

Remark: The bus idle state will generate a DC suspend interrupt corresponding to the

toggle of the SUSP bit in the DcInterrupt register (address: 218h), when accordingly

enabled.

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6. The A-device detects lack of bus activity for more than 3 ms and turns off its DP

pull-up. Alternatively, if the A-device has no further need to communicate with the

B-device, the A-device may turn off V_BUSand end the session.

7. The B-device turns on its pull-up.

8. After waiting 30 µs to ensure that the DP line is not HIGH because of the residual

effect of the A-device pull-up, the A-device notices that the DP-line is HIGH and the

DM line is LOW, indicating that the B-device is signaling a connect and is ready to

respond as a peripheral. At this point, the A-device becomes a host and asserts the

bus reset to start using the bus.

9.4.2 OTG state diagrams

Figure 15 and Figure 16 show state diagrams for the dual-role A-device and the dual-role

B-device, respectively. For a detailed explanation, refer to Ref. 3 “On-The-Go Supplement

to the USB Speciﬁcation Rev. 1.3”.

The OTG state machine is implemented with software. The inputs to the state machine

come from four sources: hardware signals from the USB bus, software signals from the

application program, internal variables with the state machines, and timers:

• Hardware inputs: Include id, a_vbus_vld, a_sess_vld, b_sess_vld, b_sess_end,

a_conn, b_conn, a_bus_suspend, b_bus_suspend, a_bus_resume, b_bus_resume,

a_srp_det and b_se0_srp. All these inputs can be derived from the OTG Interrupt and

OTG Status registers.

• Software inputs: Include a_bus_req, a_bus_drop and b_bus_req.

• Internal variables: Include a_set_b_hnp_en, b_hnp_enable and b_srp_done.

• Timers: The HNP state machine uses four timers: a_wait_vrise_tmr,

a_wait_bcon_tmr, a_aidl_bdis_tmr and b_ase0_brst, tmr. All timers are started on

entry to and reset on exit from their associated states. The ISP1761 provides a

programmable timer that can be used as any of these four timers.

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b_idle

drv_vbus/

chrg_vbus/

loc_conn/

loc_sof/

START

a_idle

drv_vbus/

chrg_vbus/

loc_conn/

loc_sof/

id

id | a_bus_req |

a_bus_drop/ &

(a_sess_vld/ &

b_conn/)

(a_bus_req |

a_srp_det)

id | a_bus_drop |

a_wait_bcon_tmout

a_wait_vfall

a_wait_vrise

drv_vbus

loc_conn/

loc_sof/

drv_vbus/

loc_conn/

loc_sof/

id | a_bus_drop

b_bus_suspend

id | a_bus_drop |

a_vbus_vld |

a_wait_vrise_tmout

id | a_bus_drop

a_vbus_err

drv_vbus/

loc_conn/

loc_sof/

a_vbus_vld/

a_peripheral

drv_vbus

loc_conn

loc_sof/

a_wait_bcon

a_vbus_vld/

drv_vbus

loc_conn/

loc_sof/

b_conn/ &

a_set_b_hnp_en/

b_conn/ &

a_set_b_hnp_en

id |

b_conn/ |

b_conn

id |

a_bus_drop

a_bus_drop |

a_aidl_bdis_tmout

a_bus_req |

b_bus_resume

a_suspend

drv_vbus

loc_conn/

loc_sof/

a_host

drv_vbus

loc_conn/

loc_sof

a_bus_req/ |

a_suspend_req

004aaa566

Fig 15. Dual-role A-device state diagram

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Hi-Speed USB OTG controller

a_idle

drv_vbus/

chrg_vbus/

loc_conn/

loc_sof/

START

b_idle

drv_vbus/

chrg_vbus/

loc_conn/

loc_sof/

id/

b_bus_req &

b_sess_end &

b_se0_srp

id/ |

b_sess_vld/

id/ |

b_srp_done

id/ |

b_sess_vld/

b_host

chrg_vbus/

loc_conn/

loc_sof

b_srp_init

pulse loc_conn

pulse chrg_vbus

loc_sof/

id/ |

b_sess_vld/

b_sess_vld

b_bus_req/ |

a_conn/

a_conn

a_bus_resume |

b_ase0_brst_tmout

b_wait_acon

chrg_vbus/

loc_conn/

loc_sof/

b_peripheral

chrg_vbus/

loc_conn

b_bus_req &

b_hnp_en &

a_bus_suspend

loc_sof/

004aaa567

Fig 16. Dual-role B-device state diagram

9.4.3 HNP implementation and OTG state machine

The OTG state machine is the software behind all the OTG functionality. It is implemented

in the microprocessor system that is connected to the ISP1761. The ISP1761 provides

registers for all input status, the output control and timers to fully support the state

machine transitions in Figure 15 and Figure 16. These registers include:

• OTG Control register: Provides control to V_BUSdriving, charging or discharging, data

line pull-up or pull-down, SRP detection, and so on.

• OTG Status register: Provides status detection on V_BUSand data lines including ID,

V_BUSsession valid, session end, overcurrent and bus status.

• OTG Interrupt Latch register: Provides interrupts for status change in OTG Interrupt

Status register bits and the OTG Timer time-out event.

• OTG Interrupt Enable Fall and OTG Interrupt Enable Rise registers: Provide interrupt

mask for OTG Interrupt Latch register bits.

• OTG Timer register: Provides 0.01 ms base programmable timer for use in the OTG

state machine.

The following steps are required to enable an OTG interrupt:

1. Set the polarity and level-triggering or edge-triggering mode of the HW Mode Control

register.

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2. Set the corresponding bits of the OTG Interrupt Enable Rise and OTG Interrupt

Enable Fall registers.

3. Set bit OTG_IRQ_E of the HcInterruptEnable register (bit 10).

4. Set bit GLOBAL_INTR_EN of the HW Mode Control register (bit 0).

When an interrupt is generated on HC_IRQ, perform these steps in the interrupt service

routine to get the related OTG status:

1. Read the HcInterrupt register. If OTG_IRQ (bit 10) is set, then step 2.

2. Read the OTG Interrupt Latch register. If any of the bits 0 to 4 are set, then step 3.

3. Read the OTG Status register.

The OTG state machine routines are called when any of the inputs is changed. These

inputs come from either OTG registers (hardware) or application program (software). The

outputs of the state machine include control signals to the OTG register (for hardware)

and states or error codes (for software).

The ISP1761 can be conﬁgured in OTG mode or in pure host or peripheral mode.

Programming the ISP1761 in OTG mode is done by conﬁguring bit 10 of the OTG control

register. This will enable OTG-speciﬁc mechanisms controlled by the OTG control register

bits.

When the OTG protocol is not implemented by the software, the ISP1761 can be used as

a host or a peripheral. In this case, bit 10 of the OTG control register will be set to logic 0.

The host or peripheral functionality is determined by bit 7 of the OTG Control register.

Programming of OTG registers is done by a SET and RESET scheme. An OTG register

has two parts: a 16-bit SET and a 16-bit RESET. Writing logic 1 in a certain position to the

SET-type dedicated 16-bit register part will set the respective bit to logic 1 while writing

logic 1 to the RESET-type 16-bit dedicated register will change the corresponding bit to

logic 0.

9.5 OTG controller registers

Table 79. OTG controller-speciﬁc register overview

Address

Register

Reset value

References

037Xh to 038Xh OTG registers

-

Table 80. Address mapping of registers: 32-bit data bus mode

Address

Byte 3

Byte 2

Byte 1

Byte 0

Device ID registers

0370h

Product ID (read only)

Vendor ID (read only)

OTG Control (set)

OTG Control register

0374h

OTG Control (clear)

OTG Interrupt registers

0378h

037Ch

0380h

0384h

reserved

OTG Status (read only)

OTG Interrupt Latch (clear)

OTG Interrupt Latch (set)

OTG Interrupt Enable Fall (clear)

OTG Interrupt Enable Rise (clear)

OTG Interrupt Enable Fall (set)

OTG Interrupt Enable Rise (set)

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Table 80. Address mapping of registers: 32-bit data bus mode …continued

Address

Byte 3

Byte 2

Byte 1

Byte 0

OTG Timer register

0388h

OTG Timer (Lower word: clear)

OTG Timer (Higher word: clear)

OTG Timer (Lower word: set)

OTG Timer (Higher word: set)

038Ch

Table 81. Address mapping of registers: 16-bit data bus mode

Address

Byte 1

Byte 0

Reference

Device ID registers

0370h

0372h

Vendor ID (read only)

Section 9.5.1.1 on page 92

Section 9.5.1.2 on page 92

Product ID (read only)

OTG Control register

0374h

0376h

OTG Control (set)

OTG Control (clear)

Section 9.5.2.1 on page 93

OTG Interrupt registers

0378h

037Ah

037Ch

037Eh

0380h

0382h

0384h

0386h

OTG Status (read only)

Section 9.5.3.1 on page 94

reserved

-

OTG Interrupt Latch (set)

OTG Interrupt Latch (clear)

OTG Interrupt Enable Fall (set)

OTG Interrupt Enable Fall (clear)

OTG Interrupt Enable Rise (set)

OTG Interrupt Enable Rise (clear)

Section 9.5.3.2 on page 95

Section 9.5.3.3 on page 96

Section 9.5.3.4 on page 96

OTG Timer register

0388h

038Ah

038Ch

038Eh

OTG Timer (Lower word: set)

Section 9.5.4.1 on page 97

OTG Timer (Lower word: clear)

OTG Timer (Higher word: set)

OTG Timer (Higher word: clear)

9.5.1 Device Identiﬁcation registers

9.5.1.1 Vendor ID register

Table 82 shows the bit description of the register.

Table 82. Vendor ID - Vendor Identiﬁer (address 0370h) register: bit description

Bit

Symbol

Access

Value

Description

NXP Semiconductors’ Vendor ID

15 to 0

VENDOR_ID[15:0]

R

04CCh

9.5.1.2 Product ID register (R: 0372h)

The bit description of the register is given in Table 83.

Table 83. Product ID - Product Identiﬁer register (address 0372h) bit description

Bit

Symbol

Access

Value

Description

15 to 0

PRODUCT_ID[15:0]

R

1761h

Product ID of the ISP1761

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9.5.2 OTG Control register

9.5.2.1 OTG Control register

Table 84 shows the bit allocation of the register.

Table 84. OTG Control register (address set: 0374h, clear: 0376h) bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

reserved^[1]

OTG_

DISABLE

OTG_SE0_

EN

BDIS_

ACON_EN

Reset

Access

Bit

0

R/S/C

7

0

R/S/C

6

0

R/S/C

5

0

R/S/C

4

0

R/S/C

3

0

R/S/C

2

0

R/S/C

1

0

R/S/C

0

Symbol

SW_SEL_

HC_DC

VBUS_

CHRG

VBUS_

DISCHRG

VBUS_

DRV

SEL_CP_

EXT

DM_PULL

DOWN

DP_PULL

DOWN

DP_PULL

UP

Reset

1

0

1

0

Access

R/S/C

[1] The reserved bits should always be written with the reset value.

Table 85. OTG Control register (address set: 0374h, clear: 0376h) bit description

Bit^[1]

Symbol

Description

15 to 11 -

reserved for future use

10

9

OTG_DISABLE

0 — OTG functionality enabled

1 — OTG disabled; pure host or peripheral

OTG_SE0_EN

This bit is used by the host controller to send SE0 on remote

connect.

0 — No SE0 sent on remote connect detection

1 — SE0 (bus reset) sent on remote connect detection

Remark: This bit is normally set when the B-device goes into the

B_WAIT_ACON state (recommended sequence: LOC_CONN =

0 → DELAY → 0 ms → OTG_SEQ_EN = 1 → SEL_HC_DC = 0)

and is cleared when it comes out of the B_WAIT_ACON state.

8

7

BDIS_ACON_EN Enables the A-device to connect if the B-device disconnect is

detected

SW_SEL_HC_

DC

In software HNP mode, this bit selects between the host controller

and the peripheral controller.

0 — Host controller connected to ATX

1 — Peripheral controller connected to ATX

This bit is set to logic 1 by hardware when there is an event

corresponding to the BDIS_ACON interrupt. BDIS_ACON_EN is set

and there is an automatic pull-up connection on remote disconnect.

6

5

4

3

VBUS_CHRG

Connect V_BUSto V_CC(I/O)through a resistor

VBUS_DISCHRG Discharge V_BUSto ground through a resistor

VBUS_DRV

Drive V_BUSto 5 V using the charge pump

0 — Internal charge pump selected

1 — External charge pump selected

SEL_CP_EXT

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Table 85. OTG Control register (address set: 0374h, clear: 0376h) bit description …continued

Bit^[1]

Symbol

Description

2

DM_PULLDOWN DM pull-down:

0 — Disable

1 — Enable

1

0

DP_PULLDOWN DP pull-down:

0 — Disable

1 — Enable

DP_PULLUP

0 — The pull-up resistor is disconnected from the DP line. The data

line pulsing is stopped.

1 — An internal 1.5 kΩ pull-up resistor is present on the DP line.

The data line pulsing is started.

Remark: When port 1 is in peripheral mode or it plays the role of a

peripheral while the OTG functionality is enabled, it depends on the

setting of DP_PULLUP and the V_BUSsensing signal to connect the

DP line to HIGH through a pull-up resister. V_BUSis an internal signal.

When 5 V is present on the V_BUSpin, V_BUS= 1.

[1] To use port 1 as a host controller, write 0080 0018h to this register after power-on. To use port 1 as a

peripheral controller, write 0006 0400h to this register after power-on.

9.5.3 OTG Interrupt registers

9.5.3.1 OTG Status register

This register indicates the current state of the signals that can generate an interrupt. The

bit allocation of the register is given in Table 86.

Table 86. OTG Status register (address 0378h) bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

reserved

B_SE0_

SRP

Reset

Access

Bit

0

R

7

0

R

6

0

R

5

0

R

4

0

R

3

0

R

1

0

R

0

R

2

Symbol

B_SESS_

END

reserved

RMT_

CONN

ID

DP_SRP

A_B_SESS VBUS_VLD

_VLD

[1]

Reset

0

Access

R

[1] The reset value depends on the corresponding OTG status. For details, see Table 87.

Table 87. OTG Status register (address 0378h) bit description

Bit

Symbol

Description

15 to 9

8

-

reserved for future use

2 ms of SE0 detected in the B-idle state

B_SE0_SRP

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Table 87. OTG Status register (address 0378h) bit description …continued

Bit

Symbol

B_SESS_END

-

Description

7

V_BUS< 0.8 V

6 to 5

reserved

4

3

2

1

0

RMT_CONN

ID

Remote connect detection

ID pin digital input

DP asserted during SRP

DP_SRP

A_B_SESS_VLD A-session valid for the A-device. B-session valid for the B-device.

VBUS_VLD A-device V_BUSvalid comparator, indicates V_BUS> 4.4 V

9.5.3.2 OTG Interrupt Latch register

The OTG Interrupt Latch register indicates the source that generated the interrupt. The

status of this register bits depends on the settings of the Interrupt Enable Fall and

Interrupt Enable Rise registers, and the occurrence of the respective events.

The bit allocation of the register is given in Table 88.

Table 88. OTG Interrupt Latch register (address set: 037Ch, clear: 037Eh) bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

reserved^[1]

OTG_TMR_

TIMEOUT

B_SE0_

SRP

Reset

Access

Bit

0

R/S/C

7

0

R/S/C

6

0

R/S/C

4

0

R/S/C

3

0

R/S/C

1

0

R/S/C

0

R/S/C

R

2

5

Symbol

B_SESS_

END

BDIS_

ACON

OTG_

RESUME

RMT_

CONN

ID

DP_SRP

A_B_SESS VBUS_VLD

_VLD

Reset

0

Access

R/S/C

[1] The reserved bits should always be written with the reset value.

Table 89. OTG Interrupt Latch register (address set: 037Ch, clear: 037Eh) bit description

Bit

Symbol

Description

15 to 10

-

reserved for future use

9

8

7

6

5

4

3

2

1

OTG_TMR_TIMEOUT OTG timer time-out

B_SE0_SRP

B_SESS_END

BDIS_ACON

OTG_RESUME

RMT_CONN

ID

2 ms of SE0 detected in the B-idle state

V_BUS< 0.8 V

Indicates that the BDIS_ACON event has occurred

J → K resume change detected

Remote connect detection

Indicates change on pin ID

DP asserted during SRP

DP_SRP

A_B_SESS_VLD

A-session valid for the A-device. B-session valid for the

B-device.

0

VBUS_VLD

Indicates change in the VBUS_VLD status

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9.5.3.3 OTG Interrupt Enable Fall register

Table 90 shows the bit allocation of this register that enables interrupts on transition from

HIGH-to-LOW.

Table 90. OTG Interrupt Enable Fall register (address set: 0380h, clear: 0382h) bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

reserved^[1]

B_SE0_

SRP

Reset

Access

Bit

0

R/S/C

7

0

R/S/C

6

0

R/S/C

5

0

R/S/C

4

0

R/S/C

3

0

R/S/C

2

0

R/S/C

1

0

R/S/C

0

Symbol

B_SESS_

END

reserved

RMT_

CONN

ID

reserved

A_B_SESS VBUS_VLD

_VLD

Reset

0

Access

R/S/C

[1] The reserved bits should always be written with the reset value.

Table 91. OTG Interrupt Enable Fall register (address set: 0380h, clear: 0382h) bit

description

Bit

Symbol

Description

15 to 9

8

-

reserved for future use

B_SE0_SRP

IRQ asserted when the bus exits from at least 2 ms of the SE0

state

7

B_SESS_END

IRQ asserted when V_BUS> 0.8 V

reserved

6 to 5

-

4

3

2

1

RMT_CONN

IRQ asserted on RMT_CONN removal

IRQ asserted on the ID pin transition from HIGH to LOW

reserved

ID

-

A_B_SESS_VLD

IRQ asserted on removing A-session valid for the A-device or

B-session valid for the B-device condition

0

VBUS_VLD

IRQ asserted on the falling edge of V_BUS

9.5.3.4 OTG Interrupt Enable Rise register

This register (see Table 92 for bit allocation) enables interrupts on transition from

LOW-to-HIGH.

Table 92. OTG Interrupt Enable Rise register (address set: 0384h, clear: 0386h) bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

reserved^[1]

OTG_TMR_

TIMEOUT

B_SE0_

SRP

Reset

0

Access

R/S/C

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Bit

7

6

5

4

3

2

1

0

Symbol

B_SESS_

END

BDIS_

ACON

OTG_

RESUME

RMT_

CONN

ID

DP_SRP

A_B_SESS VBUS_VLD

_VLD

Reset

0

Access

R/S/C

[1] The reserved bits should always be written with the reset value.

Table 93. OTG Interrupt Enable Rise register (address set: 0384h, clear: 0386h) bit

description

Bit

Symbol

Description

15 to 10

-

reserved

9

8

OTG_TMR_TIMEOUT IRQ asserted on OTG timer time-out

B_SE0_SRP

IRQ asserted when at least 2 ms of SE0 is detected in the

B-idle state

7

6

5

4

3

2

1

B_SESS_END

BDIS_ACON

OTG_RESUME

RMT_CONN

ID

IRQ asserted when V_BUSis less than 0.8 V

IRQ asserted on BDIS_ACON condition

IRQ asserted on J-K resume

IRQ asserted on RMT_CONN

IRQ asserted on the ID pin transition from LOW to HIGH

IRQ asserted when DP is asserted during SRP

DP_SRP

A_B_SESS_VLD

IRQ asserted on the A-session valid for the A-device or on the

B-session valid for the B-device

0

VBUS_VLD

IRQ asserted on the rising edge of V_BUS

9.5.4 OTG Timer register

9.5.4.1 OTG Timer register

This is a 32-bit register organized as two 16-bit ﬁelds. These two ﬁelds have separate set

and clear addresses. Table 94 shows the bit allocation of the register.

Table 94. OTG Timer register (address low word set: 0388h, low word clear: 038Ah; high word set: 038Ch, high

word clear: 038Eh) bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

START_

TMR

reserved^[1]

Reset

Access

Bit

0

R/S/C

23

R/S/C

22

R/S/C

21

R/S/C

20

R/S/C

19

R/S/C

18

R/S/C

17

R/S/C

16

Symbol

Reset

Access

Bit

TIMER_INIT_VALUE[23:16]

0

R/S/C

9

0

R/S/C

8

R/S/C

15

R/S/C

14

R/S/C

13

R/S/C

12

R/S/C

11

R/S/C

10

Symbol

Reset

Access

TIMER_INIT_VALUE[15:8]

0

R/S/C

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Bit

7

6

5

4

3

2

1

0

Symbol

Reset

Access

TIMER_INIT_VALUE[7:0]

0

R/S/C

[1] The reserved bits should always be written with the reset value.

Table 95. OTG Timer register (address low word set: 0388h, low word clear: 038Ah; high

word set: 038Ch, high word clear: 038Eh) bit description

Bit

Symbol

Description

31

START_TMR

This is the start/stop bit of the OTG timer. Writing logic 1 will

cause the OTG timer to load TMR_INIT_VALUE into the counter

and start to count. Writing logic 0 will stop the timer. This bit is

automatically cleared when the OTG timer is timed out.

0 — stop the timer

1 — start the timer

30 to 24

23 to 0

-

reserved

TIMER_INIT_

VALUE[23:0]

These bits deﬁne the initial value used by the OTG timer. The

timer interval is 0.01 ms. Maximum time allowed is 167.772 s.

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10. Peripheral controller

10.1 Introduction

The design of the peripheral controller in the ISP1761 is compatible with the NXP

ISP1582 Hi-Speed Universal Serial Bus peripheral controller IC. The functionality of the

peripheral controller in the ISP1761 is similar to the ISP1582 in 16-bit bus mode. In

addition, the register sets are also similar, with only a few variations.

The USB protocol and data transfer operations of the peripheral controller are executed

using external ﬁrmware. The external microcontroller or microprocessor can access the

peripheral controller-speciﬁc registers through the local bus interface. The transfer of data

between a microprocessor and the peripheral controller can be done in PIO mode or

programmed DMA mode.

For details on general functional description of the peripheral controller, refer to the

ISP1582 data sheet. For details on the software programming, refer to Ref. 6 “ISP1582/83

Firmware Programming Guide (AN10039)” and Ref. 4 “ISP1582/83 Control Pipe

(AN10031)”.

10.1.1 Direct Memory Access (DMA)

The DMA controller of the ISP1761 is used to transfer data between the system memory

and endpoints buffers. It is a slave DMA controller that requires an external DMA master

to control the transfer.

10.1.1.1 DMA for the IN endpoint

When the internal DMA is enabled and at least one buffer is free, the DC_DREQ line is

asserted. The external DMA controller then starts negotiating for control of the bus. As

soon as it has access, it asserts the DC_DACK line and starts writing data. The burst

length is programmable. When the number of bytes equal to the burst length has been

written, the DC_DREQ line is de-asserted. As a result, the DMA controller de-asserts the

DC_DACK line and releases the bus. At that moment, the whole cycle restarts for the next

burst. When the buffer is full, the DC_DREQ line is de-asserted and the buffer is validated,

which means that it is sent to the host at the next IN token. When the DMA transfer is

terminated, the buffer is also validated, even if it is not full.

10.1.1.2 DMA for the OUT endpoint

When the internal DMA is enabled and at least one buffer is full, the DC_DREQ line is

asserted. The external DMA controller then starts negotiating for control of the bus. As

soon as it has access, it asserts the DC_DACK line and starts reading data. The burst

length is programmable. When the number of bytes equal to the burst length has been

read, the DC_DREQ line is de-asserted. As a result, the DMA controller de-asserts the

DC_DACK line and releases the bus. At that moment, the whole cycle restarts for the next

burst. When all the data is read, the DC_DREQ line is de-asserted and the buffer is

cleared. This means that it can be overwritten when a new packet arrives.

10.1.1.3 DMA initialization

To reduce the power consumption, a controllable clock that drives DMA controller circuits

is turned off, by default. If the DMA functionality is required by an application, DMACLKON

(bit 9) of the Mode register (address: 020Ch) must be enabled during initialization of the

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peripheral controller. If DMA is not required by the application, DMACLKON can be

permanently disabled to save current. The burst counter, DMA bus width, and the polarity

of DC_DREQ and DC_DACK must accordingly be set.

The ISP1761 supports only counter mode DMA transfer. To enable counter mode, ensure

that DIS_XFER_CNT in the DcDMAConﬁguration register (address: 0238h) is set to zero.

Before starting the DMA transfer, preset the interrupt enable bit IEDMA in the Interrupt

Enable register (address: 0214h) and the DMA Interrupt Enable register (address: 0254h).

The ISP1761 supports two interrupt trigger modes: level and edge. The pulse width, which

in edge mode, is determined by setting the Interrupt Pulse Width register (address:

0280h). The default value is 1Eh, which indicates that the interrupt pulse width is 1 µs.

The minimum interrupt pulse width is approximately 30 ns when set to logic 1. Do not

write a zero to this register.

The interrupt polarity must also be correctly set.

Remark: DMA can apply to all endpoints on the chip. It, however, can only take place for

one endpoint at a time. The selected endpoint is assigned by setting the endpoint number

in the DMA Endpoint register (address: 0258h). It will also internally redirect the endpoint

buffer of the selected endpoint to the DMA controller bus. In addition, it requires a

preceding process to program the endpoint type, the endpoint maximum packet size, and

the direction of the endpoint.

When setting the Endpoint Index register (address: 022Ch), the endpoint buffer of the

selected endpoint is directed to the internal CPU bus for the PIO access. Therefore, it is

required to reconﬁgure the Endpoint Index register with endpoint number, which is not an

endpoint number in use for the DMA transfer to avoid any confusion.

10.1.1.4 Starting DMA

Dynamically assign the DMA Transfer Counter register (address: 0234h) for each DMA

transfer.

The transfer will end once transfer counter reaches zero. Bit DMA_XFER_OK in the DMA

Interrupt Reason register (address: 0250h) will be asserted to indicate that the DMA

transfer has successfully stopped. If the transfer counter is larger than the burst counter,

the DC_DREQ signal will drop at the end of each burst transfer. DC_DREQ will reassert at

the beginning of each burst. For a 32-bit DMA transfer, the minimum burst length is

4 bytes. This means that the burst length is only one DMA cycle. Therefore, DC_DREQ

and DC_DACK will toggle by each DMA cycle. For a 16-bit DMA transfer, the minimum

burst length is 2 bytes.

Setting bit GDMA read or GDMA write in the DMA Command register (address: 0230h)

will start the DMA transfer.

Remark: DACK and CS_N should not be active at the same time.

10.1.1.5 DMA stop and interrupt handling

The DMA transfer will either successfully be completed or terminated, which can be

identiﬁed by reading the status in the DcInterrupt register (address: 0218h) and DMA

Interrupt Reason register (address: 0250h).

If bit DMA_XFER_OK in the DMA Interrupt Reason register is asserted, it means that the

transfer counter has reached zero and the DMA transfer is successfully stopped.

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If bit INT_EOT in the DMA Interrupt Reason register is set, it indicates that a short or

empty packet is received. This means that DMA transfer terminated. Normally, for an OUT

transfer, it means that remote host wishes to terminate the DMA transfer.

If both the bits DMA_XFER_OK and INT_EOT are set, it means that the transfer counter

reached zero and the last packet of the transfer is a short packet. Therefore, the DMA

transfer is successfully stopped.

Setting bit GDMA Stop in the DMA Command register (address: 0230h) will force the

DMA to stop and bit GDMA_STOP in the DMA Interrupt Reason register (address: 0250h)

will be set to indicate this event.

Setting bit Reset DMA in the DMA Command register (address: 0230h) will force the DMA

to stop and initialize the DMA core to its power-on reset state.

10.2 Endpoint description

Each USB peripheral is logically composed of several independent endpoints. An

endpoint acts as a terminus of a communication ﬂow between the USB host and the USB

peripheral. At design time, each endpoint is assigned a unique endpoint identiﬁer; see

Table 96. The combination of the peripheral address (given by the host during

enumeration), the endpoint number, and the transfer direction allows each endpoint to be

uniquely referenced.

The peripheral controller has 8 kB of internal FIFO memory, which is shared among the

enabled USB endpoints. The two control endpoints are ﬁxed 64 bytes long. Any of the

seven IN and seven OUT endpoints can separately be enabled or disabled. The endpoint

type (interrupt, isochronous or bulk) and packet size of these endpoints can individually be

conﬁgured, depending on the requirements of the application. Optional double buffering

increases the data throughput of these data endpoints.

Table 96. Endpoint access and programmability

Endpoint

identiﬁer

Maximum packet

size

Double buffering Endpoint type

Direction

EP0SETUP

EP0RX

EP0TX

EP1RX

EP1TX

EP2RX

EP2TX

EP3RX

EP3TX

EP4RX

EP4TX

EP5RX

EP5TX

EP6RX

8 bytes (ﬁxed)

64 bytes (ﬁxed)

programmable

no

set-up token

OUT

IN

no

control OUT

no

control IN

yes

programmable

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

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Table 96. Endpoint access and programmability …continued

Endpoint

Maximum packet

size

Double buffering Endpoint type

Direction

identiﬁer

EP6TX

EP7RX

EP7TX

programmable

yes

programmable

IN

OUT

IN

10.3 Clear buffer

Use clear buffer when data needs to be discarded under the following conditions:

• IN endpoint: If the host aborts a read operation, the residual data in the IN endpoint

buffer must be cleared using the Clear Buffer command. See Table 126.

• OUT endpoint: If the host aborts a write operation, the residual data in the OUT

endpoint buffer must be cleared using the CLBUF bit. See Table 113.

For example, to clear a double buffer data IN endpoint 1, set the following registers in the

ﬁrmware as:

1. Assign a value to the Endpoint Index register. It can be any value other than the value

assigned to the DMA Endpoint register. In this example, do not assign 3h to the

Endpoint Index register. See remark in Section 10.6.1.

2. Assign DMA Endpoint register = 3h

3. Assign DMA Command register = 0Fh

4. Assign DMA Endpoint register = 3h

5. Assign DMA Command register = 0Fh

For example, to clear a double buffer data OUT endpoint 1, set the following registers in

the ﬁrmware as:

1. Assign a value to the DMA Endpoint register. It can be any value other than the value

assigned to the Endpoint Index register. In this example, do not assign 2h to the DMA

Endpoint register. See remark in Section 10.6.1.

2. Assign Endpoint Index register = 2h

3. Assign Control Function register = 10Fh

4. Assign Endpoint Index register = 2h

5. Assign Control Function register = 10Fh

10.4 Differences between the ISP1761 and ISP1582 peripheral controllers

This section explains the variations between the ISP1761 and ISP1582 peripheral

controllers in terms of register bits and their associated functions.

10.4.1 ISP1761 initialization registers

• The ISP1582 supports 16-bit bus access. The register addresses are 2 bytes aligned.

The ISP1761 supports 16-bit and 32-bit bus accesses. To support the 32-bit access,

the DATA_BUS_WIDTH bit in the HW Mode Control register must be initialized.

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• In 32-bit bus access mode, the register addresses are 4 bytes aligned. Therefore, the

DcBufferStatus register can be accessed using the upper-two bytes of the Buffer

Length register.

• The SOFTCT bit in the Mode register has been removed. The DP_PULLUP control bit

in the OTG Control register is used in the ISP1761 in place of the SOFTCT bit in the

ISP1582.

• Added the Interrupt Pulse Width register to deﬁne the pulse width of the interrupt

signal.

10.4.2 ISP1761 DMA

• DMA mode 1 and DMA mode 2 in the ISP1582 are not supported in the ISP1761.

• In DMA mode 0, counter mode is supported and external-EOT mode has been

removed.

• Supports the 16-bit and 32-bit DMA. Does not support the 8-bit DMA.

• The RD_N and WR_N signals are available for the DMA data strobe. These signals

are also used as data strobe signals during the PIO access. An internal multiplex will

redirect these signals to the DMA controller for the DMA transfer or to registers for the

PIO access.

For details on the DMA programming, refer to application note Ref. 7 “ISP1761 Peripheral

DMA Initialization (AN10040)”.

10.4.3 ISP1761 peripheral suspend indication

• A HIGH level on the DC_SUSPEND/WAKEUP_N pin indicates that the peripheral has

entered suspend mode. The pulse indication mode has been removed.

10.4.4 ISP1761 interrupt and DMA common mode

In common mode, the interrupt and DMA signals of the peripheral controller are redirected

to pins that are used by the host controller because the host controller and the peripheral

controller share the same pins. Some control bits must be set in the HW Mode Control

register, see Section 8.3.1.

10.5 Peripheral controller-speciﬁc registers

Table 97. Peripheral controller-speciﬁc register overview

Address Register

Reset value

References

Initialization registers

0200h

020Ch

0210h

0212h

0214h

0300h

0374h

Address

00h

Section 10.5.1 on page 104

Section 10.5.2 on page 105

Section 10.5.3 on page 106

Section 10.5.4 on page 107

Section 10.5.5 on page 108

Section 8.3.1 on page 43

Section 9.5.2.1 on page 93

Mode

0000h

Interrupt Conﬁguration

Debug

FCh

0008h

DcInterruptEnable

HW Mode Control

OTG Control

0000 0000h

0000 0086h

Data ﬂow registers

022Ch Endpoint Index

20h

Section 10.6.1 on page 109

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Table 97. Peripheral controller-speciﬁc register overview …continued

Address Register

Reset value

00h

References

0228h

0220h

021Ch

021Eh

0204h

0208h

Control Function

Data Port

Section 10.6.2 on page 110

Section 10.6.3 on page 112

Section 10.6.4 on page 112

Section 10.6.5 on page 113

Section 10.6.6 on page 114

Section 10.6.7 on page 114

0000 0000h

0000h

Buffer Length

DcBufferStatus

Endpoint MaxPacketSize

Endpoint Type

00h

0000h

DMA registers

0230h

0234h

0238h

023Ch

0250h

0254h

0258h

0264h

DMA Command

FFh

Section 10.7.1 on page 116

Section 10.7.2 on page 117

Section 10.7.3 on page 118

Section 10.7.4 on page 119

Section 10.7.5 on page 120

Section 10.7.6 on page 121

Section 10.7.7 on page 121

Section 10.7.8 on page 122

DMA Transfer Counter

DcDMAConﬁguration

DMA Hardware

0000 0000h

0001h

04h

DMA Interrupt Reason

DMA Interrupt Enable

DMA Endpoint

0000h

00h

DMA Burst Counter

0004h

General registers

0218h

0270h

0274h

0278h

027Ch

0280h

0284h

DcInterrupt

0000 0000h

0015 8210h

0000h

Section 10.8.1 on page 123

Section 10.8.2 on page 125

Section 10.8.3 on page 125

Section 10.8.4 on page 125

Section 10.8.5 on page 126

Section 10.8.6 on page 126

Section 10.8.7 on page 127

DcChipID

Frame Number

DcScratch

0000h

Unlock Device

Interrupt Pulse Width

Test Mode

0000h

001Eh

00h

10.5.1 Address register

This register sets the USB assigned address and enables the USB peripheral. Table 98

shows the bit allocation of the register.

The DEVADDR[6:0] bits will be cleared whenever a bus reset, a power-on reset or a soft

reset occurs. The DEVEN bit will be cleared whenever a power-on reset or a soft reset

occurs, and will remain unchanged on a bus reset.

In response to standard USB request SET_ADDRESS, ﬁrmware must write the (enabled)

peripheral address to the Address register, followed by sending an empty packet to the

host. The new peripheral address is activated when the peripheral receives

acknowledgment from the host for the empty packet token.

Table 98. Address register (address 0200h) bit allocation

Bit

7

DEVEN

0

6

5

4

3

2

1

0

Symbol

Reset

DEVADDR[6:0]

0

Bus reset

Access

unchanged

R/W

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Table 99. Address register (address 0200h) bit description

Bit

Symbol

Description

7

DEVEN

Device Enable: Logic 1 enables the device. The device will not

respond to the host, unless this bit is set.

6 to 0

DEVADDR[6:0]

Device Address: This ﬁeld speciﬁes the USB device peripheral.

10.5.2 Mode register

This register consists of 2 bytes (bit allocation: see Table 100).

The Mode register controls resume, suspend and wake-up behavior, interrupt activity, soft

reset and clock signals.

Table 100. Mode register (address 020Ch) bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

reserved^[1]

DMACLK

ON

VBUSSTAT

Reset

0

Bus reset

Access

Bit

0

R/W

4

R/W

3

R/W

2

R/W

1

R/W

0

7

6

5

Symbol

Reset

CLKAON

SNDRSU

GOSUSP

SFRESET GLINTENA WKUPCS

reserved^[1]

0

Bus reset

Access

unchanged

R/W

unchanged

R/W

[1] The reserved bits should always be written with the reset value.

Table 101. Mode register (address 020Ch) bit description

Bit

Symbol

Description

15 to 10

9

-

reserved

DMACLKON DMA Clock On:

1 — Supply clock to the DMA circuit.

0 — Power saving mode. The DMA circuit will stop completely to save

power.

8

7

VBUSSTAT

CLKAON

V_BUSStatus: This bit reﬂects the V_BUSpin status.

When implementing a pure host or peripheral, the OTG_DISABLE bit in

the OTG Control register (374h) must be set to logic 1 so that the

VBUSSTAT bit is updated with the correct value.

Clock Always On:

1 — Enable the Clock-Always-On feature

0 — Disable the Clock-Always-On feature

When the Clock-Always-On feature is disabled, a GOSUSP event can

stop the clock. The clock is stopped after a delay of approximately 2 ms.

Therefore, the peripheral controller will consume less power.

If the Clock-Always-On feature is enabled, clocks are always running

and the GOSUSP event is unable to stop the clock while the peripheral

controller enters the suspend state.

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Table 101. Mode register (address 020Ch) bit description …continued

Bit

Symbol

Description

6

SNDRSU

Send Resume: Writing logic 1, followed by logic 0 will generate an

upstream resume signal of 10 ms duration, after a 5 ms delay.

5

4

GOSUSP

SFRESET

Go Suspend: Writing logic 1, followed by logic 0 will activate suspend

mode.

Soft Reset: Writing logic 1, followed by logic 0 will enable a

software-initiated reset to the ISP1761. A soft reset is similar to a

hardware-initiated reset using the RESET_N pin.

3

GLINTENA

Global Interrupt Enable: Logic 1 enables all interrupts. Individual

interrupts can be masked by clearing the corresponding bits in the

DcInterruptEnable register.

When this bit is not set, an unmasked interrupt will not generate an

interrupt trigger on the interrupt pin. If the global interrupt, however, is

enabled while there is any pending unmasked interrupt, an interrupt

signal will immediately be generated on the interrupt pin. If the interrupt

is set to pulse mode, the interrupt events that were generated before the

global interrupt is enabled may be dropped.

2

WKUPCS

Wake up on Chip Select: Logic 1 enables wake-up through a valid

register read on the ISP1761. A read will invoke the chip clock to restart.

A write to the register before the clock is stable may cause

malfunctioning.

1 to 0

-

reserved

10.5.3 Interrupt Conﬁguration register

This 1 byte register determines the behavior and polarity of the INT output. The bit

allocation is shown in Table 102. When the USB SIE receives or generates an ACK, NAK

or NYET, it will generate interrupts depending on three Debug mode ﬁelds.

CDBGMOD[1:0] — Interrupts for the control endpoint 0

DDBGMODIN[1:0] — Interrupts for the DATA IN endpoints 1 to 7

DDBGMODOUT[1:0] — Interrupts for the DATA OUT endpoints 1 to 7

The Debug mode settings for CDBGMOD, DDBGMODIN and DDBGMODOUT allow you

to individually conﬁgure when the ISP1761 sends an interrupt to the external

microprocessor. Table 104 lists the available combinations.

Bit INTPOL controls the signal polarity of the INT output: active HIGH or LOW, rising or

falling edge. For level-triggering, bit INTLVL must be made logic 0. By setting INTLVL to

logic 1, an interrupt will generate a pulse of 60 ns (edge-triggering).

Table 102. Interrupt Conﬁguration register (address 0210h) bit allocation

Bit

7

6

5

4

3

2

1

INTLVL

0

INTPOL

0

Symbol

Reset

CDBGMOD[1:0]

DDBGMODIN[1:0]

DDBGMODOUT[1:0]

1

Bus reset

Access

unchanged unchanged

R/W R/W

R/W

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Table 103. Interrupt Conﬁguration register (address 0210h) bit description

Bit Symbol Description

7 to 6 CDBGMOD[1:0]

5 to 4 DDBGMODIN[1:0]

Control 0 Debug Mode: For values, see Table 104

Data Debug Mode IN: For values, see Table 104

3 to 2 DDBGMODOUT[1:0] Data Debug Mode OUT: For values, see Table 104

1

INTLVL

Interrupt Level: Selects signaling mode on output INT: 0 = level;

1 = pulsed. In pulsed mode, an interrupt produces a 60 ns pulse.

Bus reset value: unchanged.

0

INTPOL

Interrupt Polarity: Selects the signal polarity on output INT: 0 =

active LOW; 1 = active HIGH. Bus reset value: unchanged.

Table 104. Debug mode settings

Value CDBGMOD

DDBGMODIN

DDBGMODOUT

00h

interrupt on all ACK and

NAK

interrupt on all ACK and

NAK

interrupt on all ACK, NYET and

NAK

01h

1Xh

interrupt on all ACK

interrupt on ACK

interrupt on ACK and NYET

interrupt on all ACK and

ﬁrst NAK^[1]

interrupt on all ACK and

ﬁrst NAK^[1]

interrupt on all ACK, NYET and

ﬁrst NAK^[1]

[1] First NAK: The ﬁrst NAK on an IN or OUT token after a previous ACK response.

10.5.4 Debug register

This register can be accessed using address 0212h in 16-bit bus access mode or using

the upper-two bytes of the Interrupt Conﬁguration register in 32-bit bus access mode. For

the bit allocation, see Table 105.

Table 105. Debug register (address 0212h) bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Reset

reserved^[1]

0

Bus reset

Access

Bit

0

R/W

0

R/W

7

R/W

6

R/W

5

R/W

3

R/W

2

R/W

1

4

Symbol

Reset

reserved^[1]

DEBUG

0

1

0

Bus reset

Access

0

R/W

[1] The reserved bits should always be written with the reset value.

Table 106. Debug register (address 0212h) bit allocation

Bit

Symbol

-

Description

15 to 1

0

reserved

DEBUG

Always set this bit to logic 0 in both 16-bit and 32-bit accesses.

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10.5.5 DcInterruptEnable register

This register enables or disables individual interrupt sources. The interrupt for each

endpoint can individually be controlled through the associated IEPnRX or IEPnTX bits,

here n represents the endpoint number. All interrupts can globally be disabled through

bit GLINTENA in the Mode register (see Table 100).

An interrupt is generated when the USB SIE receives or generates an ACK or NAK on the

USB bus. The interrupt generation depends on Debug mode settings of bit ﬁelds

CDBGMOD[1:0], DDBGMODIN[1:0] and DDBGMODOUT[1:0].

All data IN transactions use the Transmit buffers (TX) that are handled by DDBGMODIN

bits. All data OUT transactions go through the Receive buffers (RX) that are handled by

DDBGMODOUT bits. Transactions on control endpoint 0 (IN, OUT and SETUP) are

handled by CDBGMOD bits.

Interrupts caused by events on the USB bus (SOF, suspend, resume, bus reset, set up

and high-speed status) can also be individually controlled. A bus reset disables all

enabled interrupts, except bit IEBRST (bus reset) that remains unchanged.

The DcInterruptEnable register consists of 4 bytes. The bit allocation is given in Table 107.

Table 107. DcInterruptEnable - Device Controller Interrupt Enable register (address 0214h) bit allocation

Bit

31

30

29

28

reserved^[1]

27

26

25

24

Symbol

Reset

IEP7TX

IEP7RX

0

Bus reset

Access

Bit

0

R/W

17

0

R/W

16

R/W

23

22

21

20

19

18

Symbol

Reset

IEP6TX

IEP6RX

IEP5TX

IEP5RX

IEP4TX

IEP4RX

IEP3TX

0

IEP3RX

0

Bus reset

Access

Bit

0

R/W

9

R/W

8

15

14

13

12

11

10

Symbol

Reset

IEP2TX

IEP2RX

IEP1TX

IEP1RX

IEP0TX

IEP0RX

reserved^[1]IEP0SETUP

0

Bus reset

Access

Bit

0

R/W

6

0

R/W

1

0

R/W

7

5

4

3

2

0

Symbol

Reset

IEVBUS

IEDMA

0

IEHS_STA

IERESM

IESUSP

IEPSOF

IESOF

0

IEBRST

0

Bus reset

Access

0

unchanged

R/W

[1] The reserved bits should always be written with the reset value.

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Table 108. DcInterruptEnable - Device Controller Interrupt Enable register (address 0214h)

bit description

Bit

31 to 26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

Symbol

-

Description

reserved

EP7TX

EP7RX

EP6TX

EP6RX

EP5TX

EP5RX

EP4TX

EP4RX

EP3TX

EP3RX

EP2TX

EP2RX

EP1TX

IEP1RX

IEP0TX

IEP0RX

-

Logic 1 enables interrupt from the indicated endpoint.

Logic 1 enables interrupt from the control IN endpoint 0.

Logic 1 enables interrupt from the control OUT endpoint 0.

reserved

8

IEP0SETUP Logic 1 enables interrupt for the set-up data received on endpoint 0.

7

IEVBUS

IEDMA

Logic 1 enables interrupt for V_BUSsensing.

6

Logic 1 enables interrupt on detecting a DMA status change.

Logic 1 enables interrupt on detecting a high-speed status change.

Logic 1 enables interrupt on detecting a resume state.

Logic 1 enables interrupt on detecting a suspend state.

Logic 1 enables interrupt on detecting a pseudo SOF.

Logic 1 enables interrupt on detecting an SOF.

5

IEHS_STA

IERESM

IESUSP

IEPSOF

IESOF

4

3

2

1

0

IEBRST

Logic 1 enables interrupt on detecting a bus reset.

10.6 Data ﬂow registers

10.6.1 Endpoint Index register

The Endpoint Index register selects a target endpoint for register access by the

microcontroller. The register consists of 1 byte, and the bit allocation is shown in

Table 109.

The following registers are indexed:

• Buffer Length

• DcBufferStatus

• Control Function

• Data Port

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• Endpoint MaxPacketSize

• Endpoint Type

For example, to access the OUT data buffer of endpoint 1 using the Data Port register, the

Endpoint Index register must be written ﬁrst with 02h.

Remark: The Endpoint Index register and the DMA Endpoint register must not point to the

same endpoint, irrespective of IN and OUT.

Table 109. Endpoint Index register (address 022Ch) bit allocation

Bit

7

6

5

4

3

2

1

0

DIR

0

Symbol

Reset

reserved^[1]

EP0SETUP

ENDPIDX[3:0]

0

1

0

Bus reset

Access

0

R/W

[1] The reserved bits should always be written with the reset value.

Table 110. Endpoint Index register (address 022Ch) bit description

Bit

7 to 6

5

Symbol

Description

-

reserved

EP0SETUP

Endpoint 0 Set up: Selects the SETUP buffer for endpoint 0.

0 — Data buffer

1 — SETUP buffer

Must be logic 0 for access to endpoints other than set-up token buffer.

4 to 1 ENDPIDX[3:0] Endpoint Index: Selects the target endpoint for register access of buffer

length, buffer status, control function, data port, endpoint type and

MaxPacketSize.

0

DIR

Direction bit: Sets the target endpoint as IN or OUT.

0 — Target endpoint refers to OUT (RX) FIFO

1 — Target endpoint refers to IN (TX) FIFO

Table 111. Addressing of endpoint buffers

Buffer name

SETUP

EP0SETUP

ENDPIDX

00h

DIR

0

1

0

Control OUT

Control IN

Data OUT

Data IN

00h

0

00h

1

0Xh

0

0Xh

1

10.6.2 Control Function register

The Control Function register performs the buffer management on endpoints. It consists

of 1 byte, and the bit conﬁguration is given in Table 112. The register bits can stall, clear or

validate any enabled data endpoint. Before accessing this register, the Endpoint Index

register must ﬁrst be written to specify the target endpoint.

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Table 112. Control Function register (address 0228h) bit allocation

Bit

7

6

5

4

CLBUF

0

3

VENDP

0

2

DSEN

0

1

0

STALL

0

Symbol

Reset

reserved^[1]

STATUS

0

Bus reset

Access

0

R/W

W

R/W

[1] The reserved bits should always be written with the reset value.

Table 113. Control Function register (address 0228h) bit description

Bit Symbol Description

7 to 5 - reserved

4

CLBUF

Clear Buffer: Logic 1 clears the RX buffer of the indexed endpoint; the TX

buffer is not affected. The RX buffer is automatically cleared once the endpoint

is completely read. This bit is set only when it is necessary to forcefully clear

the buffer.

Remark: If using double buffer, to clear both the buffers issue the CLBUF

command two times, that is, set and clear this bit two times.

3

2

VENDP

DSEN

Validate Endpoint: Logic 1 validates data in the TX FIFO of an IN endpoint for

sending on the next IN token. In general, the endpoint is automatically validated

when its FIFO byte count has reached the endpoint MaxPacketSize. This bit is

set only when it is necessary to validate the endpoint with the FIFO byte count

that is below the Endpoint MaxPacketSize.

Data Stage Enable: This bit controls the response of the ISP1761 to a control

transfer. After the completion of the set-up stage, ﬁrmware must determine

whether a data stage is required. For control OUT, ﬁrmware will set this bit and

the ISP1761 goes into the data stage. Otherwise, the ISP1761 will NAK the

data stage transfer. For control IN, ﬁrmware will set this bit before writing data to

the TX FIFO and validate the endpoint. If no data stage is required, ﬁrmware

can immediately set the STATUS bit after the set-up stage.

Remark: The DSEN bit is cleared once the OUT token is acknowledged by the

device and the IN token is acknowledged by the PC host. This bit cannot be

read back and reading this bit will return logic 0.

1

STATUS Status Acknowledge: Only applicable for control IN and OUT.

This bit controls the generation of ACK or NAK during the status stage of a

SETUP transfer. It is automatically cleared when the status stage is completed

and a SETUP token is received. No interrupt signal will be generated.

0 — Sends NAK

1 — Sends an empty packet following the IN token (peripheral-to-host) or ACK

following the OUT token (host-to-peripheral)

Remark: The STATUS bit is cleared to zero once the zero-length packet is

acknowledged by the device or the PC host.

Remark: Data transfers preceding the status stage must ﬁrst be fully completed

before the STATUS bit can be set.

0

STALL

Stall Endpoint: Logic 1 stalls the indexed endpoint. This bit is not applicable for

isochronous transfers.

Remark: Stalling a data endpoint will confuse the Data Toggle bit about the

stalled endpoint because the internal logic picks up from where it is stalled.

Therefore, the Data Toggle bit must be reset by disabling and re-enabling the

corresponding endpoint (by setting bit ENABLE to logic 0, followed by logic 1 in

the Endpoint Type register) to reset the PID.

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10.6.3 Data Port register

This register provides direct access for a microcontroller to the FIFO of the indexed

endpoint.

Peripheral to host (IN endpoint): After each write, an internal counter is automatically

incremented, by two in 16-bit mode and four in 32-bit mode, to the next location in the TX

FIFO. When all bytes have been written (FIFO byte count = endpoint MaxPacketSize), the

buffer is automatically validated. The data packet will then be sent on the next IN token.

Whenever required, the Control Function register (bit VENDP) can validate the endpoint

whose byte count is less than MaxPacketSize.

Remark: The buffer can automatically be validated using the Buffer Length register.

Host to peripheral (OUT endpoint): After each read, an internal counter is automatically

decremented, by two in 16-bit mode and four in 32-bit mode, to the next location in the RX

FIFO. When all bytes have been read, the buffer contents are automatically cleared. A

new data packet can then be received on the next OUT token. Buffer contents can also be

cleared through the Control Function register (bit CLBUF), whenever it is necessary to

forcefully clear contents.

The Data Port register description when the ISP1761 is in 32-bit mode is given in

Table 114.

Table 114. Data Port register (address 0220h) bit description

Bit

Symbol

Access Value

Description

31 to 0 DATAPORT R/W

[31:0]

0000 0000h

Data Port: A 500 ns delay starting from the reception of the endpoint

interrupt may be required for the ﬁrst read from the data port.

The Data Port register description when the ISP1761 is in 16-bit mode is given in

Table 115.

Table 115. Data Port register (address 0220h) bit description

Bit

Symbol

Access Value

Description

15 to 0

DATAPORT

[15:0]

R/W

0000 0000h Data Port: A 500 ns delay starting from the reception of the endpoint

interrupt may be required for the ﬁrst read from the data port.

10.6.4 Buffer Length register

This register determines the current packet size (DATACOUNT) of the indexed endpoint

FIFO. The bit description is given in Table 116.

The Buffer Length register is automatically loaded with the FIFO size, when the Endpoint

MaxPacketSize register is written (see Table 120). A smaller value can be written when

required. After a bus reset, the Buffer Length register is made zero.

IN endpoint: When the data transfer is performed in multiples of MaxPacketSize, the

Buffer Length register is not signiﬁcant. This register is useful only when transferring data

that is not a multiple of MaxPacketSize. The following two examples demonstrate the

signiﬁcance of the Buffer Length register.

Example 1: Consider that the transfer size is 512 bytes and the MaxPacketSize is

programmed as 64 bytes, the Buffer Length register need not be ﬁlled. This is because the

transfer size is a multiple of MaxPacketSize, and MaxPacketSize packets will be

automatically validated because the last packet is also of MaxPacketSize.

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Example 2: Consider that the transfer size is 510 bytes and the MaxPacketSize is

programmed as 64 bytes, the Buffer Length register should be ﬁlled with 62 bytes just

before the microcontroller writes the last packet of 62 bytes. This ensures that the last

packet, which is a short packet of 62 bytes, is automatically validated.

Use the VENDP bit in the Control register if you are not using the Buffer Length register.

This is applicable only to PIO mode access.

OUT endpoint: The DATACOUNT value is automatically initialized to the number of data

bytes sent by the host on each ACK.

Remark: When using a 16-bit microprocessor bus, the last byte of an odd-sized packet is

output as the lower byte (LSByte).

Table 116. Buffer Length register (address 021Ch) bit description

Bit

Symbol

Access Value

Description

15 to 0 DATACOUNT R/W

[15:0]

0000h

Data Count: Determines the current packet size of the indexed endpoint

FIFO.

10.6.5 DcBufferStatus register

This register is accessed using an index. The endpoint index must ﬁrst be set before

accessing this register for the corresponding endpoint. It reﬂects the status of the endpoint

FIFO. Table 117 shows the bit allocation of the DcBufferStatus register.

Remark: This register is not applicable to the control endpoint.

Remark: For the endpoint IN data transfer, ﬁrmware must ensure a 200 ns delay between

writing of the data packet and reading the DcBufferStatus register. For the endpoint OUT

data transfer, ﬁrmware must also ensure a 200 ns delay between the reception of the

endpoint interrupt and reading the DcBufferStatus register. For more information, refer to

Ref. 10 “ISP1760/1 Frequently Asked Questions (AN10054)”.

Table 117. DcBufferStatus - Device Controller Buffer Status register (address 021Eh) bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

Reset

reserved^[1]

BUF1

BUF0

0

Bus reset

Access

R/W

R

[1] The reserved bits should always be written with the reset value.

Table 118. DcBufferStatus - Device Controller Buffer Status register (address 021Eh) bit

description

Bit

Symbol

-

Description

7 to 2

1 to 0

reserved

BUF[1:0]

Buffer:

00 — The buffers are not ﬁlled.

01 — One of the buffers is ﬁlled.

10 — One of the buffers is ﬁlled.

11 — Both the buffers are ﬁlled.

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10.6.6 Endpoint MaxPacketSize register

This register determines the maximum packet size for all endpoints, except control 0. The

register contains 2 bytes, and the bit allocation is given in Table 119.

Each time the register is written, the Buffer Length register of the corresponding endpoint

is re-initialized to the FFOSZ ﬁeld value. NTRANS bits control the number of transactions

allowed in a single microframe for high-speed isochronous and interrupt endpoints only.

Table 119. Endpoint MaxPacketSize register (address 0204h) bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Reset

reserved^[1]

NTRANS[1:0]

FFOSZ[10:8]

0

Bus reset

Access

Bit

R/W

7

R/W

6

R/W

5

R/W

4

R/W

3

R/W

2

R/W

1

R/W

0

Symbol

Reset

FFOSZ[7:0]

0

Bus reset

Access

R/W

[1] The reserved bits should always be written with the reset value.

Table 120. Endpoint MaxPacketSize register (address 0204h) bit description

Bit

Symbol

Description

15 to 13

12 to 11

-

reserved

NTRANS[1:0] Number of Transactions: HS mode only.

00 — One packet per microframe

01 — Two packets per microframe

10 — Three packets per microframe

11 — reserved

These bits are applicable only for isochronous or interrupt

transactions.

10 to 0

FFOSZ[10:0] FIFO Size: Sets the FIFO size, in bytes, for the indexed endpoint.

Applies to both high-speed and full-speed operations.

The ISP1761 supports all the transfers given in Ref. 1 “Universal Serial Bus Speciﬁcation

Rev. 2.0”.

Each programmable FIFO can be independently conﬁgured using its Endpoint

MaxPacketSize register (R/W: 04h), but the total physical size of all enabled endpoints (IN

plus OUT), including set-up token buffer, control IN and control OUT, must not exceed

8192 bytes.

10.6.7 Endpoint Type register

This register sets the endpoint type of the indexed endpoint: isochronous, bulk or

interrupt. It also serves to enable the endpoint and conﬁgure it for double buffering.

Automatic generation of an empty packet for a zero-length TX buffer can be disabled using

bit NOEMPKT. The register contains 2 bytes. See Table 121.

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Table 121. Endpoint Type register (address 0208h) bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Reset

reserved^[1]

0

Bus reset

Access

Bit

0

R/W

7

R/W

5

R/W

1

R/W

0

6

4

3

2

Symbol

Reset

reserved^[1]

NOEMPKT

ENABLE

DBLBUF

ENDPTYP[1:0]

0

Bus reset

Access

R/W

[1] The reserved bits should always be written with the reset value.

Table 122. Endpoint Type register (address 0208h) bit description

Bit

Symbol

Description

15 to 5

4

-

reserved

NOEMPKT

No Empty Packet: Logic 0 causes the ISP1761 to return a null length

packet for the IN token after the DMA IN transfer is complete. Set to

logic 1 to disable the generation of the null length packet.

3

ENABLE

Endpoint Enable: Logic 1 enables the FIFO of the indexed endpoint.

The memory size is allocated as speciﬁed in the Endpoint

MaxPacketSize register. Logic 0 disables the FIFO.

Remark: Stalling a data endpoint will confuse the Data Toggle bit on the

stalled endpoint because the internal logic picks up from where it has

stalled. Therefore, the Data Toggle bit must be reset by disabling and

re-enabling the corresponding endpoint (by setting bit ENABLE to

logic 0, followed by logic 1 in the Endpoint Type register) to reset the

PID.

2

DBLBUF

Double Buffering: Logic 1 enables double buffering for the indexed

endpoint. Logic 0 disables double buffering.

1 to 0

ENDPTYP[1:0] Endpoint Type: These bits select the endpoint type as follows.

00 — Not used

01 — Isochronous

10 — Bulk

11 — Interrupt

10.7 DMA registers

The Generic DMA (GDMA) transfer can be done by writing the proper opcode in the DMA

Command register. The control bits are given in Table 123.

GDMA read or write (opcode = 00h/01h) for Generic DMA slave mode

The GDMA (slave) can operate in counter mode. RD_N and WR_N are DMA data strobe

signals. These signals are also used as data strobe signals during the PIO access. An

internal multiplex will redirect these signals to the DMA Controller for the DMA transfer or

to registers for the PIO access.

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In counter mode, the DIS_XFER_CNT bit in the DcDMAConﬁguration register must be set

to logic 0. The DMA Transfer Counter register must be programmed before any DMA

command is issued. The DMA transfer counter is set by writing from the LSByte to the

MSByte (address: 234h to 237h). The DMA transfer count is internally updated only after

the MSByte is written. Once the DMA transfer is started, the transfer counter starts

decrementing and on reaching 0, the DMA_XFER_OK bit is set and an interrupt is

generated by the ISP1761.

The DMA transfer starts once the DMA command is issued. Any of the following three

ways will terminate this DMA transfer:

• Detecting an internal EOT (short packet on an OUT token)

• Resetting the DMA

• GDMA stop command

There are two interrupts that are programmable to differentiate the method of DMA

termination: the INT_EOT and DMA_XFER_OK bits in the DMA Interrupt Reason register.

For details, see Table 135.

Table 123. Control bits for GDMA read or write (opcode = 00h/01h)

Control bits

Mode register

DMACLKON

Description

Reference

Table 101

Table 130

Set DMACLKON to logic 1

DcDMAConﬁguration register

MODE[1:0]

WIDTH

Determines the active read or write data strobe signals

Selects the DMA bus width: 16-bit or 32-bit

DIS_XFER_CNT Disables the use of the DMA Transfer Counter

DMA Hardware register

DACK_POL,

DREQ_POL

Select the polarity of the DMA handshake signals

Table 132

Remark: The DMA bus defaults to 3-state, until a DMA command is executed. All the

other control signals are not 3-state.

10.7.1 DMA Command register

The DMA Command register is a 1-byte register (for bit allocation, see Table 124) that

initiates all DMA transfer activities on the DMA controller. The register is write-only:

reading it will return FFh.

Remark: The DMA bus will be in 3-state until a DMA command is executed.

Table 124. DMA Command register (address 0230h) bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

Reset

DMA_CMD[7:0]

1

Bus reset

Access

W

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Table 125. DMA Command register (address 0230h) bit description

Bit

Symbol

Description

7 to 0

DMA_CMD[7:0]

DMA command code; see Table 126.

Table 126. DMA commands

Code

Name

Description

00h

GDMA Read

Generic DMA IN token transfer: Data is transferred from the

external DMA bus to the internal buffer.

01h

GDMA Write

-

Generic DMA OUT token transfer: Data is transferred from the

internal buffer to the external DMA bus.

02h to 0Dh

0Eh

reserved

Validate Buffer Validate Buffer (for debugging only): Request from the

microcontroller to validate the endpoint buffer, following a

DMA-to-USB data transfer.

0Fh

Clear Buffer

Clear Buffer: Request from the microcontroller to clear the endpoint

buffer, after a DMA-to-USB data transfer. Logic 1 clears the TX

buffer of the indexed endpoint; the RX buffer is not affected. The TX

buffer is automatically cleared once data is sent on the USB bus.

This bit is set only when it is necessary to forcefully clear the buffer.

Remark: If using double buffer, to clear both the buffers issue the

Clear Buffer command two times, that is, set and clear this bit two

times.

10h

11h

-

reserved

Reset DMA

Reset DMA: Initializes the DMA core to its power-on reset state.

Remark: When the DMA core is reset during the Reset DMA

command, the DREQ, DACK, RD_N and WR_N handshake pins

will temporarily be asserted. This can confuse the external DMA

controller. To prevent this, start the external DMA controller only

after the DMA reset.

12h

13h

-

reserved

GDMA Stop

GDMA stop: This command stops the GDMA data transfer. Any

data in the OUT endpoint that is not transferred by the DMA will

remain in the buffer. The FIFO data for the IN endpoint will be

written to the endpoint buffer. An interrupt bit will be set to indicate

that the DMA Stop command is complete.

14h to FFh

-

reserved

10.7.2 DMA Transfer Counter register

This 4 bytes register sets up the total byte count for a DMA transfer (DMACR). It indicates

the remaining number of bytes left for transfer. The bit allocation is given in Table 127.

For IN endpoint — Because there is a FIFO in the ISP1761 DMA controller, some data

may remain in the FIFO during the DMA transfer. The maximum FIFO size is 8 bytes, and

the maximum delay time for the data to be shifted to endpoint buffer is 60 ns.

For OUT endpoint — Data will not be cleared for the endpoint buffer, until all the data has

been read from the DMA FIFO.

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Table 127. DMA Transfer Counter register (address 0234h) bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

DMACR4 = DMACR[31:24]

0

Bus reset

Access

Bit

R/W

23

R/W

22

R/W

21

R/W

20

R/W

19

R/W

18

R/W

17

R/W

16

Symbol

Reset

DMACR3 = DMACR[23:16]

0

Bus reset

Access

Bit

R/W

15

R/W

14

R/W

13

R/W

12

R/W

11

R/W

10

R/W

9

R/W

8

Symbol

Reset

DMACR2 = DMACR[15:8]

0

Bus reset

Access

Bit

R/W

7

R/W

6

R/W

5

R/W

4

R/W

3

R/W

2

R/W

1

R/W

0

Symbol

Reset

DMACR1 = DMACR[7:0]

0

Bus reset

Access

R/W

Table 128. DMA Transfer Counter register (address 0234h) bit description

Bit

Symbol

Description

31 to 24

23 to 16

15 to 8

7 to 0

DMACR4, DMACR[31:24]

DMACR3, DMACR[23:16]

DMACR2, DMACR[15:8]

DMACR1, DMACR[7:0]

DMA Counter 4: DMA transfer counter byte 4

DMA Counter 3: DMA transfer counter byte 3

DMA Counter 2: DMA transfer counter byte 2

DMA Counter 1: DMA transfer counter byte 1

10.7.3 DcDMAConﬁguration register

This register deﬁnes the DMA conﬁguration for GDMA mode. The DcDMAConﬁguration

register consists of 2 bytes. The bit allocation is given in Table 129.

Table 129. DcDMAConﬁguration - Device Controller Direct Memory Access Conﬁguration register (address 0238h)

bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Reset

reserved^[1]

0

Bus reset

Access

R/W

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Bit

7

6

5

4

3

2

1

0

Symbol

DIS_

reserved^[1]

MODE[1:0]

reserved

WIDTH

XFER_CNT

Reset

0

1

Bus reset

Access

R/W

[1] The reserved bits should always be written with the reset value.

Table 130. DcDMAConﬁguration - Device Controller Direct Memory Access Conﬁguration

register (address 0238h) bit description

Bit

Symbol

Description

15 to 8

7

-

reserved

DIS_XFER_CNT Disable Transfer Counter: Write logic 0 to perform DMA operation.

Logic 1 disables the DMA transfer counter (see Table 127).

6 to 4

3 to 2

-

reserved

MODE[1:0]

Mode:

00 — WR_N slave strobes data from the DMA bus into the

ISP1761; RD_N slave puts data from the ISP1761 on the DMA bus

01, 10, 11 — reserved

1

0

-

reserved

WIDTH

Width: This bit selects the DMA bus width for GDMA.

0 — 32-bit data bus

1 — 16-bit data bus

10.7.4 DMA Hardware register

The DMA Hardware register consists of 1 byte. The bit allocation is shown in Table 131.

This register determines the polarity of bus control signals (DACK and DREQ).

Table 131. DMA Hardware register (address 023Ch) bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

reserved^[1]

DACK_

POL

DREQ_

POL

reserved^[1]

Reset

0

1

0

Bus reset

Access

R/W

[1] The reserved bits should always be written with the reset value.

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Table 132. DMA Hardware register (address 023Ch) bit description

Bit

7 to 4

3

Symbol

Description

-

reserved

DACK_POL

DACK Polarity: Selects the DMA acknowledgment polarity.

0 — DACK is active LOW

1 — DACK is active HIGH

2

DREQ_POL

DREQ Polarity: Selects the DMA request polarity.

0 — DREQ is active LOW

1 — DREQ is active HIGH

1 to 0

-

reserved

10.7.5 DMA Interrupt Reason register

This 2-byte register shows the source(s) of DMA interrupt. Each bit is refreshed after a

DMA command is executed. An interrupt source is cleared by writing logic 1 to the

corresponding bit. On detecting the interrupt, the external microprocessor must read the

DMA Interrupt Reason register and mask it with the corresponding bits in the DMA

Interrupt Enable register to determine the source of the interrupt.

The bit allocation is given in Table 133.

Table 133. DMA Interrupt Reason register (address 0250h) bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

reserved

GDMA_

STOP

reserved

INT_EOT

reserved^[1]

DMA_

XFER_OK

Reset

0

Bus reset

Access

Bit

R/W

7

R/W

6

R/W

5

R/W

4

R/W

3

R/W

2

R/W

1

R/W

0

Symbol

Reset

reserved^[1]

0

Bus reset

Access

R/W

[1] The reserved bits should always be written with the reset value.

Table 134. DMA Interrupt Reason register (address 0250h) bit description

Bit

Symbol

Description

15 to 13

12

-

reserved

GDMA_STOP

GDMA Stop: When the GDMA_STOP command is issued to DMA

Command registers, it means that the DMA transfer has

successfully terminated.

11

10

-

reserved

INT_EOT

Internal EOT: Logic 1 indicates that an internal EOT is detected;

see Table 135.

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Table 134. DMA Interrupt Reason register (address 0250h) bit description …continued

Bit

9

Symbol

Description

-

reserved

8

DMA_XFER_OK DMA Transfer OK: Logic 1 indicates that the DMA transfer has

been completed, that is, DMA transfer counter has become zero.

7 to 0

-

reserved

Table 135. Internal EOT-functional relation with the DMA_XFER_OK bit

INT_EOT

DMA_XFER_OK Description

1

0

1

During the DMA transfer, there is a premature termination with

short packet.

1

0

DMA transfer is completed with a short packet and the DMA

transfer counter has reached 0.

DMA transfer is completed without any short packet and the

DMA transfer counter has reached 0.

10.7.6 DMA Interrupt Enable register

This 2 bytes register controls the interrupt generation of the source bits in the DMA

Interrupt Reason register. The bit allocation is given in Table 136. The bit description is

given in Table 134.

Logic 1 enables the interrupt generation. The values after a (bus) reset are logic 0

(disabled).

Table 136. DMA Interrupt Enable register (address 0254h) bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

reserved^[1]

IE_GDMA_ reserved^[1]

STOP

IE_INT_

EOT

reserved^[1]

IE_DMA_

XFER_OK

Reset

0

Bus reset

Access

Bit

R/W

7

R/W

6

R/W

5

R/W

4

R/W

3

R/W

2

R/W

1

R/W

0

Symbol

Reset

reserved^[1]

0

Bus reset

Access

R/W

[1] The reserved bits should always be written with the reset value.

10.7.7 DMA Endpoint register

This 1 byte register selects a USB endpoint FIFO as the source or destination for DMA

transfers. The bit allocation is given in Table 137.

Table 137. DMA Endpoint register (address 0258h) bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

reserved^[1]

EPIDX[2:0]

DMADIR

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Table 137. DMA Endpoint register (address 0258h) bit allocation …continued

Bit

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset

Bus reset

Access

0

R/W

[1] The reserved bits should always be written with the reset value.

Table 138. DMA Endpoint register (address 0258h) bit description

Bit

Symbol

-

Description

7 to 4

3 to 1

0

reserved

EPIDX[2:0]

DMADIR

Selects the indicated endpoint for DMA access

DMA Direction:

0 — Selects the RX/OUT FIFO for DMA write transfers

1 — Selects the TX/IN FIFO for DMA read transfers

The DMA Endpoint register must not reference the endpoint that is indexed by the

Endpoint Index register (022Ch) at any time. Doing so will result in data corruption.

Therefore, if the DMA Endpoint register is unused, point it to an unused endpoint. If the

DMA Endpoint register, however, is pointed to an active endpoint, the ﬁrmware must not

reference the same endpoint on the Endpoint Index register.

10.7.8 DMA Burst Counter register

The bit allocation of the register is given in Table 139.

Table 139. DMA Burst Counter register (address 0264h) bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Reset

reserved^[1]

BURSTCOUNTER[12:8]

0

Bus reset

Access

Bit

R/W

7

R/W

6

R/W

5

R/W

4

R/W

1

R/W

0

3

2

Symbol

Reset

BURSTCOUNTER[7:0]

0

1

0

Bus reset

Access

R/W

[1] The reserved bits should always be written with the reset value.

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Table 140. DMA Burst Counter register (address 0264h) bit description

Bit

Symbol

-

Description

15 to 13

12 to 0

reserved

BURST

Burst Counter: This register deﬁnes the burst length. The counter

COUNTER[12:0] must be programmed to be a multiple of two in 16-bit mode and four

in 32-bit mode.

The value of the burst counter must be programmed so that the

buffer counter is a factor of the burst counter. In 16-bit mode, DREQ

will drop at every DMA read or write cycle when the burst counter

equals 2. In 32-bit mode, DREQ will drop at every DMA read or

write cycle when the burst counter equals 4.

10.8 General registers

10.8.1 DcInterrupt register

The DcInterrupt register consists of 4 bytes. The bit allocation is given in Table 141.

When a bit is set in the DcInterrupt register, it indicates that the hardware condition for an

interrupt has occurred. When the DcInterrupt register content is non-zero, the INT output

will be asserted. On detecting the interrupt, the external microprocessor must read the

DcInterrupt register to determine the source of the interrupt.

Each endpoint buffer has a dedicated interrupt bit (EPnTX, EPnRX). In addition, various

bus states can generate an interrupt: resume, suspend, pseudo SOF, SOF and bus reset.

The DMA controller has only one interrupt bit: the source for a DMA interrupt is shown in

the DMA Interrupt Reason register.

Each interrupt bit can individually be cleared by writing logic 1. The DMA Interrupt bit can

be cleared by writing logic 1 to the related interrupt source bit in the DMA Interrupt

Reason register and writing logic 1 to the DMA bit of the DcInterrupt register.

Table 141. DcInterrupt - Device Controller Interrupt register (address 0218h) bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

reserved^[1]

EP7TX

EP7RX

0

Bus reset

Access

Bit

0

R/W

16

R/W

23

R/W

22

R/W

21

R/W

20

R/W

19

R/W

18

R/W

17

Symbol

Reset

EP6TX

0

EP6RX

0

EP5TX

0

EP5RX

0

EP4TX

0

EP4RX

0

EP3TX

0

EP3RX

0

Bus reset

Access

Bit

0

R/W

15

R/W

14

R/W

13

R/W

12

R/W

11

R/W

10

R/W

9

R/W

8

Symbol

Reset

EP2TX

0

EP2RX

0

EP1TX

0

EP1RX

0

EP0TX

0

EP0RX

0

reserved^[1]EP0SETUP

0

Bus reset

Access

0

R/W

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Bit

7

VBUS

0

6

DMA

0

5

4

3

SUSP

0

2

PSOF

0

1

SOF

0

BRESET

0

Symbol

Reset

HS_STAT

RESUME

0

Bus reset

Access

0

unchanged

R/W

[1] The reserved bits should always be written with the reset value.

Table 142. DcInterrupt - Device Controller Interrupt register (address 0218h) bit

description

Bit

31 to 26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

Symbol

-

Description

reserved

EP7TX

EP7RX

EP6TX

EP6RX

EP5TX

EP5RX

EP4TX

EP4RX

EP3TX

EP3RX

EP2TX

EP2RX

EP1TX

EP1RX

EP0TX

EP0RX

-

Logic 1 indicates the endpoint 7 TX buffer as interrupt source.

Logic 1 indicates the endpoint 7 RX buffer as interrupt source.

Logic 1 indicates the endpoint 6 TX buffer as interrupt source.

Logic 1 indicates the endpoint 6 RX buffer as interrupt source.

Logic 1 indicates the endpoint 5 TX buffer as interrupt source.

Logic 1 indicates the endpoint 5 RX buffer as interrupt source.

Logic 1 indicates the endpoint 4 TX buffer as interrupt source.

Logic 1 indicates the endpoint 4 RX buffer as interrupt source.

Logic 1 indicates the endpoint 3 TX buffer as interrupt source.

Logic 1 indicates the endpoint 3 RX buffer as interrupt source.

Logic 1 indicates the endpoint 2 TX buffer as interrupt source.

Logic 1 indicates the endpoint 2 RX buffer as interrupt source.

Logic 1 indicates the endpoint 1 TX buffer as interrupt source.

Logic 1 indicates the endpoint 1 RX buffer as interrupt source.

Logic 1 indicates the endpoint 0 data TX buffer as interrupt source.

Logic 1 indicates the endpoint 0 data RX buffer as interrupt source.

reserved

8

EP0SETUP Logic 1 indicates that a SETUP token was received on endpoint 0.

7

VBUS

Logic 1 indicates a transition from LOW to HIGH on V_BUS.

When implementing a pure host or peripheral, the OTG_DISABLE bit in

the OTG Control register (374h) must be set to logic 1 so that the VBUS

bit is updated with the correct value.

6

5

DMA

DMA status: Logic 1 indicates a change in the DMA Interrupt Reason

register.

HS_STAT

High-Speed Status: Logic 1 indicates a change from full-speed to

high-speed mode (HS connection). This bit is not set when the system

goes into the full-speed suspend.

4

3

RESUME

SUSP

Resume status: Logic 1 indicates that a status change from suspend

to resume (active) was detected.

Suspend status: Logic 1 indicates that a status change from active to

suspend was detected on the bus.

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Table 142. DcInterrupt - Device Controller Interrupt register (address 0218h) bit

description …continued

Bit

Symbol

Description

2

PSOF

Pseudo SOF interrupt: Logic 1 indicates that a pseudo SOF or µSOF

was received. Pseudo SOF is an internally generated clock signal

(full-speed: 1 ms period, high-speed: 125 µs period) that is not

synchronized to the USB bus SOF or µSOF.

1

0

SOF

SOF interrupt: Logic 1 indicates that a SOF or µSOF was received.

Bus Reset: Logic 1 indicates that a USB bus reset was detected.

BRESET

10.8.2 DcChipID register

This read-only register contains the chip identiﬁcation and hardware version numbers.

The ﬁrmware must check this information to determine functions and features supported.

The register contains 3 bytes, and the bit allocation is shown in Table 143.

Table 143. DcChipID - Device Controller Chip Identiﬁer register (address 0270h) bit description

Bit

Symbol

Access Value

Description

31 to 0

CHIPID[31:0]

R

0015 8210h Chip ID: This registers represents the hardware version number

(0015h) and the chip ID (8210h) for the peripheral controller.

10.8.3 Frame Number register

This read-only register contains the frame number of the last successfully received

Start-Of-Frame (SOF). The register contains 2 bytes, and the bit allocation is given in

Table 144.

Table 144. Frame Number register (address 0274h) bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Reset

reserved

MICROSOF[2:0]

SOFR[10:8]

0

Bus reset

Access

Bit

R

7

R

6

R

5

R

4

R

3

R

2

R

1

R

0

Symbol

Reset

SOFR[7:0]

0

Bus reset

Access

R

Table 145. Frame Number register (address 0274h) bit description

Bit

Symbol

Description

15 to 14

13 to 11

10 to 0

-

reserved

MICROSOF[2:0]

SOFR[10:0]

microframe number

frame number

10.8.4 DcScratch register

This 16-bit register can be used by the ﬁrmware to save and restore information. For

example, the device status before it enters the suspend state; see Table 146.

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Table 146. DcScratch - Device Controller Scratch register (address 0278h) bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Reset

SFIRH[7:0]

0

Bus reset

Access

Bit

unchanged

R/W

7

6

5

4

3

2

1

0

Symbol

Reset

SFIRL[7:0]

0

Bus reset

Access

unchanged

R/W

Table 147. DcScratch - Device Controller Scratch register (address 0278h) bit description

Bit

Symbol

Description

15 to 8

7 to 0

SFIRH[7:0]

SFIRL[7:0]

Scratch ﬁrmware information register (higher byte)

Scratch ﬁrmware information register (lower byte)

10.8.5 Unlock Device register

To protect registers from getting corrupted when the ISP1761 goes into suspend, the write

operation is disabled. In this case, when the chip resumes, the Unlock Device command

must ﬁrst be issued to this register before attempting to write to the rest of the registers.

This is done by writing unlock code (AA37h) to this register. The bit allocation of the

Unlock Device register is given in Table 148.

Table 148. Unlock Device register (address 027Ch) bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Reset

ULCODE[15:8] = AAh

not applicable

Bus reset

Access

Bit

not applicable

W

7

6

5

4

3

2

1

0

Symbol

Reset

ULCODE[7:0] = 37h

not applicable

Bus reset

Access

not applicable

W

Table 149. Unlock Device register (address 027Ch) bit description

Bit

Symbol

Description

15 to 0

ULCODE[15:0] Unlock Code: Writing data AA37h unlocks internal registers and

FIFOs for writing, following a resume.

10.8.6 Interrupt Pulse Width register

Table 150 shows the bit description of the register.

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Table 150. Interrupt Pulse Width register (address 0280h) bit description

Bit

Symbol

Access Value Description

15 to 0

INTR_PULSE_ R/W

WIDTH[15:0]

001Eh Interrupt Pulse Width: The interrupt signal pulse width is conﬁgurable

while it is in pulse signaling mode. The minimum pulse width is 3.33 ns

when this register is set to logic 1. The power-on reset value of 1Eh allows

a pulse of 1 µs to be generated.

10.8.7 Test Mode register

This 1 byte register allows the ﬁrmware to set the DP and DM pins to predetermined

states for testing purposes. The bit allocation is given in Table 151.

Remark: Only one bit can be set to logic 1 at a time.

Table 151. Test Mode register (address 0284h) bit allocation

Bit

7

FORCEHS

0

6

5

4

FORCEFS

0

3

PRBS

0

2

1

JSTATE

0

Symbol

Reset

reserved^[1]

KSTATE

SE0_NAK

0

Bus reset

Access

unchanged

R/W

unchanged

R/W

0

R/W

[1] The reserved bits should always be written with the reset value.

Table 152. Test Mode register (address 0284h) bit description

Bit

Symbol

Description

7

FORCEHS Force High-Speed: Logic 1^[1]forces the hardware to high-speed mode only

and disables the chirp detection logic.

6 to 5 -

reserved.

4

FORCEFS Force Full-Speed: Logic 1^[1]forces the physical layer to full-speed mode

only and disables the chirp detection logic.

3

2

1

0

PRBS

Logic 1^[2]sets pins DP and DM to toggle in a predetermined random pattern.

K State: Writing logic 1^[2]sets the DP and DM pins to the K state.

J State: Writing logic 1^[2]sets the DP and DM pins to the J state.

KSTATE

JSTATE

SE0_NAK

SE0 NAK: Writing logic 1^[2]sets pins DP and DM to a high-speed quiescent

state. The device only responds to a valid high-speed IN token with a NAK.

[1] Either FORCEHS or FORCEFS must be set at a time.

[2] Of the four bits, PRBS, KSTATE, JSTATE and SE0_NAK, only one bit must be set at a time.

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11. Power consumption

Table 153. Power consumption

Number of ports working

One port working (high-speed)

V_CC= 5.0 V, V_CC(I/O)= 3.3 V

V_CC= 3.3 V, V_CC(I/O)= 3.3 V

V_CC= 5.0 V, V_CC(I/O)= 1.8 V

V_CC= 3.3 V, V_CC(I/O)= 1.8 V

Two ports working (high-speed)

V_CC= 5.0 V, V_CC(I/O)= 3.3 V

V_CC= 3.3 V, V_CC(I/O)= 3.3 V

V_CC= 5.0 V, V_CC(I/O)= 1.8 V

V_CC= 3.3 V, V_CC(I/O)= 1.8 V

Three ports working (high-speed)

V_CC= 5.0 V, V_CC(I/O)= 3.3 V

V_CC= 3.3 V, V_CC(I/O)= 3.3 V

V_CC= 5.0 V, V_CC(I/O)= 1.8 V

V_CC= 3.3 V, V_CC(I/O)= 1.8 V

I_CC

90 mA

77 mA

82 mA

77 mA

110 mA

97 mA

102 mA

97 mA

130 mA

117 mA

122 mA

117 mA

The idle operating current, I_CC, that is, when the ISP1761 is in operational mode,

initialized and without any devices connected, is 70 mA. The additional current

consumption on I_CCis below 1 mA per port in the case of full-speed and low-speed

devices.

Deep-sleep suspend mode ensures the lowest power consumption when V_CCis always

supplied to the ISP1761. In this case, the suspend current, I_CC(susp), is typically about

150 µA at ambient temperature of +25 °C. The suspend current may increase if the

ambient temperature increases. For details, see Section 7.6.

In hybrid mode, when V_CCis disconnected I_CC(I/O)will generally be below 100 µA. The

average value is 60 µA to 70 µA.

Under the condition of constant read and write accesses occurring on the 32-bit data bus,

the maximum I_CC(I/O)drawn from V_CC(I/O)is measured as 25 mA, when the NXP ISP1761

evaluation board is connected to a BSQUARE PXA255 development platform. This

current will vary depending on the platform because of the different access timing, the

type of data patterns written on the data bus, and loading on the data bus.

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12. Limiting values

Table 154. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_CC(I/O)

V_CC(5V0)

V_{CC(C_IN)}

I_lu

Parameter

Conditions

Min

−0.5

-

Max

+4.6

+5.6

4.6

Unit

V

input/output supply voltage

supply voltage

V

supply voltage

V

latch-up current

V_I< 0 V or V_I> V_CC

-

100

mA

V

V_esd

electrostatic discharge voltage

storage temperature

I_LI< 1 µA (all pins)

−4000

−40

+4000

+125

T_stg

°C

13. Recommended operating conditions

Table 155. Recommended operating conditions

Symbol

Parameter

Conditions

Min

3.0

1.65

3

Typ

Max

3.6

Unit

V_CC(I/O)

input/output supply voltage

V_CC(I/O)= 3.3 V

V_CC(I/O)= 1.8 V

3.3

V

1.8

1.95

5.5

V

V_CC(5V0)

V_{CC(C_IN)}

T_amb

supply voltage

-

V

[1]

[2]

supply voltage

3.15

−40

-

3.6

V

ambient temperature

junction temperature

suspend supply current

-

+85

+125

-

°C

µA

T_j

-

I_CC(susp)

T_amb= 25 °C;

150

V_CC(5V0)= 3.3 V

[1] For details, see Figure 17 and Figure 18.

[2] Deep sleep suspend current.

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14. Static characteristics

Table 156. Static characteristics: digital pins

All digital pins^[1], except pins ID, PSW1_N, PSW2_N, PSW3_N and BAT_ON_N.

T

_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_CC(I/O)= 1.65 V to 1.95 V

V_IH

V_IL

HIGH-level input voltage

1.2

-

V

LOW-level input voltage

hysteresis voltage

-

0.5

V

V_hys

V_OL

V_OH

I_LI

0.4

-

0.7

V

LOW-level output voltage

HIGH-level output voltage

input leakage current

input capacitance

I_OL= 3 mA

-

0.22V_CC(I/O)

V

0.8V_CC(I/O)

-

V

V_I= 0 V to V_CC(I/O)

-

1

-

µA

pF

C_in

2.75

V_CC(I/O)= 3.0 V to 3.6 V

V_IH

V_IL

HIGH-level input voltage

2.0

-

V

LOW-level input voltage

hysteresis voltage

-

0.8

0.7

0.4

-

V

V_hys

V_OL

V_OH

I_LI

0.4

-

V

LOW-level output voltage

HIGH-level output voltage

input leakage current

input capacitance

I_OL= 3 mA

-

V

2.4

-

V

V_I= 0 V to V_CC(I/O)

-

1

µA

pF

C_in

2.75

-

[1] Includes OC1_N/V_BUS, OC2_N and OC3_N when used as digital overcurrent pins.

Table 157. Static characteristics: PSW1_N, PSW2_N, PSW3_N

V_CC(I/O)= 1.65 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

V_OL

Parameter

Conditions

Min

Typ

Max

0.4

-

Unit

V

LOW-level output voltage I_OL= 8 mA; pull-up to V_CC(5V0)

HIGH-level output voltage pull-up to V_CC(I/O)

-

V_OH

V_CC(I/O)

V

Table 158. Static characteristics: USB interface block (pins DM1 to DM3 and DP1 to DP3)

V_CC(I/O)= 1.65 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Input levels for high-speed

V_HSSQ

high-speed squelch detection

threshold voltage (differential signal

amplitude)

squelch detected

-

100

-

mV

no squelch

detected

150

V_HSDSC

high-speed disconnect detection

threshold voltage (differential signal detected

amplitude)

disconnect

625

-

mV

disconnect not

detected

525

+500

V_HSCM

high-speed data signaling common

mode voltage range (guideline for

receiver)

−50

ISP1761_5

Product data sheet

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130 of 163

ISP1761

NXP Semiconductors

Hi-Speed USB OTG controller

Table 158. Static characteristics: USB interface block (pins DM1 to DM3 and DP1 to DP3) …continued

V_CC(I/O)= 1.65 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Output levels for high-speed

V_HSOI

high-speed idle level voltage

−10

-

+10

440

mV

V_HSOH

high-speed data signaling

HIGH-level voltage

360

V_HSOL

high-speed data signaling LOW-level

voltage

−10

-

+10

mV

V_CHIRPJ

V_CHIRPK

chirp J level (differential voltage)

chirp K level (differential voltage)

700^[1]

−900^[1]

-

1100

mV

−500

Input levels for full-speed and low-speed

V_IH

HIGH-level input voltage

drive

2.0

2.7

-

V

V_IHZ

V_IL

HIGH-level input voltage (ﬂoating)

LOW-level input voltage

3.6

0.8

-

V_DI

differential input sensitivity

|V_DP− V_DM

|

0.2

0.8

V_CM

differential common mode voltage

range

2.5

Output levels for full-speed and low-speed

V_OH

HIGH-level output voltage

LOW-level output voltage

SE1 output voltage

2.8

0

-

3.6

0.3

-

V

V_OL

V_OSE1

V_CRS

0.8

1.3

output signal crossover voltage

2.0

[1] The HS termination resistor is disabled, and the pull-up resistor is connected. Only during reset, when both the hub and the device are

capable of the high-speed operation.

Table 159. Static characteristics: REF5V

V_CC(I/O)= 1.65 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_IH

HIGH-level input voltage

-

5

-

V

Table 160. Static characteristics: V_BUScomparators

V_CC(I/O)= 1.65 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min^[1]

4.4

Typ

Max^[2]

Unit

V_{A_VBUS_VLD}

V_{B_SESS_VLD}

A-device V_BUSvalid voltage

B-device session valid voltage

4.5

1.6

4.6

2.0

V

for A-device and

B-device

0.8

V_{hys(B_SESS_VLD)}B-device session valid hysteresis voltage

V_{B_SESS_END}B-device session end voltage

70

150

0.5

210

0.8

mV

V

0.2

[1] Minimum trigger voltage at extreme low temperature (−40 °C).

[2] Minimum trigger voltage at extreme high temperature (+85 °C).

ISP1761_5

Product data sheet

Rev. 05 — 13 March 2008

131 of 163

ISP1761

NXP Semiconductors

Hi-Speed USB OTG controller

Table 161. Static characteristics: V_BUSresistors

V_CC(I/O)= 1.65 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

R_UP(VBUS)

pull-up resistance on pin V_BUS

connect to REG3V3

281

680

-

Ω

when VBUS_CHRG = 1

R_DN(VBUS)

pull-down resistance on pin V_BUSconnect to ground when

VBUS_DISCHRG = 1

656

40

-

800

58.5

197

-

Ω

R_{I(idle)(VBUS)(A)}

R_{I(idle)(VBUS)(B)}

idle input resistance on pin V_BUSID pin LOW

(A-device)

100

280

kΩ

idle input resistance on pin V_BUSID pin HIGH

(B-device)

004aaa667

150

I

CP

(mA)

T

= −40 °C

25 °C

amb

100 °C

100

50

0

3

3.4

3.8

V

4.2

(V)

CC(C_IN)

Fig 17. Charge pump current versus voltage at various temperatures (worst case)

004aaa668

150

I

CP

(mA)

T

= −40°C

25 °C

amb

100 °C

100

50

0

3

3.4

3.8

4.2

V

(V)

CC(C_IN)

Fig 18. Charge pump current versus voltage at various temperatures (typical case)

ISP1761_5

Product data sheet

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132 of 163

ISP1761

NXP Semiconductors

Hi-Speed USB OTG controller

15. Dynamic characteristics

Table 162. Dynamic characteristics: system clock timing

V_CC(I/O)= 1.65 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Crystal oscillator

[2]

f_clk

clock frequency

crystal^[1]

oscillator

-

12

-

MHz

External clock input

J

external clock jitter

-

500

ps

%

V

δ

clock duty cycle

input voltage on pin XTAL1

rise time

50

-

V_i(XTAL1)

V_CC(I/O)

-

t_r

t_f

-

3

ns

fall time

[1] Recommended values for external capacitors when using a crystal are 22 pF to 27 pF.

[2] Recommended accuracy of the clock frequency is 50 ppm for the crystal and oscillator. The oscillator used depends on V_CC(I/O)

.

Table 163. Dynamic characteristics: CPU interface block

V_CC(I/O)= 1.65 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

SR

slew rate

standard load (rise, fall)

1

-

4

V/ns

Table 164. Dynamic characteristics: high-speed source electrical characteristics

V_CC(I/O)= 1.65 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Driver characteristics

t_HSR

rise time (10 % to 90 %)

500

40.5

-

ps

Ω

t_HSF

fall time (10 % to 90 %)

-

Z_HSDRV

driver output impedance (which

also serves as high-speed

termination)

includes the R_S

resistor

45

49.5

Clock timing

t_HSDRAT

high-speed data rate

microframe interval

479.76

124.9375

1

-

480.24

Mbit/s

µs

t_HSFRAM

125.0625

t_HSRFI

consecutive microframe interval

difference

four

high-speed

bit times

ns

Table 165. Dynamic characteristics: full-speed source electrical characteristics

V_CC(I/O)= 1.65 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Driver characteristics

t_FR

rise time

fall time

C_L= 50 pF; 10 % to

4

-

20

ns

90 % of |V_OH− V_OL

C_L= 50 pF; 90 % to

10 % of |V_OH− V_OL

|

t_FF

|

ISP1761_5

Product data sheet

Rev. 05 — 13 March 2008

133 of 163

ISP1761

NXP Semiconductors

Hi-Speed USB OTG controller

Table 165. Dynamic characteristics: full-speed source electrical characteristics …continued

V_CC(I/O)= 1.65 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

t_FRFM

differential rise and fall time

matching

90

-

111.1

%

Z_DRV

driver output impedance for

driver which is not high-speed

capable

28

-

44

Ω

Data timing: see Figure 19

t_FDEOP

source jitter for differential

full-speed timing

low-speed timing

−2

-

+5

ns

transition to SE0 transition

source SE0 interval of EOP

receiver SE0 interval of EOP

t_FEOPT

t_FEOPR

t_LDEOP

160

82

-

175

-

ns

upstream facing port source

jitter for differential transition to

SE0 transition

−40

+100

t_LEOPT

t_LEOPR

t_FST

source SE0 interval of EOP

receiver SE0 interval of EOP

1.25

670

-

1.5

-

µs

ns

width of SE0 interval during

differential transition

14

Table 166. Dynamic characteristics: low-speed source electrical characteristics

V_CC(I/O)= 1.65 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Driver characteristics

t_LR

transition time: rise time

75

90

-

300

125

ns

%

t_LF

transition time: fall time

t_LRFM

rise and fall time matching

T

PERIOD

+3.3 V

crossover point

extended

crossover point

differential

data lines

0 V

differential data to

SE0/EOP skew

source EOP width: t

, t

FEOPT LEOPT

N × T

+ t

FDEOP

+ t

LDEOP

PERIOD

receiver EOP width: t

, t

FEOPR LEOPR

004aaa929

T_PERIODis the bit duration corresponding with the USB data rate.

Fig 19. USB source differential data-to-EOP transition skew and EOP width

ISP1761_5

Product data sheet

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134 of 163

ISP1761

NXP Semiconductors

Hi-Speed USB OTG controller

15.1 Host timing

15.1.1 PIO timing

15.1.1.1 Register or memory write

t

h31

A[17:1]

address 01

address 02

t

su21

t

h21

CS_N

t

su31

t

w11

WR_N

t

su11

t

h11

DATA

data 01

data 02

004aaa527

Fig 20. Register or memory write

Table 167. Register or memory write

T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

Parameter

Min

Max

Unit

V_CC(I/O)= 1.65 V to 1.95 V

t_h11

data hold after WR_N HIGH

2

-

ns

t_h21

CS_N hold after WR_N HIGH

address hold after WR_N HIGH

WR_N pulse width

1

t_h31

2

t_w11

t_su11

t_su21

t_su31

17

5

data set-up time before WR_N HIGH

address set-up time before WR_N HIGH

CS_N set-up time before WR_N HIGH

5

V_CC(I/O)= 3.3 V to 3.6 V

t_h11

data hold after WR_N HIGH

2

-

ns

t_h21

CS_N hold after WR_N HIGH

address hold after WR_N HIGH

WR_N pulse width

1

t_h31

2

t_w11

t_su11

t_su21

t_su31

17

5

data set-up time before WR_N HIGH

address set-up time before WR_N HIGH

CS_N set-up time before WR_N HIGH

5

ISP1761_5

Product data sheet

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135 of 163

ISP1761

NXP Semiconductors

Hi-Speed USB OTG controller

15.1.1.2 Register read

t

su12

A[17:1]

address 01

address 02

t

su22

CS_N

RD_N

t

d22

t

w12

DATA

004aaa524

t

d12

Fig 21. Register read

Table 168. Register read

T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol Parameter

V_CC(I/O)= 1.65 V to 1.95 V

Min

Max

Unit

t_su12

t_su22

t_w12

t_d12

address set-up time before RD_N LOW

0

-

ns

CS_N set-up time before RD_N LOW

RD_N pulse width

0

-

> t_d12

-

data valid time after RD_N LOW

data valid time after RD_N HIGH

-

35

1

t_d22

V_CC(I/O)= 3.3 V to 3.6 V

t_su12

t_su22

t_w12

t_d12

address set-up time before RD_N LOW

0

-

ns

CS_N set-up time before RD_N LOW

RD_N pulse width

0

-

> t_d12

-

data valid time after RD_N LOW

data valid time after RD_N HIGH

-

22

1

t_d22

15.1.1.3 Register access

CS_N

WR_N

t

WHWL

RD_N

t

WHRL

t

RHRL

RHWL

004aaa983

Fig 22. Register access

ISP1761_5

Product data sheet

Rev. 05 — 13 March 2008

136 of 163

ISP1761

NXP Semiconductors

Hi-Speed USB OTG controller

Table 169. Register access

T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

t_WHRL

t_RHRL

Parameter

Min

25^[1]

25

Max

Unit

ns

WR_N HIGH to RD_N LOW time

RD_N HIGH to RD_N LOW time

RD_N HIGH to WR_N LOW time

WR_N HIGH to WR_N LOW time

-

ns

t_RHWL

t_WHWL

ns

25^[1]

ns

[1] For EHCI operational registers, minimum value is 195 ns.

15.1.1.4 Memory read

A[17:1]

address = 33C

data

address 1

address 2

address 3

data 3

t

su23

DATA

data 1

data 2

CS_N

t

d13

WR_N

t

p13

d23

RD_N

004aaa523

T

cy13

t

w13

t

su13

Fig 23. Memory read

Table 170. Memory read

T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol Parameter

V_CC(I/O)= 1.65 V to 1.95 V

Min

Max

Unit

t_p13

initial pre-fetch time

90

40

-

ns

T_cy13

t_d13

memory RD_N cycle time

-

data valid time after RD_N LOW

data available time after RD_N HIGH

RD_N pulse width

31

1

-

t_d23

-

t_w13

t_su13

t_su23

32

0

CS_N set-up time before RD_N LOW

address set-up time before RD_N LOW

-

0

-

V_CC(I/O)= 3.3 V to 3.6 V

t_p13

initial pre-fetch time

90

36

-

ns

T_cy13

t_d13

memory RD_N cycle time

-

data valid time after RD_N LOW

data available time after RD_N HIGH

20

1

t_d23

-

ISP1761_5

Product data sheet

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ISP1761

NXP Semiconductors

Hi-Speed USB OTG controller

Table 170. Memory read …continued

T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

t_w13

Parameter

Min

21

0

Max

Unit

ns

RD_N pulse width

-

t_su13

CS_N set-up time before RD_N LOW

address set-up time before RD_N LOW

ns

t_su23

0

ns

15.1.2 DMA timing

In the following sections:

• Polarity of DACK is active HIGH

• Polarity of DREQ is active HIGH

15.1.2.1 Single cycle: DMA read

t

a44

DREQ

DACK

RD_N

DATA

t

a34

a14

t

w14

td14

t

a24

t

h14

004aaa530

Fig 24. DMA read (single cycle)

Table 171. DMA read (single cycle)

T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol Parameter

V_CC(I/O)= 1.65 V to 1.95 V

Min

Max

Unit

t_a14

t_a24

t_d14

t_w14

t_a34

t_a44

t_h14

DACK assertion time after DREQ assertion

0

-

ns

RD_N assertion time after DACK assertion

data valid time after RD_N assertion

RD_N pulse width

0

-

24

-

> t_d14

-

DREQ de-assertion time after RD_N assertion

29

56

5

DACK de-assertion to next DREQ assertion time -

data hold time after RD_N de-asserts

-

V_CC(I/O)= 3.3 V to 3.6 V

t_a14

t_a24

t_d14

t_w14

DACK assertion time after DREQ assertion

0

-

ns

RD_N assertion time after DACK assertion

data valid time after RD_N assertion

RD_N pulse width

0

-

20

-

> t_d14

ISP1761_5

Product data sheet

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138 of 163

ISP1761

NXP Semiconductors

Hi-Speed USB OTG controller

Table 171. DMA read (single cycle) …continued

T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

t_a34

Parameter

Min

Max

18

56

5

Unit

ns

DREQ de-assertion time after RD_N assertion

-

t_a44

DACK de-assertion to next DREQ assertion time -

data hold time after RD_N de-asserts

ns

t_h14

-

ns

15.1.2.2 Single cycle: DMA write

t

DREQ

cy15

t

a15

t

a35

DACK

t

w15

t

a25

h25

WR_N

DATA

t

su15

t

h15

data

data 1

004aaa525

DREQ and DACK are active HIGH.

Fig 25. DMA write (single cycle)

Table 172. DMA write (single cycle)

T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol Parameter

V_CC(I/O)= 1.65 V to 1.95 V

Min

Max

Unit

t_a15

t_a25

t_h15

t_h25

t_su15

t_a35

t_cy15

DACK assertion time after DREQ assertion

0

1

3

0

5.5

-

ns

WR_N assertion time after DACK assertion

data hold time after WR_N de-assertion

DACK hold time after WR_N de-assertion

data set-up time before WR_N de-assertion

DREQ de-assertion time after WR_N assertion

-

28

82

last DACK strobe de-assertion to next DREQ

assertion time

-

t_w15

WR_N pulse width

22

-

ns

V_CC(I/O)= 3.3 V to 3.6 V

t_a15

t_a25

t_h15

t_h25

t_su15

t_a35

t_cy15

DACK assertion time after DREQ assertion

0

1

2

0

5.5

-

ns

WR_N assertion time after DACK assertion

data hold time after WR_N de-assertion

DACK hold time after WR_N de-assertion

data set-up time before WR_N de-assertion

DREQ de-assertion time after WR_N assertion

-

16

82

last DACK strobe de-assertion to next DREQ

assertion time

-

t_w15

WR_N pulse width

22

-

ns

ISP1761_5

Product data sheet

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139 of 163

ISP1761

NXP Semiconductors

Hi-Speed USB OTG controller

15.1.2.3 Multi-cycle: DMA read

t

a46

a36

DREQ

DACK

t

a16

t

T

a26

cy16

t

w16

RD_N

DATA

t

h16

data n-1

data n

data 1

data 0

004aaa531

t

d16

DREQ and DACK are active HIGH.

Fig 26. DMA read (multi-cycle burst)

Table 173. DMA read (multi-cycle burst)

T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol Parameter

Min

Max

Unit

V_CC(I/O)= 1.65 V to 1.95 V

t_a16

t_a26

t_d16

t_w16

T_cy16

t_a36

DACK assertion after DREQ assertion

RD_N assertion after DACK assertion

data valid time after RD_N assertion

RD_N pulse width

0

-

ns

0

-

31

-

38

46

-

read-to-read cycle time

-

DREQ de-assertion time after last burst RD_N

de-assertion

30

t_a46

t_h16

DACK de-assertion to next DREQ assertion time

data hold time after RD_N de-asserts

-

82

5

ns

V_CC(I/O)= 3.3 V to 3.6 V

t_a16

t_a26

t_d16

t_w16

T_cy16

t_a36

DACK assertion after DREQ assertion

0

-

ns

RD_N assertion after DACK assertion

data valid time after RD_N assertion

RD_N pulse width

0

-

16

-

17

38

-

read-to-read cycle time

-

DREQ de-assertion time after last burst RD_N

de-assertion

20

t_a46

t_h16

DACK de-assertion to next DREQ assertion time

data hold time after RD_N de-asserts

-

82

5

ns

ISP1761_5

Product data sheet

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140 of 163

ISP1761

NXP Semiconductors

Hi-Speed USB OTG controller

15.1.2.4 Multi-cycle: DMA write

t

a57

DREQ

DACK

WR_N

DATA

t

a17

t

h27

t

T

a37

su17

cy17

t

w17

t

a47

t

a27

t

h17

data n-1

data 1

data 2

data n

004aaa526

Fig 27. DMA write (multi-cycle burst)

Table 174. DMA write (multi-cycle burst)

T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol Parameter

Min

Max

Unit

V_CC(I/O)= 1.65 V to 1.95 V

T_cy17

t_su17

t_h17

DMA write cycle time

51

5

2

0

2

-

ns

data set-up time before WR_N de-assertion

data hold time after WR_N de-assertion

DACK assertion time after DREQ assertion

WR_N assertion time after DACK assertion

-

t_a17

-

t_a27

-

t_a37

DREQ de-assertion time at last strobe (WR_N)

assertion

28

t_h27

t_a47

t_w17

t_a57

DACK hold time after WR_N de-assertion

0

-

ns

strobe de-assertion to next strobe assertion time 34

-

WR_N pulse width

17

-

DACK de-assertion to next DREQ assertion time

82

V_CC(I/O)= 3.3 V to 3.6 V

T_cy17

t_su17

t_h17

DMA write cycle time

51

5

2

0

1

-

ns

data set-up time before WR_N de-assertion

data hold time after WR_N de-assertion

DACK assertion time after DREQ assertion

WR_N assertion time after DACK assertion

-

t_a17

-

t_a27

-

t_a37

DREQ de-assertion time at last strobe (WR_N)

assertion

16

t_h27

t_a47

t_w17

t_a57

DACK hold time after WR_N de-assertion

0

-

ns

strobe de-assertion to next strobe assertion time 34

-

WR_N pulse width

17

-

DACK de-assertion to next DREQ assertion time

82

ISP1761_5

Product data sheet

Rev. 05 — 13 March 2008

141 of 163

ISP1761

NXP Semiconductors

Hi-Speed USB OTG controller

15.2 Peripheral timing

15.2.1 PIO timing

15.2.1.1 PIO register read or write

t

d58

t

d68

t

d38

t

d48

CS_N

t

h28

t

h18

AD[17:1]

t

d18

t

d28

(read) DATA[31:0]

RD_N

t

su18

w18

t

h38

su28

(write) DATA[31:0]

WR_N

t

su38

t

w28

004aaa529

Fig 28. ISP1761 register access timing: separate address and data buses (8051 style)

Table 175. PIO register read or write

T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol Parameter

V_CC(I/O)= 1.65 V to 1.95 V

Reading

Min

Max

Unit

t_w18

t_su18

t_h18

RD_N LOW pulse width

> t_d18

-

ns

address set-up time before RD_N LOW

address hold time after RD_N HIGH

RD_N LOW to data valid delay

0

-

t_d18

33

1

-

t_d28

RD_N HIGH to data outputs 3-state delay

RD_N HIGH to CS_N HIGH delay

CS_N LOW to RD_N LOW delay

-

t_d38

0

t_d48

-

Writing

t_w28

t_su28

t_h28

WR_N LOW pulse width

15

0

-

ns

address set-up time before WR_N LOW

address hold time after WR_N HIGH

data set-up time before WR_N HIGH

data hold time after WR_N HIGH

WR_N HIGH to CS_N HIGH delay

0

t_su38

t_h38

5

2

t_d58

1

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Table 175. PIO register read or write …continued

T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol Parameter

Min

Max

Unit

t_d68

CS_N LOW to WR_N LOW delay

0

-

ns

V_CC(I/O)= 3.3 V to 3.6 V

Reading

t_w18

t_su18

t_h18

RD_N LOW pulse width

> t_d18

-

ns

address set-up time before RD_N LOW

address hold time after RD_N HIGH

RD_N LOW to data valid delay

0

-

t_d18

21

1

-

t_d28

RD_N HIGH to data outputs 3-state delay

RD_N HIGH to CS_N HIGH delay

CS_N LOW to RD_N LOW delay

0

t_d38

t_d48

-

Writing

t_w28

t_su28

t_h28

WR_N LOW pulse width

15

0

-

ns

address set-up time before WR_N LOW

address hold time after WR_N HIGH

data set-up time before WR_N HIGH

data hold time after WR_N HIGH

WR_N HIGH to CS_N HIGH delay

CS_N LOW to WR_N LOW delay

1

t_su38

t_h38

5

2

t_d58

1

t_d68

0

15.2.1.2 PIO register access

CS_N

WR_N

RD_N

t

WHWL

t

WHRL

t

RHWL

RHRL

004aaa984

Fig 29. PIO register access

Table 176. Register access

T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

t_WHRL

t_RHWL

t_WHWL

t_RHRL

Parameter

Min

86

Max

Unit

WR_N HIGH to RD_N LOW time

RD_N HIGH to WR_N LOW time

WR_N HIGH to WR_N LOW time

RD_N HIGH to RD_N LOW time

-

ns

86

86^[1]

[1] For the Data Port register, the minimum value is 25 ns.

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15.2.2 DMA timing

15.2.2.1 DMA read or write

(2)

DREQ

t

su19

t

h19

(1)

t

T

w19

DACK

cy19

t

d19

su39

RD_N/WR_N

t

w29

t

a19

t

d29

h29

[31

]

(read) DATA :0

t

h39

su29

[31

(write) DATA :0

004aaa528

DREQ is continuously asserted until the last transfer is done or the FIFO is full.

Data strobes: RD_N (read) and WR_N (write).

(1) Programmable polarity: shown as active LOW.

(2) Programmable polarity: shown as active HIGH.

Fig 30. DMA read or write

Table 177. DMA read or write

T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol Parameter

Min

Max

Unit

V_CC(I/O)= 1.65 V to 1.95 V

T_cy19

t_su19

t_d19

read or write cycle time

75

10

33.33

0

-

ns

DREQ set-up time before ﬁrst DACK on

DREQ on delay after last strobe off

DREQ hold time after last strobe on

RD_N/WR_N pulse width

-

t_h19

53

t_w19

t_w29

t_d29

40

36

-

600

RD_N/WR_N recovery time

-

read data valid delay after strobe on

read data hold time after strobe off

write data hold time after strobe off

write data set-up time before strobe off

DACK set-up time before RD_N/WR_N assertion

30

5

-

t_h29

-

t_h39

1

t_su29

t_su39

t_a19

10

0

-

DACK de-assertion after RD_N/WR_N

de-assertion

3

-

V_CC(I/O)= 3.3 V to 3.6 V

T_cy19

t_su19

t_d19

read or write cycle time

75

-

ns

DREQ set-up time before ﬁrst DACK on

DREQ on delay after last strobe off

10

33.33

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Table 177. DMA read or write …continued

T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol Parameter

Min

0

Max

Unit

ns

t_h19

t_w19

t_w29

t_d29

t_h29

t_h39

t_su29

t_su39

t_a19

DREQ hold time after last strobe on

RD_N/WR_N pulse width

53

39

36

-

600

RD_N/WR_N recovery time

-

read data valid delay after strobe on

read data hold time after strobe off

write data hold time after strobe off

write data set-up time before strobe off

DACK set-up time before RD_N/WR_N assertion

20

5

-

1

10

0

-

DACK de-assertion after RD_N/WR_N

de-assertion

3

-

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16. Package outline

LQFP128: plastic low profile quad flat package; 128 leads; body 14 x 20 x 1.4 mm

SOT425-1

y

X

A

102

103

65

64

Z

E

e

H

A

E

2

A

E

(A )

3

A

1

θ

w M

p

L

p

b

pin 1 index

detail X

39

38

128

1

v

M

A

Z

w M

D

b

p

e

D

B

H

v

M

B

D

0

5

10 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

D

H

L

v

w

y

Z

E

θ

1

2

3

p

E

p

D

max.

7^o

0^o

0.15 1.45

0.05 1.35

0.27 0.20 20.1 14.1

0.17 0.09 19.9 13.9

22.15 16.15

21.85 15.85

0.75

0.45

0.81 0.81

0.59 0.59

mm

1.6

0.25

1

0.2 0.12 0.1

0.5

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

00-01-19

03-02-20

SOT425-1

136E28

MS-026

Fig 31. Package outline SOT425-1 (LQFP128)

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TFBGA128: plastic thin fine-pitch ball grid array package; 128 balls; body 9 x 9 x 0.8 mm

SOT857-1

D

B

A

ball A1

index area

A

E

2

A

1

detail X

C

e

1

y

C

1

y

M

v

C A

C

B

b

e

1/2 e

w

T

R

P

M

K

H

e

N

L

J

e

2

G

E

C

A

1/2 e

F

D

B

ball A1

index area

1

3

5

7

9

11 13 15

2

4

6

8

10 12 14 16

X

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

UNIT

A

1

A

2

b

D

E

e

v

w

y

1

2

max

0.25 0.85 0.35

0.15 0.75 0.25

9.1

8.9

9.1

8.9

mm

1.1

0.5

7.5

0.15 0.05 0.08

0.1

REFERENCES

OUTLINE

VERSION

EUROPEAN

ISSUE DATE

PROJECTION

IEC

JEDEC

JEITA

04-05-05

04-06-22

SOT857-1

MO-195

Fig 32. Package outline SOT857-1 (TFBGA128)

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17. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reﬂow

soldering description”.

17.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

17.2 Wave and reﬂow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reﬂow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature proﬁle. Leaded packages,

packages with solder balls, and leadless packages are all reﬂow solderable.

Key characteristics in both wave and reﬂow soldering are:

• Board speciﬁcations, including the board ﬁnish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

17.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and ﬂux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath speciﬁcations, including temperature and impurities

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17.4 Reﬂow soldering

Key characteristics in reﬂow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 33) than a SnPb process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classiﬁed in accordance with

Table 178 and 179

Table 178. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

235

≥ 350

220

< 2.5

≥ 2.5

220

Table 179. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reﬂow

soldering, see Figure 33.

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maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 33. Temperature proﬁles for large and small components

For further information on temperature proﬁles, refer to Application Note AN10365

“Surface mount reﬂow soldering description”.

18. Soldering of through-hole mount packages

18.1 Introduction to soldering through-hole mount packages

This text gives a very brief insight into wave, dip and manual soldering.

Wave soldering is the preferred method for mounting of through-hole mount IC packages

on a printed-circuit board.

18.2 Soldering by dipping or by solder wave

Driven by legislation and environmental forces the worldwide use of lead-free solder

pastes is increasing. Typical dwell time of the leads in the wave ranges from

3 seconds to 4 seconds at 250 °C or 265 °C, depending on solder material applied, SnPb

or Pb-free respectively.

The total contact time of successive solder waves must not exceed 5 seconds.

The device may be mounted up to the seating plane, but the temperature of the plastic

body must not exceed the speciﬁed maximum storage temperature (T_stg(max)). If the

printed-circuit board has been pre-heated, forced cooling may be necessary immediately

after soldering to keep the temperature within the permissible limit.

18.3 Manual soldering

Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the

seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is

less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is

between 300 °C and 400 °C, contact may be up to 5 seconds.

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18.4 Package related soldering information

Table 180. Suitability of through-hole mount IC packages for dipping and wave soldering

Package

Soldering method

Dipping

Wave

CPGA, HCPGA

-

suitable

DBS, DIP, HDIP, RDBS, SDIP, SIL

PMFP^[2]

suitable

-

suitable^[1]

not suitable

[1] For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit

board.

[2] For PMFP packages hot bar soldering or manual soldering is suitable.

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19. Abbreviations

Table 181. Abbreviations

Acronym

ACK

ASIC

ATL

Description

Acknowledgment

Application-Speciﬁc Integrated Circuit

Asynchronous Transfer List

Analog Transceiver

Complete Split

ATX

CS

DMA

DSC

DW

Direct Memory Access

Digital Still Camera

Double Word

EHCI

EMI

Enhanced Host Controller Interface

ElectroMagnetic Interference

End-Of-Packet

EOP

EOT

ESD

ESR

FIFO

FS

End-Of-Transfer

ElectroStatic Discharge

Effective Series Resistance

First In, First Out

Full-Speed

FLS

Frame List Size

GDMA

GPIO

GPS

HC

Generic DMA

General-Purpose Input/Output

Global Positioning System

Host Controller

HNP

HS

Host Negotiation Protocol

High-Speed

iTD

isochronous Transfer Descriptor

Interrupt

INT

ISO

Isochronous

ISR

Interrupt Service Routine

Isochronous (ISO) Transfer List

Low-Speed

ITL

LS

LSByte

MSByte

NAK

NYET

OC

Least Signiﬁcant Byte

Most Signiﬁcant Byte

Not Acknowledged

Not Yet

Overcurrent

OHCI

OTG

PCI

Open Host Controller Interface

On-the-Go

Peripheral Component Interconnect

Packet Identiﬁer

PID

PIO

Programmed Input/Output

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Table 181. Abbreviations …continued

Acronym

Description

PLL

Phase-Locked Loop

PMOS

POR

PORP

PTD

RAM

RISC

SE0

Positive-channel Metal-Oxide Semiconductor

Power-On Reset

Power-On Reset Pulse

Philips Transfer Descriptor

Random Access Memory

Reduced Instruction Set Computer

Single Ended 0

SE1

Single Ended 1

SIE

Serial Interface Engine

split isochronous Transfer Descriptor

Start-Of-Frame

siTD

SOF

SRAM

SRP

SS

Static Random Access Memory

Session Request Protocol

Start Split

TT

Transaction Translator

Universal Host Controller Interface

Universal Serial Bus

UHCI

USB

20. References

[1] Universal Serial Bus Speciﬁcation Rev. 2.0

[2] Enhanced Host Controller Interface Speciﬁcation for Universal Serial Bus Rev. 1.0

[3] On-The-Go Supplement to the USB Speciﬁcation Rev. 1.3

[4] ISP1582/83 Control Pipe (AN10031)

[5] Interfacing the ISP176x to the Intel PXA25x processor (AN10037)

[6] ISP1582/83 Firmware Programming Guide (AN10039)

[7] ISP1761 Peripheral DMA Initialization (AN10040)

[8] ISP176x Linux Programming Guide (AN10042)

[9] Embedded Systems Design with the ISP176x (AN10043)

[10] ISP1760/1 Frequently Asked Questions (AN10054)

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21. Revision history

Table 182. Revision history

Document ID

ISP1761_5

Release date

Data sheet status

Change notice

Supersedes

20080313

Product data sheet

-

ISP1761_4

Modiﬁcations:

• Changed mini-A, mini-B and mini-AB to micro-A, micro-B and micro-AB, respectively.

• Changed On-The-Go Supplement to the USB Speciﬁcation from Rev. 1.2 to Rev. 1.3.

• Table 52 “Power Down Control register (address 0354h) bit description”: updated description for bits

12 and 11.

• Section 9.4.3 “HNP implementation and OTG state machine”: updated the third last paragraph.

• Section 10.1.1.3 “DMA initialization”: updated the second paragraph.

• Table 101 “Mode register (address 020Ch) bit description”: updated description for bit 8.

• Section 10.6.2 “Control Function register”: updated bit 2 access and description.

• Table 117 “DcBufferStatus - Device Controller Buffer Status register (address 021Eh) bit allocation”:

updated access type for bits 1 and 0 from R/W to R.

• Table 142 “DcInterrupt - Device Controller Interrupt register (address 0218h) bit description”:

updated description for bit 7.

• Table 154 “Limiting values”: updated the conditions column of V_esd

.

• Table 160 “Static characteristics: V_BUScomparators”: added Table note 1 and Table note 2.

ISP1761_4

ISP1761_3

20070305

20061127

20051005

Product data sheet

-

ISP1761_3

ISP1761_2

ISP1761_1

ISP1761_2

(9397 750 15191)

ISP1761_1

20050112

Product data sheet

-

(9397 750 13258)

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22. Legal information

22.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

to result in personal injury, death or severe property or environmental

22.2 Deﬁnitions

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

22.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

22.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

SoftConnect — is a trademark of NXP B.V.

23. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

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24. Tables

Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .4

Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .7

Table 3. Port connection scenarios . . . . . . . . . . . . . . . .16

Table 4. Memory address . . . . . . . . . . . . . . . . . . . . . . .18

Table 5. Using the IRQ Mask AND or IRQ Mask OR

registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Table 6. Hybrid mode . . . . . . . . . . . . . . . . . . . . . . . . . .28

Table 7. Pin status during hybrid mode . . . . . . . . . . . . .29

Table 8. Host controller-speciﬁc register overview . . . .32

Table 9. CAPLENGTH - Capability Length register

(address 0000h) bit description . . . . . . . . . . . .33

Table 10. HCIVERSION - Host Controller Interface Version

Number register (address 0002h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Table 11. HCSPARAMS - Host Controller Structural

Parameters register (address 0004h) bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Table 12. HCSPARAMS - Host Controller Structural

Parameters register (address 0004h) bit

Table 26. ISO PTD Skip Map register (address 0134h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 27. ISO PTD Last PTD register (address 0138h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 28. INT PTD Done Map register (address 0140h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 29. INT PTD Skip Map register (address 0144h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 30. INT PTD Last PTD register (address 0148h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 31. ATL PTD Done Map register (address 0150h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 32. ATL PTD Skip Map register (address 0154h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 33. ATL PTD Last PTD register (address 0158h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 34. HW Mode Control - Hardware Mode Control

register (address 0300h) bit allocation . . . . . . 43

Table 35. HW Mode Control - Hardware Mode Control

register (address 0300h) bit description . . . . . 44

Table 36. HcChipID - Host Controller Chip Identiﬁer register

(address 0304h) bit description . . . . . . . . . . . . 45

Table 37. HcScratch - Host Controller Scratch register

(address 0308h) bit description . . . . . . . . . . . . 45

Table 38. SW Reset - Software Reset register (address

030Ch) bit allocation . . . . . . . . . . . . . . . . . . . . 45

Table 39. SW Reset - Software Reset register (address

030Ch) bit description . . . . . . . . . . . . . . . . . . . 46

Table 40. HcDMAConﬁguration - Host Controller Direct

Memory Access Conﬁguration register (address

0330h) bit allocation . . . . . . . . . . . . . . . . . . . . 46

Table 41. HcDMAConﬁguration - Host Controller Direct

Memory Access Conﬁguration register (address

0330h) bit description . . . . . . . . . . . . . . . . . . . 47

Table 42. HcBufferStatus - Host Controller Buffer Status

register (address 0334h) bit allocation . . . . . . 47

Table 43. HcBufferStatus - Host Controller Buffer Status

register (address 0334h) bit description . . . . . 48

Table 44. ATL Done Timeout register (address 0338h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 45. Memory register (address 033Ch) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Table 13. HCCPARAMS - Host Controller Capability

Parameters register (address 0008h) bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Table 14. HCCPARAMS - Host Controller Capability

Parameters register (address 0008h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Table 15. USBCMD - USB Command register (address

0020h) bit allocation . . . . . . . . . . . . . . . . . . . . .36

Table 16. USBCMD - USB Command register (address

0020h) bit description . . . . . . . . . . . . . . . . . . .36

Table 17. USBSTS - USB Status register (address 0024h)

bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Table 18. USBSTS - USB Status register (address 0024h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .37

Table 19. FRINDEX - Frame Index register (address:

002Ch) bit allocation . . . . . . . . . . . . . . . . . . . .37

Table 20. FRINDEX - Frame Index register (address:

002Ch) bit description . . . . . . . . . . . . . . . . . . .38

Table 21. CONFIGFLAG - Conﬁgure Flag register (address

0060h) bit allocation . . . . . . . . . . . . . . . . . . . . .38

Table 22. CONFIGFLAG - Conﬁgure Flag register (address

0060h) bit description . . . . . . . . . . . . . . . . . . .39

Table 23. PORTSC1 - Port Status and Control 1 register

(address 0064h) bit allocation . . . . . . . . . . . . .39

Table 24. PORTSC1 - Port Status and Control 1 register

(address 0064h) bit description . . . . . . . . . . . .40

Table 25. ISO PTD Done Map register (address 0130h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 46. Memory register (address 033Ch) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 47. Edge Interrupt Count register (address 0340h) bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 48. Edge Interrupt Count register (address 0340h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

continued >>

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Product data sheet

Rev. 05 — 13 March 2008

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NXP Semiconductors

Hi-Speed USB OTG controller

Table 49. DMA Start Address register (address 0344h) bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Table 50. DMA Start Address register (address 0344h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Table 51. Power Down Control register (address 0354h) bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Table 52. Power Down Control register (address 0354h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Table 53. HcInterrupt - Host Controller Interrupt register

(address 0310h) bit allocation . . . . . . . . . . . . .53

Table 54. HcInterrupt - Host Controller Interrupt register

(address 0310h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Table 55. HcInterruptEnable - Host Controller Interrupt

Enable register (address 0314h) bit allocation 55

Table 56. HcInterruptEnable - Host Controller Interrupt

Enable register (address 0314h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Table 57. ISO IRQ Mask OR register (address 0318h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Table 58. INT IRQ Mask OR register (address 031Ch) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Table 59. ATL IRQ Mask OR register (address 0320h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

Table 60. ISO IRQ Mask AND register (address 0324h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

Table 61. INT IRQ MASK AND register (address 0328h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

Table 62. ATL IRQ MASK AND register (address 032Ch) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

Table 63. High-speed bulk IN and OUT: bit allocation . . .61

Table 64. High-speed bulk IN and OUT: bit description .62

Table 65. High-speed isochronous IN and OUT: bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Table 66. High-speed isochronous IN and OUT: bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Table 67. High-speed interrupt IN and OUT: bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Table 68. High-speed interrupt IN and OUT: bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

Table 69. Microframe description . . . . . . . . . . . . . . . . . .72

Table 70. Start and complete split for bulk: bit allocation 73

Table 71. Start and complete split for bulk: bit

Table 76. Start and complete split for interrupt: bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 77. Microframe description . . . . . . . . . . . . . . . . . . 84

Table 78. SE description . . . . . . . . . . . . . . . . . . . . . . . . . 84

Table 79. OTG controller-speciﬁc register overview . . . . 91

Table 80. Address mapping of registers: 32-bit data bus

mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Table 81. Address mapping of registers: 16-bit data bus

mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Table 82. Vendor ID - Vendor Identiﬁer (address 0370h)

register: bit description . . . . . . . . . . . . . . . . . . 92

Table 83. Product ID - Product Identiﬁer register (address

0372h) bit description . . . . . . . . . . . . . . . . . . . 92

Table 84. OTG Control register (address set: 0374h, clear:

0376h) bit allocation . . . . . . . . . . . . . . . . . . . . 93

Table 85. OTG Control register (address set: 0374h, clear:

0376h) bit description . . . . . . . . . . . . . . . . . . . 93

Table 86. OTG Status register (address 0378h) bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Table 87. OTG Status register (address 0378h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Table 88. OTG Interrupt Latch register (address set: 037Ch,

clear: 037Eh) bit allocation . . . . . . . . . . . . . . . 95

Table 89. OTG Interrupt Latch register (address set: 037Ch,

clear: 037Eh) bit description . . . . . . . . . . . . . . 95

Table 90. OTG Interrupt Enable Fall register (address set:

0380h, clear: 0382h) bit allocation . . . . . . . . . 96

Table 91. OTG Interrupt Enable Fall register (address set:

0380h, clear: 0382h) bit description . . . . . . . . 96

Table 92. OTG Interrupt Enable Rise register (address set:

0384h, clear: 0386h) bit allocation . . . . . . . . . 96

Table 93. OTG Interrupt Enable Rise register (address set:

0384h, clear: 0386h) bit description . . . . . . . . 97

Table 94. OTG Timer register (address low word set: 0388h,

low word clear: 038Ah; high word set: 038Ch, high

word clear: 038Eh) bit allocation . . . . . . . . . . . 97

Table 95. OTG Timer register (address low word set: 0388h,

low word clear: 038Ah; high word set: 038Ch, high

word clear: 038Eh) bit description . . . . . . . . . . 98

Table 96. Endpoint access and programmability . . . . . 101

Table 97. Peripheral controller-speciﬁc register

overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Table 98. Address register (address 0200h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

Table 72. SE description . . . . . . . . . . . . . . . . . . . . . . . . .76

Table 73. Start and complete split for isochronous: bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

Table 74. Start and complete split for isochronous: bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

Table 75. Start and complete split for interrupt: bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Table 99. Address register (address 0200h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Table 100.Mode register (address 020Ch) bit allocation 105

Table 101.Mode register (address 020Ch) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Table 102.Interrupt Conﬁguration register (address 0210h)

bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . 106

continued >>

ISP1761_5

Product data sheet

Rev. 05 — 13 March 2008

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NXP Semiconductors

Hi-Speed USB OTG controller

Table 103.Interrupt Conﬁguration register (address 0210h)

bit description . . . . . . . . . . . . . . . . . . . . . . . .107

Table 104.Debug mode settings . . . . . . . . . . . . . . . . . . .107

Table 105.Debug register (address 0212h) bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . .107

Table 106.Debug register (address 0212h) bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . .107

Table 107.DcInterruptEnable - Device Controller Interrupt

Enable register (address 0214h) bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . .108

Table 108.DcInterruptEnable - Device Controller Interrupt

Enable register (address 0214h) bit

Table 129.DcDMAConﬁguration - Device Controller Direct

Memory Access Conﬁguration register (address

0238h) bit allocation . . . . . . . . . . . . . . . . . . . 118

Table 130.DcDMAConﬁguration - Device Controller Direct

Memory Access Conﬁguration register (address

0238h) bit description . . . . . . . . . . . . . . . . . . 119

Table 131.DMA Hardware register (address 023Ch) bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Table 132.DMA Hardware register (address 023Ch) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Table 133.DMA Interrupt Reason register (address 0250h)

bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . 120

Table 134.DMA Interrupt Reason register (address 0250h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . 120

Table 135.Internal EOT-functional relation with the

DMA_XFER_OK bit . . . . . . . . . . . . . . . . . . . . 121

Table 136.DMA Interrupt Enable register (address 0254h) bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Table 137.DMA Endpoint register (address 0258h) bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Table 138.DMA Endpoint register (address 0258h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Table 139.DMA Burst Counter register (address 0264h) bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Table 140.DMA Burst Counter register (address 0264h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Table 141.DcInterrupt - Device Controller Interrupt register

(address 0218h) bit allocation . . . . . . . . . . . . 123

Table 142.DcInterrupt - Device Controller Interrupt register

(address 0218h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Table 143.DcChipID - Device Controller Chip Identiﬁer

register (address 0270h) bit description . . . . 125

Table 144.Frame Number register (address 0274h) bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Table 145.Frame Number register (address 0274h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Table 146.DcScratch - Device Controller Scratch register

(address 0278h) bit allocation . . . . . . . . . . . . 126

Table 147.DcScratch - Device Controller Scratch register

(address 0278h) bit description . . . . . . . . . . . 126

Table 148.Unlock Device register (address 027Ch) bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Table 149.Unlock Device register (address 027Ch) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Table 150.Interrupt Pulse Width register (address 0280h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Table 151.Test Mode register (address 0284h) bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Table 152.Test Mode register (address 0284h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

description . . . . . . . . . . . . . . . . . . . . . . . . . . .109

Table 109.Endpoint Index register (address 022Ch) bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . .110

Table 110.Endpoint Index register (address 022Ch) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . .110

Table 111.Addressing of endpoint buffers . . . . . . . . . . .110

Table 112.Control Function register (address 0228h) bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . .111

Table 113.Control Function register (address 0228h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . .111

Table 114.Data Port register (address 0220h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . .112

Table 115.Data Port register (address 0220h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . .112

Table 116.Buffer Length register (address 021Ch) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . .113

Table 117.DcBufferStatus - Device Controller Buffer Status

register (address 021Eh) bit allocation . . . . .113

Table 118.DcBufferStatus - Device Controller Buffer Status

register (address 021Eh) bit description . . . .113

Table 119.Endpoint MaxPacketSize register (address

0204h) bit allocation . . . . . . . . . . . . . . . . . . . .114

Table 120.Endpoint MaxPacketSize register (address

0204h) bit description . . . . . . . . . . . . . . . . . .114

Table 121.Endpoint Type register (address 0208h) bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . .115

Table 122.Endpoint Type register (address 0208h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . .115

Table 123.Control bits for GDMA read or write (opcode =

00h/01h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116

Table 124.DMA Command register (address 0230h) bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . .116

Table 125.DMA Command register (address 0230h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . .117

Table 126.DMA commands . . . . . . . . . . . . . . . . . . . . . .117

Table 127.DMA Transfer Counter register (address 0234h)

bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . .118

Table 128.DMA Transfer Counter register (address 0234h)

bit description . . . . . . . . . . . . . . . . . . . . . . . .118

continued >>

ISP1761_5

Product data sheet

Rev. 05 — 13 March 2008

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Hi-Speed USB OTG controller

Table 153.Power consumption . . . . . . . . . . . . . . . . . . . .128

Table 154.Limiting values . . . . . . . . . . . . . . . . . . . . . . . .129

Table 155.Recommended operating conditions . . . . . . .129

Table 156.Static characteristics: digital pins . . . . . . . . . .130

Table 157.Static characteristics: PSW1_N, PSW2_N,

PSW3_N . . . . . . . . . . . . . . . . . . . . . . . . . . . .130

Table 158.Static characteristics: USB interface block (pins

DM1 to DM3 and DP1 to DP3) . . . . . . . . . . .130

Table 159.Static characteristics: REF5V . . . . . . . . . . . .131

Table 160.Static characteristics: V_BUScomparators . . . .131

Table 161.Static characteristics: V_BUSresistors . . . . . . .132

Table 162.Dynamic characteristics: system clock timing 133

Table 163.Dynamic characteristics: CPU interface block 133

Table 164.Dynamic characteristics: high-speed source

electrical characteristics . . . . . . . . . . . . . . . .133

Table 165.Dynamic characteristics: full-speed source

electrical characteristics . . . . . . . . . . . . . . . .133

Table 166.Dynamic characteristics: low-speed source

electrical characteristics . . . . . . . . . . . . . . . .134

Table 167.Register or memory write . . . . . . . . . . . . . . .135

Table 168.Register read . . . . . . . . . . . . . . . . . . . . . . . . .136

Table 169.Register access . . . . . . . . . . . . . . . . . . . . . . .137

Table 170.Memory read . . . . . . . . . . . . . . . . . . . . . . . . .137

Table 171.DMA read (single cycle) . . . . . . . . . . . . . . . . .138

Table 172.DMA write (single cycle) . . . . . . . . . . . . . . . .139

Table 173.DMA read (multi-cycle burst) . . . . . . . . . . . . .140

Table 174.DMA write (multi-cycle burst) . . . . . . . . . . . . .141

Table 175.PIO register read or write . . . . . . . . . . . . . . .142

Table 176.Register access . . . . . . . . . . . . . . . . . . . . . . .143

Table 177.DMA read or write . . . . . . . . . . . . . . . . . . . . .144

Table 178.SnPb eutectic process (from J-STD-020C) . .149

Table 179.Lead-free process (from J-STD-020C) . . . . .149

Table 180.Suitability of through-hole mount IC packages for

dipping and wave soldering . . . . . . . . . . . . . .151

Table 181.Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .152

Table 182.Revision history . . . . . . . . . . . . . . . . . . . . . . .154

ISP1761_5

Product data sheet

Rev. 05 — 13 March 2008

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ISP1761

NXP Semiconductors

Hi-Speed USB OTG controller

25. Figures

Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Fig 2. Pin conﬁguration (LQFP128); top view . . . . . . . . .6

Fig 3. Pin conﬁguration (TFBGA128); top view . . . . . . . .6

Fig 4. Internal hub . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Fig 5. ISP1761 clock scheme . . . . . . . . . . . . . . . . . . . .15

Fig 6. Memory segmentation and access block

diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Fig 7. ISP1761 power supply connection. . . . . . . . . . . .27

Fig 8. Most commonly used power supply connection .28

Fig 9. Hybrid mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Fig 10. Adjusting analog overcurrent detection limit

(optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Fig 11. Internal power-on reset timing . . . . . . . . . . . . . . .31

Fig 12. Clock with respect to the external

power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . .31

Fig 13. NextPTD traversal rule. . . . . . . . . . . . . . . . . . . . .60

Fig 14. HNP sequence of events . . . . . . . . . . . . . . . . . . .87

Fig 15. Dual-role A-device state diagram. . . . . . . . . . . . .89

Fig 16. Dual-role B-device state diagram. . . . . . . . . . . . .90

Fig 17. Charge pump current versus voltage

at various temperatures (worst case). . . . . . . . .132

Fig 18. Charge pump current versus voltage

at various temperatures (typical case). . . . . . . .132

Fig 19. USB source differential data-to-EOP transition

skew and EOP width . . . . . . . . . . . . . . . . . . . . .134

Fig 20. Register or memory write. . . . . . . . . . . . . . . . . .135

Fig 21. Register read . . . . . . . . . . . . . . . . . . . . . . . . . . .136

Fig 22. Register access . . . . . . . . . . . . . . . . . . . . . . . . .136

Fig 23. Memory read . . . . . . . . . . . . . . . . . . . . . . . . . . .137

Fig 24. DMA read (single cycle). . . . . . . . . . . . . . . . . . .138

Fig 25. DMA write (single cycle) . . . . . . . . . . . . . . . . . .139

Fig 26. DMA read (multi-cycle burst) . . . . . . . . . . . . . . .140

Fig 27. DMA write (multi-cycle burst). . . . . . . . . . . . . . .141

Fig 28. ISP1761 register access timing: separate

address and data buses (8051 style). . . . . . . . .142

Fig 29. PIO register access . . . . . . . . . . . . . . . . . . . . . .143

Fig 30. DMA read or write . . . . . . . . . . . . . . . . . . . . . . .144

Fig 31. Package outline SOT425-1 (LQFP128) . . . . . . .146

Fig 32. Package outline SOT857-1 (TFBGA128). . . . . .147

Fig 33. Temperature proﬁles for large and small

components . . . . . . . . . . . . . . . . . . . . . . . . . . . .150

ISP1761_5

Product data sheet

Rev. 05 — 13 March 2008

160 of 163

ISP1761

NXP Semiconductors

Hi-Speed USB OTG controller

26. Contents

1

General description . . . . . . . . . . . . . . . . . . . . . . 1

8.2.9

8.2.10

8.2.11

8.2.12

8.2.13

8.2.14

8.2.15

8.3

8.3.1

8.3.2

8.3.3

8.3.4

8.3.5

8.3.6

8.3.7

8.3.8

8.3.9

8.3.10

8.3.11

8.4

8.4.1

8.4.2

8.4.3

8.4.4

8.4.5

8.4.6

8.4.7

8.4.8

8.5

8.5.1

8.5.2

8.5.3

8.5.4

8.5.5

8.5.6

ISO PTD Last PTD register . . . . . . . . . . . . . . 41

INT PTD Done Map register. . . . . . . . . . . . . . 41

INT PTD Skip Map register . . . . . . . . . . . . . . 41

INT PTD Last PTD register . . . . . . . . . . . . . . 42

ATL PTD Done Map register . . . . . . . . . . . . . 42

ATL PTD Skip Map register . . . . . . . . . . . . . . 42

ATL PTD Last PTD register . . . . . . . . . . . . . . 43

Conﬁguration registers. . . . . . . . . . . . . . . . . . 43

HW Mode Control register . . . . . . . . . . . . . . . 43

HcChipID register. . . . . . . . . . . . . . . . . . . . . . 45

HcScratch register . . . . . . . . . . . . . . . . . . . . . 45

SW Reset register . . . . . . . . . . . . . . . . . . . . . 45

HcDMAConﬁguration register. . . . . . . . . . . . . 46

HcBufferStatus register . . . . . . . . . . . . . . . . . 47

ATL Done Timeout register . . . . . . . . . . . . . . 48

Memory register . . . . . . . . . . . . . . . . . . . . . . . 48

Edge Interrupt Count register. . . . . . . . . . . . . 49

DMA Start Address register . . . . . . . . . . . . . . 50

Power Down Control register . . . . . . . . . . . . . 51

Interrupt registers. . . . . . . . . . . . . . . . . . . . . . 53

HcInterrupt register . . . . . . . . . . . . . . . . . . . . 53

HcInterruptEnable register . . . . . . . . . . . . . . . 55

ISO IRQ MASK OR register. . . . . . . . . . . . . . 57

INT IRQ MASK OR register . . . . . . . . . . . . . . 57

ATL IRQ MASK OR register. . . . . . . . . . . . . . 57

ISO IRQ MASK AND register. . . . . . . . . . . . . 58

INT IRQ MASK AND register . . . . . . . . . . . . . 58

ATL IRQ MASK AND register. . . . . . . . . . . . . 58

Philips Transfer Descriptor (PTD). . . . . . . . . . 58

High-speed bulk IN and OUT . . . . . . . . . . . . . 61

High-speed isochronous IN and OUT . . . . . . 65

High-speed interrupt IN and OUT . . . . . . . . . 69

Start and complete split for bulk. . . . . . . . . . . 73

Start and complete split for isochronous . . . . 77

Start and complete split for interrupt . . . . . . . 81

2

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Host/peripheral roles. . . . . . . . . . . . . . . . . . . . . 3

Ordering information. . . . . . . . . . . . . . . . . . . . . 4

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3

3.1

4

5

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 6

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7

7

7.1

Functional description . . . . . . . . . . . . . . . . . . 14

ISP1761 internal architecture: advanced

NXP slave host controller and hub . . . . . . . . . 14

Internal clock scheme and port selection . . . . 15

Host controller buffer memory block . . . . . . . . 16

General considerations. . . . . . . . . . . . . . . . . . 16

Structure of the ISP1761 host controller

7.1.1

7.2

7.2.1

7.2.2

memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Accessing the ISP1761 host controller

7.3

memory: PIO and DMA . . . . . . . . . . . . . . . . . 19

PIO mode access, memory read cycle. . . . . . 20

PIO mode access, memory write cycle . . . . . 20

PIO mode access, register read cycle . . . . . . 21

PIO mode access, register write cycle . . . . . . 21

DMA mode, read and write operations . . . . . . 21

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Phase-Locked Loop (PLL) clock multiplier . . . 24

Power management . . . . . . . . . . . . . . . . . . . . 25

Power supply . . . . . . . . . . . . . . . . . . . . . . . . . 26

Hybrid mode . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Overcurrent detection . . . . . . . . . . . . . . . . . . . 29

Power-On Reset (POR) . . . . . . . . . . . . . . . . . 30

7.3.1

7.3.2

7.3.3

7.3.4

7.3.5

7.4

7.5

7.6

7.7

7.7.1

7.8

7.9

8

8.1

Host controller . . . . . . . . . . . . . . . . . . . . . . . . . 32

EHCI capability registers . . . . . . . . . . . . . . . . 33

CAPLENGTH register. . . . . . . . . . . . . . . . . . . 33

HCIVERSION register . . . . . . . . . . . . . . . . . . 33

HCSPARAMS register . . . . . . . . . . . . . . . . . . 33

HCCPARAMS register . . . . . . . . . . . . . . . . . . 34

EHCI operational registers . . . . . . . . . . . . . . . 35

USBCMD register . . . . . . . . . . . . . . . . . . . . . . 35

USBSTS register . . . . . . . . . . . . . . . . . . . . . . 36

USBINTR register. . . . . . . . . . . . . . . . . . . . . . 37

FRINDEX register. . . . . . . . . . . . . . . . . . . . . . 37

CONFIGFLAG register . . . . . . . . . . . . . . . . . . 38

PORTSC1 register . . . . . . . . . . . . . . . . . . . . . 39

ISO PTD Done Map register. . . . . . . . . . . . . . 40

ISO PTD Skip Map register . . . . . . . . . . . . . . 41

8.1.1

8.1.2

8.1.3

8.1.4

8.2

8.2.1

8.2.2

8.2.3

8.2.4

8.2.5

8.2.6

8.2.7

8.2.8

9

9.1

9.2

9.3

9.3.1

9.3.2

9.4

9.4.1

9.4.2

9.4.3

9.5

OTG controller . . . . . . . . . . . . . . . . . . . . . . . . 85

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Dual-role device . . . . . . . . . . . . . . . . . . . . . . . 85

Session Request Protocol (SRP). . . . . . . . . . 86

B-device initiating SRP. . . . . . . . . . . . . . . . . . 86

A-device responding to SRP . . . . . . . . . . . . . 86

Host Negotiation Protocol (HNP) . . . . . . . . . . 87

Sequence of HNP events. . . . . . . . . . . . . . . . 87

OTG state diagrams. . . . . . . . . . . . . . . . . . . . 88

HNP implementation and OTG state machine 90

OTG controller registers. . . . . . . . . . . . . . . . . 91

Device Identiﬁcation registers . . . . . . . . . . . . 92

Vendor ID register . . . . . . . . . . . . . . . . . . . . . 92

9.5.1

9.5.1.1

continued >>

ISP1761_5

Product data sheet

Rev. 05 — 13 March 2008

161 of 163

ISP1761

NXP Semiconductors

Hi-Speed USB OTG controller

9.5.1.2

9.5.2

9.5.2.1

9.5.3

9.5.3.1

9.5.3.2

9.5.3.3

9.5.3.4

9.5.4

Product ID register (R: 0372h) . . . . . . . . . . . . 92

10.8.1

10.8.2

10.8.3

10.8.4

10.8.5

10.8.6

10.8.7

DcInterrupt register . . . . . . . . . . . . . . . . . . . 123

DcChipID register. . . . . . . . . . . . . . . . . . . . . 125

Frame Number register . . . . . . . . . . . . . . . . 125

DcScratch register . . . . . . . . . . . . . . . . . . . . 125

Unlock Device register . . . . . . . . . . . . . . . . . 126

Interrupt Pulse Width register. . . . . . . . . . . . 126

Test Mode register . . . . . . . . . . . . . . . . . . . . 127

OTG Control register . . . . . . . . . . . . . . . . . . . 93

OTG Interrupt registers. . . . . . . . . . . . . . . . . . 94

OTG Status register . . . . . . . . . . . . . . . . . . . . 94

OTG Interrupt Latch register. . . . . . . . . . . . . . 95

OTG Interrupt Enable Fall register . . . . . . . . . 96

OTG Interrupt Enable Rise register . . . . . . . . 96

OTG Timer register. . . . . . . . . . . . . . . . . . . . . 97

11

12

13

14

Power consumption . . . . . . . . . . . . . . . . . . . 128

Limiting values . . . . . . . . . . . . . . . . . . . . . . . 129

Recommended operating conditions . . . . . 129

Static characteristics . . . . . . . . . . . . . . . . . . 130

9.5.4.1

10

10.1

10.1.1

Peripheral controller . . . . . . . . . . . . . . . . . . . . 99

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Direct Memory Access (DMA) . . . . . . . . . . . . 99

15

15.1

15.1.1

Dynamic characteristics. . . . . . . . . . . . . . . . 133

Host timing . . . . . . . . . . . . . . . . . . . . . . . . . . 135

PIO timing . . . . . . . . . . . . . . . . . . . . . . . . . . 135

10.1.1.1 DMA for the IN endpoint . . . . . . . . . . . . . . . . . 99

10.1.1.2 DMA for the OUT endpoint . . . . . . . . . . . . . . . 99

10.1.1.3 DMA initialization . . . . . . . . . . . . . . . . . . . . . . 99

10.1.1.4 Starting DMA . . . . . . . . . . . . . . . . . . . . . . . . 100

10.1.1.5 DMA stop and interrupt handling . . . . . . . . . 100

10.2

10.3

10.4

15.1.1.1 Register or memory write. . . . . . . . . . . . . . . 135

15.1.1.2 Register read . . . . . . . . . . . . . . . . . . . . . . . . 136

15.1.1.3 Register access . . . . . . . . . . . . . . . . . . . . . . 136

15.1.1.4 Memory read . . . . . . . . . . . . . . . . . . . . . . . . 137

Endpoint description. . . . . . . . . . . . . . . . . . . 101

Clear buffer . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Differences between the ISP1761 and

15.1.2

DMA timing. . . . . . . . . . . . . . . . . . . . . . . . . . 138

15.1.2.1 Single cycle: DMA read . . . . . . . . . . . . . . . . 138

15.1.2.2 Single cycle: DMA write . . . . . . . . . . . . . . . . 139

15.1.2.3 Multi-cycle: DMA read . . . . . . . . . . . . . . . . . 140

15.1.2.4 Multi-cycle: DMA write . . . . . . . . . . . . . . . . . 141

15.2

15.2.1

15.2.1.1 PIO register read or write. . . . . . . . . . . . . . . 142

15.2.1.2 PIO register access . . . . . . . . . . . . . . . . . . . 143

15.2.2

ISP1582 peripheral controllers . . . . . . . . . . . 102

ISP1761 initialization registers . . . . . . . . . . . 102

ISP1761 DMA. . . . . . . . . . . . . . . . . . . . . . . . 103

ISP1761 peripheral suspend indication . . . . 103

ISP1761 interrupt and DMA common mode. 103

Peripheral controller-speciﬁc registers . . . . . 103

Address register . . . . . . . . . . . . . . . . . . . . . . 104

Mode register . . . . . . . . . . . . . . . . . . . . . . . . 105

Interrupt Conﬁguration register. . . . . . . . . . . 106

Debug register . . . . . . . . . . . . . . . . . . . . . . . 107

DcInterruptEnable register . . . . . . . . . . . . . . 108

Data ﬂow registers . . . . . . . . . . . . . . . . . . . . 109

Endpoint Index register. . . . . . . . . . . . . . . . . 109

Control Function register . . . . . . . . . . . . . . . 110

Data Port register . . . . . . . . . . . . . . . . . . . . . 112

Buffer Length register . . . . . . . . . . . . . . . . . . 112

DcBufferStatus register. . . . . . . . . . . . . . . . . 113

Endpoint MaxPacketSize register. . . . . . . . . 114

Endpoint Type register . . . . . . . . . . . . . . . . . 114

DMA registers. . . . . . . . . . . . . . . . . . . . . . . . 115

DMA Command register . . . . . . . . . . . . . . . . 116

DMA Transfer Counter register . . . . . . . . . . . 117

DcDMAConﬁguration register . . . . . . . . . . . . 118

DMA Hardware register . . . . . . . . . . . . . . . . 119

DMA Interrupt Reason register. . . . . . . . . . . 120

DMA Interrupt Enable register . . . . . . . . . . . 121

DMA Endpoint register . . . . . . . . . . . . . . . . . 121

DMA Burst Counter register . . . . . . . . . . . . . 122

General registers . . . . . . . . . . . . . . . . . . . . . 123

10.4.1

10.4.2

10.4.3

10.4.4

10.5

10.5.1

10.5.2

10.5.3

10.5.4

10.5.5

10.6

10.6.1

10.6.2

10.6.3

10.6.4

10.6.5

10.6.6

10.6.7

10.7

10.7.1

10.7.2

10.7.3

10.7.4

10.7.5

10.7.6

10.7.7

10.7.8

10.8

Peripheral timing . . . . . . . . . . . . . . . . . . . . . 142

PIO timing . . . . . . . . . . . . . . . . . . . . . . . . . . 142

DMA timing. . . . . . . . . . . . . . . . . . . . . . . . . . 144

15.2.2.1 DMA read or write . . . . . . . . . . . . . . . . . . . . 144

16

Package outline . . . . . . . . . . . . . . . . . . . . . . . 146

17

Soldering of SMD packages . . . . . . . . . . . . . 148

Introduction to soldering. . . . . . . . . . . . . . . . 148

Wave and reﬂow soldering . . . . . . . . . . . . . . 148

Wave soldering. . . . . . . . . . . . . . . . . . . . . . . 148

Reﬂow soldering. . . . . . . . . . . . . . . . . . . . . . 149

17.1

17.2

17.3

17.4

18

18.1

Soldering of through-hole mount packages 150

Introduction to soldering through-hole

mount packages. . . . . . . . . . . . . . . . . . . . . . 150

Soldering by dipping or by solder wave . . . . 150

Manual soldering . . . . . . . . . . . . . . . . . . . . . 150

Package related soldering information. . . . . 151

18.2

18.3

18.4

19

20

21

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . 152

References. . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Revision history . . . . . . . . . . . . . . . . . . . . . . 154

22

Legal information . . . . . . . . . . . . . . . . . . . . . 155

Data sheet status . . . . . . . . . . . . . . . . . . . . . 155

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . 155

22.1

22.2

22.3

continued >>

ISP1761_5

Product data sheet

Rev. 05 — 13 March 2008

162 of 163

ISP1761

NXP Semiconductors

Hi-Speed USB OTG controller

22.4

23

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . 155

Contact information. . . . . . . . . . . . . . . . . . . . 155

Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

24

25

26

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 13 March 2008

Document identifier: ISP1761_5


型号：	ISP1761ET,551
厂家：	NXP
描述：	USB Bus Controller, CMOS, PBGA128, 9 X 9 MM, 0.80 MM HEIGHT, PLASTIC, MO-195, SOT857-1, TFBGA-128 时钟 PC 外围集成电路
文件：	总164页 (文件大小：768K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISP1761ET,551 [NXP]

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