IW416_技术文档

IW416

Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

Rev. 4 — 25 June 2021

Product data sheet

1 Product overview

The IW416 is a highly integrated Wi-Fi 4 and Bluetooth 5.1 System-on-Chip (SoC)

enabling a low-cost connectivity solution. Supporting a 1x1 SISO Wi-Fi operation in the

2.4ꢀGHz and the 5ꢀGHz band, the SoC provides a full-feature Wi-Fi subsystem with a

peak PHY date rate of 150ꢀMbit/s. In addition to classic Bluetooth features, the IW416

enables Bluetooth 5.1 capabilities including Low Energy (LE), LE long range and LE data

up to 2ꢀMbit/s.

With integrated transmit (Tx) PAs, receive (Rx) LNAs and Tx/Rx switches for the Wi-Fi

and Bluetooth radios, the IW416 simplifies design allowing quick integration of either dual

or single-antenna operation. The dual-antenna configuration enables simultaneous Wi-Fi

and Bluetooth operation. With the single-antenna configuration, simultaneous 5ꢀGHz Wi-

Fi and Bluetooth is supported and in the 2.4ꢀGHz band, the single-antenna configuration

allows arbitrated transmit and receive operation of Wi-Fi and Bluetooth.

Promoting synergistic operation, the IW416 implements advanced Wi-Fi and Bluetooth

co-existence hardware in conjunction with algorithms to optimize collaborative

performance. In addition, support for external radio co-existence (e.g. cellular) is provided

through an external interface.

Available in both HVQFN68 and WLCSP76 packages with two operating temperature

ranges of 0 to 70°C and -40 to 85°C, the IW416 supports a SDIO host interface for the

Wi-Fi radio and a UART host interface for Bluetooth radio.

Wi-Fi antenna

SDIO interface

IW416

Wi-Fi 5 GHz Tx/Rx

Wi-Fi 2.4 GHz Tx/Rx

UART interface

Diplexer

Audio interface

(I2S/PCM)

Bluetooth antenna

GPIO interface

Supply voltages

Bluetooth Tx/Rx

Coexistence

Power-down

XTAL_IN

XTAL_OUT

Figure 1.ꢀApplication block diagram

Note: More application details in IW416 Design Guide (AN13125)

NXP Semiconductors

IW416

Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

1.1 Applications

• Smart home: Voice assist device, smart printer, smart speaker, home automation

gateway, and IP camera

• Industrial and building automation

• Asset management

• Retail/POS

• Healthcare and medical devices

• Smart city

1.2 Wi-Fi key features

• Support 802.11 a/b/g/n

• Dual band: 2.4 GHz and 5 GHz

• Single stream 802.11n with 20 MHz and 40 MHz channels

• Up to MCS7 data rates (150 Mbit/s)

• Dynamic Rapid Channel Switching (DRCS) for simultaneous operation in 2.4 GHz and

5 GHz bands

• Interface to coexist with 802.15.4, LTE, or other radios

• Security: WPA3, WPA2, WPA2 and WPA mixed mode, WEP

1.3 Bluetooth key features

• Full Bluetooth 5.1 features

• Long range - 4x coverage

• 2 Mbit/s data rate - 2x faster

• Improved advertisement capability - enables more IoT services

• I2S and PCM audio interfaces

• AES security

1.4 Host interfaces

Wi-Fi and Bluetooth host interface options

Wi-Fi

Bluetooth

SDIO 3.0

UART

IW416

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NXP Semiconductors

IW416

Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

1.5 Operating characteristics

• Supply voltage: 1.05V, 1.8V, and 2.2V

• Operating temperature:

– Commercial: 0 to 70°C

– Industrial: -40 to 85°C

1.6 General features

• Package options

– HVQFN68 (68 pins, 0.4ꢀmm pitch, 8ꢀmm x 8ꢀmm x 0.85ꢀmm body)

– WLCSP76 (76 terminals, 3.95 mm x 3.565 mm x 0.495 mm body)

• Simultaneous Wi-Fi and Bluetooth operation supported with dual antenna configuration

– Shared Wi-Fi and Bluetooth operation with single antenna is possible

• Power saving features

– Efficient power management system

– Sleep and standby modes

– Deep-sleep mode

• Independent ARM-based Wi-Fi and Bluetooth CPUs

– Wi-Fi CPU: 160ꢀMHz clock speed

– Bluetooth CPU: 128 MHz clock speed

• Memory:

– Internal SRAM

– Boot ROM

– OTP memory to store the MAC address and calibration data

• Peripheral Interface

– General-Purpose I/O (GPIO) interface

IW416

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NXP Semiconductors

IW416

Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

1.7 Internal block diagram

Wi-Fi 5G Tx/Rx

5 GHz PA/LNA

SPDT

Wi-Fi 4

MAC/Baseband

SDIO 3.0

Wi-Fi CPU

Wi-Fi 2.4G Tx/Rx

2.4 GHz PA/LNA

UART

Bluetooth/

Bluetooth LE

Baseband

Bluetooth Tx/Rx

Bluetooth

CPU

Bluetooth RF

I2S/PCM

Supply voltages

Power regulator

OTP

Coexistence

Figure 2.ꢀInternal block diagram

IW416

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IW416

Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

2 Ordering information

IW416xx/xxxxx

Packing code

Temperature code

C = Commercial

I = Industrial

Part number

Package code

Die version

Figure 3.ꢀPart numbering scheme

Table 1.ꢀPart order codes

Part order code

Package type

Operating

Packing

temperature range

Commercial

Industrial

IW416HN/A1CK

HVQFN68 - 8 x 8 x 0.85 mm, with 0.4ꢀmm pitch

Tray

IW416HN/A1CMP HVQFN68 - 8 x 8 x 0.85 mm, with 0.4ꢀmm pitch

Tape and Reel

Tray

IW416HN/A1IK

IW416HN/A1IMP

IW416UK/A1CZ

IW416UK/A1IZ

HVQFN68 - 8 x 8 x 0.85 mm, with 0.4ꢀmm pitch

WLCSP76 - 3.95 x 3.565 x 0.495 mm

Industrial

Tape and Reel

Commercial

Industrial

WLCSP76 - 3.95 x 3.565 x 0.495 mm

IW416

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NXP Semiconductors

IW416

Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

3 Wi-Fi subsystem

3.1 IEEE 802.11 standards

• 802.11n maximum data rates up to 72ꢀMbit/s (20ꢀMHz channel bandwidth), 150ꢀMbit/s

(40ꢀMHz channel bandwidth)

• 802.11a/g/b backward compatibility

• 802.11d international roaming

• 802.11e quality of service

• 802.11h transmit power control

• 802.11h DFS radar pulse detection

• 802.11i enhanced security

• 802.11k radio resource measurement

• 802.11n block acknowledgment extension

• 802.11r fast hand-off for AP roaming

• 802.11u Hotspot 2.0 (STA mode only)

• 802.11v TIM frame transmission/reception

• 802.11w protected management frames

• Fully supports clients (stations) implementing IEEE Power Save mode

3.2 Wi-Fi MAC

The Wi-Fi MAC has the following features:

• Simultaneous peer-to-peer and infrastructure modes

• RTS/CTS for operation under DCF

• Hardware filtering of 32 multicast addresses and duplicate frame detection for up to 32

unicast addresses

• On-chip Tx and Rx FIFO for maximum throughput

• Open System and Shared Key Authentication services

• A-MPDU Rx (de-aggregation) and Tx (aggregation)

• 20/40 MHz coexistence

• Reduced Inter-Frame Spacing (RIFS) receive

• Packet drop scheme

• Management information base counters

• Radio resource measurement counters

• Quality of service queues

• Block acknowledgment extension

• Dynamic frequency selection

• TIM frame transmission/reception

• Multiple BSS/Station

• Transmit rate adaptation

• Transmit power control

• Long and short preamble generation on a frame-by-frame basis for 802.11b frames

• NXP mobile hotspot

IW416

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IW416

Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

3.3 Wi-Fi baseband

The Wi-Fi baseband has the following features:

• 802.11n 1x1 SISO

• Bandwidth supported:

– 20ꢀMHz

– 20 in 40ꢀMHz (upper and lower)

– 40ꢀMHz

– 20ꢀMHz duplicate

• 802.11n modulation coding scheme (MCS) 0-7 and MCS 32 (HT duplicate mode)

• 802.11n 400ꢀns and 800ꢀns guard interval

• Dynamic frequency selection (radar detection)

– Enhanced radar detection for long and short pulse radar

– Enhanced AGC scheme for DFS channel

• Radio resource measurement

• Optional 802.11n SISO features:

– 20/40 MHz coexistence

– 1 spatial stream STBC reception

– Short guard interval

– RIFS on receive path for 802.11n packets

– 802.11n greenfield Tx/Rx

• Power save features

3.4 Wi-Fi radio

The Wi-Fi radio has the following features:

• Integrated direct-conversion radio

• 20 MHz and 40 MHz channel bandwidths

Wi-Fi Rx path

• Direct conversion architecture: no need for an external SAW filter

• On-chip gain selectable LNA with optimized noise figure and power consumption

• High dynamic range AGC function in receive mode

Wi-Fi Tx path

• Internal PA with power control

• Optimized Tx gain distribution for linearity and noise performance

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IW416

Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

Radio channel frequencies

The Wi-Fi RF radio integrates all the necessary functions for transmit and receive

operation.

The channel frequencies are controlled through an internal bus and software

programmable.

Table 2 shows the frequencies supported by the 20 MHz channels.

Table 2.ꢀFrequencies supported by 20 MHz channels

Channel

1

Frequency (GHz)

2.412

2.417

2.422

2.427

2.432

2.437

2.442

2.447

2.452

2.457

2.462

2.467

2.472

--

2

3

4

5

6

7

8

9

10

11

12

13

--

36

40

44

48

52

56

60

64

100

104

108

112

116

120

124

128

5.180

5.200

5.220

5.240

5.260

5.280

5.300

5.320

5.500

5.520

5.540

5.560

5.580

5.600

5.620

5.640

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IW416

Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

Table 2.ꢀFrequencies supported by 20 MHz channels...continued

Channel

Frequency (GHz)

5.660

132

136

140

149

153

157

161

165

128

132

136

140

149

153

157

161

165

5.680

5.700

5.745

5.765

5.785

5.805

5.825

5.640

5.660

5.680

5.700

5.745

5.765

5.785

5.805

5.825

Table 3 shows the frequencies supported by the 40 MHz channels.

Table 3.ꢀFrequencies Supported by the 40 MHz channels

Channel

1–5

Frequency (GHz)

2.422

2.427

2.432

2.437

2.442

2.447

2.452

--

2–6

3–7

4–8

5–9

6–10

7–11

--

36–40

44–48

52–56

60–64

100–104

108–112

116–120

124–128

5.190

5.230

5.270

5.310

5.510

5.550

5.590

5.630

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IW416

Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

Table 3.ꢀFrequencies Supported by the 40 MHz channels...continued

Channel

Frequency (GHz)

5.670

132–136

149–153

157–161

5.755

5.795

3.5 Wi-Fi encryption

• WEP 64ꢀbit and 128ꢀbit encryption with hardware TKIP processing (WPA)

• AES/CCMP as part of the 802.11i security standard (WPA2 and WPA mixed mode)

• AES/CMAC as part of the 802.11w security standard

3.6 Wi-Fi host interfaces

• SDIO 3.0 device interface

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IW416

Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

4 Bluetooth subsystem

4.1 Bluetooth 2.4 GHz Tx/Rx

• Bluetooth 5.1

• Bluetooth Class 2 and Bluetooth Class 1

• Single-ended, shared Tx/Rx path for Bluetooth

• PCM interface for voice applications

• Baseband and radio Basic Data Rate (BDR)/Enhanced Data Rate (EDR) packet types

—1 Mbit/s (GFSK), 2 Mbit/s (π/4-DQPSK), and 3 Mbit/s (8DPSK)

• Fully functional Bluetooth baseband—Adaptive Frequency Hopping (AFH), forward

error correction, header error control, access code correlation, Cyclic Redundancy

Check (CRC), encryption bit stream generation, and whitening

• Adaptive Frequency Hopping (AFH) using Packet Error Rate (PER)

• Interlaced scan for faster connection setup

• Simultaneous active Asynchronous Connection-Less (ACL) connection support

• Automatic ACL packet type selection

• Full master and slave piconet support

• Scatternet support

• Bluetooth-based indoor location with up to 16 antenna support

• Standard UART HCI transport layer

• HCI layer to integrate with profile stack

• SCO/eSCO links with hardware accelerated audio signal processing and hardware

supported PPEC algorithm for speech quality improvement

• All standard SCO/eSCO voice coding

• All standard pairing, authentication, link key, and encryption operations

• Standard Bluetooth power saving mechanisms (hold, sniff modes, and sniff sub-rating)

• Enhanced Power Control (EPC)

• Channel Quality Driven Data Rate (CQDDR)

• Wide Band Speech (WBS) support (2 WBS link)

• Encryption (AES) support

• Low Latency Reconnection (LLR) (future BT standard)

IW416

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IW416

Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

4.2 Bluetooth Low Energy (LE)

• Broadcaster, Observer, Central, and Peripheral roles

• Supports link layer topology to be master and slave (connects up to 16 links)

• Wi-Fi/Bluetooth Coexistence protocol support

• Shared RF with BDR/EDR

• Encryption (AES) support

• Intelligent Adaptive Frequency Hopping (AFH)

• LE Privacy 1.2

• LE Secure Connection

• LE Data Length Extension

• LE Advertising Extension

• 2ꢀMbit/s LE

4.3 Bluetooth host interfaces

• High-Speed UART interface up to 4ꢀMbit/s

4.4 Audio interfaces

4.4.1 I2S interface

• I2S (Inter-IC Sound) interface for audio data connection to Analog-to-Digital Converter

(ADC)

• Master and slave modes for I2S, MSB, and LSB audio interfaces

• Tri-state I2S interface compatibility

• I2S pins shared with PCM pins

4.4.2 PCM interface

The PCM interface is used to exchange audio data between the host and the Bluetooth/

LE functional block.

• Master or slave mode

• PCM bit width size of 8 bits or 16 bits

• Up to 4 slots with configurable bit width and start positions

• PCM short frame and long frame ¹synchronization

• Tri-state PCM interface capability

• PCM pins shared with I2S pins

1 In PCM Master mode, PCM long frame synchronization is 1 clock wide. In PCM Slave mode, PCM

Master’s long frame synchronization pattern is supported.

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IW416

Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

4.4.2.1 Protocol description

The PCM interface supports short frame sync. Figure 4 shows an example of a PCM

interface with 4 signals.

SYNC

CLK

DOUT

DIN

MSb

MSb-1 MSb-2 MSb-3

d1

d0

Don't Care

aaa-036047

Figure 4.ꢀPCM Short Frame Sync

4.5 Coexistence

The advanced coexistence framework provides packet traffic arbitration (PTA) for the

following use cases:

• Coexistence between internal Wi-Fi and internal Bluetooth radios

• Coexistence between internal Wi-Fi and Bluetooth radios and an external radio such

as 802.15.4, LTE or 5G. The external radio can be connected to the PTA interface or

WCI-2 interface. WCI-2 message format and message type comply with Bluetooth

special interest group (SIG) core specification volume 7 part C.

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IW416

Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

5 Pin information

5.1 Signal diagram

Figure 5 shows the signals for the device. Some signals are muxed through GPIO.

IW416

SD_CLK

RF_TR_2

SD_CMD

SD_DAT[3:0]

SDIO Interface

Wi-Fi Radio Interface

RF_TR_5

BRF_ANT

Bluetooth Radio Interface

UART_SIN

RF_CNTL0_N

RF_CNTL1_P

RF_CNTL2_N

RF_CNTL3_P

UART_SOUT

RF Front End

Control Interface

UART_RTSn

UART_CTSn

UART Interface

(through GPIO)

UART_DTRn

UART_DSRn

I2S_LRCLK

I2S_BCLK

I2S_DOUT

I2S_DIN

I2S Interface

(through GPIO)

WCI-2_SIN

WCI-2_SOUT

I2S_CCLK

WCI-2 interface

PCM_SYNC

PCM_CLK

PCM_MCLK

PCM_DIN

PCM Interface

(through GPIO)

EXT_STATE

EXT_GNT

EXT_FREQ

EXT_PRI

PCM_DOUT

PTA interface

Power Management

Interface

DVSC[0]

DVSC[1]

EXT_REQ

(through GPIO)

LDO_VIN

LDO_VOUT

LDO Interface

GPIO[15:0]

GPIO Interface

XTAL_IN

XTAL_OUT

SLP_CLK_IN

JTAG_TCK

JTAG_TDI

JTAG_TDO

JTAG_TMS

Clock Interface

Power-down

JTAG Interface

(through GPIO)

XOSC_EN

PDn

Signals may be muxed. See Section 5.5 "Pin description".

Figure 5.ꢀSignal diagram

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IW416

Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

5.2 Pin assignment - HVQFN68 package

Note that some pins have muxed signals. See Section 5.5 "Pin description".

51

AVDD33

VIO

1

2

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

GPIO[7]

GPIO[5]

GPIO[14]

GPIO[15]

GPIO[8]

AVDD18

DNC

3

4

DNC

5

GPIO[9]

6

GPIO[10]

VIO

WCI-2_SOUT

WCI-2_SIN

DNC

7

8

GPIO[11]

GPIO[12]

GPIO[13]

9

IW416

SLP_CLK_IN

AVDD18

10

11

12

13

14

15

16

17

GPIO[0]

VCORE

XTAL_OUT

XTAL_IN

AVDD18

AVSS

VIO_RF

RF_CNTL1_P

RF_CNTL0_N

RF_CNTL3_P

RF_CNTL2_N

Figure 6.ꢀPin assignment (package top view) - HVQFN68

Note: See Section 9.10 "Reference clock specifications" for electrical specifications.

See Section 10.3 "Package marking" for more information on package marking and pin 1

location.

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IW416

Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

5.2.1 Pin list by number - HVQFN68 package

The following table shows the pin list sorted by pin number.

Table 4.ꢀPin list by number - HVQFN68 package

Pin number

Pin name

AVDD33

AVDD18

DNC

Power

Type

1

--

Power

2

--

Power

3

—

DNC

4

DNC

—

DNC

5

GPIO[9]

DNC

VIO

I/O

5

—

Do not connect

6

GPIO[10]

VIO

I/O

7

--

Power

8

GPIO[11]

GPIO[12]

GPIO[13]

GPIO[0]

VCORE

VIO_RF

RF_CNTL1_P

RF_CNTL0_N

RF_CNTL3_P

RF_CNTL2_N

AVDD18

BRF_ANT

NC

VIO

I/O

9

VIO

I/O

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

VIO

I/O

VIO

I/O

--

Power

--

Power

VIO_RF

O

VIO_RF

O

VIO_RF

O

VIO_RF

O

--

Power

A, I/O

NC

--

AVDD18

--

VCORE

NC

--

Power

NC

--

RF_TR_2

AVDD18

NC

AVDD18

A, I/O

Power

NC

--

VPA

--

Power

A, I/O

Power

NC

VPA

--

RF_TR_5

AVDD18

NC

AVDD18

--

NC

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Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

Table 4.ꢀPin list by number - HVQFN68 package...continued

Pin number

Pin name

NC

Power

--

Type

NC

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

AVSS

--

Ground

Power

A, I/O

Power

I

AVDD18

XTAL_IN

XTAL_OUT

AVDD18

SLP_CLK_IN

DNC

--

AVDD18

--

AVDD18

--

DNC

I

WCI-2_SIN

WCI-2_SOUT

GPIO[8]

GPIO[15]

GPIO[14]

GPIO[5]

GPIO[7]

VIO

AVDD18

VIO

O

I/O

VIO

I/O

VIO

I/O

VIO

I/O

VIO

I/O

--

Power

I/O

GPIO[1]

GPIO[4]

GPIO[2]

GPIO[6]

GPIO[3]

AVDD18

PDn

VIO

I/O

VIO

I/O

VIO

I/O

VIO

I/O

--

Power

I

AVDD18

--

VCORE

Power

I/O

LDO_VOUT

LDO_VIN

SD_CMD

SD_CLK

VIO_SD

SD_DAT[0]

SD_DAT[1]

SD_DAT[2]

SD_DAT[3]

--

VIO_SD

--

I

Power

I/O

VIO_SD

I/O

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Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

5.2.2 Pin list by name - HVQFN68 package

The following table shows the pin list sorted by pin name.

Table 5.ꢀPin by name - HVQFN68 package

Pin name

AVDD18

AVDD33

AVSS

Pin number

Power

--

Type

Power

Ground

A, I/O

DNC

I/O

2

18

19

20

26

31

36

37

38

41

57

1

--

35

21

43

11

52

6

--

BRF_ANT

DNC

AVDD18

--

GPIO[0]

GPIO[1]

GPIO[10]

GPIO[11]

GPIO[12]

GPIO[13]

GPIO[14]

GPIO[15]

GPIO[2]

GPIO[3]

GPIO[4]

GPIO[5]

GPIO[6]

GPIO[7]

GPIO[8]

GPIO[9]

LDO_VIN

LDO_VOUT

NC

VIO

--

I/O

8

I/O

9

I/O

10

48

47

54

56

53

49

55

50

46

5

I/O

61

60

22

Power

NC

--

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Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

Table 5.ꢀPin by name - HVQFN68 package...continued

Pin name

Pin number

24

27

32

33

34

58

15

14

17

16

25

30

63

62

65

66

67

68

42

4

Power

--

Type

NC

--

NC

--

NC

--

NC

--

NC

PDn

AVDD18

VIO_RF

AVDD18

VIO_SD

AVDD18

—

I

RF_CNTL0_N

RF_CNTL1_P

RF_CNTL2_N

RF_CNTL3_P

RF_TR_2

RF_TR_5

SD_CLK

SD_CMD

SD_DAT[0]

SD_DAT[1]

SD_DAT[2]

SD_DAT[3]

SLP_CLK_IN

DNC

O

A, I/O

I

I/O

I

DNC

Power

I

DNC

3

—

VCORE

VIO

12

23

59

7

--

VIO

51

13

64

28

29

44

45

39

40

--

VIO_RF

VIO_SD

VPA

--

VPA

--

WCI-2_SIN

WCI-2_SOUT

XTAL_IN

XTAL_OUT

AVDD18

O

A, I/O

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5.3 Bump locations - WLCSP76 package

Figure 7.ꢀBump locations - WLCSP76 (non-bump side view, bumps down)

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5.3.1 Bump positions relative to die center - WLCSP76

Table 6.ꢀBump names and locations on WLCSP76 top view

Bump location relative to die

center (non-bump side view)

Alpha-numeric

Signal name

designation

X ( um )

-1080.696

-730.696

-380.696

81.805

Y ( um )

1562.352

1377.352

1124.852

1212.352

774.852

862.352

774.852

724.852

424.852

512.352

424.852

A2

SD_DAT[1]

SD_DAT[3]

VIO

A3

A5

A7

VIO_RF

RF_CNTL1_P

AVDD18

VSS

A8

431.805

781.805

1131.805

1506.805

-1430.696

-1080.696

-730.696

-380.696

81.805

A9

A10

B11

C1

C2

C3

C5

C7

C8

C9

C10

D1

D2

D3

D5

D7

D8

D9

D10

D11

E1

LDO_VIN

VIO_SD

SD_DAT[2]

VCORE

GPIO[0]

VSS

431.805

781.805

1131.805

-1430.696

-1080.696

-730.696

-380.696

81.805

VSS

LDO_VOUT

SD_CLK

SD_DAT[0]

GPIO[10]

GPIO[13]

RF_CNTL0_N

RF_CNTL3_P

VSS

431.805

781.805

1156.805

1506.805

-1430.696

-1080.696

-730.696

-380.696

81.805

BRF_ANT

VCORE

E2

SD_CMD

VSS

E3

E5

GPIO[9]

GPIO[11]

GPIO[12]

RF_CNTL2_N

VSS

E7

E8

431.805

781.805

1131.805

E9

E10

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Table 6.ꢀBump names and locations on WLCSP76 top view...continued

Bump location relative to die

center (non-bump side view)

Alpha-numeric

Signal name

designation

X ( um )

1506.805

-1430.696

-1080.696

-618.196

-268.196

81.805

Y ( um )

374.852

E11

F1

AVDD18

VSS

74.852

F2

GPIO[3]

GPIO[7]

VSS

74.852

F3

74.852

F5

74.852

F7

WCI-2_SOUT

WCI-2_SIN

VSS

74.852

F8

431.805

74.852

F10

G1

G2

G3

G5

G7

G8

G10

G11

H1

H2

H3

H5

H9

H10

J1

1131.805

-1430.696

-1080.696

-618.196

-268.196

81.805

74.852

GPIO[6]

GPIO[4]

GPIO[5]

GPIO[14]

SLP_CLK_IN

DNC

-275.148

-625.148

-975.148

-1325.148

431.805

AVDD18

RF_TR_2

PDn

1116.805

1481.805

-1430.696

-1080.696

-618.196

-268.196

781.805

GPIO[1]

GPIO[8]

VSS

VCORE

VSS

1131.805

-1430.696

-1080.696

-618.196

-268.196

81.805

AVDD18

VSS

J2

J3

AVDD18

VSS

J5

J7

VSS

J8

VSS

431.805

J9

VSS

781.805

J10

J11

K1

K2

K4

K6

VPA

1131.805

1481.805

-1430.696

-1080.696

-518.196

-168.196

RF_TR_5

GPIO[2]

VIO

XTAL_OUT

VSS

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Table 6.ꢀBump names and locations on WLCSP76 top view...continued

Bump location relative to die

center (non-bump side view)

Alpha-numeric

Signal name

designation

X ( um )

181.805

781.805

1131.805

-1080.696

-493.196

-143.195

781.805

1131.805

Y ( um )

-1325.148

-1675.148

K7

K9

K10

L2

AVDD18

VSS

GPIO[15]

XTAL_IN

AVDD18

VSS

L4

L6

L9

L10

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5.4 Pin types

Table 7.ꢀPin types

Pin type

I/O

Description

Digital input/output

Digital input

I

O

Digital output

Analog input

Analog output

Analog input/output

No connect

A, I

A,O

A, I/O

NC

DNC

Power

Ground

Do not connect

Power

Ground

5.5 Pin description

5.5.1 Pin states

The pin states information provided in the tables includes:

• No Pad Power State indicates the state when there is no power

• PwrDwn State denotes the power-down state in default configuration. Many pads have

programmable power-down values, which can be set by firmware.

• Reset State is the state after the power-on-reset state and before the hardware state

(HW State)

• HW State (hardware state) is the state after boot code finishes and before firmware

download begins (firmware may change the pin state). HW State may differ based on

the pin muxing/strap setting. For example, for UART_RTSn and UART_SOUT, the boot

code will enable the UART interface when the device is in SDIO-UART mode, making

the HW states output high and output low, respectively.

• PwrDwn Prog indicates if the power-down state can be programmed

• Internal PU/PD columns indicates the following:

– Type of PU/PD (weak vs nominal)

– The polarity (PU vs. PD)

The internal pull-up or pull-down applies when the pin is in input mode

• PU denotes whether the pull-up can be programmed or not

• PD denotes whether the pull-down can be programmed or not

• Pull-up and pull-down are only effective when the pad is in input mode

• After firmware is downloaded, the pads (GPIO, RF control, and so on) are programmed

in functional mode per the functionality of the pins

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5.5.2 General purpose I/O (GPIO) (MFP)

Table 8.ꢀGPIO^[1](MFP)

Pins may be Multi-Functional Pins (MFP).

Pin Name

Supply

No Pad

Power

State

Reset

State

HW State PwrDwn

State

PwrDwn

Prog

Internal PU/ PU

PD

GPIO[15]

VIO

tristate

input

drive high

yes

nominal PU

yes

GPIO mode: GPIO[15] (input/output)

JTAG mode: JTAG_TMS - JTAG test mode select (input). See Section 5.5.13 "JTAG interface".

Reset recovery mode: Independent software reset for Bluetooth subsystem (input)

GPIO[14]

VIO

tristate

input

tristate

yes

nominal PU

yes

GPIO mode: GPIO[14] (input/output)

JTAG mode: JTAG_TCK - JTAG test clock (input). See Section 5.5.13 "JTAG interface".

Reset recovery mode: Independent software reset for Wi-Fi subsystem (input)

GPIO[13]

VIO

tristate

input

drive high

yes

GPIO mode: GPIO[13] (input/output)

UART mode: UART_DTRn - UART data-terminal-ready (output). See Section 5.5.6 "UART host interface".

Out-of-band wake-up mode: Host to IW416 Wi-Fi wake-up (input)

GPIO[12]

VIO

tristate

input

tristate

yes

nominal PU

GPIO mode: GPIO[12] (input/output)

UART mode: UART_DSRn - UART data-set-ready (input) (active low).See Section 5.5.6 "UART host interface".

Host wake-up mode: Host to IW416 Bluetooth wake-up (input)

GPIO[11]

VIO

tristate

output

input

drive high

yes

weak PU

yes

GPIO mode: GPIO[11] (input/output)

This pin is used as a configuration pin: CON[8] (input)

See Section 5.6 "Configuration pins".

UART mode: UART_RTSn - UART request-to-send (output) (active low). See Section 5.5.6 "UART host interface".

GPIO[10]

GPIO mode: GPIO[10] (input/output)

UART mode: UART_SOUT - UART serial (output). See Section 5.5.6 "UART host interface".

GPIO[9] VIO tristate output input tristate yes

GPIO mode: GPIO[9] (input/output)

UART mode: UART_SIN - UART serial (input). See Section 5.5.6 "UART host interface".

GPIO[8] VIO tristate input input drive low yes

GPIO mode: GPIO[8] (input/output)

VIO

tristate

input

tristate

yes

nominal PU

weak PU

yes

This pin is used as a configuration pin: CON[7] (input)

See Section 5.6 "Configuration pins".

UART mode: UART_CTSn - UART clear-to-send input signal (input, active low). See Section 5.5.6 "UART host interface".

GPIO[7] VIO tristate input input tristate yes nominal PU yes yes

GPIO mode: GPIO[7] (input/output)

PCM mode: PCM_SYNC - PCM frame sync (input if slave, output if master). See Section 5.5.7 "Audio interface".

I2S mode: I2S_LRCLK - I2S left-right clock (input if slave, output if master). See Section 5.5.7 "Audio interface".

PTA mode: EXT_REQ - Request from the external radio (input). See Section 5.5.8 "PTA interface".

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Table 8.ꢀGPIO^[1](MFP)...continued

Pins may be Multi-Functional Pins (MFP).

Pin Name

Supply

No Pad

Power

State

Reset

State

HW State PwrDwn

State

PwrDwn

Prog

Internal PU/ PU

PD

GPIO[6]

VIO

tristate

input

tristate

yes

nominal PU

yes

GPIO mode: GPIO[6] (input/output)

PCM mode: PCM_CLK - PCM data clock (input if slave, output if master). See Section 5.5.7 "Audio interface".

I2S mode: I2S_BCLK - I2S bit clock (input if slave, output if master). See Section 5.5.7 "Audio interface".

PTA mode: EXT_PRI - External radio priority signal (input). See Section 5.5.8 "PTA interface".

GPIO[5]

GPIO mode: GPIO[5] (input/output)

PCM mode: PCM_DIN^[2]- PCM receive signal (input). See Section 5.5.7 "Audio interface".

VIO

tristate

input

tristate

yes

weak PU

yes

I2S mode: I2S_DOUT/I2S_DIN - I2S transmit/receive signal (output/input) (depending on the configuration). See

Section 5.5.7 "Audio interface".

PTA mode: EXT_GNT - External radio grant signal (output). See Section 5.5.8 "PTA interface".

GPIO[4]

GPIO mode: GPIO[4] (input/output)

PCM mode: PCM_DOUT^[3]- PCM transmit signal (output). See Section 5.5.7 "Audio interface".

VIO

tristate

output

input

tristate

yes

nominal PU

yes

I2S mode: I2S_DOUT/I2S_DIN (depending on the configuration. If GPIO[5] is configured as I2S_DIN, then GPIO[4] is set

as I2S_DOUT, and vice-verse). See Section 5.5.7 "Audio interface".

PTA mode: EXT_FREQ - External radio frequency signal (input). See Section 5.5.8 "PTA interface".

Out-of-band wake-up mode: IW416 Bluetooth to host wake-up signal (output)^[4]

GPIO[3]

GPIO mode: GPIO[3] (input/output)

Power management mode: DVSC[1], Digital voltage scaling control (output)

JTAG mode: JTAG_TDO, JTAG test data (output). See Section 5.5.13 "JTAG interface".

VIO

tristate

input

tristate

yes

weak PU

yes

PCM mode: PCM_MCLK (output) - PCM clock signal (output, optional). See Section 5.5.7 "Audio interface".

I2S mode: I2S_CCLK - I2S clock (output, optional). See Section 5.5.7 "Audio interface".

GPIO[2]

GPIO mode: GPIO[2] (input/output)

Power management mode: DVSC[0], Digital voltage scaling control (output)

JTAG mode: JTAG_TDI, JTAG test data (input). See Section 5.5.13 "JTAG interface".

GPIO[1] VIO tristate input input tristate yes

GPIO mode: GPIO[1] (input/output)

This pin is used as a configuration pin: CON[9] (input). See Section 5.6 "Configuration pins".

VIO

tristate

input

tristate

yes

weak PU

yes

weak PU

PTA mode: EXT_STATE - External radio state signal (input). See Section 5.5.8 "PTA interface".

Out-of-band wake-up mode: IW416 Wi-Fi to host wake-up signal (output)

GPIO[0]

VIO

tristate

output

drive low

yes

nominal PU

yes

GPIO mode: GPIO[0] (input/output)

Oscillator enable mode: XOSC_EN (output) (active high). See Section 5.5.10 "Clock interface".

[1] Not all GPIO pins can be used for Host-to-SoC wake-up signals.

[2] The function can be swapped with GPIO[4] using a software command without affecting the hardware connection.

[3] The function can be swapped with GPIO[5] using a software command without affecting the hardware connection.

[4] If PCM and UART interfaces are used in application, use GPIO[0] as alternative for this wake-up signal

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5.5.3 Wi-Fi/Bluetooth radio interface

Table 9.ꢀWi-Fi/Bluetooth radio interface

Pin Name

RF_TR_2

RF_TR_5

BRF_ANT

Type

A, I/O

Supply

Description

AVDD18

Wi-Fi Transmit/Receive (2.4 GHz)

Wi-Fi Transmit/Receive (5 GHz)

Bluetooth Transmit/Receive

5.5.4 Wi-Fi RF front-end control interface

Table 10.ꢀWi-Fi RF front-end control interface

Pin Name

Supply

No Pad

Power

State

Reset

State

HW State PwrDwn

State

PwrDwn

Prog

Internal

PU/PD

PU

PD

RF_CNTL0_N

VIO_RF

tristate

input

output

drive low

yes

weak PU

no

RF Control 0—RF Control Output Low (output)

This pin is used as a configuration pin: CON[0] (input)

See Section 5.6 "Configuration pins".

RF_CNTL1_P

VIO_RF

tristate

input

output

drive high

drive low

yes

weak PU

no

RF Control 1—RF Control Output High (output)

This pin is used as a configuration pin: CON[6] (input)

RF_CNTL2_N

VIO_RF

tristate

input

RF Control 2—RF Control Output Low (output)

This pin is used as a configuration pin: CON[1] (input)

See Section 5.6 "Configuration pins".

RF_CNTL3_P

VIO_RF

tristate

input

output

drive high

yes

weak PU

no

RF Control 3—RF Control Output High (output)

This pin is used as a configuration pin: CON[5] (input)

See Section 5.6 "Configuration pins".

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5.5.5 SDIO host interface (MFP)

Table 11.ꢀSDIO host i (MFP)

Pins may be Multi-Functional Pins (MFP). See pin descriptions for functional modes.

Pin Name

Supply

No Pad

Power

State

Reset

State

HW State PwrDwn

State

PwrDwn

Prog

Internal PU/ PU

PD

SD_CLK

VIO_SD

tristate

input

tristate

no

nominal PU

yes

SDIO 4-bit mode: Clock input

SDIO 1-bit mode: Clock input

SD_CMD

VIO_SD

tristate

input

tristate

no

nominal PU

yes

SDIO 4-bit mode: Command/response (input/output)

SDIO 1-bit mode: Command line

SD_DAT[3]

VIO_SD

tristate

input

tristate

no

nominal PU

yes

SDIO 4-bit mode: Data line Bit[3]

SDIO 1-bit mode: Reserved

SD_DAT[2]

VIO_SD

tristate

input

SDIO 4-bit mode: Data line Bit[2] or read wait (optional)

SDIO 1-bit mode: Read wait (optional)

SD_DAT[1]

VIO_SD

tristate

input

SDIO 4-bit mode: Data line Bit[1]

SDIO 1-bit mode: Interrupt

SD_DAT[0]

VIO_SD

tristate

input

SDIO 4-bit mode: Data line Bit[0]

SDIO 1-bit mode: Data line

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5.5.6 UART host interface

Table 12.ꢀUART host interface (MFP)

Pins may be Multi-Functional Pins (MFP).

Pin Name

Type

Supply

VIO

Description

UART_SIN

UART_SOUT

UART_RTSn

I

UART serial input signal - muxed with GPIO[9]

UART serial output signal - muxed with GPIO[10]

O

VIO

UART request-to-send output signal (active low) - muxed with

GPIO[11]

UART_CTSn

UART_DTRn

I

VIO

UART clear-to-send input signal (active low) - muxed with GPIO[8]

O

UART data-terminal-ready output signal (active low) - muxed with

GPIO[13]

UART_DSRn

I

VIO

UART data-set-ready input signal (active low) - muxed with GPIO[12]

5.5.7 Audio interface

Table 13.ꢀAudio interface pins (MFP)

Pins may be Multi-Functional Pins (MFP). See pin descriptions for functional modes.

Pin Name

Type

I

Supply

VIO

Description

PCM_DIN

PCM receive input signal - muxed with GPIO[4]/GPIO[5]

PCM transmit output signal - muxed with GPIO[4]/GPIO[5]

PCM_DOUT

PCM_SYNC

O

VIO

I/O

VIO

PCM frame sync - muxed with GPIO[7]

• Output if master

• Input if slave

PCM_CLK

I/O

O

VIO

PCM data clock - muxed with GPIO[6]

• Output if master

• Input if slave

PCM_MCLK

PCM clock signal (output, optional) - muxed with GPIO[3]

Optional clock used for some codecs.

I2S_DIN

I

VIO

I2S receive input signal - muxed with GPIO[4]/GPIO[5] , depending

on the configuration.

I2S_DOUT

I2S_LRCLK

O

I/O

I2S transmit output data signal - muxed with GPIO[4]/GPIO[5] ,

depending on the configuration.

I2S left-right clock - muxed with GPIO[7]

• Output if master

• Input if slave

I2S_BCLK

I2S_CCLK

I/O

O

VIO

I2S bit clock - muxed with GPIO[6]

• Output if master

• Input if slave

I2S clock (output/optional) - muxed with GPIO[3] .

Optional clock used for some codecs.

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5.5.8 PTA interface

Table 14.ꢀPTA interface (MFP)

Pins may be Multi-Functional Pins (MFP). See pin descriptions for functional modes.

Pin Name

Type

Supply

Description

EXT_STATE

I

VIO

External radio state input signal - muxed with GPIO[1]

External radio traffic direction (Tx/Rx):

• 1: Tx

• 0: rx

EXT_GNT

O

I

VIO

External radio grant output signal - muxed with GPIO[5]

EXT_FREQ

External radio frequency input signal - muxed with GPIO[4]

Frequency overlap between external radio and Wi-Fi:

• 1: overlap

• 0: non-overlap

This signal is useful when the external radio is a frequency hopping

device.

EXT_PRI

I

VIO

External radio input priority signal - muxed with GPIO[6]

Priority of the request from the external radio. Can support 1 bit

priority (sample once) and 2 bit priority (sample twice). Can also have

Tx/Rx info following the priority info if EXT_STATE is not used.

EXT_REQ

Request from the external radio - muxed with GPIO[7]

5.5.9 WCI-2 interface

Table 15.ꢀWCI-2 interface

Pin Name

Supply

No Pad

Power

State

Reset

State

HW

State

PwrDwn

State

PwrDwn

Prog

Internal

PU/PD

PU

PD

WCI-2_SIN

AVDD18

tristate

input

tristate

no

weak PU

yes

WCI-2_SIN (input)

WCI-2_SOUT

tristate

output

WCI-2_SOUT (output)

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5.5.10 Clock interface

Table 16.ꢀClock interface

Pin Name

Supply

No Pad

Power

State

Reset

State

HW

State

PwrDwn

State

PwrDwn

Prog

Internal PU/ PU

PD

XTAL_IN

AVDD18

--

Reference clock input

Reference clock signal frequency must be 26ꢀMHz or 40ꢀMHz from an external crystal or external crystal oscillator.

Power consumption in sleep mode is lower with an external crystal compared to an external crystal oscillator when an

external sleep clock is not used.

See Section 9.10 "Reference clock specifications".

XTAL_OUT

Connect this pin to an external crystal when an external crystal is used.

When an external crystal oscillator is used, connect this pin to ground with resistance less than 100 Ω.

SLP_CLK_IN AVDD18 tristate input input tristate no nominal PU

Sleep clock input (optional)

Used for lower power operation in sleep mode.

AVDD18

--

yes

• An external sleep clock of 32.768 kHz can be used to reduce the current consumption in sleep mode.

• If no external sleep clock is used, leave this pin floating (DNC).

XOSC_EN

VIO

--

Oscillator enable (output) (active high)

XOSC_EN signal can be used ONLY when an external sleep clock is used.

Used to enable an external oscillator.

0 = disable external oscillator

1 = enable external oscillator

Note: Muxed with GPIO[0].

5.5.11 Power down (PDn) pin

Table 17.ꢀPower down (PDn) pin

Pin Name

Supply

No Pad

Power

State

Reset

State

HW

State

PwrDwn

State

PwrDwn

Prog

Internal PU/ PU

PD

PDn

AVDD18

--

Full power-down (input) (active low)

0 = full power-down mode

1 = normal mode

• PDn can accept an input of 1.8V to 4.5V

• PDn may be driven by the host

• PDn must be high for normal operation

No internal pull-up on this pin.

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5.5.12 Power supply and ground

Table 18.ꢀPower and ground pins

Pin Name

VCORE

VIO

Type

Description

Power

1.05V core power supply

1.8V/3.3V digital I/O power supply

VIO_SD

1.8V/3.3V digital I/O SDIO power supply

Note:

1. For SDIO 2.0, VIO_SD must be 3.3ꢀV

2. For SDIO 3.0, VIO_SD must be 1.8ꢀV

VIO_RF

AVDD33

Power

1.8V/3.3V analog I/O RF power supply

3.3V analog power supply

Note: For new designs, leave this pin unconnected.

AVDD18

VPA

Power

Ground

NC

1.8V analog power supply

2.2V analog power supply

LDO voltage input (1.8V)

LDO voltage output

Ground

LDO_VIN

LDO_VOUT

AVSS

NC

No Connect

DNC

Do Not Connect

Do not connect these pins. Leave these pins floating.

5.5.13 JTAG interface

Table 19.ꢀJTAG interface pins (MFP)

Pins may be Multi-Functional Pins (MFP).

Pin Name

JTAG_TDO

JTAG_TDI

JTAG_TMS

JTAG_TCK

Type

Supply

VIO

Description

O

I

JTAG test data output signal - muxed with GPIO[3]

JTAG test data input signal - muxed with GPIO[2]

JTAG test mode select input signal - muxed with GPIO[15]

JTAG test clock input signal - muxed with GPIO[14]

VIO

I

VIO

I

VIO

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5.6 Configuration pins

The table below shows the pins used as configuration inputs to set parameters following

a reset. The definition of these pins changes immediately after reset to their usual

function.

To set a configuration bit to 0, attach a 50 kΩ–100 kΩ resistor from the pin to ground. No

external circuitry is required to set a configuration bit to 1.

Table 20.ꢀConfiguration pins

Configuration bits

CON[9]

Pin name

GPIO[1]

Configuration function

Reserved

Set to 111.

CON[8]

GPIO[11]

GPIO[8]

CON[7]

CON[6]

RF_CNTL1_P

Reserved

Set to 1.

CON[5]

RF_CNTL3_P

Reference clock frequency select

1 = 26ꢀMHz (default)

0 = 40ꢀMHz

CON[1]

CON[0]

RF_CNTL2_N

RF_CNTL0_N

Host configuration options (see Table 21).

No hardware impact. Software reads and boots

accordingly. See the table below.

Note: The boot code needs to use the strap value to set

the correct boot sequence.

Table 21 shows the host configuration options.

Table 21.ꢀHost configuration options

RF_CNTL2_N/

CON[1]

RF_CNTL0_N/

CON[0]

Wi-Fi

Bluetooth/

Bluetooth LE

Number of SDIO functions

1

0

SDIO

UART

1 (Wi-Fi)

—

Others

Reserved

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6 Power information

The table in Section 5.5.12 "Power supply and ground" shows the required voltage levels

for each rail and PDn input signal.

6.1 Power modes

The IW416 power modes reflect the combination of the respective state of Wi-Fi and

Bluetooth subsystems.

Table 22 shows the device power modes, Wi-Fi and Bluetooth states, and associated Wi-

Fi and Bluetooth CPU status.

Refer to Section 9.6 "Current consumption" for the power consumption values of Wi-Fi

and Bluetooth subsystems.

Table 22.ꢀDevice power modes

Device mode

Wi-Fi state

Bluetooth state

Wi-Fi CPU status

Bluetooth CPU

status

Wi-Fi and Bluetooth active

Standby

Active

WFI

Active

WFI ^[1]

Active

WFI

Standby

Active

Standby

Sleep

Wi-Fi active

Bluetooth active

Sleep

Active

Sleep

WFI

Deep-sleep^[2]

Deep-sleep

--

[1] Wait for Interrupt: the ARM-based CPU is in low-power standby state.

[2] Memory placed in low-power retention mode.

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6.2 Power-up sequence

The IW416 VCORE is supplied through an external PMIC. The PDn pin of the IW416 is

tied to 1.8V. The ramp-up is controlled by the Host using PMIC_EN, the input enable pin

of the power regulator.

The power configuration is detailed in Section 6.2.1 "Configuration—VCORE from PMIC"

and Section 6.2.2 "Power-up sequence timing" shows the power-up timing.

6.2.1 Configuration—VCORE from PMIC

• VCORE from PMIC

• PMIC_EN ramps up from Host 3.3V or Host GPIO pin

• PDn supplied from AVDD18 (follow AVDD18; PDn is connected 1.8V supply)

• External VPA/AVDD18 from PMIC

• External VIO/VIO_RF from Host (1.8V/3.3V)

Table 23.ꢀConfiguration—VCORE from PMIC ^[1]

IW416

PMIC

2.2V

1.8V

VPA

VIN

Host

AVDD18/PDn

VCORE

1.05V

3.3V/

Power-down from Host

GPIO

EN (PMIC_EN)

1.8V/3.3V (from GPIOs)

DVSC[1:0]

1.8V/3.3V

VIO/VIO_RF

Figure 8.ꢀConfiguration—VCORE from PMIC

[1] A minimum time of 100 ms is required after PMIC_EN is deasserted (=0) and before it is asserted (=1).

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6.2.2 Power-up sequence timing

• VPA must be good (90%) before AVDD18 starts ramping up.

• AVDD18 must be good (90%) before VCORE starts ramping up.

Figure 9 shows the power-up sequence.

VIO/VIO_RF

VPA

Power_good (90%)

2.2V

Power_good (90%)

1.8V

AVDD18

PDn

1.05V

VCORE

Internal POR

External Crystal

Oscillator (if used)

XTAL_IN (Crystal,

if used)

Boot ROM execution starts

and firmware download

begins

Strap/Internal

RESETn

Figure 9.ꢀPower-up sequence

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6.3 Power-down sequence

6.3.1 Power-down sequence

During the power-down sequence, VPA ramps down before AVDD18 in order for the

RF PA to turn the logic off (depends on the control logic generated from AVDD18).

Also, when the PMIC VBAT is removed, the PMIC cannot guarantee a ramp-down

requirement.

Figure 10 shows the recommended power-down sequence.

VPA (2.2V)

AVDD18 (1.8V)

VCORE (1.05V)

Figure 10.ꢀPower-down sequence

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6.3.2 Host power-down pin (PMIC_EN) usage

The maximum ramp-down time for VCORE from PMIC_EN assertion is 10 ms. PMIC_EN

must be asserted a minimum of 100 ms to guarantee that VCORE and AVDD18 are

discharged to less than 0.2V for the POR to generate properly after PMIC_EN is

deasserted.

Figure 11 shows the sequence.

min 100 ms

EN (PMIC_EN)

VPA (2.2V)

AVDD18 (1.8V)/PDn

VCORE (1.05V)

max 10 ms

Internal POR

Figure 11.ꢀPMIC_EN pin usage—PMIC/SoC both in power-down mode

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6.4 Leakage optimization

For applications not using Wi-Fi and Bluetooth, the device can be put into a low-leakage

mode of operation. Two methods are available to set the device to low-leakage mode:

• Using PDn pin

The power-down state provides the lowest leakage mode of operation. Assert PDn low

to enter power-down. If firmware is not downloaded, the device must be kept in power-

down mode to reduce the leakage.

• Powering off all the rails

Alternatively, all the power rails can be powered off. In this case, the state of the PDn

pin is irrelevant.

6.5 Deep sleep

When a programmable power regulator is used to supply VCORE, the IW416 may use

the power management interface to reduce VCORE to approximately 0.8V to reduce

power consumption in deep sleep mode.

6.6 Reset

The IW416 is reset to its default operating state under any of the following conditions:

• Internal Power-On Reset (POR): POR is triggered when the device receives power and

VCORE and AVDD18 supplies are good. See Section 6.2 "Power-up sequence".

• Software/firmware reset: software/firmware issues a reset.

• External PDn pin assertion: the device is reset when the PDn input pin is <0.2V and

transitions from low to high.

See Section 9.11 "Power down (PDn) pin specifications" for the electrical specifications.

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7 Absolute maximum ratings

CAUTION: The absolute maximum ratings table defines the limitations for electrical and

thermal stresses. These limits prevent permanent damage to the device. Exposure to

conditions at or beyond these ratings is not guaranteed and can damage the device.

Table 24.ꢀAbsolute maximum ratings

Symbol Parameter

Min

Max

1.15

2.2

Unit

V

VCORE Core power supply

-

VIO

1.8ꢀV/3.3ꢀV digital I/O power supply

-

V

-

4.0

V

VIO_SD 1.8ꢀV/3.3ꢀV digital I/O power supply

VIO_RF 1.8ꢀV/3.3ꢀV digital I/O power supply

AVDD18 1.8ꢀV analog power supply

-

2.2

V

-

4.0

V

-

2.2

V

-

4.0

V

-

1.98

2.3

V

VPA

2.2ꢀV analog power supply

-

V

AVDD33 3.3ꢀV analog power supply

LDO_VIN LDO input voltage supply

T_STORAGEStorage temperature

3.96

2.0

V

-

V

-55

+125

°C

Table 25.ꢀLimiting values (HVQFN68 package)

Symbol

Parameter

Condition

Min

-2

Max

+2

Unit

kV

V

V_ESD

Electrostatic discharge

human body model (HBM)^[1]

charged device model (CDM)^[2]

-500

+500

[1] According to ANSI/ESDA/JEDEC JS-001.

[2] According to ANSI/ESDA/JEDEC JS-002

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8 Recommended operating conditions

Note: Operation beyond the recommended operating conditions is neither

recommended nor guaranteed.

Table 26.ꢀRecommended operating conditions

Symbol

Parameter

Condition

Min

Typ

Max

Unit

VCORE

1.05V core power supply

Active mode

1.018

1.05

1.10

V

VIO

1.8V/3.3V digital I/O power --

1.62

2.97

1.62

2.97

1.62

2.97

1.71

2.09

3.14

1.71

0

1.8

3.3

1.8

3.3

1.8

3.3

1.8

2.2

3.3

1.8

--

1.98

3.47

1.98

3.47

1.98

3.47

1.89

2.26

3.46

1.89

70

V

°C

supply

--

VIO_SD

VIO_RF

1.8V/3.3V digital I/O SDIO

power supply

--

1.8V/3.3V I/O power supply --

--

AVDD18

VPA

1.8V analog power supply

2.2V analog power supply

3.3V analog power supply

LDO input voltage supply

--

AVDD33

LDO_VIN

T_A

--

Ambient operating

temperature

Commercial

T_A

T_J

Ambient operating

temperature

Industrial

--

-40

--

-

85

°C

Junction temperature

--

125

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9 Electrical specifications

9.1 GPIO/LED interface specifications

The GPIO pins are powered by VIO voltage supply.

9.1.1 VIO DC characteristics

9.1.1.1 1.8V operation

Table 27.ꢀDC electrical characteristics—1.8V operation (VIO)

Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"

Symbol

V_IH

Parameter

Condition

Min

0.7*VIO

-0.4

Typ

--

Max

VIO+0.4

0.3*VIO

--

Unit

V

Input high voltage

Input low voltage

Input hysteresis

Output high voltage

Output low voltage

--

V_IL

--

V

V_HYS

V_OH

100

--

mV

V

VIO-0.4

--

V_OL

--

0.4

V

9.1.1.2 3.3V operation

Table 28.ꢀDC electrical characteristics—3.3V operation (VIO)

Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"

Symbol

V_IH

Parameter

Condition

Min

0.7*VIO

-0.4

Typ

--

Max

VIO+0.4

0.3*VIO

--

Unit

V

Input high voltage

Input low voltage

Input hysteresis

Output high voltage

Output low voltage

--

V_IL

--

V

V_HYS

V_OH

100

--

mV

V

VIO-0.4

--

V_OL

--

0.4

V

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9.2 RF front-end control interface specifications

9.2.1 VIO_RF DC characteristics

9.2.1.1 1.8V operation

Table 29.ꢀDC electrical characteristics—1.8V operation (VIO_RF)

Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"

Symbol

V_IH

Parameter

Condition

Min

0.7*VIO_RF

-0.4

Typ

--

Max

Unit

V

Input high voltage

Input low voltage

Input hysteresis

Output high voltage

Output low voltage

--

VIO_RF+0.4

V_IL

--

0.3*VIO_RF

V

V_HYS

V_OH

100

--

mV

V

VIO_RF-0.4

--

V_OL

--

0.4

V

9.2.1.2 3.3V operation

Table 30.ꢀDC electrical characteristics—3.3V operation (VIO_RF)

Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"

Symbol

V_IH

Parameter

Condition

Min

0.7*VIO_RF

-0.4

Typ

--

Max

Unit

V

Input high voltage

Input low voltage

Input hysteresis

Output high voltage

Output low voltage

--

VIO_RF+0.4

V_IL

--

0.3*VIO_RF

V

V_HYS

V_OH

100

--

mV

V

VIO_RF-0.4

--

V_OL

--

0.4

V

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9.3 Wi-Fi radio specifications

The Wi-Fi radio interface pins are powered by AVDD18.

9.3.1 Wi-Fi radio performance measurement

The Wi-Fi transmit/receive performance is measured either at the antenna port or at the

chip port.

IW416

Wi-Fi 5G Tx/Rx

Filter

Diplexer

Wi-Fi 2.4G Tx/Rx

Antenna

port

Chip port

Figure 12.ꢀRF performance measurement points

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9.3.2 2.4ꢁGHz Wi-Fi receive performance

Note: Unless otherwise stated, all specifications are at 25°C, nominal voltage, and at the

chip port.

Table 31.ꢀ2.4 GHz Wi-Fi receive performance

Parameter

Conditions

Min

2400

--

Typ

--

Max

2490

2

Unit

MHz

dBm

RF frequency range

Maximum Rx input level

2.4 GHz—IEEE 802.11n/g/b

Maximum Rx input level without

device damage

--

1 Mbit/s

2 Mbit/s

5.5 Mbit/s

11 Mbit/s

6 Mbit/s

9 Mbit/s

12 Mbit/s

18 Mbit/s

24 Mbit/s

36 Mbit/s

48 Mbit/s

54 Mbit/s

MCS0

--

-99

-95

-94

-91

-92

-91

-89

-86

-83

-78

-77

-92

-90

-87

-84

-81

-76

-75

-73^[2]

-89

-87

-84

-82

-78

-74

-72

-71

--

dBm

Receiver sensitivity 802.11b

Receiver sensitivity 802.11g

MCS1

MCS2

MCS3

Receiver sensitivity 802.11n

HT20^[1]

MCS4

MCS5

MCS6

MCS7

MCS0

MCS1

MCS2

MCS3

Receiver sensitivity 802.11n

HT40^[1]

MCS4

MCS5

MCS6

MCS7

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Table 31.ꢀ2.4 GHz Wi-Fi receive performance...continued

Parameter

Conditions

802.11b

802.11g

MCS0-4

MCS5

Min

--

Typ

5

Max

--

Unit

dBm

dB

-4

-2

Receiver maximum input level

802.11

-4

MCS6

-5

MCS7

-8

1Mbit/s

2Mbit/s

5.5Mbit/s

11Mbit/s

6Mbit/s

9Mbit/s

12Mbit/s

18Mbit/s

24Mbit/s

36Mbit/s

48Mbit/s

54Mbit/s

MCS0

41

39

38

37

31

30

28

29

26

23

19

21

31

28

31

30

27

25

24

23

28

27

24

23

19

16

14

12

Receiver adjacent channel

interference rejection (ACI)

802.11b

dB

Receiver adjacent channel

interference rejection (ACI)

802.11g

dB

MCS1

dB

MCS2

dB

Receiver adjacent channel

interference rejection (ACI)

802.11n HT20

MCS3

dB

MCS4

dB

MCS5

dB

MCS6

dB

MCS7

dB

MCS0

dB

MCS1

dB

MCS2

dB

Receiver adjacent channel

interference rejection (ACI)

802.11n HT40

MCS3

dB

MCS4

dB

MCS5

dB

MCS6

dB

MCS7

dB

[1] With BCC waveform

[2] De-sense of ~1ꢀdB at 2417ꢀMHz

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9.3.3 5 GHz receive performance

Note: Unless otherwise stated, all specifications are at 25°C, nominal voltage, averaged

over one channel per sub-band, and at the chip port.

Table 32.ꢀ5ꢁGHz Wi-Fi receive performance

Parameter

Conditions

Min

Typ

--

Max

5850

2

Unit

MHz

dBm

5150

RF frequency range

Maximum receiver input level

5 GHz—IEEE 802.11n/a

Maximum receive input level

without device damage

--

6Mbit/s

9Mbit/s

12Mbit/s

18Mbit/s

14Mbit/s

36Mbit/s

48Mbit/s

54Mbit/s

MCS0

--

-90

-89

-87

-85

-81

-77

-75

-90

-87

-85

-82

-79

-75

-73

-71

-86

-85

-82

-79

-76

-72

-70

-69

0

--

dBm

Receiver sensitivity 802.11a

MCS1

MCS2

MCS3

Receiver sensitivity 802.11n

HT20^[1]

MCS4

MCS5

MCS6

MCS7

MCS0

MCS1

MCS2

MCS3

Receiver sensitivity 802.11n

HT40^[1]

MCS4

MCS5

MCS6

MCS7

802.11a 6-36ꢀMbit/s

802.11a 48-54ꢀMbit/s

MCS0-4

MCS5

-5

-1

Receiver maximum input level

802.11

-5

MCS6

-6

MCS7

-9

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Table 32.ꢀ5ꢁGHz Wi-Fi receive performance...continued

Parameter

Conditions

6Mbit/s

9Mbit/s

12Mbit/s

18Mbit/s

24Mbit/s

36Mbit/s

48Mbit/s

54Mbit/s

MCS0

Min

--

Typ

30

28

26

23

19

16

15

28

25

22

17

14

12

10

29

27

24

19

17

14

12

Max

--

Unit

dB

Receiver adjacent channel

interference rejection (ACI)

802.11a

MCS1

MCS2

Receiver adjacent channel

interference rejection (ACI)

802.11n HT20

MCS3

MCS4

MCS5

MCS6

MCS7

MCS0

MCS1

MCS2

Receiver adjacent channel

interference rejection (ACI)

802.11n HT40

MCS3

MCS4

MCS5

MCS6

MCS7

[1] With BCC waveform

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9.3.4 2.4 GHz transmit performance

Note: Unless otherwise stated, all specifications are at 25°C, nominal voltage, and at the

chip port.

Table 33.ꢀ2.4 GHz Wi-Fi transmit performance

Parameter

Conditions

Min

2490

--

Typ

--

Max

2500

--

Unit

MHz

dBc

RF frequency range

2.4 GHz—IEEE 802.11n/g/b

I/Q suppression at chip output

Transmit I/Q suppression with IQ

calibration

-45

802.11b

--

21

19

18

--

dBm

OFDM BPSK

OFDM QPSK

OFDM 16-QAM

OFDM 64-QAM

OFDM BPSK

OFDM QPSK

OFDM 16-QAM

OFDM 64-QAM

Transmit power (EVM and mask

compliant) 20ꢀMHz

Transmit power (EVM and mask

compliant) 40ꢀMHz

Transmit output power level

control range

--

21^[1]

--

dB

Transmit output power control step --

--

1

--

dB

Transmit output power accuracy

Transmit carrier suppression

--

1.5

46

802.11n MCS7 HT40, at 17ꢀdBm

[1] 0-21ꢀdBm. For 802.11b data rates, TX power range is 8-21ꢀdBm

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9.3.5 5 GHz transmit performance

Note: Unless otherwise stated, all specifications are at 25°C, nominal voltage, and at the

chip port.

Table 34.ꢀ5ꢁGHz Wi-Fi transmit performance

Parameter

Conditions

Min

5150

--

Typ

--

Max

5925

--

Unit

MHz

dBc

RF frequency range

5 GHz—IEEE 802.11n/a

I/Q suppression at chip output

Transmit I/Q suppression with IQ

calibration

-45

OFDM BPSK

OFDM QPSK

OFDM 16-QAM

OFDM 64-QAM

OFDM BPSK

OFDM QPSK

OFDM 16-QAM

OFDM 64-QAM

--

20

19

18

--

dBm

Transmit power (EVM and mask

compliant) 20ꢀMHz

Transmit power (EVM and mask

compliant) 40ꢀMHz

Transmit output power level

control range

--

20^[1]

--

dB

Transmit output power control step --

--

1

--

dB

Transmit output power accuracy

Transmit carrier suppression

--

1.5

51

802.11n MCS7 HT40, at 16ꢀdBm

[1] 0-20ꢀdBm

9.3.6 Local oscillator

Table 35.ꢀLocal oscillator

Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"

Parameter

Condition

Min

Typ

Max

Unit

Phase noise

Measured at 2.438ꢀGHz at

100ꢀkHz offset

--

-103

--

dBc/Hz

Measured at 5.501ꢀGHz at

100ꢀkHz offset

--

-100

0.35

0.65

--

dBc/Hz

degrees

kHz

Integrated RMS phase noise at RF Reference clock frequency =

output (from 10 kHz–10ꢀMHz)

26ꢀMHz (2.4ꢀGHz)

Reference clock frequency =

26ꢀMHz (5ꢀGHz)

--

Frequency resolution

--

0.02

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9.4 Bluetooth radio specifications

The Bluetooth radio interface pin is powered by AVDD18 voltage supply.

9.4.1 Bluetooth/Bluetooth LE receive performance

Note: Unless otherwise stated, all specifications are at 25°C, nominal voltage, and at

BRF_ANT pin.

Table 36.ꢀBluetooth/Bluetooth LE receive performance

Parameter

Conditions

Min

2.4

--

Typ

--

Max

2.5

--

Unit

GHz

dBm

RF frequency range

--

Input IP3

-19

(@ maximum gain of 72 dB)

Out-of-band blocking

30–2000 MHz

2–2.399 GHz

2.484–3 GHz

3–12.75 GHz

Resolution = 1 dB

DH5

--

-12.5

-12.4

-18

--

0

dBm

-2.6

-90

RSSI Range

Sensitivity^[1]

-97

--

2DH5

-96

(RCV/CA/01/C & RCV/CA/02/C &

RCV/CA/07/C)

3DH5

-89.5

-98

LE 1ꢀMbit/s

Bluetooth LE sensitivity ^[1]

(RCV-LE/CA/02/C)

LE 2ꢀMbit/s

-96

LE coded 500ꢀkbit/s (S = 2)

LE coded 125ꢀkbit/s (S = 8)

-100

-106

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Table 36.ꢀBluetooth/Bluetooth LE receive performance...continued

Parameter

Conditions

Min

Typ

Max

Unit

DH1- Co-Channel interference, C/I

co-channel

dB

--

10

--

DH1- Adjacent (1 MHz) interference,

C/I 1ꢀMHz

dB

--

-9

--

DH1- Adjacent (2ꢀMHz) interference,

C/I 2ꢀMHz

-45

-52

-29

DH1- Adjacent (2ꢀMHz) interference,

C/I >= 3ꢀMHz

DH1- Image frequency interference,

C/I image channel

DH1- Adjacent (1ꢀMHz) interference

to in-band mirror frequency, C/I

image ± 1ꢀMHz

--

-44

--

2DHx- Co-channel interference, C/I

co-channel

dB

--

9

--

2DHx- Adjacent (1ꢀMHz)

interference, C/I 1ꢀMHz

-11

-45

-50

-29

2DHx- Adjacent (2ꢀMHz)

interference, C/I 2ꢀMHz

C/I performance (RCV/CA/03/C &

RCV/CA/09/C)^[2]

2DHx- Adjacent (2ꢀMHz)

interference, C/I >= 3ꢀMHz

2DHx- Image frequency interference,

C/I image channel

2DHx- Adjacent (1ꢀMHz) interference

to in-band mirror frequency, C/I

image ± 1ꢀMHz

--

-45

--

3DHx- Co-channel interference, C/I

co-channel

dB

--

15

-7

--

3DHx- Adjacent (1ꢀMHz)

interference, C/I 1ꢀMHz

3DHx- Adjacent (2ꢀMHz)

interference, C/I 2ꢀMHz

-39

-44

-23

3DHx- Adjacent (2ꢀMHz)

interference, C/I >= 3ꢀMHz

3DHx- Image frequency interference,

C/I image channel

3DHx- Adjacent (1ꢀMHz) interference

to in-band mirror frequency,

--

-38

--

C/I image ± 1ꢀMHz

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Table 36.ꢀBluetooth/Bluetooth LE receive performance...continued

Parameter

Conditions

Min

Typ

Max

Unit

LE 1 Mbit/s - Co-channel

interference, C/I co-channel

dB

--

8.5

--

LE 1 Mbit/s- Adjacent (1 MHz)

interference, C/I 1 MHz

dB

--

-5

-42

--

LE 1 Mbit/s- Adjacent (2 MHz)

interference, C/I 2ꢀMHz

LE 1 Mbit/s- Adjacent (2 MHz)

interference, C/I >= 3 MHz

-50

LE 1 Mbit/s- Image frequency

interference, C/I image channel

-30.5

LE 1 Mbit/s- Adjacent (1 MHz)

interference to in-band mirror

frequency,

--

-38.5

--

C/I image ± 1 MHz

LE 2 Mbit/s- Co-channel interference,

C/I co-channel

dB

--

6

--

LE 2 Mbit/s- Adjacent (2 MHz)

interference, C/I 2ꢀMHz

-24.5

-51

C/I performance (RCV/BV/03/C,

RCV/BV/09/C, RCV/BV/28/C and

RDC/BV/29/C)

LE 2 Mbit/s- Adjacent (4ꢀMHz)

interference, C/I 4ꢀMHz

LE 2 Mbit/s- Adjacent (6 MHz)

interference, C/I >= 6ꢀMHz

-52.5

-30

LE 2 Mbit/s- Image frequency

Interference C/I image channel

LE 2 Mbit/s- Adjacent (2 MHz)

interference to in-band mirror

frequency,

--

-37

--

C/I image ± 2ꢀMHz

LE coded 500ꢀkbit/s (S = 2)- Co-

channel interference, C/I co-channel

dB

--

7.5

-8

--

LE coded 500ꢀkbit/s (S = 2)- Adjacent

(1 MHz) interference, C/I 1ꢀMHz

LE coded 500ꢀkbit/s (S = 2)- Adjacent

(2 MHz) interference, C/I 2ꢀMHz

-47.5

-55.5

LE coded 500ꢀkbit/s (S = 2)- Adjacent

(2 MHz) interference, C/I > = 3ꢀMHz

LE coded 500ꢀkbit/s (S = 2)- Image

frequency interference, C/I image

channel

--

-32

--

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Table 36.ꢀBluetooth/Bluetooth LE receive performance...continued

Parameter

Conditions

Min

Typ

Max

Unit

C/I performance (RCV/CA/09/C)

(continued)

LE coded 500ꢀkbit/s (S = 2)- Adjacent

(1 MHz) interference to in-band

mirror frequency, C/I image ± 1 MHz

dB

--

-41

--

LE coded 125ꢀkbit/s (S = 8)- Co-

channel interference, C/I co channel

dB

--

7

--

LE coded 125ꢀkbit/s (S = 8)- Adjacent

(1 MHz) interference, C/I 1ꢀMHz

-9

LE coded 125ꢀkbit/s (S = 8)- Adjacent

(2 MHz) interference, C/I 2ꢀMHz

-51

-61

LE coded 125ꢀkbit/s (S = 8)- Adjacent

(3ꢀMHz) interference, C/I >= 3ꢀMHz

LE coded 125ꢀkbit/s (S = 8)- Image

frequency Interference, C/I image

channel

--

-33

-42

--

LE coded 125ꢀkbit/s (S = 8)- Adjacent

(1 MHz) interference to in-band

mirror frequency,

dB

C/I image ± 1 MHz

[1] De-rated at 2418ꢀMHz, 2444ꢀMHz and 2470ꢀMHz. Compliant with BT SIG requirements.

[2] Primary/reference channels: 2405ꢀMHz, 2441ꢀMHz, and 2477ꢀMHz. Average value across the three channels.

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9.4.2 Bluetooth/Bluetooth LE transmit performance

Note: Unless otherwise stated, all specifications are at 25°C, nominal voltage, and at

BRF_ANT pin.

Table 37.ꢀBluetooth/Bluetooth LE transmit performance

Parameter

Conditions

Min

2.4

--

Typ

--

Max

Unit

GHz

dBm

dB

RF frequency range

Output power

--

2.5

Class 1 without external PA—BDR

+13

+10

30

--

Class 1 without external PA—EDR

--

Gain range

Class 1 without external PA

--

Gain resolution

--

0.5

-20

-33

-45

-26

-29

-40

-65

-23

--

dB

Spurious emission (BDR)

(in-band)

±500 kHz

±2 MHz

--

dBc

dBm

dBc

dBm

--

±3 MHz

--

Spurious emission (EDR)

(in-band)

±1ꢀMHz

--

±2ꢀMHz

--

±3ꢀMHz

--

Spurious emission (out-of-band)

30–88 MHz

88–960 MHz

--

-41.25

-18

--

0.96–20 GHz

--

All frequencies in this range

<ꢀ-41.25ꢀdBm, except at 2x Bluetooth

channel frequency.

Measured at pin without external

filter.

Restricted—2.38–2.39 GHz

Restricted—2.4835–2.6 GHz

GSM850 (869–894 MHz)

--

-55

-41.25

-50

-41.25

Out-of-band/

-140

-135

-140

-130

-140

--

dBm/Hz

Cellular band noise

GSM900 (925–960 MHz)

GSM DCS (1805–1880 MHz)

GSM PCS (1930–1990 MHz)

GPS (1575.42 ±1.023 MHz)

WCDMA Band I (2110–2170 MHz)

WCDMA Band V (869–894 MHz)

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Table 37.ꢀBluetooth/Bluetooth LE transmit performance...continued

Parameter

Conditions

Min

Typ

Max

Unit

Bluetooth classic

BDR

EDR

--

13.5

11

--

dBm

dB

Transmit output power

(TRM/CA/01/C)

Power control

(TRM/CA/03/C)^[1]

3 to 6.4

Low range

High range

DH5 packets

--

2401

2481

--

MHz

kHz

Frequency range

(TRM/CA/04/C)

-20 dB bandwidth

(TRM/CA/05/C)

957

Delta F1 avg

--

166

100

0.9

--

kHz

%

Delta F2 max threshold

Delta F2/Delta F1

Delta F2 avg

Modulation characteristics

(TRM/CA/07/C)

--

149

kHz

Initial carrier frequency tolerance

(ICTF) test (TRM/CA/08/C)

DH1 packets

--

-11

--

Max Drift - DH1

Drift rate - DH1

Max Drift - DH3

Drift rate - DH3

Max drift - DH5

Drift rate - DH5

2DH5 (DPSK/GFSK)

3DH5 (DPSK/GFSK)

2DH5 peak DEVM

2DH5 RMS DEVM

3DH5 Peak DEVM

3DH5 RMS DEVM

2DH5

--

-16

±1.5^[2]

-17

--

kHz

dB

%

Carrier frequency drift

(TRM/CA/09/C)

-2^[3]

-16

±2^[4]

-0.2

0.14

0.05

0.16

0.06

100

EDR relative power

(TRM/CA/10/C)

EDR carrier frequency stability and

modulation accuracy

%

(TRM/CA/11/C)

%

Diff. phase encoding (TRM/CA/12/C)

3DH5

100

%

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Table 37.ꢀBluetooth/Bluetooth LE transmit performance...continued

Parameter

Conditions

Min

Typ

Max

Unit

Bluetooth LE

LE 1ꢀMbit/s

--

12

253

1

--

dBm

kHz

--

LE 2ꢀMbit/s

Bluetooth LE output power

(TRM/-LE/CA/01/C)

LE coded 500ꢀkbit/s (S = 2)

LE coded 125ꢀkbit/s (S = 8)

Delta F1 avg - LE 1ꢀMbit/s

Delta F2/Delta F1- LE 1ꢀMbit/s

Delta F2 avg- LE 1ꢀMbit/s

Delta F1 avg - LE 2ꢀMbit/s

Delta F2/Delta F1- LE 2ꢀMbit/s

Delta F2 avg- LE 2ꢀMbit/s

Max drift - LE 1ꢀMbit/s

Drift rate - LE 1ꢀMbit/s

Max drift - LE 2ꢀMbit/s

Drift rate - LE 2ꢀMbit/s

Bluetooth LE modulation

characteristics

223

505

1

kHz

--

(TRM-LE/CA/05/C)

460

-9

kHz

1

-12

1

Max drift - LE coded 500ꢀkbit/s

(S = 2)

--

-6

-5

-6

-5

--

Bluetooth LE carrier frequency drift

(TRM-LE/CA/06/C)

Drift rate - LE coded 500ꢀkbit/s

(S = 2)

kHz

Max Drift - LE coded 125ꢀkbit/s

(S = 8)

Drift rate - LE coded 125ꢀkbit/s

(S = 8)

LE 1ꢀMbit/s

--

-15

--

kHz

LE 2ꢀMbit/s

Frequency accuracy

(TRM-LE/CA/BV-06-C)

LE coded 500ꢀkbit/s (S = 2)

LE coded 125ꢀkbit/s (S = 8)

[1] Specifies the minimum and maximum transmit power step size. As per Bluetooth SIG specification, min step size = 2ꢀdB and max step size = 8ꢀdB

[2] As per Bluetooth SIG specification, the lower limit is -20ꢀkHz and the upper limit is +20ꢀkHz.

[3] Calculated over 50ꢀus - Bluetooth SIG specification.

[4] As per Bluetooth SIG specification, the lower limit is -40ꢀkHz and the upper limit is +40ꢀkHz.

9.5 PTA interface specifications

The IW416 PTA interface pins are powered by VIO voltage supply.

See Section 9.1.1 "VIO DC characteristics" for specifications.

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9.6 Current consumption

Note: Unless otherwise stated, all specifications are at 25°C, nominal voltage, and

typical value.

Table 38.ꢀCurrent consumption values

VIO

(3.3ꢁV)

Mode

Conditions

VPA AVDD18 VCORE

Unit

Sleep mode

Power down

—

0.003

0.005

0.04

0.4

0

mA

Wi-Fi and Bluetooth in deep-sleep

mode

0.025

0.44

0.03

Bluetooth LE current consumption^[1]

Bluetooth LE advertise

Interval = 1.28ꢀs

0.005

0.06

0.14

0.145

27

0.28

0.4

0.49

19

0.03

0.24

mA

Bluetooth LE scan

Interval = 1.28ꢀs, window = 11.25ꢀms

Master mode, interval=1.28ꢀs

@ 0ꢀdBm, 1ꢀMbit/s

Bluetooth LE link

Bluetooth LE peak transmit

Bluetooth LE peak receive

Bluetooth current consumption^[1]

Bluetooth page scan

@ 4ꢀdBm, 1ꢀMbit/s

31

19

@ 7ꢀdBm, 1ꢀMbit/s

50

19

@ 10ꢀdBm, 1ꢀMbit/s

1Mbit/s

66

19

16

20

--

0.005

0.19

0.3

0.46

0.6

0.03

mA

Bluetooth page and inquiry scan

Master sniff mode

interval=1.28s

Bluetooth ACL link

0.005

0.12

0.24

0.4

0.03

mA

Master sniff mode

interval = 500ꢀms

0.64

Bluetooth ACL

Data pump, DH1

Data pump, 2-DH3

Data pump, 3-DH5

@ 0ꢀdBm

0.005

11.8

19.2

21.6

26

13.1

15.4

16.1

19

0.24

mA

Bluetooth ACL

Bluetooth SCO HV3 peak transmit

Bluetooth SCO HV3 peak receive

Bluetooth peak transmit

Bluetooth peak receive

@ 4ꢀdBm

31

19

@ 10ꢀdBm

67

19

@ 13ꢀdBm

88

19

--

15.5

26

20

@ 0ꢀdBm, DH5

@ 4ꢀdBm, DH5

@ 10ꢀdBm, DH5

@ 13ꢀdBm, DH5

DH5

19

31

19

67

19

88

19

15.5

20

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Table 38.ꢀCurrent consumption values...continued

VIO

(3.3ꢁV)

Mode

Conditions

VPA AVDD18 VCORE

Unit

IEEE power save^[2]

IEEE-PS_2GHz-Legacy (DTIM-1)

IEEE-PS_2GHz-Legacy (DTIM-3)

IEEE-PS_2GHz-Legacy (DTIM-5)

IEEE-PS_2GHz-Legacy (DTIM-10)

IEEE-PS_5GHz-Legacy (DTIM-1)

IEEE-PS_5GHz-Legacy (DTIM-3)

IEEE-PS_5GHz-Legacy (DTIM-5)

IEEE-PS_5GHz-Legacy (DTIM-10)

Wi-Fi receive current consumption^[2]

0.005

0.94

0.33

0.21

0.17

0.75

0.26

0.19

0.12

1.18

0.7

0.03

mA

0.59

0.55

0.91

0.62

0.55

0.52

Beacon interval : 100 msec

5G basic rate for beacon Tx: 6 Mbit/s

2G basic rate for beacon Tx: 1 Mbit/s

802.11b, 11ꢀMbit/s

0.005

33

37

35

36

50

60

27

38

47

60

39

48

60

0.24

mA

802.11g, 54ꢀMbit/s

2.4 GHz Wi-Fi receive

802.11n, HT20 MCS7

802.11n, HT40 MCS7

802.11a, 54 Mbit/s

802.11n, HT20 MCS7

802.11n, HT40 MCS7

5 GHz Wi-Fi receive mode

Wi-Fi transmit current consumption^[2]

802.11b, 1ꢀMbit/s @ 20 dBm

313

323

311

325

274

278

272

280

227

95

88

90

0.24

mA

802.11b, 11ꢀMbit/s @ 20ꢀdBm

802.11g, 54ꢀMbit/s @ 20 dBm

802.11n, HT20 MCS0 @ 20ꢀdBm

802.11n, HT20 MCS7 @ 20ꢀdBm

802.11n, HT40 MCS0 @ 20ꢀdBm

802.11n, HT40 MCS7 @ 20ꢀdBm

802.11a, 6ꢀMbit/s @ 19ꢀdBm

96

95

2.4 GHz Wi-Fi transmit mode

(Tx referred to pin)

96

98

96

98

97

105

99

97

158

157

158

155

157

802.11a, 54ꢀMbit/s @ 19ꢀdBm

802.11n, HT20 MCS0 @ 19ꢀdBm

802.11n, HT20 MCS7 @ 19ꢀdBm

802.11n, HT40 MCS0 @ 17ꢀdBm

802.11n, HT40 MCS7 @ 17ꢀdBm

103

100

102

105

115

5 GHz Wi-Fi transmit mode

(Tx power was referred to pin)

Peak current

Peak current during device

initialization

--

862

224

141

0.24

mA

[1] Wi-Fi in deep-sleep mode

[2] Bluetooth in deep-sleep mode

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9.7 SDIO host interface specifications

The SDIO host interface pins are powered by VIO_SD voltage supply.

See Section 9.7.1 "VIO_SD DC characteristics" for specifications.

The SDIO electrical specifications are identical for 4-bit SDIO and 1-bit SDIO transfer

modes.

9.7.1 VIO_SD DC characteristics

Table 39.ꢀVIO_SD requirements

SDIO version

Specifications

Default speed

High speed

SDR12

Maximum frequency

25ꢀMHz

VIO_SD value

3.3ꢀV

SDIO 2.0

50ꢀMHz

3.3ꢀV

SDIO 3.0

25ꢀMHz

1.8ꢀV

SDR25

50ꢀMHz

1.8ꢀV

SDR50

100ꢀMHz

1.8ꢀV

SDR50

50ꢀMHz

1.8ꢀV

9.7.1.1 1.8V operation

Table 40.ꢀDC electrical characteristics—1.8V operation (VIO_SD)

Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"

Symbol

V_IH

Parameter

Condition

Min

0.7*VIO_SD

-0.4

Typ

--

Max

Unit

V

Input high voltage

Input low voltage

Input hysteresis

Output high voltage

Output low voltage

--

VIO_SD+0.4

V_IL

--

0.3*VIO_SD

V

V_HYS

V_OH

100

--

mV

V

VIO_SD-0.4

--

V_OL

--

0.4

V

9.7.1.2 3.3V operation

Table 41.ꢀDC electrical characteristics—3.3V operation (VIO_SD)

Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"

Symbol

V_IH

Parameter

Condition

Min

0.7*VIO_SD

-0.4

Typ

--

Max

Unit

V

Input high voltage

Input low voltage

Input hysteresis

Output high voltage

Output low voltage

--

VIO_SD+0.4

V_IL

--

0.3*VIO_SD

V

V_HYS

V_OH

100

--

mV

V

VIO_SD-0.4

--

V_OL

--

0.4

V

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9.7.2 Default speed, high-speed modes

f

PP

T

WH

WL

Clock

Input

T

IH

ISU

T

ODLY

Output

aaa-036116

Figure 13.ꢀSDIO protocol timing diagram—Default speed mode

f

PP

T

WH

WL

Clock

Input

T

IH

ISU

T

OH

ODLY

Output

aaa-036119

Figure 14.ꢀSDIO protocol timing diagram—High-speed mode

Table 42.ꢀSDIO timing data—Default speed, high-speed modes

Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"

Symbol

Parameter

Condition

Normal

Min

0

Typ

--

Max

25

50

--

Unit

MHz

ns

f_PP

Clock frequency

High-speed

Normal

0

--

T_WL

T_WH

T_ISU

T_IH

Clock low time

Clock high time

Input setup time

Input hold time

10

7

--

High-speed

Normal

--

ns

10

7

--

ns

High-speed

Normal

--

ns

5

--

ns

High-speed

Normal

6

--

ns

5

--

ns

High-speed

Normal

2

--

ns

T_ODLY

Output delay time

--

14

ns

CL ≤ 40 pF (1 card)

High-speed

--

ns

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Table 42.ꢀSDIO timing data—Default speed, high-speed modes...continued

Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"

Symbol

Parameter

Condition

Min

Typ

Max

Unit

T_OH

Output hold time

High-speed

2.5

--

ns

9.7.3 SDR12, SDR25, SDR50 modes (up to 100 MHz) (1.8V)

T

CLK

f

PP

Clock

Input

T

CR

T

CF

T

IH

IS

T

ODLY

T

OH

Output

aaa-036120

Figure 15.ꢀSDIO protocol timing diagram—SDR12, SDR25, SDR50 modes (up to 100MHz) (1.8V)

Table 43.ꢀSDIO timing data——SDR12, SDR25, SDR50 modes (up to 100MHz) (1.8V)

Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"

Symbol

f_PP

Parameter

Condition

Min

25

3

Typ

--

Max

Unit

MHz

ns

Clock frequency

Input setup time

Input hold time

Clock time

SDR12/25/50

100

T_IS

--

T_IH

0.8

10

--

ns

T_CLK

T_CR, T_CF

--

40

ns

Rise time, fall time

--

0.2*T_CLK

ns

T_CR, T_CF< 2 ns (max) at

100 MHz

C_CARD= 10 pF

T_ODLY

Output delay time

C_L≤ 30 pF

SDR12/25/50

--

7.5

--

ns

T_OH

Output hold time

C_L= 15 pF

1.5

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9.7.4 DDR50 mode (50MHz) (1.8V)

T

CLK

Clock

T

CF

T

IS

T

IH

CR

CMD Input

T

OHLD

ODLY

CMD Output

aaa-036117

Figure 16.ꢀSDIO CMD timing diagram—DDR50 mode (50MHz)

In DDR50 mode, DAT[3:0] lines are sampled on both edges of the clock (not applicable

for CMD line).

T

CLK

Clock

T

IH2x

T

IS2x

DAT[3:0]

Input

T

ODLY2x(max)

T

ODLY2x(max)

DAT[3:0]

Output

T

ODLY2x(min)

aaa-036118

Figure 17.ꢀSDIO DAT[3:0] timing diagram—DDR50mode

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Table 44.ꢀSDIO timing data—DDR50 mode (50MHz)

Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"

Symbol

Clock

T_CLK

Parameter

Condition

Min

Typ

Max

Unit

Clock time

DDR50

20

--

ns

50 MHz (max) between rising

edges

T_CR, T_CF

Rise time, fall time

DDR50

--

0.2*T_CLK

ns

%

T_CR, T_CF< 4.00 ns (max) at 50

MHz

C_CARD= 10 pF

Clock Duty

--

45

55

CMD Input (referenced to clock rising edge)

T_IS

Input setup time

DDR50

6

--

ns

C_CARD≤ 10 pF (1 card)

T_IH

Input hold time

0.8

C_CARD≤ 10 pF (1 card)

CMD Output (referenced to clock rising edge)

T_ODLY

Output delay time during data

transfer mode

DDR50

--

13.7

--

ns

C_L≤ 30 pF (1 card)

T_OHLD

Output hold time

1.5

C_L≥ 15 pF (1 card)

DAT[3:0] Input (referenced to clock rising and falling edges)

T_IS2x

Input setup time

DDR50

3

--

ns

C_CARD≤ 10 pF (1 card)

T_IH2x

Input hold time

DDR50

0.8

C_CARD≤ 10 pF (1 card)

DAT[3:0] Output (referenced to clock rising and falling edges)

T_{ODLY2x (max)}Output delay time during data

transfer mode

DDR50

--

7.0

--

ns

C_L≤ 25 pF (1 card)

T_{ODLY2x (min)}

Output hold time

DDR50

1.5

C_L≥ 15 pF (1 card)

9.7.5 SDIO internal pull-up/pull-down specifications

Table 45.ꢀSDIO internal pull-up/pull-down specifications

Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"

Parameter

Condition

Min

Typ

Max

120

Unit

Internal nominal pull-up/pull-down --

resistance

60

90

kΩ

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9.8 High-speed UART specifications

The UART Tx and Rx pins are powered by VIO voltage supply.

See Section 9.1.1 "VIO DC characteristics" for DC specifications.

T

BAUD

UART Tx

UART Rx

aaa-036128

Figure 18.ꢀUART timing diagram

Table 46.ꢀUART timing data ^[1]

Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"

Symbol

Parameter

Condition

Min

Typ

Max

Units

T_BAUD

Baud rate

26 MHz or 40 MHz input clock

250

--

ns

[1] The acceptable deviation from the UART Rx target baud rate is ±3%.

9.9 Audio interface specifications

The device has two audio interfaces: I2S interface and PCM interface.

9.9.1 I2S interface specifications

The I2S pins are powered by VIO voltage supply. See Section 9.1.1 "VIO DC

characteristics" for the specifications.

9.9.2 PCM interface specifications

The PCM pins are powered by VIO voltage supply. See Section 9.1.1 "VIO DC

characteristics" for specifications.

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Master Mode

T_BCLK

PCM_CLK

T_DO

PCM_DOUT

PCM_DIN

T_DISU

T_DIHO

Figure 19.ꢀPCM timing specification diagram for data signals—Master mode

T_BCLK

PCM_CLK

T_BF

PCM_SYNC

Figure 20.ꢀPCM timing specification diagram for PCM_SYNC signal—Master mode

Table 47.ꢀPCM Timing Specification Data—Master Mode

Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"

Symbol

Parameter

Condition

Min

--

Typ

2/2.048

0.5

Max

--

Unit

MHz

--

F_BCLK

Bit clock frequency

--

Duty Cycle_BCLKBit clock duty cycle

0.4

--

0.6

--

T_{BCLK rise/fall}

T_DO

PCM_CLK rise/fall time

3

ns

Delay from PCM_CLK rising edge to

PCM_DOUT rising edge

--

15

ns

T_DISU

T_DIHO

T_BF

Setup time for PCM_DIN before PCM_ --

CLK falling edge

20

15

--

ns

Hold time for PCM_DIN after PCM_CLK --

falling edge

Delay from PCM_CLK rising edge to

PCM_SYNC rising edge

--

15

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Slave Mode

T_BCLK

PCM_CLK

T_DO

PCM_DOUT

PCM_DIN

T_DISU

T_DIHO

Figure 21.ꢀPCM timing specification diagram for data signals—Slave mode

T_BCLK

PCM_CLK

T_BFSU

T_BFHO

T_BF

PCM_SYNC

Figure 22.ꢀPCM timing specification diagram for PCM_SYNC signal—Slave mode

Table 48.ꢀPCM timing specification data—Slave mode

Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"

Symbol

Parameter

Condition

Min

--

Typ

2/2.048

0.5

Max

--

Unit

MHz

--

F_BCLK

Bit clock frequency

--

Duty Cycle_BCLKBit clock duty cycle

0.4

--

0.6

--

T_{BCLK rise/fall}

T_DO

PCM_CLK rise/fall time

3

ns

Delay from PCM_CLK rising edge to

PCM_DOUT rising edge

--

30

ns

T_DISU

T_DIHO

T_BFSU

T_BFHO

Setup time for PCM_DIN before PCM_ --

CLK falling edge

15

10

15

10

--

ns

Hold time for PCM_DIN after PCM_CLK --

falling edge

Setup time for PCM_SYNC before

PCM_CLK falling edge

--

Hold time for PCM_SYNC after PCM_

CLK falling edge

--

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9.10 Reference clock specifications

9.10.1 External crystal oscillator specifications

Note: The reference clock from the external crystal oscillator requires a CMOS input

signal.

Table 49.ꢀClock DC specifications ^[1]

Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"

Parameter

Condition

Min

--

Typ

--

Max

1.8

--

Unit

V

Single-ended high-level voltage

Single-ended low-level voltage

Clock amplitude (pk-pk)

Mid-point slope

--

0

--

V

0.5

125

--

1

V

--

MV/s

[1] AC-coupling capacitor is integrated into the SoC.

Table 50.ꢀ26 MHz clock timing

Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"

Parameter

Condition

Min

Typ

Max

Unit

XO26 period

--

38.46 -

20 ppm

38.46

38.46 +

20 ppm

ns

XO26 rise time

XO26 fall time

XO26 duty cycle

--

5.00

ns

%

48.05

50

51.95

Table 51.ꢀ40 MHz clock timing

Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"

Parameter

Condition

Min

Typ

Max

Unit

XO40 period

--

25.00 -

20 ppm

25.00

25.00 +

20 ppm

ns

XO40 rise time

XO40 fall time

XO40 duty cycle

--

2.00

53

ns

%

47

50

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Table 52.ꢀPhase noise—2.4 GHz operation

Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"

Parameter

Condition

Min

--

Typ

--

Max

-126

-137

-145

-126

-137

-145

Unit

Fref = 26 MHz

Offset = 1 kHz

Offset = 10 kHz

Offset = 100 kHz

Offset > 1 MHz

Offset = 1 kHz

Offset = 10 kHz

Offset = 100 kHz

Offset > 1 MHz

dBc/Hz

--

Fref = 40 MHz

--

Table 53.ꢀPhase noise—5 GHz operation

Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"

Parameter

Test Conditions

Offset = 1 kHz

Offset = 10 kHz

Offset = 100 kHz

Offset > 1 MHz

Offset = 1 kHz

Offset = 10 kHz

Offset = 100 kHz

Offset > 1 MHz

Min

--

Typ

--

Max

-130

-150

-156

-130

-150

-156

Unit

Fref = 26 MHz

dBc/Hz

--

Fref = 40 MHz

--

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9.10.2 External crystal specifications

Table 54.ꢀExternal crystal specifications

Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"

Parameter

Condition

Min

--

Typ

Max

--

Unit

MHz

--

Fundamental frequencies

Resonance mode

--

26 (40)

--

A1,

--

Fundamental

Equivalent differential load

capacitance

--

5

--

pF

Shunt capacitance

Frequency tolerance

Frequency stability

Aging

--

2

--

pF

Over process at 25ºC

±10

±2

ppm

Over operating temperature

--

ppm/5

years

Series resistance (ESR)

26 MHz

40 MHz

at DC 100V

--

60

--

Ω

--

Insulation resistance

Drive level

500

150

MΩ

µW

--

9.10.3 External sleep clock specifications

Table 55.ꢀExternal sleep clock specifications ^[1]

Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"

Parameter

Min

Typ

Max

Unit

Clock frequency range/accuracy

• CMOS input clock signal type

• ±250 ppm (initial, aging, temperature)

--

32.768

--

kHz

Phase noise requirement (@ 100 kHz)

Cycle jitter

--

-125

1.5

--

dBc/Hz

ns (RMS)

ns

--

Slew rate limit (10-90%)

Duty cycle tolerance

--

100

80

20

--

%

[1] Voltage input level = 1.8V. See Section 9.1.1 "VIO DC characteristics".

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9.11 Power down (PDn) pin specifications

9.11.1 PDn asserted low—All power supplies good

Figure 23 and Table 56 show the specifications for the PDn signal when it is asserted

(low) while all power supplies to the device are good.

Power

PDn

T

RPW

T

PU_RESET

aaa-036126

Figure 23.ꢀPDn pin (Power-down) timing—Power remains high at PDn assertion

Table 56.ꢀPDn pin (Power Down) specifications—Power remains high at PDn assertion

Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"

Symbol

Parameter

Condition

Min

Typ

Max

Unit

T_{PU_RESET}

Valid power to PDn de-

asserted

--

0

--

ms

T_RPW

V_IH

PDn pulse width

Input high voltage

Input low voltage

--

1 ^[1]

1.4

--

µs

V

4.5

0.5

V_IL

-0.4

V

[1] Minimum value guaranteed for a valid reset. Smaller values may put the device in an undefined state.

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9.11.2 PDn asserted low—One or more power supplies ramp down

Figure 24 and Table 57 show the specifications for the PDn signal when it is asserted

(low) while 1 or more of the power supplies (including VCORE) ramps down. When the

integrated LDO is used, VCORE will ramp down when PDn is asserted.

Power

0.2 V

T

RD

PDn

T

PU_RESET

RPW

T

= time from PDn assertion until power supply drops to 0.2 V

aaa-036125

RD

Figure 24.ꢀPDn pin (Power Down) timing—Power ramps down at PDn assertion

Table 57.ꢀPDn pin (Power Down) specifications—Power ramps down at PDn assertion

Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"

Symbol

Parameter

Condition

Min

Typ

Max

Unit

T_{PU_RESET}

Valid power to PDn de-

asserted

--

0

--

ms

[1]

T_RPW

V_IH

PDn pulse width

Input high voltage

Input low voltage

--

T_RD

--

µs

V

1.4

4.5

0.2

V_IL

-0.4

V

[1] Minimum value guaranteed for a valid reset. Smaller values may put the device in an undefined state.

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9.12 Configuration pin specifications

For a list of configuration pins, see Section 5.6 "Configuration pins".

Table 58.ꢀConfiguration pin specifications ^[1]

Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"

Parameter

Condition

Min

--

Typ

800

100

Max

--

Unit

kΩ

Internal weak pull-up resistance

Around 1 ms following any reset

Internal nominal pull-up resistance Around 1 ms following any reset

--

kΩ

[1] After approximately 1 ms, the configuration pins become functional pins.

9.13 JTAG interface specifications

JTAG interface pins are powered by VIO voltage supply.

See Section 9.1.1 "VIO DC characteristics" for specifications.

T

P_TCK

T

H_TCK

L_TCK

JTAG_TCK

T

HD_TDI

SU_TDI

JTAG_TDI

JTAG_TMS

T

DLY_TDO

JTAG_TDO

aaa-036123

Figure 25.ꢀJTAG timing diagram

Table 59.ꢀJTAG timing data ^[1]

Unless otherwise specified, the values apply per Section 8 "Recommended operating conditions"

Symbol

T_{P_TCK}

T_{H_TCK}

T_{L_TCK}

Parameter

TCK period

TCK high

TCK low

Condition

Min

40

12

10

0

Typ

--

Max

--

Unit

--

ns

--

T_{SU_TDI}

T_{HD_TDI}

T_{DLY_TDO}

TDI, TMS to TCK setup time --

TDI, TMS to TCK hold time --

--

TCK to TDO delay

--

15

[1] Does not apply to JTAG enabled by the JTAG_TMS pin.

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10 Package information

10.1 Package thermal conditions

10.1.1 HVQFN68 thermal conditions

Table 60.ꢀPackage thermal conditions—HVQFN68

Symbol

Parameter

Condition

Typ

Units

θ_JA

Thermal resistance

JEDEC 3 in. x 4.5 in.

4-layer PCB

28.4

°C/W

Junction to ambient of package.

θ_JA= (T_J- T_A)/ P

no air flow

P = total power dissipation

JEDEC 3 in. x 4.5 in.

4-layer PCB

27.6

26.1

25.3

0.44

°C/W

1 meter/sec air flow

JEDEC 3 in. x 4.5 in.

4-layer PCB

2 meter/sec air flow

JEDEC 3 in. x 4.5 in.

4-layer PCB

3 meter/sec air flow

ψ_JT

ψ_JB

θ_JC

Thermal characteristic parameter

Junction to top-center of package.

ψ_JT= (T_J- T_TOP)/P

JEDEC 3 in. x 4.5 in.

4-layer PCB

no air flow

T_TOP= temperature on top-center of package

Thermal characteristic parameter

Junction to bottom surface, center of PCB.

ψ_JB= (T_J- T_B)/P

JEDEC 3 in. x 4.5 in.

4-layer PCB

15.4

13.0

°C/W

no air flow

T_B= surface temperature of PCB

Thermal resistance

JEDEC 3 in. x 4.5 in.

4-layer PCB

Junction to case of the package.

θ_JC= (T_J- T_C)/ P_TOP

no air flow

T_C= temperature on top-center of package

P_TOP= power dissipation from top of package

θ_JB

Thermal resistance

JEDEC 3 in. x 4.5 in.

4-layer PCB

15.6

°C/W

Junction to board of package.

θ_JB= (T_J- T_B)/ P_BOTTOM

no air flow

P_BOTTOM= power dissipation from bottom of package to PCB

surface

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10.1.2 WLCSP76 thermal conditions

Table 61.ꢀPackage thermal conditions—WLCSP76

Symbol

Parameter

Board type^[1]

Typ

Units

θ_JA

Junction to ambient thermal resistance^[2]

θ_JA= (T_J- T_A)/ P

JESD51-9, 2s2p

37.6

°C/W

P = total power dissipation

ψ_JT

Junction to top of package thermal characterization parameter^[2]

ψ_JT= (T_J- T_TOP)/P

JESD51-9, 2s2p

1.3

°C/W

T_TOP= temperature on top-center of package

[1] The thermal test board meets JEDEC specification for this package (JESD51-9).

[2] Determined in accordance to JEDEC JESD51-2A natural convection environment. Thermal resistance data in this report is solely for a thermal

performance comparison of one package to another in a standardized specified environment. It is not meant to predict the performance of a package in an

application-specific environment.

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10.2 Package mechanical drawing

Table 62.ꢀPackage information

Package name

Link to package information on NXP website

HVQFN68

WLCSP76

SOT2107-1

SOT2073-1

10.2.1 HVQFN68 mechanical drawing

Figure 26.ꢀHVQFN68 package mechanical drawing

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Figure 27.ꢀHVFQN68 package mechanical drawing - Detail G

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10.2.2 WLCSP76 mechanical drawing

Backside coating included

Figure 28.ꢀWLCSP76 package mechanical drawing

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Backside coating included

Figure 29.ꢀWLCSP76 package mechanical drawing - Detail E

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10.3 Package marking

10.3.1 HVFQN68 marking

Figure 30 and Figure 31 show the location of pin 1 and describe each line of the package

marking on HVQFN68.

Pin 1 location

IW416HNA1C

XXXXX.%%

IW416 = Part number

HN = Package code

A1 = Die version

C = Commercial operating temperature range

JEADYYWWX

JE = Foundry

A = Assembly center

D = RoHS

YYWW = Date code

XXXXX = Diffusion lot number - dot - %% = ASID number

(YY = year - WW = week)

X = used for engineering samples

Note: The above drawing is not drawn to scale. The location of markings is approximate.

Figure 30.ꢀPackage marking and pin 1 location—HVQFN68, commercial operating temperature

Pin 1 location

IW416HNA1I

XXXXX.%%

JEADYYWWX

IW416 = Part number

HN = Package code

A1 = Die version

I = industrial operating temperature range

JE = Foundry

A = Assembly center

D = RoHS

YYWW = Date code

XXXXX = Diffusion lot number - dot - %% = ASID number

(YY = year - WW = week)

X = used for engineering samples

Note: The above drawing is not drawn to scale. The location of markings is approximate.

Figure 31.ꢀPackage marking and pin 1 location—HVQFN68, industrial operating temperature

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10.3.2 WLCSP76 marking

Figure 32 and Figure 33 show the location of pin 1 and describes each line of the

package marking on the WLCSP76.

Pin 1 location

IW416 = Part number - HN = Package code - A1 = Die version

C = Commercial operating temperature range

IW416UKA1C

XXXXX = Diffusion lot # - %% = wafer number

XXXXX.%%

JEkDYYWW

JE = Foundry

XY die coordinates

XXX-YYY

NXP X

k = Bumping center

D = RoHS

NXP (fixed)

X: engineering samples

YYWW = date code – YY = year – WW = week

Note: The above drawing is not drawn to scale. The location of markings is approximate.

Figure 32.ꢀPackage marking and pin 1 location—WLCSP76, commercial operating temperature range

Pin 1 location

IW416 = Part number - HN = Package code - A1 = Die version

I = Industrial operating temperature range

IW416UKA1I

XXXXX = Diffusion lot # - %% = wafer number

XXXXX.%%

JEkDYYWW

JE = Foundry

XY die coordinates

XXX-YYY

NXP X

k = Bumping center

D = RoHS

NXP (fixed)

X: engineering samples

YYWW = date code – YY = year – WW = week

Note: The above drawing is not drawn to scale. The location of markings is approximate.

Figure 33.ꢀPackage marking and pin 1 location—WLCSP76, industrial operating temperature range

IW416

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IW416

Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

11 Acronyms and abbreviations

Table 63.ꢀAcronyms and abbreviations

Definition

Acronym

A2DP

ABR

ACK

ADAS

ADC

AES

AFC

AFH

AGC

AHB

AIFS

AoA

Advanced audio distribution profiles

Automatic baud rate

Acknowledgment

Advanced driver assistance systems

Analog-to-digital converter

Advanced encryption standard

Automatic frequency correction

Adaptive frequency hopping

Automatic gain control

Advanced high-performance bus

Arbitration inter-frame space

Angle of arrival

AoD

Angle of departure

AP

Access point

APB

API

Advanced peripheral bus

Application program interface

Advanced RISC machine

Announcement traffic indication message

Base address mask register

Base address register

ARM

ATIM

BAMR

BAR

BBU

BCB

BDR

BER

BOM

BR

Baseband processor unit

Benzocyclobutene (flip chip bump process)

Basic data rate

Bit error rate

Bill of materials

Baud rate

BRF

BSS

BSSID

BTM

BTU

BWQ

CBC

CBP

Bluetooth RF unit

Basic service set

Basic service set identifier

BSS transition management

Bluetooth baseband unit

Bandwidth queue

Cipher block chaining

Contention-based period

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Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

Table 63.ꢀAcronyms and abbreviations...continued

Acronym Definition

CCA

Clear channel assessment

Complementary code keying

Counter mode CBC-MAC protocol

Close descriptor enable

CCK

CCMP

CDE

CFP

Contention-free period

CFQ

Contention-free queue

CID

Connection identifier

CIS

Card information structure

CPU interface unit

CIU

CMD

CMQ

CRC

CS

Command

Control management queue

Cyclic redundancy check

Card select

CSL

Coordinated sampled listening

Carrier sense multiple access / collision avoidance

Carrier sense multiple access / collision detection

Clocked serial unit

CSMA/CA

CSMA/CD

CSU

CTS

Clear to send

DAC

Digital-to-analog converter

Differential binary phase shift keying

Device controller driver

DBPSK

DCD

DCE

Data communication equipment

Distributed coordination function

Direct current level adjustment

Digital contactless bridge

DMA controller unit

DCF

DCLA

DCLB

DCU

DFS

Dynamic frequency selection

Distributed inter frame space

Direct memory access

DIFS

DMA

dQH

Device queue head

DQPSK

DSM

DSP

Differential quadrature phase shift keying

Distribution system medium

Digital signal processor

DSRC

dTD

Dedicated short range communications

Linked list transfer descriptors

Delivery traffic indication message

DTIM

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Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

Table 63.ꢀAcronyms and abbreviations...continued

Acronym Definition

DUP

DVSC

EAP

Duplicated packet

Digital voltage scaling control

Extensible authentication protocol

Extended block random access memory

Elliptic curve digital signature algorithm

Energy detect

EBRAM

ECDSA

ED

EDCA

EEPROM

EIFS

EMC

ER

Enhanced distributed channel access

Electrically erasable programmable read only memory

Extended inter frame Space

Electromagnetic compatibility

Extended range

ERP-OFDM

ETSI

eWLP

FAE

Extended rate PHY-orthogonal frequency division multiplexing

European telecommunications standards institute

Embedded wafer level package

Field application engineer

Federal communications commission

First in first out

FCC

FIFO

FIPS

FIQ

Federal information processing standards

Fast interrupt request

FPU

Floating point unit

FW

Firmware

GATT

GCMP

GI

Generic attribute profile

Galois/counter mode protocol

Guard interval

GPIO

GPL

General purpose input/output

General Public License

GPT

General purpose timer

GPU

HID

General purpose input/output unit

Human interface device

HIU

Host interface unit

HOGP

HSP

HID over GATT profile

Hands-free profile

HT

High throughput

HVQFN

HW

Thermal enhanced very thin quad flat package

Hardware

I/F

Interface

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IW416

Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

Table 63.ꢀAcronyms and abbreviations...continued

Acronym Definition

I/Q

In-phase/quadrature

IB

In band

IBSS

ICE

Independent basic service set

In-circuit emulator (or emulation)

Interrupt cause register

Interrupt controller unit

Integrity check value

ICR

ICU

ICV

IE

Information element

IEEE

IEMR

IFS

Institute of electrical and electronics engineers

Interrupt event mask register

inter frame space

IMR

IPG

IPsec

IR

Interrupt mask register

Inter-packet gap

Internet protocol security

Infrared

IRQ

ISA

Interrupt request

Instruction set architecture

Integrated services digital network

Industrial, scientific, and medical

Interrupt status mask register

Interrupt status register

Joint electronic device engineering council

Joint test action group

Low complexity communication codec

Low density parity check

Low energy

ISDN

ISM

ISMR

ISR

JEDEC

JTAG

LC3

LDPC

LE

LED

LME

LNA

LPM

LSb

LSB

LSP

LTE

MAC

MC

Light emitting diode

Layer management entity

Low noise amplifier

Low power management

Least significant bit

Least significant byte

Low-speed peripheral

Long term evolution

Media/medium access controller

Memory controller

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Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

Table 63.ꢀAcronyms and abbreviations...continued

Acronym Definition

MCI

Microcontroller subsystem

Modulation and coding scheme

MAC Control unit

MCS

MCU

MDI

Modem data interface

MIB

Management information base

Message integrity code

Media independent interface

Multiple input multiple output

Million instructions per second

MAC sublayer management entity

Modem management interface

MAC management protocol data unit

Memory management unit

MAC protocol data unit

MIC

MII

MIMO

MIPS

MLME

MMI

MMPDU

MMU

MPDU

MPU

Memory protection unit

MSb

Most significant bit

MSB

Most significant byte

MSDU

MU-MIMO

MU-PPDU

MWS

MAC service data unit

Multi user MIMO

Multi user PPDU

Mobile wireless system

Multimedia wireless system

NAV

NBS

NDP

NL

Network allocation vector

Narrow band speech

Null data packet

No load

NPTR

Nsts

NVIC

OCB

OFDM

OID

Next descriptor pointer

Number of space time streams

Nested vector interrupt controller

Outside the context of a BSS

Orthogonal frequency division multiplexing

Object identifier

OOB

OTP

P2P

PA

Out of band

One time programmable

Peer-to-peer

Power amplifier

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Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

Table 63.ꢀAcronyms and abbreviations...continued

Acronym Definition

PAD

PBU

PC

Packet assembler/disassembler

Peripheral bus unit

Point coordinator

PCB

PCF

PCI

Printed circuit board

Point coordination function

Peripheral component interconnect

PCI express

PCIe

PCM

PDn

PDU

PEAP

PHY

PIFS

PLL

Pulse code modulation

Power down

Protocol data unit

Protected EAP

Physical layer

Priority inter frame space

Phase-locked loop

PLME

PMU

POS

POST

PPDU

PPK

PPM

PSK

PTA

Physical layer management entity

Power management unit

Point of sale

Power-on self test

PHY protocol data unit

Per-packet key

Pulse position modulation

Pre shared keys

Packet traffic arbitration

Physically unclonable function

Pairwise key

PUF

PWK

QAM

QFN

QoS

RA

Quadrature amplitude modulation

Quad flat non-leaded package

Quality of service

Receiver address

RBDS

RDS

RF

Radio broadcast data system

Radio data system

Radio frequency

RFID

RIFS

RISC

ROM

Radio frequency identification

Reduced inter frame space

Reduced instruction set computer

Read only memory

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Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

Table 63.ꢀAcronyms and abbreviations...continued

Acronym Definition

RSSI

RTC

RTS

RTU

RU

Receiver signal strength indication

Real time clock

Request to send

General purpose timer unit

Resource unit

SA

Source address

SAP

SCLK

SDA

SDK

SE

Service access point

Serial interface clock

Serial interface data

Software development kit

Secure element

SFD

SHA

SIFS

SISO

SIU

Start of frame delimiter

Secure hash algorithm

Short inter frame space

Single input single output

Serial interface unit (UART)

System/software JTAG controller unit

Switch module

SJU

SM

SMI

Serial management interface

Signal-to-noise ratio

Serial out

SNR

SO

SoC

SPDT

SPI

System-on-chip

Single pole double throw

Serial peripheral interface

Internal SRAM unit

SQU

SRWB

SS

Serial interface read write

Service set

SSID

STA

STBC

SWD

SWP

SysTick

TA

Service set identifier

Station

Space-time block code

Serial wire debug

Single wire protocol

System tick timer

Transmitter address

Time base generator

Target beacon transmission time

TBG

TBTT

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IW416

Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

Table 63.ꢀAcronyms and abbreviations...continued

Acronym Definition

TCM

Tightly coupled memory

TCP/IP

TCQ

Transmission control protocol/internet protocol

Traffic category queue

TEE

Trusted execution environment

Traffic indication map

TIM

TKIP

Temporal key integrity protocol

Transmit power control

TPC

TQFP

TRPC

TSC

Thin quad flat pack

Transmit rate-based power control

TKIP sequence counter

TSF

Timing synchronization function

Target wait time

TWT

UART

USART

UBM

Universal asynchronous receiver/transmitter

Universal synchronous/asynchronous receiver/transmitter

Under bump metal

UDP

User datagram protocol

UNII

Unlicensed national information infrastructure

Voltage controlled oscillator

Very high throughput

VCO

VHT

VIF

Voice interface

WAP

Wireless application protocol

Wireless access in vehicular environments

Wide band speech

WAVE

WBS

WCI-2

WEP

WI

Wireless coexistence interface 2

Wired equivalent privacy

Wired interface

Wi-Fi

WLAN

WLCSP

WMM

WPA

Hardware implementation of IEEE 802.11 for wireless connectivity

Wireless local area network

Wafer level chip scale package

Wi-Fi multimedia

Wi-Fi protected access

WPA2

WPA2-PSK

WPA3

WPA-PSK

XIP

Wi-Fi protected access 2

Wi-Fi protected access 2 - pre shared key

Wi-Fi protected access 3

Wi-Fi protected access - pre shared key

Execute in place

IW416

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IW416

Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

Table 63.ꢀAcronyms and abbreviations...continued

Acronym Definition

XOSC

ZIF

Crystal oscillator

Zero intermediate frequency

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IW416

Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

12 Revision history

Table 64.ꢀRevision history

Document ID

IW416 v.4.0

Modifications

Release date

Data sheet status

Change notice

Supersedes

20210625

Product data sheet

-

IW416 v.3.0

Product overview

• Figure 1 "Application block diagram": Added a reference to IW416 design guide

• Section 1.5 "Operating characteristics": Removed "3.3ꢀV (optional)"

Pin information

• Section 5.5.12 "Power supply and ground": Added a note to AVDD33 description

Electrical specifications

• Section 9.6 "Current consumption": added the values for VIO (3.3ꢀV)

• Table 39 "VIO_SD requirements": added

Package information

• Table 62 "Package information" : added

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IW416

Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

Table 64.ꢀRevision history...continued

Document ID

IW416 v.3.0

Modifications

Release date

Data sheet status

Change notice

Supersedes

20210312

Preliminary data sheet -

IW416 v.2.0

Product overview

• Section 1 "Product overview": updated

• Section 1.2 "Wi-Fi key features": updated

• Section 1.3 "Bluetooth key features": updated

• Section 1.4 "Host interfaces": updated

Ordering information

• Figure 3 "Part numbering scheme": updated

• Table 1 "Part order codes": updated

Wi-Fi subsystem

• Section 3.1 "IEEE 802.11 standards": updated

• Section 3.3 "Wi-Fi baseband": updated

• Section 3.6 "Wi-Fi host interfaces": updated

Bluetooth subsystem

• Section 4.3 "Bluetooth host interfaces": updated

• Section 4.5 "Coexistence": updated

Pin information

• Section 5.4 "Pin types": added A I/O

• Section 5.5.1 "Pin states": updated

• Section 5.5.2 "General purpose I/O (GPIO) (MFP)": updated GPIO[15], GPIO[14],

GPIO[13], GPIO[12], GPIO[5] , GPIO[4], and GPIO[1] description

• Section 5.5.10 "Clock interface": updated XTAL_IN and SLP_CLK_IN descriptions

• Section 5.5.12 "Power supply and ground": updated VIO_SD description

• Section 5.5.13 "JTAG interface": added

• Section 5.6 "Configuration pins": updated the second table Host configuration options

Power information

• Section 6.1 "Power modes": added a table footnote for deep-sleep mode

• Section 6.2 "Power-up sequence": updated the introduction

• Section 6.3 "Power-down sequence": updated VCORE value in the figure

• Section 6.3.2 "Host power-down pin (PMIC_EN) usage": updated VCORE value in the

figure

Absolute maximum ratings

• Table 24 "Absolute maximum ratings ": updated the parameter definitions and removed the

column with typical values. No change for the min. and max. values.

Electrical specifications

• Section 9.10.2 "External crystal specifications": updated the series resistance (ESR)

maximum value

• Section 9.3.1 "Wi-Fi radio performance measurement": added

• Section 9.3.2 "2.4ꢀGHz Wi-Fi receive performance": updated

• Section 9.3.3 "5 GHz receive performance": updated

• Section 9.3.4 "2.4 GHz transmit performance": updated

• Section 9.4.1 "Bluetooth/Bluetooth LE receive performance": updated

• Section 9.4.2 "Bluetooth/Bluetooth LE transmit performance": updated

• Section 9.6 "Current consumption": updated

Package information

• Section 10.1.2 "WLCSP76 thermal conditions": added

• Section 10.3.1 "HVFQN68 marking": updated

• Section 10.3.2 "WLCSP76 marking": added

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IW416

Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

Table 64.ꢀRevision history...continued

Document ID

IW416 v.2.0

Modifications

Release date

Data sheet status

Change notice

Supersedes

20200731

Preliminary data sheet -

88W8978 v.1.0

Overall document

• Changed the document title

• Renamed WLAN as Wi-Fi

Product overview

• Updated the introduction

• Replaced the overall block diagram with the application block diagram and the internal

block diagram

Section 1.6 "General features": added WLCSP76 package option

Wi-Fi subsystem

• Moved the content related to Wi-Fi in former Main Features section into this section

Bluetooth subsystem

• Moved the content related to Bluetooth in former Main Features section into this section

Pin information

• Updated Section 5.1 "Signal diagram"

• Corrected pins 39 and 40 in Section 5.2 "Pin assignment - HVQFN68 package" and

rotated the diagram to reflect the position of pin 1 on the top left side

• Added Pin lists for HVQFN68 package

• Added Section 5.5 "Pin description"

• Added Section 5.3 "Bump locations - WLCSP76 package"

Absolute maximum ratings

• Section 7 "Absolute maximum ratings": added the table with limiting values

Recommended operating conditions

• Updated VCORE minimum value

Electrical specifications

• Section 9.10.1 "External crystal oscillator specifications": added 40 MHz reference clock

• Section 9.10.2 "External crystal specifications": updated fundamental frequencies typical

value

Package information

• Updated Section 10.2.1 "HVQFN68 mechanical drawing"

• Added Section 10.2.2 "WLCSP76 mechanical drawing"

• Added Section 10.1.2 "WLCSP76 thermal conditions"

• Updated Section 10.3.1 "HVFQN68 marking"

• Added Section 10.3.2 "WLCSP76 marking"

Ordering information

• Added the part numbering scheme and updated the part order codes

88W8978 v.1.0

20200110

Objective data sheet

-

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Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

13 Legal information

13.1 Data sheet status

Document status^[1][2]

Product status^[3]

Definition

Objective [short] data sheet

Development

This document contains data from the objective specification for product

development.

Preliminary [short] data sheet

Product [short] data sheet

Qualification

Production

This document contains data from the preliminary specification.

This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term 'short data sheet' is explained in section "Definitions".

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple

devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

13.2 Definitions

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer’s own

risk.

Draft — A draft status on a document indicates that the content is still

under internal review and subject to formal approval, which may result

in modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included in a draft version of a document and shall have no

liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is

intended for quick reference only and should not be relied upon to contain

detailed and full information. For detailed and full information see the

relevant full data sheet, which is available on request via the local NXP

Semiconductors sales office. In case of any inconsistency or conflict with the

short data sheet, the full data sheet shall prevail.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes

no representation or warranty that such applications will be suitable

for the specified use without further testing or modification. Customers

are responsible for the design and operation of their applications and

products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications

and products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with

their applications and products. NXP Semiconductors does not accept any

liability related to any default, damage, costs or problem which is based

on any weakness or default in the customer’s applications or products, or

the application or use by customer’s third party customer(s). Customer is

responsible for doing all necessary testing for the customer’s applications

and products using NXP Semiconductors products in order to avoid a

default of the applications and the products or of the application or use by

customer’s third party customer(s). NXP does not accept any liability in this

respect.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product

is deemed to offer functions and qualities beyond those described in the

Product data sheet.

13.3 Disclaimers

Limited warranty and liability — Information in this document is believed

to be accurate and reliable. However, NXP Semiconductors does not

give any representations or warranties, expressed or implied, as to the

accuracy or completeness of such information and shall have no liability

for the consequences of use of such information. NXP Semiconductors

takes no responsibility for the content in this document if provided by an

information source outside of NXP Semiconductors. In no event shall NXP

Semiconductors be liable for any indirect, incidental, punitive, special or

consequential damages (including - without limitation - lost profits, lost

savings, business interruption, costs related to the removal or replacement

of any products or rework charges) whether or not such damages are based

on tort (including negligence), warranty, breach of contract or any other

legal theory. Notwithstanding any damages that customer might incur for

any reason whatsoever, NXP Semiconductors’ aggregate and cumulative

liability towards customer for the products described herein shall be limited

in accordance with the Terms and conditions of commercial sale of NXP

Semiconductors.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those

given in the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Right to make changes — NXP Semiconductors reserves the right to

make changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

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IW416

Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or

the grant, conveyance or implication of any license under any copyrights,

patents or other industrial or intellectual property rights.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

Security — Customer understands that all NXP products may be subject

to unidentified or documented vulnerabilities. Customer is responsible

for the design and operation of its applications and products throughout

their lifecycles to reduce the effect of these vulnerabilities on customer’s

applications and products. Customer’s responsibility also extends to other

open and/or proprietary technologies supported by NXP products for use

in customer’s applications. NXP accepts no liability for any vulnerability.

Customer should regularly check security updates from NXP and follow up

appropriately. Customer shall select products with security features that best

meet rules, regulations, and standards of the intended application and make

the ultimate design decisions regarding its products and is solely responsible

for compliance with all legal, regulatory, and security related requirements

concerning its products, regardless of any information or support that may

be provided by NXP. NXP has a Product Security Incident Response Team

(PSIRT) (reachable at PSIRT@nxp.com) that manages the investigation,

reporting, and solution release to security vulnerabilities of NXP products.

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor

tested in accordance with automotive testing or application requirements.

NXP Semiconductors accepts no liability for inclusion and/or use of non-

automotive qualified products in automotive equipment or applications. In

the event that customer uses the product for design-in and use in automotive

applications to automotive specifications and standards, customer (a) shall

use the product without NXP Semiconductors’ warranty of the product for

such automotive applications, use and specifications, and (b) whenever

customer uses the product for automotive applications beyond NXP

Semiconductors’ specifications such use shall be solely at customer’s own

risk, and (c) customer fully indemnifies NXP Semiconductors for any liability,

damages or failed product claims resulting from customer design and use

of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

13.4 Trademarks

Notice: All referenced brands, product names, service names and

trademarks are the property of their respective owners.

NXP — wordmark and logo are trademarks of NXP B.V.

IW416

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 25 June 2021

95 / 99

NXP Semiconductors

IW416

Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

Tables

Tab. 1.

Tab. 2.

Part order codes ............................................... 5

Frequencies supported by 20 MHz

Tab. 35. Local oscillator ................................................ 50

Tab. 36. Bluetooth/Bluetooth LE receive

channels ............................................................ 8

Frequencies Supported by the 40 MHz

performance .................................................... 51

Tab. 37. Bluetooth/Bluetooth LE transmit

Tab. 3.

channels ............................................................ 9

Pin list by number - HVQFN68 package ..........16

Pin by name - HVQFN68 package ..................18

Bump names and locations on WLCSP76

performance .................................................... 55

Tab. 38. Current consumption values ............................58

Tab. 39. VIO_SD requirements ..................................... 60

Tab. 40. DC electrical characteristics—1.8V

Tab. 4.

Tab. 5.

Tab. 6.

top view ...........................................................21

Pin types ......................................................... 24

GPIO (MFP) .................................................... 25

Wi-Fi/Bluetooth radio interface ........................27

operation (VIO_SD) .........................................60

Tab. 41. DC electrical characteristics—3.3V

Tab. 7.

Tab. 8.

Tab. 9.

operation (VIO_SD) .........................................60

Tab. 42. SDIO timing data—Default speed, high-

speed modes ...................................................61

Tab. 43. SDIO timing data——SDR12, SDR25,

SDR50 modes (up to 100MHz) (1.8V) ............ 62

Tab. 44. SDIO timing data—DDR50 mode (50MHz) ..... 64

Tab. 45. SDIO internal pull-up/pull-down

specifications ...................................................64

Tab. 46. UART timing data ............................................65

Tab. 47. PCM Timing Specification Data—Master

Mode ............................................................... 66

Tab. 48. PCM timing specification data—Slave

mode ............................................................... 67

Tab. 49. Clock DC specifications .................................. 68

Tab. 50. 26 MHz clock timing ........................................68

Tab. 51. 40 MHz clock timing ........................................68

Tab. 52. Phase noise—2.4 GHz operation ....................69

Tab. 53. Phase noise—5 GHz operation .......................69

Tab. 54. External crystal specifications ......................... 70

Tab. 55. External sleep clock specifications ..................70

Tab. 56. PDn pin (Power Down) specifications—

Power remains high at PDn assertion .............71

Tab. 57. PDn pin (Power Down) specifications—

Power ramps down at PDn assertion ..............72

Tab. 58. Configuration pin specifications .......................73

Tab. 59. JTAG timing data ............................................ 73

Tab. 60. Package thermal conditions—HVQFN68 ........ 74

Tab. 61. Package thermal conditions—WLCSP76 ........ 75

Tab. 62. Package information ........................................76

Tab. 63. Acronyms and abbreviations ...........................82

Tab. 64. Revision history ...............................................91

Tab. 10. Wi-Fi RF front-end control interface ................ 27

Tab. 11. SDIO host i (MFP) .......................................... 28

Tab. 12. UART host interface (MFP) .............................29

Tab. 13. Audio interface pins (MFP) ............................. 29

Tab. 14. PTA interface (MFP) ........................................30

Tab. 15. WCI-2 interface ............................................... 30

Tab. 16. Clock interface ................................................ 31

Tab. 17. Power down (PDn) pin ....................................31

Tab. 18. Power and ground pins ...................................32

Tab. 19. JTAG interface pins (MFP) ..............................32

Tab. 20. Configuration pins ........................................... 33

Tab. 21. Host configuration options ...............................33

Tab. 22. Device power modes ...................................... 34

Tab. 23. Configuration—VCORE from PMIC .................35

Tab. 24. Absolute maximum ratings ..............................40

Tab. 25. Limiting values (HVQFN68 package) .............. 40

Tab. 26. Recommended operating conditions ...............41

Tab. 27. DC electrical characteristics—1.8V

operation (VIO) ................................................42

Tab. 28. DC electrical characteristics—3.3V

operation (VIO) ................................................42

Tab. 29. DC electrical characteristics—1.8V

operation (VIO_RF) .........................................43

Tab. 30. DC electrical characteristics—3.3V

operation (VIO_RF) .........................................43

Tab. 31. 2.4 GHz Wi-Fi receive performance ................45

Tab. 32. 5ꢀGHz Wi-Fi receive performance ................... 47

Tab. 33. 2.4 GHz Wi-Fi transmit performance ...............49

Tab. 34. 5ꢀGHz Wi-Fi transmit performance .................. 50

Figures

Fig. 1.

Fig. 2.

Fig. 3.

Fig. 4.

Fig. 5.

Fig. 6.

Application block diagram ................................. 1

Internal block diagram .......................................4

Part numbering scheme ....................................5

PCM Short Frame Sync ..................................13

Signal diagram ................................................ 14

Pin assignment (package top view) -

HVQFN68 ........................................................15

Bump locations - WLCSP76 (non-bump

side view, bumps down) ..................................20

Configuration—VCORE from PMIC .................35

Power-up sequence ........................................ 36

Fig. 10. Power-down sequence ....................................37

Fig. 11.

PMIC_EN pin usage—PMIC/SoC both in

power-down mode ...........................................38

Fig. 12. RF performance measurement points .............44

Fig. 13. SDIO protocol timing diagram—Default

speed mode .................................................... 61

Fig. 14. SDIO protocol timing diagram—High-speed

mode ............................................................... 61

Fig. 15. SDIO protocol timing diagram—SDR12,

SDR25, SDR50 modes (up to 100MHz)

Fig. 7.

Fig. 8.

Fig. 9.

(1.8V) ...............................................................62

IW416

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Product data sheet

Rev. 4 — 25 June 2021

96 / 99

NXP Semiconductors

IW416

Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

Fig. 16. SDIO CMD timing diagram—DDR50 mode

(50MHz) ...........................................................63

Fig. 17. SDIO DAT[3:0] timing diagram—DDR50

mode ............................................................... 63

Fig. 18. UART timing diagram ......................................65

Fig. 19. PCM timing specification diagram for data

signals—Master mode .....................................66

Fig. 20. PCM timing specification diagram for

PCM_SYNC signal—Master mode ..................66

Fig. 21. PCM timing specification diagram for data

signals—Slave mode .......................................67

Fig. 22. PCM timing specification diagram for

PCM_SYNC signal—Slave mode ................... 67

Fig. 23. PDn pin (Power-down) timing—Power

remains high at PDn assertion ........................71

Fig. 24. PDn pin (Power Down) timing—Power

ramps down at PDn assertion .........................72

Fig. 25. JTAG timing diagram .......................................73

Fig. 26. HVQFN68 package mechanical drawing .........76

Fig. 27. HVFQN68 package mechanical drawing -

Detail G ........................................................... 77

Fig. 28. WLCSP76 package mechanical drawing ........ 78

Fig. 29. WLCSP76 package mechanical drawing -

Detail E ........................................................... 79

Fig. 30. Package marking and pin 1 location

—HVQFN68, commercial operating

temperature ..................................................... 80

Fig. 31. Package marking and pin 1 location—

HVQFN68, industrial operating temperature ... 80

Fig. 32. Package marking and pin 1 location

—WLCSP76, commercial operating

temperature range ...........................................81

Fig. 33. Package marking and pin 1

location—WLCSP76, industrial operating

temperature range ...........................................81

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Product data sheet

Rev. 4 — 25 June 2021

97 / 99

NXP Semiconductors

IW416

Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

Contents

1

Product overview ................................................ 1

6.3.2

6.4

6.5

6.6

7

8

9

9.1

9.1.1

9.1.1.1

9.1.1.2

9.2

9.2.1

9.2.1.1

9.2.1.2

9.3

9.3.1

9.3.2

9.3.3

9.3.4

9.3.5

9.3.6

9.4

Host power-down pin (PMIC_EN) usage .........38

Leakage optimization .......................................39

Deep sleep ...................................................... 39

Reset ................................................................39

Absolute maximum ratings ..............................40

Recommended operating conditions .............. 41

Electrical specifications ................................... 42

GPIO/LED interface specifications ...................42

VIO DC characteristics .................................... 42

1.8V operation ................................................. 42

3.3V operation ................................................. 42

RF front-end control interface specifications ....43

VIO_RF DC characteristics ..............................43

1.8V operation ................................................. 43

3.3V operation ................................................. 43

Wi-Fi radio specifications .................................44

Wi-Fi radio performance measurement ........... 44

2.4ꢀGHz Wi-Fi receive performance .................45

5 GHz receive performance .............................47

2.4 GHz transmit performance ........................ 49

5 GHz transmit performance ........................... 50

Local oscillator .................................................50

Bluetooth radio specifications ..........................51

Bluetooth/Bluetooth LE receive

1.1

1.2

1.3

1.4

1.5

1.6

1.7

2

Applications ........................................................2

Wi-Fi key features ............................................. 2

Bluetooth key features .......................................2

Host interfaces ...................................................2

Operating characteristics ...................................3

General features ................................................3

Internal block diagram ....................................... 4

Ordering information .......................................... 5

Wi-Fi subsystem ..................................................6

IEEE 802.11 standards ......................................6

Wi-Fi MAC ......................................................... 6

Wi-Fi baseband ................................................. 7

Wi-Fi radio ......................................................... 7

Wi-Fi encryption ...............................................10

Wi-Fi host interfaces ........................................10

Bluetooth subsystem ........................................11

Bluetooth 2.4 GHz Tx/Rx .................................11

Bluetooth Low Energy (LE) ..............................12

Bluetooth host interfaces .................................12

Audio interfaces ...............................................12

I2S interface .................................................... 12

PCM interface ..................................................12

Protocol description ......................................... 13

Coexistence ..................................................... 13

Pin information ..................................................14

Signal diagram .................................................14

Pin assignment - HVQFN68 package ..............15

Pin list by number - HVQFN68 package ..........16

Pin list by name - HVQFN68 package .............18

Bump locations - WLCSP76 package ..............20

Bump positions relative to die center -

WLCSP76 ........................................................ 21

Pin types ..........................................................24

Pin description .................................................24

Pin states .........................................................24

General purpose I/O (GPIO) (MFP) .................25

Wi-Fi/Bluetooth radio interface ........................ 27

Wi-Fi RF front-end control interface .................27

SDIO host interface (MFP) .............................. 28

UART host interface ........................................ 29

Audio interface .................................................29

PTA interface ................................................... 30

WCI-2 interface ................................................30

Clock interface .................................................31

Power down (PDn) pin .................................... 31

Power supply and ground ................................32

JTAG interface .................................................32

Configuration pins ............................................33

Power information .............................................34

Power modes ...................................................34

Power-up sequence .........................................35

Configuration—VCORE from PMIC .................35

Power-up sequence timing .............................. 36

Power-down sequence .................................... 37

3

3.1

3.2

3.3

3.4

3.5

3.6

4

4.1

4.2

4.3

4.4

4.4.1

4.4.2

4.4.2.1

4.5

5

9.4.1

performance .....................................................51

Bluetooth/Bluetooth LE transmit

9.4.2

5.1

5.2

5.2.1

5.2.2

5.3

5.3.1

performance .....................................................55

PTA interface specifications .............................57

Current consumption ....................................... 58

SDIO host interface specifications ...................60

VIO_SD DC characteristics ............................. 60

1.8V operation ................................................. 60

3.3V operation ................................................. 60

Default speed, high-speed modes ...................61

SDR12, SDR25, SDR50 modes (up to 100

9.5

9.6

9.7

9.7.1

9.7.1.1

9.7.1.2

9.7.2

9.7.3

5.4

5.5

5.5.1

5.5.2

5.5.3

5.5.4

5.5.5

5.5.6

5.5.7

5.5.8

5.5.9

5.5.10

5.5.11

5.5.12

5.5.13

5.6

6

6.1

6.2

6.2.1

6.2.2

6.3

MHz) (1.8V) ..................................................... 62

DDR50 mode (50MHz) (1.8V) ......................... 63

SDIO internal pull-up/pull-down

9.7.4

9.7.5

specifications ................................................... 64

High-speed UART specifications ..................... 65

Audio interface specifications .......................... 65

I2S interface specifications ..............................65

PCM interface specifications ........................... 65

Reference clock specifications ........................ 68

External crystal oscillator specifications ...........68

External crystal specifications ..........................70

External sleep clock specifications .................. 70

Power down (PDn) pin specifications .............. 71

PDn asserted low—All power supplies good ... 71

PDn asserted low—One or more power

supplies ramp down ........................................ 72

Configuration pin specifications .......................73

JTAG interface specifications .......................... 73

Package information .........................................74

Package thermal conditions .............................74

HVQFN68 thermal conditions ..........................74

9.8

9.9

9.9.1

9.9.2

9.10

9.10.1

9.10.2

9.10.3

9.11

9.11.1

9.11.2

9.12

9.13

10

10.1

10.1.1

6.3.1

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Product data sheet

Rev. 4 — 25 June 2021

98 / 99

NXP Semiconductors

IW416

Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC

10.1.2

10.2

10.2.1

10.2.2

10.3

10.3.1

10.3.2

11

WLCSP76 thermal conditions ..........................75

Package mechanical drawing ..........................76

HVQFN68 mechanical drawing ....................... 76

WLCSP76 mechanical drawing ....................... 78

Package marking .............................................80

HVFQN68 marking .......................................... 80

WLCSP76 marking .......................................... 81

Acronyms and abbreviations ...........................82

Revision history ................................................ 91

Legal information ..............................................94

12

13

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section 'Legal information'.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 25 June 2021


型号：	IW416
厂家：	NXP
描述：	Dual-band 1x1 Wi-Fi 4 and Bluetooth 5.1 Combo SoC
文件：	总99页 (文件大小：996K)
中文：	中文翻译
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IW416 [NXP]

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