J108 [NXP]

N-channel silicon junction FETs; N沟道硅结场效应晶体管
J108
型号: J108
厂家: NXP    NXP
描述:

N-channel silicon junction FETs
N沟道硅结场效应晶体管

晶体 晶体管 场效应晶体管
文件: 总7页 (文件大小:49K)
中文:  中文翻译
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DISCRETE SEMICONDUCTORS  
DATA SHEET  
J108; J109; J110  
N-channel silicon junction FETs  
Product specification  
1996 Jul 30  
Supersedes data of April 1995  
File under Discrete Semiconductors, SC07  
Philips Semiconductors  
Productspecification  
N-channel silicon junction FETs  
J108; J109; J110  
FEATURES  
PINNING - TO-92  
High speed switching  
PIN  
SYMBOL  
DESCRIPTION  
Interchangeability of drain and source connections  
Low RDSon at zero gate voltage (<8 for J108).  
1
2
3
g
s
d
gate  
source  
drain  
APPLICATIONS  
Analog switches  
Choppers and commutators.  
1
handbook, halfpage  
2
DESCRIPTION  
3
d
g
s
N-channel symmetrical silicon junction field-effect  
transistors in a TO-92 package.  
MAM197  
CAUTION  
The device is supplied in an antistatic package. The  
gate-source input must be protected against static  
discharge during transport or handling.  
Fig.1 Simplified outline and symbol.  
QUICK REFERENCE DATA  
SYMBOL  
VDS  
PARAMETER  
drain-source voltage  
CONDITIONS  
MIN.  
MAX.  
±25  
UNIT  
V
VGSoff  
gate-source cut-off voltage  
ID = 1 µA; VDS = 5 V  
J108  
3  
10  
6  
V
V
V
J109  
2  
J110  
0.5  
4  
IDSS  
drain current  
VGS = 0; VDS = 5 V  
J108  
80  
40  
10  
mA  
mA  
mA  
mW  
J109  
J110  
Ptot  
total power dissipation  
up to Tamb = 50 °C  
400  
1996 Jul 30  
2
Philips Semiconductors  
Productspecification  
N-channel silicon junction FETs  
J108; J109; J110  
LIMITING VALUES  
In accordance with the Absolute Maximum Rating System (IEC 134).  
SYMBOL  
VDS  
PARAMETER  
drain-source voltage  
CONDITIONS  
MIN.  
MAX.  
±25  
UNIT  
V
V
V
VGSO  
VGDO  
IG  
gate-source voltage  
open drain  
25  
25  
50  
gate-drain voltage  
open source  
forward gate current (DC)  
total power dissipation  
storage temperature  
mA  
mW  
°C  
Ptot  
Tstg  
Tj  
up to Tamb = 50 °C  
400  
150  
150  
65  
operating junction temperature  
°C  
THERMAL CHARACTERISTICS  
SYMBOL  
PARAMETER  
VALUE  
250  
UNIT  
Rth j-a  
thermal resistance from junction to ambient  
K/W  
STATIC CHARACTERISTICS  
Tj = 25 °C; unless otherwise specified.  
SYMBOL  
V(BR)GSS  
VGSoff  
PARAMETER  
CONDITIONS  
IG = 1 µA; VDS = 0  
ID = 1 µA; VDS = 5 V  
MIN.  
TYP.  
MAX.  
25  
UNIT  
gate-source breakdown voltage  
V
V
V
V
V
gate-source cut-off voltage  
J108  
3  
10  
6  
J109  
2  
J110  
0.5  
4  
IDSS  
drain current  
VGS = 0; VDS = 15 V  
J108  
80  
40  
10  
mA  
mA  
mA  
nA  
J109  
J110  
IGSS  
gate leakage current  
VGS = 15 V; VDS = 0  
VGS = 10 V; VDS = 5 V  
VGS = 0; VDS = 100 mV  
3  
3
IDSX  
drain-source cut-off current  
nA  
RDSon  
drain-source on-state resistance  
J108  
J109  
J110  
8
12  
18  
1996 Jul 30  
3
Philips Semiconductors  
Productspecification  
N-channel silicon junction FETs  
J108; J109; J110  
DYNAMIC CHARACTERISTICS  
Tj = 25 °C; unless otherwise specified.  
SYMBOL  
Cis  
PARAMETER  
input capacitance  
CONDITIONS  
VDS = 0; VGS = 10 V; f = 1 MHz  
VDS = 0; VGS = 0; f = 1 MHz;  
TYP.  
15  
MAX.  
30  
UNIT  
pF  
50  
85  
pF  
Tamb = 25 °C  
Crs  
reverse transfer capacitance  
VDS = 0; VGS = 10 V; f = 1 MHz  
8
15  
pF  
Switching times; see Fig.2  
td  
delay time  
note 1  
2
4
4
6
ns  
ns  
ns  
ns  
ton  
ts  
turn-on time  
storage time  
turn-off time  
toff  
Note  
1. Test conditions for switching times are as follows:  
DD = 1.5 V; VGS = 0 to VGSoff (all types)  
V
VGSoff = 12 V; RL = 100 (J108)  
VGSoff = 7 V; RL = 100 (J109)  
VGSoff = 5 V; RL = 100 (J110).  
0.1 µF  
handbook, halfpage  
50 Ω  
V
DD  
10 nF  
10 µF  
R
L
SAMPLING  
SCOPE  
50 Ω  
DUT  
50 Ω  
MGE773  
Fig.2 Switching circuit.  
1996 Jul 30  
4
Philips Semiconductors  
Productspecification  
N-channel silicon junction FETs  
J108; J109; J110  
V
= 0 V  
GS  
10%  
90%  
V
i
V
GS off  
t
t
on  
off  
t
t
t
t
r
s
f
d
90%  
10%  
V
o
MGE774  
Fig.3 Input and output waveforms.  
1996 Jul 30  
5
Philips Semiconductors  
Productspecification  
N-channel silicon junction FETs  
J108; J109; J110  
PACKAGE OUTLINE  
n
0.40  
min  
4.2 max  
1.7  
1.4  
5.2 max  
12.7 min  
0.48  
0.40  
1
4.8  
max  
2.54  
2
3
0.66  
0.56  
(1)  
MBC014 - 1  
2.0 max  
Dimensions in mm.  
(1) Terminal dimensions in this zone are uncontrolled.  
Fig.4 TO-92 (SOT54).  
1996 Jul 30  
6
Philips Semiconductors  
Productspecification  
N-channel silicon junction FETs  
J108; J109; J110  
DEFINITIONS  
Data Sheet Status  
Objective specification  
Preliminary specification  
Product specification  
This data sheet contains target or goal specifications for product development.  
This data sheet contains preliminary data; supplementary data may be published later.  
This data sheet contains final product specifications.  
Limiting values  
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or  
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation  
of the device at these or at any other conditions above those given in the Characteristics sections of the specification  
is not implied. Exposure to limiting values for extended periods may affect device reliability.  
Application information  
Where application information is given, it is advisory and does not form part of the specification.  
LIFE SUPPORT APPLICATIONS  
These products are not designed for use in life support appliances, devices, or systems where malfunction of these  
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for  
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such  
improper use or sale.  
1996 Jul 30  
7

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