JN5179/001Z [NXP]
JN517x - IEEE802.15.4 Wireless Microcontroller;型号: | JN5179/001Z |
厂家: | NXP |
描述: | JN517x - IEEE802.15.4 Wireless Microcontroller 无线 微控制器 外围集成电路 |
文件: | 总100页 (文件大小:3422K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
JN517x
JN517x
IEEE802.15.4 Wireless Microcontroller
Rev. 3.0 — 7 November 2017
Product data sheet
1. General description
The JN517x series is a range of ultra low power, high performance wireless
microcontrollers suitable for ZigBee applications to facilitate the development of Smart
Home and Smart Lighting applications. It features a high-performance and low-power
ARM Cortex-M3 processor with debug with programmable clock speeds. The JN517x
devices are available in JN5174, JN5178 and JN5179 variants, respectively having 160
kB, 256 kB and 512 kB of embedded Flash memory as well as 32 kB of RAM and 4 kB of
EEPROM. The embedded Flash can support “Over-The-Air” code download of software
stacks. Radio transmit power is configurable up to +10 dBm output. The very-low receive
operating current (down to 12.7 mA and with a 0.6 A sleep timer mode) gives excellent
battery life allowing operation direct from a coin cell. The JN517x also includes a 2.4 GHz
“IEEE802.15.4 compliant” transceiver and a comprehensive mix of analog and digital
peripherals.
The JN517x is ideal for battery-operated applications supported through the
comprehensive power-saving modes available in the device. The on-chip peripherals,
which include a fail-safe I2C-bus, SPI-bus ports (both master and slave), and a
six-channel analog-digital converter with internal temperature sensor support a wide
range of applications directly without extra hardware.
2. Features and benefits
2.1 Benefits
Very low current solution for long battery life: over 10 years
Very low receive current for low standby power of receiver always on nodes
Integrated power amplifier for long range and robust communication
Large embedded Flash memory to enable Over-The-Air (OTA) firmware updates
without external Flash memory
Single chip device to run communication stack and application
Supports multiple network stacks
Peripherals customized for lighting applications
System BOM is low in component count and cost
Flexible sensor interfacing
Package
6 6 mm HVQFN40, 0.5 mm pitch
lead-free and RoHS compliant
Temperature range: 40 C to +125 C
JN517x
NXP Semiconductors
IEEE802.15.4 Wireless Microcontroller
2.2 Radio features
2.4 GHz IEEE802.15.4 compliant Ref. 1
Receive current 14.8 mA, in low-power receive mode 12.7 mA
Receiver sensitivity 96 dBm
Configurable transmit power, for reduced current consumption, for example:
10 dBm, 22.5 mA
8.5 dBm, 19.6 mA
3 dBm, 14 mA
Radio link budget 106 dB
Maximum input level of +10 dBm
Compensation for temperature drift of crystal oscillator frequency
2.0 V to 3.6 V battery operation
Antenna diversity (Auto RX)
Integrated ultra-low-power sleep oscillator (0.6 A)
100 nA deep sleep current with wake-up from external event
128-bit AES security processor
MAC accelerator with packet formatting, CRCs, address check, auto-acks, timers
2.3 Microcontroller features
ARM Cortex-M3 CPU with debug support
JN5174: 160 kB/32 kB/4 kB (Flash/RAM/EEPROM)
JN5178: 256 kB/32 kB/4 kB (Flash/RAM/EEPROM)
JN5179: 512 kB/32 kB/4 kB (Flash/RAM/EEPROM)
OTA firmware upgrade capability
32 MHz clock selectable down to 1 MHz for low-power operation
Dual PAN ID support
Fail-safe I2C-bus interface. operates as either master or slave
8 Timers (6 PWM and 2 timer/counters)
2 low-power sleep counters
2 UART, one with flow control
SPI-bus master and slave port, 2 simultaneous selects
Variable instruction width for high coding efficiency
Multi-stage instruction pipeline
Data EEPROM with guaranteed 100 k write operations
Supply voltage monitor with 8 programmable thresholds
Battery voltage and temperature sensors
6-input 10-bit ADC
Analog comparator
Digital monitor for ADC
Watchdog timer and POR
Low-power modes controller
Up to 18 Digital IO (DIO) and 2 digital outputs pins
JN517X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet
Rev. 3.0 — 7 November 2017
2 of 100
JN517x
NXP Semiconductors
IEEE802.15.4 Wireless Microcontroller
3. Applications
Robust and secure low-power wireless applications
ZigBee 3.0
Commercial Building and Home Automation
Smart Lighting networks
Internet of Things (IoT)
Toys and gaming peripherals
Energy harvesting, for example self-powered light switch
4. Overview
The JN517x is an IEEE802.15.4 wireless microcontroller that provides a fully integrated
solution for applications using the IEEE802.15.4 standard in the 2.4 GHz to 2.5 GHz ISM
frequency band, including ZigBee PRO.
Applications that transfer data wirelessly tend to be more complex than wired ones.
Wireless protocols make stringent demands on frequencies, data formats, timing of data
transfers, security and other issues. Application development must consider the
requirements of the wireless network in addition to the product functionality and user
interfaces. To minimize this complexity, NXP provides a series of software libraries and
interfaces that control the transceiver and peripherals of the JN517x. These libraries and
interfaces remove the need for the developer to understand wireless protocols and greatly
simplifies the programming complexities of power modes, interrupts and hardware
functionality.
In view of the above, it is not necessary to provide the register details of the JN517x in the
data sheet.
The device includes a wireless transceiver, ARM Cortex-M3 CPU, “on-chip memory” and
an extensive range of peripherals.
4.1 Wireless transceiver
The wireless transceiver comprises a 2.45 GHz radio, a modem, a baseband controller
and a security coprocessor. In addition, the radio also provides an output to control
transmit-receive switching of external devices such as power amplifiers allowing
applications that require increased transmit power to be realized very easily. Section 15.1
describes a complete reference design including Printed-Circuit Board (PCB) design and
Bill Of Materials (BOM).
The security coprocessor provides hardware-based 128-bit AES-CCM modes as
specified by the IEEE802.15.4 2006 standard. Specifically this includes encryption and
authentication covered by the MIC-32/-64/-128, ENC and ENC-MIC-32/-64/-128 modes of
operation.
The transceiver elements (radio, modem and baseband) work together to provide
IEEE802.15.4 (2006) MAC and PHY functionality under the control of a protocol stack.
The transmitter is equipped with a power amplifier with 3 options for transmit power (major
steps, fine steps and attenuator) see Figure 51. Applications incorporating IEEE802.15.4
functionality can be developed rapidly by combining user-developed application software
JN517X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet
Rev. 3.0 — 7 November 2017
3 of 100
JN517x
NXP Semiconductors
IEEE802.15.4 Wireless Microcontroller
with a protocol stack library.
4.2 CPU and memory
An ARM Cortex-M3 CPU allows software to be run on-chip, its processing power being
shared between the IEEE802.15.4 MAC protocol, other higher layer protocols and the
user application. The JN517x has a unified memory architecture, where code memory,
data memory, peripheral devices and IO ports are organized within the same linear
address space. The device contains 160 kB or 256 kB or 512 kB of Flash and 32 kB of
RAM and 4 kB EEPROM.
4.3 Peripherals
The following peripherals are available on chip:
• Master SPI-bus port with 2 simultaneous select outputs
• Slave SPI-bus port
• 2 UARTs: one capable of hardware flow control (4-wire, includes RTS/CTS) and the
other a 2-wire (RX/TX).
• 2 programmable timer/counters which support Pulse Width Modulation (PWM) and
capture/compare, plus 6 PWM timers which support PWM and Timer modes only.
• 2 programmable sleep timers and a system tick timer
• 2-wire serial interface (compatible with SMbus and I2C-bus) supporting master and
slave operation. Fail-safe open-drain IOs for I2C-bus.
• 18 digital IO lines (multiplexed with peripherals such as timers, SPI-bus and UARTs)
• 2 digital outputs (multiplexed with SPI-bus port)
• 10-bit, Analog-to-Digital Converter with 6 input channels. Autonomous multi-channel
sampling.
• Programmable analog comparator
• Digital comparator/monitor linked to ADC
• Internal temperature sensor and battery monitor
• 2 low-power pulse counters
• Random number generator
• Watchdog Timer and Supply Voltage Monitor (SVM)
• Debug support using serial-wire or 4-pin JTAG interface
• Debug trace port with up to 4 data lines.
• Transmit and receive antenna diversity with automatic receive switching based on
received energy detection
User applications access the peripherals using the Integrated Peripherals API. For further
details, refer to the JN517x Integrated Peripherals API User Guide, JN-UG-3118 on the
Wireless Connectivity area of the NXP web site Ref. 2. This allows applications to use a
tested and easily understood view of the peripherals allowing rapid system development.
JN517X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet
Rev. 3.0 — 7 November 2017
4 of 100
JN517x
NXP Semiconductors
IEEE802.15.4 Wireless Microcontroller
5. Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
Version
JN517x[1]
HVQFN40 Plastic thermal enhanced very thin quad flat package; no leads;
SOT618-8
40 terminals; body 6 6 0.85 mm
[1] x = 4: Flash = 160 kB.
x = 8: Flash = 256 kB.
x = 9: Flash = 512 kB.
For further details, refer to the Wireless Connectivity area of the NXP web site Ref. 2.
6. Block diagram
SPI-BUS MASTER
AND SLAVE
WATCHDOG
TIMER
FLASH
RAM
2
I C-BUS MASTER
AND SLAVE
VOLTAGE
BROWNOUT
6 x PWM
PLUS TIMER
ARM Cortex-M3
O-QPSK
MODEM
2.4 GHz
2 x UART
DIO
RADIO
EEPROM
INCLUDING
DIVERSITY
XTAL
IEEE802.15.4
MAC
ACCELERATOR
SLEEP COUNTER
6 CHAN
10 BIT ADC
128-BIT AES
ENCRYPTION
ACCELERATOR
POWER
MANAGEMENT
SUPPLY AND
TEMP SENSORS
aaa-015434
Fig 1. Block diagram
JN517X
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© NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet
Rev. 3.0 — 7 November 2017
5 of 100
JN517x
NXP Semiconductors
IEEE802.15.4 Wireless Microcontroller
7. Functional diagram
SPISCLK
SPISMOSI
SPISMISO
SPISSEL
SPI-BUS
TICK TIMER
SLAVE
DIO0
DIO1
DIO2
DIO3
DIO4
DIO5
DIO6
DIO7
DIO8
DIO9
DIO10
DIO11
DIO12
DIO13
DIO14
DIO15
ARM CORTEX-M3
PROGRAMMABLE
INTERRUPT
CONTROLLER
SPICLK
SPIMOSI
SPIMISO
SPISEL0
SPISEL1
SPISEL2
SPI-BUS
MASTER
from peripherals
TXD0
RXD0
RTS0
CTS0
RAM
32 kB
EEPROM
4 kB
(2)
FLASH
UART0
CPU and
system clock
TXD1
RXD1
(1)
VB_XX
UART1
V
V
DDA
VOLTAGE
TIM0CK_GT
TIM0OUT
TIM0CAP
1.8 V
REGULATORS
DDD
TIMER0
CLOCK
HIGH-
XTAL_IN
32 MHz XTAL
CLOCK
GENERATOR
SOURCE
SPEED
TIM1OUT
TIM1CAP
AND
RC
TIMER1
PWMs
RATE
OSC
XTAL_OUT
SELECT
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
WATCHDOG
TIMER
RESET_N
RESET
MUX
SUPPLY VOLTAGE
MONITOR
WAKEUP
TIMER0
DIO17
DIO18
SDA
SCL
2
I C-BUS
WAKEUP
TIMER1
PC0
PC1
PULSE
COUNTERS
DO0
DO1
32 kHz CLOCK
SELECT
32KIN
JTAG_TDI
JTAG_TMS
JTAG_TCK
JTAG_TDO
TRACESWV
TRACECLK
TRACED0
TRACED1
TRACED2
TRACED3
32 kHz
RC
OSC
32 kHz
XTAL
OSC
32KXTALIN
32KXTALOUT
JTAG
DEBUG
SUPPLY
MONITOR
ADC
ADC0
VREF/ADC1
ADC2
MUX
ADO
ADE
ANTENNA
DIVERSITY
ADC3
ADC4
ADC5
FLICK_CTRL
POWER
CONTROLLER
TEMPERATURE
SENSOR
WIRELESS
COMP1M
COMP1P
CMP_OUT
TRANSCEIVER
RFTX
RFRX
COMPARATOR
SECURITY
PROCESSOR
DIGITAL
BASEBAND
RF_IO
IBIAS
RADIO AND PA
INTERFERER
DETECTOR
aaa-021504
(1) With XX = SYNTH or VCO or RF2 or RF1 or DIG.
(2) JN5174: 160 kB, JN5178: 256 kB and JN5179: 512 kB.
Fig 2. Functional block diagram
JN517X
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© NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet
Rev. 3.0 — 7 November 2017
6 of 100
JN517x
NXP Semiconductors
IEEE802.15.4 Wireless Microcontroller
8. Pinning information
8.1 Pinning
terminal 1
index area
1
2
30
29
28
27
26
25
24
23
22
21
DIO15
DIO17
V
DDD
DIO10/RXD0
DIO9/TXD0
DIO8
3
DIO18
4
RESET_N
XTAL_OUT
XTAL_IN
VB_SYNTH
VB_VCO
5
DIO7/SPIMOSI
DIO6/SPISEL0
DO1/SPIMISO
DO0/SPICLK
DIO5
JN517x
6
7
8
9
V
DDA
10
IBIAS
DIO4
aaa-021452
Transparent top view
Refer to Section 15.1 for important applications information regarding the connection of the paddle
to the PCB.
Fig 3. Pin configuration
JN517X
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© NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet
Rev. 3.0 — 7 November 2017
7 of 100
JN517x
NXP Semiconductors
IEEE802.15.4 Wireless Microcontroller
8.2 Pin description
Table 2.
Symbol
Pin description
Pin Type[1]
Default at reset/
during boot
Default internal
pull-up/pull-down
Description
DIO15
1
IO
DIO15 (I)
pull-down
DIO15 — digital input/output 15
PWM6 — PWM6 output
JTAG_TDO — JTAG TDO data output
SPIMOSI — SPI-bus master data output
SPISEL1 — SPI-bus master select output
1
TIM0CK_GT — Timer0 - clock gate input
TRACESWV — ARM trace Serial Wire
Viewer output
SPISSEL — SPI-bus slave select input
DIO17 — digital input/output 17
JTAG_TCK — JTAG TCK input
DIO17
2
IO
at reset: DIO17 (I); pull-up
during boot:
SWCK (I)
SWCK — Serial Wire Debugger Clock
input
SPISEL0 — SPI-bus master select output
0
TIM1CAP — Timer1 capture input
COMP1P — comparator plus input
SPISMISO — SPI-bus slave data output
DIO18 — digital input/output 18
JTAG_TMS — JTAG TMS input
SWD — Serial Wire Debugger input
SPIMISO — SPI-bus master data input
TIM1OUT — Timer1 output
DIO18
3
IO
DIO18 (I)
pull-up
COMP1M — comparator minus input
SPISCLK — SPI-bus slave clock input
RESET_N — reset input
RESET_N
XTAL_OUT
XTAL_IN
VB_SYNTH
VB_VCO
VDDA
4
I
pull-up
pull-up
pull-up
5
O
I
XTAL_OUT — system crystal oscillator
XTAL_IN — system crystal oscillator
VB_SYNTH — regulated supply voltage
VB_VCO — regulated supply voltage
VDDA — analog supply voltage
6
7
P
P
P
I
8
9
IBIAS
10
IBIAS — bias current control
VREF/ADC1 11
I
VREF — analog peripheral reference
voltage
ADC1 — ADC input 1
VB_RF2
RF_IO
12 P; 1.8 V
13 IO
VB_RF2 — regulated supply voltage
RF_IO — RF antenna
VB_RF1
ADC0
14 P; 1.8 V
VB_RF1 — regulated supply voltage
ADC0 — ADC input 0
15
I
JN517X
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© NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet
Rev. 3.0 — 7 November 2017
8 of 100
JN517x
NXP Semiconductors
IEEE802.15.4 Wireless Microcontroller
Table 2.
Symbol
Pin description …continued
Pin Type[1]
Default at reset/
during boot
Default internal
pull-up/pull-down
Description
DIO0
16 IO
DIO0 (I)
pull-up
DIO0 — digital input/output 0
ADC4 — ADC input 4
SPISEL0 — SPI-bus master select
output 0
RFRX — radio receiver control output
FLICK_CTRL — flicker control output
ADO — antenna diversity odd output
DIO1 — digital input/output 1
DIO1
DIO2
17 IO
DIO1 (I)
DIO2 (I)
pull-up
pull-up
ADC3 — ADC input 3
RFTX — radio transmitter control input
PC0 — pulse counter 0 input
ADE — antenna diversity even output
DIO2 — digital input/output 2
18 IO
ADC5 — ADC input 5
SDA — I2C-bus master/slave SDA
input/output (push-pull output)
RXD1 — UART 1 receive data input
TIM0CAP — Timer0 capture input
RFRX — radios receiver control output
DIO3 — digital input/output 3
ADC2 — ADC input 2
DIO3
19 IO
DIO3 (I)
pull-down
PWM4 — PWM4 output
SCL — I2C-bus master/slave SCL
input/output (push-pull output)
TXD1 — UART 1 transmit data output
TIM0OUT — Timer0 output
RFTX — radio transmit control input
FLICK_CTRL — flicker control output
VSS — ground
VSS
20
G
DIO4
21 IO (open-drain)
DIO4 (I)
pull-up
DIO4 — digital input/output 4
SCL — I2C-bus master/slave SCL
input/output (open-drain)
RXD0 — UART 0 receive data input
TIM0CK_GT — Timer0 clock/gate input
ADO — antenna diversity odd output
JN517X
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© NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet
Rev. 3.0 — 7 November 2017
9 of 100
JN517x
NXP Semiconductors
IEEE802.15.4 Wireless Microcontroller
Table 2.
Symbol
Pin description …continued
Pin Type[1]
Default at reset/
during boot
Default internal
pull-up/pull-down
Description
DIO5
22 IO (open-drain)
DIO5 (I)
pull-up
DIO5 — digital input/output 5
SDA — I2C-bus master/slave SDA
input/output (open-drain)
TXD0 — UART 0 transmit data output
PC1 — pulse counter 1 input
TIM0CAP — Timer0 capture input
ADE — antenna diversity even output
DO0 — digital output 0
DO0[2]
DO1[3]
23
O
SPICLK (O)
SPIMISO (I)
pull-up
pull-up
SPICLK — SPI-bus master clock output
ADE — antenna diversity even output
DO1 — digital output 1
24 IO
SPIMISO — SPI-bus master data input
SPISMISO — SPI-bus slave data output
ADO — antenna diversity odd output
DIO6 — digital input/output 6
DIO6[4]
25 IO
SPISEL0 (O)
pull-up
SPISEL0 — SPI-bus master select output
0
CTS0 — UART 0 clear to send input
RXD1 — UART 1 receive data input
JTAG_TCK — JTAG TCK input
SWCK — Serial Wire Debugger Clock
input
SPISCLK — SPI-bus slave clock input
TIM1CAP — Timer1 capture input
DIO7 — digital input/output 7
DIO7[5]
26 IO
SPIMOSI (O)
pull-down
SPIMOSI — SPI-bus master data output
JTAG_TDI — JTAG TDI data input
SPISEL2 — SPI-bus master select output
2
SPISSEL — SPI-bus slave select input
CMP_OUT — comparator output
32KIN — 32 kHz External clock input
32KXTALOUT — 32 kHz clock output
DIO8 — digital input/output 8
DIO8
27 IO
DIO8 (I)
pull-down
PWM5 — PWM5 output
TIM0OUT — Timer0 output
TRACECLK — trace clock output
32KXTALIN — 32 kHz clock input
JN517X
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© NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet
Rev. 3.0 — 7 November 2017
10 of 100
JN517x
NXP Semiconductors
IEEE802.15.4 Wireless Microcontroller
Table 2.
Symbol
Pin description …continued
Pin Type[1]
Default at reset/
during boot
Default internal
pull-up/pull-down
Description
DIO9
28 IO
JTAG_TDO (O)/
TXD0 (O)
pull-up
DIO9 — digital input/output 9
JTAG_TDO — JTAG TDO data output
TXD0 — UART 0 transmit data output
TRACESWV — ARM trace serial wire
viewer output
DIO10
29 IO
JTAG_TDI (I)/
RXD0 (I)
pull-up
DIO10 — digital input/output 10
JTAG_TDI — JTAG TDI data input
RXD0 — UART 0 receive data input
VDDD — digital supply voltage
internally connected
VDDD
i.c.
30
31
32
33
34
P
-
n.c.
-
not connected
VSS
G
-
VSS — ground
n.c.
not connected
VB_DIG
DIO11
35 P; 1.8 V
36 IO
VB_DIG — regulated supply voltage
DIO11 — digital input/output 11
JTAG_TMS — JTAG TMS input
SWD — serial wire debugger input
RTS0 — UART 0 request to send output
TXD1 — UART 1 transmit data output
SPICLK — SPI-bus master clock output
SPISMOSI — SPI-bus slave data input
TIM1OUT — Timer1 output
SWD (I)
pull-up
TRACED0 — ARM trace data0 output
DIO12 — digital input/output 12
PWM1 — PWM1 output
DIO12
DIO13
37 IO
DIO12 (I)
DIO13 (I)
pull-down
pull-down
TXD0 — UART 0 transmit data output
TRACED3 — ARM trace data3 output
DIO13 — digital input/output 13
PWM2 — PWM2 output
38 IO
RXD0 — UART 0 receive data input
PC0 — pulse counter 0 input
TRACED2 — ARM trace data2 output
VSS — ground
VSS
39
G
DIO14
40 IO
DIO14 (I)
pull-down
DIO14 — digital input/output 14
PWM3 — PWM3 output
PC1 — pulse counter 1 input
CMP_OUT — comparator output
TRACED1 — ARM trace data1 output
SPISMOSI — SPI-bus slave data input
VSSA — Exposed die paddle
VSSA
-
G
-
-
JN517X
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© NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet
Rev. 3.0 — 7 November 2017
11 of 100
JN517x
NXP Semiconductors
IEEE802.15.4 Wireless Microcontroller
[1] P = power supply; G = ground; I = input, O = output; IO = input/output.
[2] JTAG programming mode: must be left floating high during reset to avoid entering JTAG programming mode.
[3] UART programming mode: leave pin floating high during reset to avoid entering UART programming mode or hold it low to program.
[4] Specific precautions have to be followed for UART flow control: CTS0 is not usable in the same time with SPISEL0.
[5] Specific precautions have to be followed if external 32 kHz crystal is used. SPI-bus Flash can not be used in the same time than
external 32 kHz crystal.
8.2.1 Power supplies
The VDDA and VDDD pins are decoupled with a 100 nF ceramic capacitor. VDDA is the
power supply to the analog circuitry; it should be decoupled to ground. VDDD is the power
supply for the digital circuitry; and should also be decoupled to ground. In addition, a
common 10 F tantalum capacitor is required to filter out low frequencies noise on the
power supply pins. Decoupling pins for the internal 1.8 V regulators are provided which
each requires a100 nF capacitor located as close to the device as practical. VB_SYNTH
and VB_DIG require only a 100 nF capacitor. VB_RF1 and VB_RF2 should be connected
together as close to the device as practical, and require one 100 nF capacitor and one
47 pF capacitor. The pin VB_VCO requires a 10 nF capacitor. Refer to Figure 55 for the
schematic diagram.
VSSA and VSS are the ground pins.
Users are strongly discouraged from connecting their own circuits to the 1.8 V regulated
supply pins, as the regulators have been optimized to supply only enough current for the
internal circuits.
Rising VDD voltage at power-up has to be done within 100 ms with a minimum IDD current
of 20 mA to avoid any start up issue.
8.2.2 Reset
RESET_N is an active low reset input pin that is connected to an internal pull-up resistor
see Table 19. It may be pulled low by an external circuit. Refer to Section 9.5.2 for more
details.
8.2.3 32 MHz oscillator
A crystal is connected between XTAL_IN and XTAL_OUT to form the reference oscillator,
which drives the system clock. A capacitor to analog ground is required on each of these
pins. Refer to Section 9.4.1 for more details. The 32 MHz reference frequency is divided
down to 16 MHz and this is used as the system clock throughout the device.
8.2.4 Radio
The radio is a single ended design, requiring only a capacitor and just 2 inductors to
match a 50 microstrip line to the RF_IO pin. In addition, extra-components are added
on the line for filtering purpose.
An external resistor (43 k) is required between IBIAS and analog ground (paddle) to set
various bias currents and references within the radio.
JN517X
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© NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet
Rev. 3.0 — 7 November 2017
12 of 100
JN517x
NXP Semiconductors
IEEE802.15.4 Wireless Microcontroller
8.2.5 Analog peripherals
The ADC requires a reference voltage to use as part of its operation. It can use either an
internal reference voltage or an external reference connected to VREF. This voltage is
referenced to analog ground and the performance of the analog peripherals is dependent
on the quality of this reference.
There are 6 ADC inputs and a pair of comparator inputs. ADC0 has a designated input pin
but ADC1 uses the same pin as VREF, invalidating its use as an ADC pin when an
external reference voltage is required. The remaining 4 ADC channels are shared with the
digital IOs DIO0, DIO1, DIO2 and DIO3. When these 4 ADC channels are selected, the
corresponding DIOs must be configured as inputs with their pull-ups disabled. Similarly,
the comparator shares pins 2 and 3 with DIO17 and DIO18, so when the comparator is
selected these pins must be configured as inputs with their pull-ups disabled. The analog
IO pins on the JN517x can have signals applied up to 0.3 V higher than VDDA. A
schematic view of the analog IO cell is shown in Figure 4. Figure 5 demonstrates a special
case, where a digital IO pin doubles as an input to analog devices. This applies to ADC2,
ADC3, ADC4, ADC5, COMP1P and COMP1M.
In reset, sleep and deep sleep, the analog peripherals are all OFF. In sleep, the
comparator may optionally be used as a wake-up source.
On platform with higher power (e.g. light Bulb, Smart Plug), unused ADC and comparator
inputs should not be left unconnected, but connected to analog ground.
V
V
DDA
ANALOG
PERIPHERAL
analog
I/O pin
SSA
aaa-017249
Fig 4. Analog IO cell
8.2.6 Digital Input Output (DIO)
When used in their primary function, all DIO pins are bidirectional and are connected to
weak internal pull-up or pull-down resistors (50 k nominal) that can be disabled. When
used in their secondary function (selected when the appropriate peripheral block is
enabled through software library calls), their direction is fixed by the function. The pull-up
or pull-down resistor is enabled or disabled independently of the function and direction;
the default state from reset is enabled.
A schematic view of the DIO cell is in Figure 5. The dotted lines through resistor RESD
represent a path that exists only on DIO0, DIO1, DIO2, DIO3, DIO17 and DIO18 which
are also inputs to the ADC (ADC2, ADC3, ADC4, ADC5) and comparator (COMP1P,
COMP1M) respectively. To use these DIO pins for their analog functions, the DIO must be
set as an input with its pull-up resistor, RPU, disabled.
JN517X
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The DIO4 and DIO5 are different from other DIOs, as these have DIO and I2C-bus mode.
In I2C-bus mode, DIO4 and DIO5 are true open-drain with “in-built” glitch filter enabled. A
schematic view of DIO4 and DIO5 cells is shown in Figure 6.
V
DDD
ADC or
COMP1 input
Pu
IE
R
R
R
ESD
PU
DN
R
PROT
(1)
I
DIOx Pin
Pd
V
SS
V
SS
O
OE
aaa-015437
(1) With x = 0, 1, 2, 3, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 17 or 18.
Fig 5. DIO (other than DIO4 and DIO5) pin equivalent schematic
V
DDD
Pu
IE
R
R
PU
R
PROT
I
DIO4/5 Pin
I_filter
DN
V
V
SS
SS
Pd
V
SS
O
OE
aaa-015438
Fig 6. DIO4 and DIO5 pin equivalent schematic
In reset, the digital peripherals are all OFF and the DIO pins are set as high-impedance
inputs. During sleep and deep sleep, the DIO pins retain both their input/output state and
output level that was set as sleep commences. If the DIO pins were enabled as inputs and
the interrupts were enabled, then these pins may be used to wake up the JN517x from
sleep or deep sleep.
JN517X
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9. Functional description
9.1 CPU
The ARM Cortex-M3 is a general purpose, 32-bit microprocessor, which offers high
performance and very low power consumption. The ARM Cortex-M3 offers many new
features, including a Thumb-2 instruction set, low interrupt latency, hardware divide,
interruptible/continuable multiple load and store instructions, automatic state save and
restore for interrupts, tightly integrated interrupt controller with wake-up interrupt
controller, and multiple core buses capable of simultaneous accesses.
Pipeline techniques are employed so that all parts of the processing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.
The ARM Cortex-M3 includes three AHB-Lite buses: the system bus, the I-CODE bus,
and the D-CODE bus. The I-CODE and D-CODE core buses are faster than the system
bus and are used similarly to TCM interfaces: one bus dedicated for instruction fetch
(I-CODE) and one bus for data access (D-CODE). The use of 2 core buses allows for
simultaneous operations if concurrent operations target different devices.
The JN517x uses a multi-layer AHB matrix to connect the ARM Cortex-M3 buses and
other bus masters to peripherals in a flexible manner that optimizes performance by
allowing peripherals that are on different slaves ports of the matrix to be accessed
simultaneously by different bus masters.
The ARM Cortex-M3 processor is described in detail in the Cortex-M3 Technical
Reference Manual that can be found on the official ARM website.
To improve power consumption a number of power-saving modes are implemented in the
JN517x, described more fully in Section 10. One of these modes is the CPU doze mode;
under software control, the processor can be shut down and on receiving an interrupt it
will wake up to service the request. Additionally, it is possible under software control, to
set the speed of the CPU to 1 MHz, 2 MHz, 4 MHz, 8 MHz, 16 MHz or 32 MHz. This
feature can be used to trade off processing power against current consumption.
9.2 Emulation and debugging
Debug and trace functions are integrated into the ARM Cortex-M3. Serial wire debug and
trace functions are supported in addition to a standard JTAG debug and parallel trace
functions. The ARM Cortex-M3 is configured to support up to 8 breakpoints and 4 watch
points.
9.3 Memory organization
This section describes the different memories found within the JN517x. The device
contains Flash, RAM, and EEPROM memory, the wireless transceiver and peripherals
registers all within the same linear address space.
JN517X
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0xFFFF_FFFF
Private Peripheral Bus
Reserved
0xE010_0000
ROM Table
0xE00F_F000
External PPB
0xE010_0000
0xE000_0000
0xE004_2000
ETM
Private peripheral bus - Internal
0xE004_1000
TPIU
0xE004_0000
Reserved
0xE000_F000
Reserved
SCS
0xE000_E000
Peripherals
Reserved
0x4001_2000
0x4001_1000
0x4001_0000
0x4000_F000
0xE000_3000
Timer ADC
PWM 6
0x4400_0000
0x4200_0000
FPB
Peripheral bit-banding alias
addressing
0xE000_2000
DWT
0xE000_1000
PWM 5
PWM 4
ITM
0xE000_0000
Reserved
0x4000_E000
0x4000_D000
PWM 3
0x4001_2000
0x4000_0000
PWM 2
Peripherals
0x4000_C000
0x4000_B000
0x4000_A000
0x4000_9000
PWM 1
SPI Slave Interface
SPI Master Interface
I2C
Reserved
0x2400_0000
0x2200_0000
SRAM bit-banding alias addressing
0x4000_8000
Timer 1
0x4000_7000
0x4000_6000
Reserved
Local SRAM (32 kB)
Reserved
Timer 0
0x2000_8000
0x2000_0000
UART 1
0x4000_5000
0x4000_4000
UART 0
GPIO
0x4000_3000
0x4000_2000
0x4000_1E00
0x4000_1C00
0x4000_1400
0x4000_0000
aaa-021505
0x0100_0FFC
0x0100_0000
Analog Peripherals
PHY Controller
AES Codec
MAC
Flash and EEPROM Registers (4 kB)
Reserved
(2)
0x0010_0000
(1)
Flash User application
0x0008_0000
0x0000_2000
0x0000_0000
Reserved
System Controller
Flash Boot code (8 kB)
(1) JN5174: 160 kB, JN5178: 256 kB and JN5179: 512 kB.
(2) JN5174: 0x000A_8000, JN5178: 0x000C_0000 and JN5179: 0x0010_0000.
Fig 7. JN517x memory map
9.3.1 Flash
The embedded Flash consists of 2 parts: an 8 kB region used for holding boot code, and a
160 kB or 256 kB or 512 kB region used for application code. The sector size of the
application code is always 32 kB, for any size of Flash memory. The guaranteed
endurance of the memory is 10,000 write cycles with typical endurance of 100,000 cycles,
while the data retention is guaranteed for at least 10 years. The boot code region is
pre-programmed by NXP on supplied parts, and contains code to handle reset, interrupts
and other events (see section Section 9.6). It also contains a Flash Programming
Interface to allow interaction with the PC-based Flash Programming Utility which allows
user code compiled using the supplied SDK to be programmed into the application space.
The memory can be erased by a single or multiple sectors and written to in units of 256
bytes, known as pagewords. For further information, refer to Flash Programmer User
Guide JN-UG-3099 on the Wireless Connectivity area of the NXP web site Ref. 2.
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9.3.2 RAM
IEEE802.15.4 Wireless Microcontroller
The JN517x devices contain 32 kB of high-speed RAM. It is primarily used to hold the
CPU Stack together with program variables and data. If necessary, the CPU can execute
code contained within the RAM (although it would normally just execute code directly from
the embedded Flash). Software can control the power supply to the RAM allowing the
contents to be maintained during a sleep period when other parts of the device are
unpowered, allowing a quicker resumption of processing once woken.
9.3.3 OTP configuration memory
The JN517x contains a quantity of One Time Programmable (OTP) memory as part of the
embedded Flash (Index Sector). This can be used to securely hold such things as a user
64-bit MAC address and a 128-bit AES security key. By default the 64-bit MAC address is
pre-programmed by NXP on supplied parts; however the pre-programmed value can be
overridden by customers providing their own MAC addresses. The user MAC address and
other data can be written to the OTP memory using the Flash programmer. Details on how
to obtain and install MAC addresses can be found in the dedicated Application Note. In
addition, 128 bits are available for customer use for storage of configuration or other
information.
For further information on how to program and use this facility, refer to Flash Programmer
User Guide JN-UG-3099 on the Wireless Connectivity area of the NXP web site Ref. 2.
9.3.4 EEPROM
The JN517x contains 4 kB of EEPROM. The guaranteed endurance of the memory is
100 000 write cycles with typical endurance of 1 million cycles, while the data retention is
guaranteed for at least 10 years. EEPROM endurance can be extended using the
Persistent Data Manager software which wear levels the EEPROM as data is written to it.
This is supplied in the NXP ZigBee SDK.
This non-volatile memory is primarily used to hold persistent data generated from such
things as the Network Stack software component (for example network topology, routing
tables). As the EEPROM holds its contents through sleep and reset events, this means
more stable operation and faster recovery is possible after outages.
The memory can be erased by a single or multiple pages of 64 bytes. It can be written to
in single or multiple bytes up to 64 bytes. For further details, refer to the JN517x
Integrated Peripherals API User Guide JN-UG-3118 on the Wireless Connectivity area of
the NXP web site Ref. 2.
9.3.5 External memory
An optional external serial non-volatile memory (for instance Flash or EEPROM) with a
SPI-bus interface may be used to provide additional storage for program code, such as a
new code image or further data for the device when external power is removed. The
memory can be connected to the SPI-bus master interface using select line SPISEL0 (see
Figure 8 for details).
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serial
memory
SPISEL0
SPIMISO
SPIMOSI
SPICLK
SS
SDO
SDI
JN517x
CLK
aaa-021453
Fig 8. Connecting external serial memory
The contents of the external serial memory may be encrypted. The AES security
processor combined with a user programmable 128-bit encryption key is used to encrypt
the contents of the external memory. The encryption key is stored in the Flash memory
index section. When bootloading program code from external serial memory, the JN517x
automatically accesses the encryption key to execute the decryption process, which is
transparent to the user, user program code does not need to handle any part of the
decryption process; it is transparent. For more details, including the how the program
code encrypts data for the external memory, refer to Application Note Boot loader
Operation JN-AN-1003 on the Wireless Connectivity area of the NXP web site Ref. 2.
Remark: SPI-bus Flash can not be used in the same time than external 32 kHz crystal.
9.3.6 Peripherals
All peripherals have their registers mapped into the memory space. Applications have
access to the peripherals through the software libraries that present a high-level view of
the peripheral's functions through a series of dedicated software routines. These routines
provide both a tested method for using the peripherals and allow bug-free application
code to be developed more rapidly. For details, see JN517x Integrated Peripherals API
User Guide JN-UG-3118 on the Wireless Connectivity area of the NXP web site Ref. 2.
9.4 System clocks
Two system clocks are used to drive the on-chip subsystems of the JN517x. The wake-up
timers are driven from a low frequency clock (notionally 32 kHz). All other subsystems
(transceiver, processor, memory and digital and analog peripherals) are driven by a
high-speed clock (notionally 32 MHz), or a divided-down version of it.
The high-speed clock is either generated by the accurate crystal-controlled oscillator
(32 MHz) or the less accurate high-speed RC oscillator (27 MHz to 32 MHz calibrated).
The low-speed clock is either generated by the less accurate RC oscillator (centered on
32 kHz) or can be supplied externally.
9.4.1 High-speed (32 MHz) system clock
The selected high-speed system clock is used directly by the radio subsystem, whereas a
divided-by-two version is used by the remainder of the transceiver and the digital and
analog peripherals. The direct or divided down version of the clock is used to drive the
processor and memories (32 MHz, 16 MHz, 8 MHz, 4 MHz, 2 MHz or 1 MHz).
JN517X
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Fig 9. System and CPU clocks
Crystal oscillators are generally slow to start. Hence to provide a fast start-up following a
sleep cycle or reset, the fast RC oscillator is always used as the initial source for the
high-speed system clock. The oscillator starts very quickly and will run at 25 MHz to
32 MHz (uncalibrated) or 32 MHz 5 % (calibrated). Although this means that the system
clock will be running at an undefined frequency (slightly slower or faster than nominal),
this does not prevent the CPU and memory subsystems operating normally, so the
program code can execute. However, it is not possible to use the radio or UARTs, as even
after calibration (initiated by the user software calling an API function) there is still a 5 %
tolerance in the clock rate over voltage and temperature. Other digital peripherals can be
used (eg SPI-bus master/slave), but care must be taken if using Timers due to the clock
frequency inaccuracy.
Further details of the high-speed RC oscillator can be found in Section 14.3.9
On wake-up from sleep, the JN517x uses the fast RC oscillator. It can then either:
• Automatically switch over to use the 32 MHz clock source when it has started up
• Continue to use the fast RC oscillator until software triggers the switch-over to the
32 MHz clock source, for example when the radio is required
• Continue to use the RC oscillator until the device goes back into one of the sleep
modes
The use of the fast RC Oscillator at wake-up means that there is no need to wait for the
32 MHz crystal oscillator to stabilize.
9.4.1.1 32 MHz crystal oscillator
The JN517x contains the necessary on chip components to build a 32 MHz reference
oscillator with the addition of an external crystal resonator and 2 tuning capacitors. The
schematics of these components are shown in Figure 10. The 2 capacitors, C1 and C2,
should typically be 12 pF and use a COG dielectric. Due to the small size of these
capacitors, it is important to keep the traces to the external components as short as
possible. The on-chip transconductance amplifier is compensated for temperature
variation, and is self-biasing by means of the internal resistor R1. This oscillator provides
the frequency reference for the radio and therefore the reference PCB layout and BOM
must be carefully followed. Refer to Section 14.3.11 for development support with the
crystal oscillator circuit. The oscillator includes a function which flags when the amplitude
of oscillation has reached a satisfactory level for full operation, and this is checked before
the source of the high-speed system clock is changed to the 32 MHz crystal oscillator.
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JN517x
R1
XTAL_IN
XTAL_OUT
C1
C2
aaa-021454
Fig 10. 32 MHz crystal oscillator connections
For operation over the extended temperature range, 85 C to 125 C, special care is
required; this is because the temperature characteristics of crystal resonators are
generally in excess of 40 ppm frequency tolerance defined by the IEEE802.15.4
standard. The oscillator cell contains additional circuitry to compensate for the poor
performance of the crystal resonators above 100 C. Full details, including the software
API function, can be found in the Temperature Dependent Operating Guidelines
JN-AN-1186 on the Wireless Connectivity area of the NXP web site Ref. 2.
9.4.1.2 High-speed RC oscillator
An on-chip high-speed RC oscillator is provided in addition to the 32 MHz crystal oscillator
for 2 purposes, to allow a fast start-up from reset or sleep and to provide a lower current
alternative to the crystal oscillator for non-timing critical applications. By default the
oscillator will run at 27 MHz typically with a wide tolerance. It can be calibrated, using a
software API function, which will result in a nominal frequency of 32 MHz with a 1.6 %
tolerance at 3 V and 25 C. However, it should be noted that over the full operating range
of voltage and temperature this will increase to 5%. The calibration information is
retained through speed cycles and when the oscillator is disabled, so typically the
calibration function only needs to be called once. No external components are required for
this oscillator. The electrical specification of the oscillator can be found in Section 14.3.9.
9.4.2 Low-speed (32 kHz) system clock
The 32 kHz system clock is used for timing the length of a sleep period (see Section 10.
The clock can be selected from one of 2 sources through the application software:
• 32 kHz RC oscillator
• 32 kHz external clock
• 32 kHz crystal oscillator
Upon a chip reset or power-up, the JN517x defaults to using the internal 32 kHz RC
oscillator. If another clock source is selected, then, it will remain in use for all 32 kHz
timing until a chip reset is performed.
9.4.2.1 32 kHz RC oscillator
The internal 32 kHz RC oscillator requires no external components. The internal timing
components of the oscillator have a wide tolerance due to manufacturing process
variation and so the oscillator runs nominally at 32 kHz 20.7 %/+52.6 %. To make this
useful as a timing source for accurate wake-up from sleep, a frequency calibration factor
derived from the more accurate 16 MHz peripheral system clock may be applied. The
JN517X
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calibration factor is derived through software, details can be found in Section 9.10.3.1.
Software must check that the 32 kHz RC oscillator is running before using it. The oscillator
has a default current consumption of around 0.5 A. Optionally, this can be reduced to
0.375 A, however, the calibrated accuracy and temperature coefficient will be worse as a
consequence. For detailed electrical specifications, see Section 14.3.9.
9.4.2.2 32 kHz External clock
An externally supplied 32 kHz reference clock on the 32KIN input (DIO7) may be provided
to the JN517x. This would allow the 32 kHz system clock to be sourced from a very stable
external oscillator module, allowing more accurate sleep cycle timings compared to the
internal RC oscillator. SPI-bus Flash can not be used in the same time than external
32 kHz crystal.
9.4.2.3 32 kHz crystal oscillator
In order to obtain more accurate sleep periods, the JN517x contains the necessary
on-chip components to build a 32 kHz oscillator with the addition of an external
32.768 kHz crystal and two tuning capacitors. The crystal should be connected between
32KXTALIN and 32KXTALOUT (DIO8 and DIO7), with two equal capacitors to ground,
one on each pin. Due to the small size of the capacitors, it is important to keep the traces
to the external components as short as possible.
The electrical specification of the oscillator can be found in Section 14.3.10. The oscillator
cell is flexible and can operate with a range of commonly available 32.768 kHz crystals
with load capacitances from 6 pF to 12.5 pF. However, the maximum ESR of the crystal
and the supply current are both functions of the actual crystal used.
JN517x
32KXTALIN
32KXTALOUT
aaa-023993
Fig 11. 32 kHz crystal oscillator connections
9.5 Reset
A system reset initializes the device to a pre-defined state and forces the CPU to start
program execution from the reset vector. The reset process that the JN517x goes through
is as follows.
When power is first applied (on VDDA and VDDD supply pins) or when the external reset is
released, the high-speed RC oscillator and 32 MHz crystal oscillator are activated. After a
short wait period (approximately 13 s) while the high-speed RC starts up, and so long as
the supply voltage satisfies the default SVM threshold (2.0 V + 0.045 V hysteresis), the
internal 1.8 V regulators are turned on to power the processor and peripheral logic. The
regulators are allowed to stabilize (about 15 s) followed by a further wait (approximately
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150 s) to allow the Flash and EEPROM bandgaps to stabilize and allow their
initialization, including reading the user SVM threshold from the Flash. This is applied to
the SVM, and after a brief pause (approximately 2.5 s) the SVM is checked again. If the
supply is above the new SVM threshold, the CPU and peripheral logic is released from
reset and the CPU starts to run code beginning at the reset vector. This runs the
bootloader code contained within the Flash, which looks for a valid application to run, first
from the internal Flash and then from any connected external serial memory over the
SPI-bus master interface. Once found, required variables are initialized in RAM before the
application is called at its AppColdStart entry point. For more details on the bootloader,
refer to Application Note Boot loader Operation JN-AN-1003 on the Wireless Connectivity
area of the NXP web site Ref. 2.
The JN517x has 5 sources of reset:
• Internal Power-On Reset/Brown-Out Reset (BOR)
• External reset
• Software reset
• Watchdog timer
• Supply voltage detect
Remark: When the device exits a reset condition, device operating parameters (voltage,
frequency, temperature, etc.) must be met to ensure operation. If these conditions are not
met, then the device must be held in reset until the operating conditions are met
(see Section 14.3.1).
9.5.1 Internal Power-On Reset/Brown-out Reset (BOR)
For most applications, the Internal POR is capable of generating the required reset signal.
When power is applied to the device, the power-on reset circuit monitors the rise of the
VDD (VDDA and VDDD) supply. When the VDD reaches the specified threshold, the reset
signal is generated. This signal is held internally until the power supply and oscillator
stabilization time has elapsed, when the internal reset signal is then removed and the
CPU is allowed to run.
The BOR circuit has the ability to reject spikes on the VDD rail to avoid false triggering of
the reset module. Typically for a negative going square pulse of duration 1s, the voltage
must fall to 1.2 V before a reset is generated. Similarly for a triangular wave pulse of 10s
width, the voltage must fall to 1.3 V before causing a reset. The exact characteristics are
complex and these are only examples. See Figure 47 for more details on BOR and SVM
characteristics.
V
DD
internal RESET
aaa-017251
Fig 12. Internal Power-On Reset
JN517X
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When the supply drops below the POR ‘falling’ threshold, it will retrigger the reset. On
platform with higher power (e.g. light bulb, smart plug) it is recommended to use this
external circuit to avoid unexpected reset due to spurs.
V
DD
R1
18 kΩ
RESET_N
JN517x
C1
470 nF
aaa-021455
Fig 13. External reset generation
9.5.2 External reset
An external reset is generated by a low level on the RESET_N pin. Reset pulses longer
than the minimum pulse width will generate a reset during active or sleep modes. Shorter
pulses are not guaranteed to generate a reset. The JN517x is held in reset while the
RESET_N pin is low. When the applied signal reaches the reset threshold voltage (Vrst) on
its positive edge, the internal reset process starts.
The JN517x has an internal pull-up resistor (see Table 19) connect to the RESET_N pin.
The pin is an input for an external reset only. By holding the RESET_N pin low, the
JN517x is held in reset, resulting in a typical current of 6A.
RESET_N pin
reset
internal reset
aaa-017252
Fig 14. External reset
9.5.3 Software reset
A system reset can be triggered at any time through software control, causing a full chip
reset and invalidating the RAM contents. For example, this can be executed within a
user’s application upon detection of a system failure.
9.5.4 Supply Voltage Monitor
An internal SVM is used to monitor the supply voltage to the JN517x; this can be used
while the device is awake or is in CPU doze mode. Dips in the supply voltage below a
variable threshold can be detected and can be used to cause the JN517x to perform a
chip reset. Equally, dips in the supply voltage can be detected and used to cause an
interrupt to the processor, when the voltage either drops below the threshold or rises
above it.
JN517X
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The supply voltage detect is enabled by default from power-up and can extend the reset
during power-up. This will keep the CPU in reset until the voltage exceeds the SVM
threshold voltage. The threshold voltage is configurable to 1.95 V, 2.0 V, 2.1 V, 2.2 V,
2.3 V, 2.4 V, 2.7 V and 3.0 V and is controllable by software. From power-up, the
threshold is set by a setting within the Flash and the default chip configuration is for the
2.0 V threshold. It is expected that the threshold is set to the minimum needed by the
system. See Figure 47 for more details on BOR and SVM characteristics.
9.5.5 Watchdog timer
A watchdog timer is provided to guard against software lockups. It operates by counting
cycles of the high-speed RC system clock. A pre-scaler is provided to allow the expiry
period to be set between typically 8 ms and 16.4 s (dependent on high-speed RC
accuracy: +30 %, 15 %). Failure to restart the watchdog timer within the pre-configured
timer period will cause a chip reset to be performed. A status bit is set if the watchdog was
triggered so that the software can differentiate watchdog initiated resets from other resets,
and can perform any required recovery once it restarts. Optionally, the watchdog can
cause an exception rather than a reset, this preserves the state of the memory and is
useful for debugging.
After power-up, reset, start from deep sleep or start from sleep, the watchdog is always
enabled with the largest time-out period and will commence counting as if it had just been
restarted. Under software control, the watchdog can be disabled. If it is enabled, the user
must regularly restart the watchdog timer to stop it from expiring and causing a reset. The
watchdog runs continuously, even during doze, however the watchdog does not operate
during sleep or deep sleep, or when the hardware debugger has taken control of the CPU.
It will recommence automatically if enabled once the debugger unstalls the CPU.
9.6 Nested Vector Interrupt controller (NVIC)
The NVIC is an integral part of the Cortex-M3. The tight coupling to the CPU allows for low
interrupt latency and efficient processing of late-arriving interrupts. The main features of
the interrupt controller are:
• Controls the system exceptions and peripheral interrupts
• Supports 20 vectored interrupts
• 16 programmable interrupt priority levels
Interrupts can be used to wake the JN517x from sleep or deep sleep. The peripherals,
baseband controller, security coprocessor and NVIC are powered down during sleep or
deep sleep but the DIO interrupts and optionally the pulse counters, wake-up timers and
analog comparator interrupts remain powered to bring the JN517x out of sleep.
The Cortex-M3 incorporates a mechanism that allows remapping the interrupt vector table
to alternate locations in the memory map. This is controlled via the Vector Table Offset
Register (VTOR) contained in the Cortex-M3. The NVIC is described in detail in the
Cortex-M3 Technical Reference Manual that can be found on official ARM website.
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9.6.1 Interrupts sources
Each peripheral device has one interrupt line connected to the NVIC but may have several
interrupt flags. Table 3 lists the interrupt sources for each peripheral function. Exception
numbers relate to where entries are stored in the exception vector table. Interrupt
numbers are used in some other contexts, such as software interrupts.
Table 3.
Interrupt sources
Interrupt ID
Exception
number
Vector offset (h) Function
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
0x40
0x44
0x48
0x4C
0x50
0x54
0x58
0x5C
0x60
0x64
0x68
0x6C
0x70
0x74
0x78
0x7C
0x80
0x84
0x88
0x8C
PWM1
1
PWM2
2
PWM3
3
PWM4
4
PWM5
5
PWM6
6
system controller
MAC
7
8
AES codec
PHY controller
UART0
9
10
11
12
13
14
15
16
17
18
19
UART1
SPI-bus slave
SPI-bus master
I2C-bus master/slave
Timer0
Timer1
timer ADC
analog peripheral
watchdog interrupt
9.7 Wireless transceiver
The wireless transceiver comprises a 2.45 GHz radio, modem, a baseband processor, a
security coprocessor and PHY controller. These blocks, with protocol software provided
as a library, implement an IEEE802.15.4 standards-based wireless transceiver that
transmits and receives data OTA in the unlicensed 2.4 GHz band.
9.7.1 Radio
Figure 15 shows the single-ended radio architecture.
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RADIO
LNA
LIM1
LIM2
LIM3
LIM4
D-TYPE
CALIBRATION
SWITCH
REFERENCE
AND BIAS
ADC
PA
SIGMA
DELTA
SYNTH
aaa-023992
Fig 15. Radio architecture
The radio comprises a low-IF receive path and a direct modulation transmit path, which
converge at the TX/RX switch. The switch connects to the external single ended matching
network, which consists of two inductors and a capacitor; this arrangement creates a 50
port and removes the need for a balun. A 50 single-ended antenna can be connected
directly to this port.
The 32 MHz crystal oscillator feeds a divider, which provides the frequency synthesizer
with a reference frequency. The synthesizer contains programmable feedback dividers,
phase detector, charge pump and internal Voltage Controlled Oscillator (VCO). The VCO
has no external components, and includes calibration circuitry to compensate for
differences in internal component values due to process and temperature variations. The
VCO is controlled by a Phase-Locked Loop (PLL) that has an internal loop filter. A
programmable charge pump is also used to tune the loop characteristic.
The receiver chain starts with the low noise amplifier/mixer combination whose outputs
are passed to a low pass filter, which provides the channel definition. The signal is then
passed to a series of amplifier blocks forming a limiting strip. The signal is converted to a
digital signal before being passed to the Modem. The gain control for the RX path is
derived in the Automatic Gain Control (AGC) block within the Modem, which samples the
signal level at various points down the RX chain. To improve the performance and reduce
current consumption, automatic calibration is applied to various blocks in the RX path.
In the transmit direction, the digital stream from the Modem is passed to a digital
sigma-delta modulator which controls the feedback dividers in the synthesizer (dual point
modulation). The VCO frequency now tracks the applied modulation. The 2.4 GHz signal
from the VCO is then passed to the RF Power Amplifier (PA), whose power control can be
selected from one of three settings. The output of the PA drives the antenna via the RX/TX
switch
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The JN517x radio when enabled is automatically calibrated for optimum performance. In
operating environments with a significant variation in temperature (e.g. greater than
20 C) due to diurnal or ambient temperature variation, it is recommended to recalibrate
the radio to maintain performance. Recalibration is only required on devices that never
sleep. Devices which sleep or deep sleep are automatically recalibrated when they wake.
A dedicated Application Note, Temperature Dependent Operating Guidelines JN-AN-1186
on the Wireless Connectivity area of the NXP web site Ref. 2, describes this in detail and
includes a software API function which can be used to test the temperature using the
on-chip temperature sensor and trigger a recalibration if there has been a significant
temperature change since the previous calibration.
9.7.1.1 Radio external components
In order to realize the full performance of the radio, the reference PCB layout and BOM
must be followed very closely (see Section 15.1).
The radio is powered from a number of internal 1.8 V regulators fed from the analog
supply VDDA, in order to provide good noise isolation between the digital logic of the
JN517x and the analog blocks. These regulators are also controlled by the baseband
controller and protocol software to minimize power consumption. Decoupling for internal
regulators is required as described in Section 8.2.1.
For single-ended antennas or connectors, a balun is not required, however a matching
network is needed.
The RF matching network requires 3 external components and the IBIAS pin requires one
external component as shown in Figure 55. These components are critical and should be
placed close to the JN517x pins and analog ground as defined in Table 34. Specifically,
the output of the network comprising L2, C1 and L1 is designed to present an accurate
match to a 50 resistive network as well as provide a DC path to the final output stage or
antenna. Users wishing to match to other active devices such as amplifiers should design
their networks to match to 50 at the output of L1.
IBIAS
R1
43 kꢀ
C3
100 nF
C4
47 pF
L2
3 nH
To coaxial socket
C2
1.8 pF
L1
or integrated antenna
4.3 nH
50 ohms line
C1
1.8 pF
aaa-018996
Fig 16. External radio components
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9.7.1.2 Antenna diversity
Support is provided for antenna diversity, which is a technique that maximizes the
performance of an antenna system. It allows the radio to switch between two antennas
that have very low correlation between their received signals. Typically, this is achieved by
spacing two antennae around 0.25 wavelengths apart or by using 2 orthogonal
polarizations. So, if a packet is transmitted and no acknowledgement is received, the
radio system can switch to the other antenna for the retry, with a different probability of
success.
Additionally antenna diversity can be enabled while in receive mode waiting for a packet.
The JN517x measures the received energy in the relevant radio channel every 40 s and
the measured energy level is compared with a pre-set energy threshold, which can be set
by the application program. The JN517x device will automatically switch the antenna if the
measurement is below this threshold, except if waiting for an acknowledgement from a
previous transmission or in the process of receiving a packet, where it will wait until this
has finished. Also, it will not switch if a preamble symbol having a signal quality above a
minimum specified threshold has not been detected in the last 40 s.
Both modes can be used at once and use the same ADO (SELA) and ADE (SELB)
outputs to control the external switch.
The JN517x provides an output (ADO) on one of DIO0, DIO4 and DO1 that is asserted on
odd-numbered retries and optionally its complement (ADE) on one of DIO1, DIO5 and
DO0, that can be used to control an antenna switch; this enables antenna diversity to be
implemented easily (see Figure 17 and Figure 18).
antenna A
A
antenna B
B
SEL
ADO
ADE
RF switch: single-pole,
double-throw (SPDT)
SELB
COM
device RF port
aaa-015444
Fig 17. Simple antenna diversity implementation using external RF switch
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ADE
ADO
TX active
RX active
st
nd
st
1
TX-RX cycle
2
TX-RX cycle (1 retry)
aaa-015445
Fig 18. Antenna diversity ADO signal for TX with acknowledgement
If two DIO pins cannot be spared, one of the signals (ADE or ADO) from the JN517x can
be used and its complement can be generated using an inverter on the PCB.
9.7.2 Modem
The modem performs all the necessary modulation and spreading functions required for
digital transmission and reception of data at 250 kbits/s in the 2.4 GHz radio frequency
band in compliance with the IEEE802.15.4 standard.
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Fig 19. Modem architecture
Features provided to support network channel selection algorithms include Energy
Detection (ED), Link Quality Indication (LQI) and fully programmable Clear Channel
Assessment (CCA).
The modem provides a digital Receive Signal Strength Indication (RSSI) that facilitates
the implementation of the IEEE802.15.4 ED and LQI functions.
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The ED and LQI are both related to received power in the same way, as shown in
Figure 20. LQI is associated with a received packet, whereas ED is an indication of signal
power on-air at a particular moment.
The CCA capability of the modem supports all modes of operation defined in the
IEEE802.15.4 standard, namely Energy above ED threshold, Carrier Sense and Carrier
Sense and/or energy above ED threshold.
aaa-023522
260
240
220
200
180
160
140
120
100
80
60
40
20
0
-105
-85
-65
-45
-25
-5
15
input power (dBm)
Fig 20. Energy detect value versus receive power level
9.7.3 Baseband processor
The baseband processor provides all time-critical functions of the IEEE802.15.4 MAC
layer. Dedicated hardware guarantees air interface timing is precise. The MAC layer
hardware/software partitioning enables software to implement the sequencing of events
required by the protocol and to schedule timed events with millisecond resolution and the
hardware to implement specific events with microsecond timing resolution. The protocol
software layer performs the higher-layer aspects of the protocol, sending management
and data messages between End Device and Co-ordinator nodes, using the services
provided by the baseband processor.
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IEEE802.15.4 Wireless Microcontroller
7;
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Fig 21. Baseband processor
9.7.3.1 Transmit
A transmission is performed by software writing the data to be transferred into the TX
frame buffer in RAM, together with parameters such as the destination address and the
number of retries allowed, as well as programming one of the protocol timers to indicate
the time at which the frame is to be sent. This time will be determined by the software
tracking the higher-layer aspects of the protocol such as superframe timing and slot
boundaries. Once the packet is prepared and the protocol timer set, the supervisor block
controls the transmission. When the scheduled time arrives, the supervisor controls the
sequencing of the radio and modem to perform the type of transmission required, fetching
the packet data directly from RAM. It can perform all the algorithms required by
IEEE802.15.4 such as CSMA/CA without processor intervention, including retries and
random back-offs.
When the transmission begins, the header of the frame is constructed from the
parameters programmed by the software and sent with the frame data through the
serializer to the modem. At the same time, the radio is prepared for transmission. During
the passage of the bitstream to the modem, it passes through a CRC checksum generator
that calculates the checksum on-the-fly, and appends it to the end of the frame.
9.7.3.2 Reception
During reception, the radio is set to receive on a particular channel. On receipt of data
from the modem, the frame is directed into the receive frame buffer in RAM where both
header and frame data can be read by the protocol software. An interrupt may be
provided on receipt of the frame. An additional interrupt may be provided after the
transmission of an acknowledgement frame in response to the received frame, if an
acknowledgement frame has been requested and the auto acknowledge mechanism is
enabled, see Section 9.7.3.3. As the frame data is being received from the modem, it is
passed through a checksum generator; at the end of the reception the checksum result is
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compared with the checksum at the end of the message to ensure that the data has been
received correctly. During reception, the modem determines the Link Quality, which is
made available at the end of the reception as part of the requirements of IEEE802.15.4.
9.7.3.3 Auto acknowledge
Part of the protocol allows for transmitted frames to be acknowledged by the destination
sending an acknowledge packet within a very short window after the transmitted frame
has been received. The JN517x baseband processor can automatically construct and
send the acknowledgement packet without processor intervention and hence avoid the
protocol software being involved in time-critical processing within the acknowledge
sequence. The JN517x baseband processor can also request an acknowledge for
packets being transmitted and handle the reception of acknowledged packets without
processor intervention.
9.7.3.4 Security
The transmission and reception of secured frames using the AES algorithm is handled by
the security coprocessor and the stack software. The application software must provide
the appropriate encrypt/decrypt keys for the transmission or reception. On transmission,
the key can be programmed at the same time as the rest of the frame data and set-up
information.
9.7.4 Security coprocessor
The security coprocessor is available to the application software to perform
encryption/decryption operations. A hardware implementation of the encryption engine
significantly speeds up the processing of the encrypted packets over a pure software
implementation. The AES library for the JN517x provides operations that utilize the
encryption engine in the device and allow the contents of memory buffers to be
transformed. Information such as the type of security operation to be performed and the
encrypt/decrypt key to be used must also be provided.
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Fig 22. Security coprocessor architecture
9.8 Digital Input Output
There are 18 Digital IO (DIO) pins which when used as general-purpose pins can be
configured as either an input or an output, with each having a selectable internal pull-up or
pull-down resistor. In addition, there are 2 Digital Output (DO) pins.
Most DIO pins are shared with the digital and analog peripherals of the device. When a
peripheral is enabled, it takes control over the device pins allocated to it. However, note
that most peripherals have two alternative pin allocations to alleviate clashes between
uses, and many peripherals can disable the use of specific pins if not required. Refer to
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Section 8.2 and the individual peripheral descriptions for full details of the available pinout
arrangements.
Following a reset (and while the RESET_N input is held low), all peripherals are forced off
and the DIO pins are configured as inputs with their default internal pull-up or pull-down
resistor connected. When a peripheral is not enabled, the DIO pins associated with it can
be used as digital inputs or outputs. Each pin can be controlled individually by setting the
direction and then reading or writing to the pin.
The individual pull-up or pull-down resistors, RPU or RDN, can also be enabled or disabled
as needed and the setting is held through sleep or deep sleep cycles. The pull-up or
pull-down resistors are generally configured once after reset depending on the external
components and functionality. For instance, outputs should generally have the pull-up or
pull-down resistor disconnected. An input that is always driven should also have the
pull-up or pull-down resistor disconnected.
When configured as an input each pin can be used to generate an interrupt upon a
change of state (selectable transition either from low to high or high to low); the interrupt
can be enabled or disabled. When the device is sleeping, these interrupts become events
that can be used to wake up the device. Equally the status of the interrupt may be read.
See Section 10 for further details on sleep and wake-up.
The state of all DIO pins can be read, irrespective of whether the DIO is configured as an
input or an output.
Throughout a sleep or deep sleep cycle, the direction of the DIO, and the state of the
outputs, is held. This is based on the contents of the GPIO Data/Direction registers and
the effect of any enabled peripherals at the point of entering sleep or deep sleep.
Following a wake-up these directions and output values are maintained under control of
the GPIO data/direction registers. Any peripherals enabled before the sleep or deep sleep
cycle are not automatically re-enabled, this must be done through software after the
wake-up.
For example, if DIO0 is configured to be SPISEL0 then it becomes an output. The output
value is controlled by the SPI-bus functional block. If the device then enters a sleep or
deep sleep cycle, the DIO will remain an output and hold the value being output when
entering sleep or deep sleep. After wake-up, the DIO will still be an output with the same
value but controlled from the GPIO Data/Direction registers. It can be altered with the
software functions that adjust the DIO, or the application may reconfigure it to be
SPISEL0.
Unused DIO pins are recommended to be set as inputs with the pull-up enabled.
2 DIO pins can optionally be used to provide control signals for RF circuitry (e.g. switches
and PA) in high-power range extenders. DIO1/DIO3/RFTX is asserted when the radio is in
the transmit state and similarly, DIO0/DIO2/RFRX is asserted when the radio is in the
receiver state.
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9.9 Serial Peripheral Interface-bus (SPI-bus)
9.9.1 SPI-bus master
The SPI-bus allows high-speed synchronous data transfer between the JN517x and
peripheral devices. The JN517x operates as a master on the SPI-bus and all other
devices connected to the SPI-bus are expected to be slave devices under the control of
the JN517x CPU. The SPI-bus includes the following features:
• Full-duplex, three-wire synchronous data transfer
• Programmable bit rates (up to 16 Mbit/s)
• Programmable transaction size up to 32-bits
• Standard SPI-bus modes 0, 1, 2 and 3
• Manual or automatic slave select generation (up to 2 simultaneous slaves)
• Supports external data in little endian as well as big endian format
• Maskable “transaction complete” interrupt
• LSB First or MSB First Data Transfer
• Supports delayed read edges
SPICLK
SPI BUS
SPIMISO
SPIMOSI
CYCLE
CLOCK
DIVIDER
16 MHz
CONTROLLER
DATA BUFFER
data
DIV
CLOCK EDGE
SELECT
CHAR_LEN
LSB
SELECT
LATCH
SPISEL0/1/2
aaa-015447
Fig 23. SPI-bus block diagram
The SPI-bus employs a simple shift-register data transfer scheme. Data is clocked out of
and into the active devices in a first-in, first-out fashion allowing SPI-bus devices to
transmit and receive data simultaneously. Master-Out-Slave-In or Master-In-Slave-Out
data transfer is relative to the clock signal SPICLK generated by the JN517x.
The JN517x provides 3 slave selects, SPISEL0 to SPISEL2 to allow 2 simultaneous
SPI-bus peripherals on the bus. The Table 4 details which DIO is used for the SPISEL
signals depending upon the software configuration.
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Table 4.
SPI-bus master I/O
Signal
DIO assignment
Standard pins
Alternative pins
DIO0, DIO17
-
SPISEL0
SPISEL1
SPISEL2
SPICLK
DIO6
DIO15
-
DIO7
DO0
DO1
DIO7
DIO11
SPIMISO
SPIMOSI
DIO18
DIO15
The interface can transfer from 1 bit to 32 bits without software intervention and can keep
the slave select lines asserted between transfers when required, to enable longer
transfers to be performed.
When the device reset is active, all the SPI-bus master pins are configured as inputs with
their pull-up resistors active. The pins stay in this state until the SPI-bus master block is
enabled, or the pins are configured for some other use.
SLAVE 0
SLAVE 1
SLAVE 2
FLASH/
EEPROM
MEMORY
SS
SS
SS
USER
DEFINED
USER
DEFINED
SI
C
SO
SI
C
SO
SI
C
SO
SPIMOSI
SPICLK
JN517x
SPIMISO
aaa-021460
Fig 24. Typical JN517x SPI-bus peripheral connection
The data transfer rate on the SPI-bus is determined by the SPICLK signal. The JN517x
supports transfers at data rates from 16 MHz to 125 kHz selected by a clock divider. Both
SPICLK clock phase and polarity are configurable. The clock phase determines which
edge of SPICLK is used by the JN517x to present new data on the SPIMOSI line; the
opposite edge will be used to read data from the SPIMISO line. The interface should be
configured appropriately for the SPI-bus slave being accessed.
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Table 5.
SPI-bus configurations
SPICLK
Mode
Description
Polarity Phase
(CPOL)
(CPHA)
0
0
0
1
2
3
SPICLK is low when idle - the first edge is positive. Valid data is
output on SPIMOSI before the first clock and changes every
negative edge. SPIMISO is sampled every positive edge.
0
1
1
1
0
1
SPICLK is low when idle – the first edge is positive. Valid data is
output on SPIMOSI every positive edge. SPIMISO is sampled
every negative edge.
SPICLK is high when idle – the first edge is negative. Valid data
is output on SPIMOSI before the first clock edge and is changed
every positive edge. SPIMISO is sampled every negative edge.
SPICLK is high when idle – the first edge is negative. Valid data
is output on SPIMOSI every negative edge. SPIMISO is
sampled every positive edge.
If more than one SPISEL line is to be used in a system, they must be used in numerical
order starting from SPISEL0. A SPISEL line can be automatically de-asserted between
transactions if required, or it may stay asserted over a number of transactions. For
devices such as memories where a large amount of data can be received by the master
by continually providing SPICLK transitions, the ability for the select line to stay asserted
is an advantage since it keeps the slave enabled over the whole of the transfer.
A transaction commences with the SPI-bus being set to the correct configuration, and
then the slave device is selected. Upon commencement of transmission, (1 to 32 bits)
data is placed in the FIFO data buffer and clocked out, at the same time generating the
corresponding SPICLK transitions. Since the transfer is full-duplex, the same number of
data bits is being received from the slave as it transmits. The data that is received during
this transmission can be read (1 to 32 bits). If the master simply needs to provide a
number of SPICLK transitions to allow data to be sent from a slave, it should perform
transmit using dummy data. An interrupt can be generated when the transaction has
completed or alternatively the interface can be polled.
If a slave device wishes to signal the JN517x indicating that it has data to provide, it may
be connected to one of the DIO pins that can be enabled as an interrupt.
Figure 25 shows a complex SPI-bus transfer, reading data from a Flash device that can
be achieved using the SPI-bus master interface. The slave select line must stay low for
many separate SPI-bus accesses, and therefore manual slave select mode must be used.
The required slave select can then be asserted (active low) at the start of the transfer. A
sequence of 8-bit and 32-bit transfers can be used to issue the command and address to
the Flash device and then to read data back. Finally, the slave select can be deselected to
end the transaction.
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IEEE802.15.4 Wireless Microcontroller
instruction transaction
(1)
SPISELx
0
1
2
3
4
5
6
7
8
9
10
28
29
30
31
SPICLK
Instruction (0x03)
24-bit address
3
23
MSB
22
21
2
1
0
SPIMOSI
SPIMISO
read data bytes transaction(s) 1-N
(1)
SPISELx
0
1
2
3
4
5
6
7
8
9
10
8N-1
SPICLK
value unused by peripherals
SPIMOSI
7
6
5
4
3
2
1
0
7
6
5
3
2
1
0
SPIMISO
MSB
MSB
LSB
byte 1
byte 2
byte N
aaa-015449
(1) With x = 0 or 1 or 2.
Fig 25. Example SPI-bus waveforms: reading from Flash device using mode 0
9.9.2 SPI-bus slave
The SPI-bus slave interface allows high-speed synchronous data transfer between the
JN517x and a peripheral device. The JN517x operates as a slave on the SPI-bus and an
external device, connected to the SPI-bus operates as the master. The pins are different
from the SPI-bus master interface and are shown in the Table 6.
Table 6.
Signal
SPI-bus slave I/O
DIO assignment
Standard pins
DIO6
Alternative pins
DIO18
SPISCLK
SPISMISO
SPISMOSI
SPISSEL
DO1
DIO17
DIO11
DIO14
DIO7
DIO15
The SPI-bus employs a simple shift-register data transfer scheme, with SPISSEL acting
as the active low select control. Data is clocked out of and into the active devices in a
first-in, first-out fashion allowing SPI-bus devices to transmit and receive data
simultaneously. Master-Out-Slave-In or Master-In-Slave-Out data transfer is relative to the
clock signal SPISCLK generated by the external master.
The SPI-bus slave includes the following features:
• Full-duplex synchronous data transfer
• Supports external clock up to 8 MHz
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• Supports 8-bit transfers (MSB or LSB first configurable), with SPISSEL deselected
between each transfer
• Internal FIFO up to 255 bytes for transmit and receive
• Standard SPI-bus mode 0, data is sampled on positive clock edge
• Maskable interrupts for receive FIFO not empty, transmit FIFO empty, receive FIFO fill
level above threshold, transmit FIFO below threshold, transmit FIFO overflow, receive
FIFO underflow, transmit FIFO underflow, receive time-out
• Programmable receive time-out period allows an interrupt to be generated to prompt
the receive FIFO to be read if no further data arrives within the time-out period
9.10 Timers
9.10.1 Peripheral timer/counters
2 general-purpose timer/counter units, Timer0 and Timer1, are available and can be
configured to operate in one of five possible modes:
1. Timer: can generate interrupts from rise and fall counts. Can be gated by external
signal
2. Counter: counts number of transitions of an external event signal. Can use low-high,
high-low or both transitions PWM/Single pulse: outputs a repeating Pulse Width
Modulation signal or a single pulse. Can set period and mark-space ratio
3. Capture: measures times between transitions of an applied signal
4. Delta-Sigma: Return-To-Zero (RTZ) and Non-Return-to-Zero (NRZ) modes
The Timer functionality is as follows:
• Clocked from internal system clock (16 MHz or 32 MHz)
• 5-bit prescaler, divides system clock by 2prescale as the clock to the timer (prescaler
range is 0 to 16)
• 17-bit counter, 17-bit Rise and Fall (period) registers
• Timer: can generate interrupts OFF Rise and Fall counts. Can be gated by external
signal
• Counter: counts number of transitions on external event signal. Can use low-high,
high-low or both transitions
• PWM/Single pulse: outputs repeating Pulse Width Modulation signal or a single pulse.
Can set period and mark-space ratio
• Capture: measures times between transitions of an applied signal
• Delta-Sigma: Return-To-Zero (RTZ) and Non-Return-to-Zero (NRZ) modes
• Timer usage of external IO can be controlled on a pin by pin basis
6 further timers are also available that support the same functionality but have no counter
or capture mode. These are referred to as PWM timers. Additionally, it is not possible to
gate these four timers with an external signal.
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IEEE802.15.4 Wireless Microcontroller
sw
reset
system single
interrupt
enable
reset
shot
RESET
GENERATOR
INTERRUPT
GENERATOR
interrupt
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=
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PWM/∆Σ
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PRESCALER
aaa-015450
(1) With x = 0 or 1.
Fig 26. Timer unit block diagram
The clock source for the Timer0/Timer1 unit is fed from the system clock, selected as
16 MHz or 32 MHz. This clock passes to a 5-bit prescaler where a value of 0 leaves the
clock unmodified and other values divide it by 2prescale value. For example, a prescale value
of 2 applied to the 16 MHz system clock source results in a timer clock of 4 MHz.
The counter is optionally gated by a signal on the clock/gate input (TIM0CK_GT). If the
gate function is selected, then the counter is frozen when the clock/gate input is high.
An interrupt can be generated whenever the counter is equal to the value in either of the
High or Low registers.
The Analog Peripheral Timer is dedicated for timing the analog peripherals, e.g. ADC and
comparator. APT inputs and outputs do not come to device pins.
Table 7 details which DIO is used for Timer0 and the PWM depending upon the
configuration.
Table 7.
Signal
Timer and PWM I/O
DIO assignment
Standard pins
DIO4
Alternative pins
DIO15
TIM0CK_GT
TIM0CAP
DIO2
DIO5
TIM0OUT
DIO3
DIO8
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Table 7.
Timer and PWM I/O …continued
DIO assignment
Signal
Standard pins
DIO6
Alternative pins
TIM1CAP
TIM1OUT
PWM1
DIO17
DIO11
DIO18
DIO12
DIO13
DIO14
DIO3
-
-
-
-
-
-
PWM2
PWM3
PWM4
PWM5
DIO8
PWM6
DIO15
When operating in timer mode, it is not necessary to use any of the DIO pins, allowing the
standard DIO functionality to be available to the application.
9.10.1.1 Pulse Width Modulation mode
Pulse Width Modulation (PWM) mode, as used by PWM timers 1, 2, 3, 4, 5 and 6 and
optionally by Timer0/Timer1, allows the user to specify an overall cycle time and pulse
length within the cycle. The pulse can be generated either as a single shot or as a train of
pulses with a repetition rate determined by the cycle time.
In this mode, the cycle time and low periods of the PWM output signal can be set by the
values of two independent 17-bit registers (Fall and Rise). The counter-increments and its
output are compared to the 17-bit Rise and Fall registers. When the counter is equal to the
Rise register, the PWM output is set to high; when the counter reaches the Fall value, the
output returns to low. In continuous mode, when the counter reaches the Fall value, it will
reset and the cycle repeats. If either the cycle time or low periods are changed while in
continuous mode, the new values are not used until a full cycle has completed. The PWM
waveform is available on PWM1, PWM2, PWM3, PWM4, PWM5, PWM6, TIM0OUT or
TIM1OUTwhen the output driver is enabled. The clock source used for pulse width
modulation could be 16 MHz or 32 MHz clock.
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Fig 27. PWM output timings
9.10.1.2 Capture mode
The capture mode can be used to measure the time between transitions of a signal
applied to the capture input (TIM0CAP or TIM1CAP). When the capture is started, on the
next low-to-high transition of the captured signal, the count value is stored in the rise
register, and on the following high-to-low transition, the counter-value is stored in the fall
register. The pulse width is the difference in counts in the two registers multiplied by the
period of the prescaled clock. Upon reading the capture registers, the counter is stopped.
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The values in the high and low registers will be updated whenever there is a
corresponding transition on the capture input, and the value stored will be relative to when
the mode was started. Therefore, if multiple pulses are seen on capture input before the
counter is stopped only the last pulse width will be stored.
9
5
3
4
CLK
(1)
TIMxCAP
t
r
t
r
t
f
t
f
capture mode enabled
9
rise
fall
x
3
x
14
7
aaa-018997
(1) With x = 0 or 1.
Fig 28. Capture mode
9.10.1.3 Counter/timer mode
The counter/timer can be used to generate interrupts, based on the timers or event
counting, for software to use. When used as a timer the clock source is taken from the
system clock, prescaled if required. The timer period is programmed into the fall register
and the Fall register match interrupt enabled. The timer is started as either a single-shot
or a repeating timer, and generates an interrupt when the counter reaches the Fall register
value.
When used to count external events on TIM0CK_GT, the clock source is selected from the
input pin and the number of events programmed into the Fall register. The Fall register
match interrupt is enabled and the counter started, usually in single shot mode. An
interrupt is generated when the programmed number of transitions is seen on the input
pin. The transitions counted can configure to be rising, falling or both rising and falling
edges. This feature is available only for Timer0.
Edges on the event signal must be at least 100 ns apart, that is pulses must be wider than
100 ns.
9.10.1.4 Delta-sigma mode
A separate delta-sigma mode is available, allowing a low speed delta-sigma DAC to be
implemented with up to 17-bit resolution. This requires that a resistor-capacitor network is
placed between the output DIO pin and digital ground. A stream of pulses with digital
voltage levels is generated which is integrated by the RC network to give an analog
voltage. A conversion time is defined in terms of a number of clock cycles. The width of
the pulses generated is the period of a clock cycle. The number of pulses output in the
cycle, together with the integrator RC values, will determine the resulting analog voltage.
For example, generating approximately half the number of pulses that make up a
complete conversion period will produce a voltage on the RC output of VDD, provided the
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RC time constant is chosen correctly. During a conversion, the pulses will be
pseudo-randomly dispersed throughout the cycle in order to produce a steady voltage on
the output of the RC network.
The output signal is asserted for the number of clock periods defined in the high register,
with the total period being 217 cycles. For the same value in the high register, the pattern
of pulses on subsequent cycles is different, due to the pseudo-random distribution.
The delta-sigma converter output can operate in a Return-To-Zero (RTZ) or a
Non-Return-to-Zero (NRZ) mode. The NRZ mode allows several pulses to be output next
to each other. The RTZ mode ensures that each pulse is separated from the next by at
least one period. This improves linearity if the rise and fall times of the output are different
to one another. Essentially, the output signal is low on every other output clock period, and
the conversion cycle time is twice the NRZ cycle time, that is 218 clocks. The integrated
output will only reach half VDDD in RTZ mode, since even at full scale only half the cycle
contains pulses. Figure 29 and Figure 30 illustrate the difference between RTZ and NRZ
for the same programmed number of pulses.
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Fig 30. Non-Return-to-Zero mode
9.10.1.5 Example timer/counter application
Figure 31 shows an application of the JN517x timers to provide closed loop speed control.
PWM1 is configured in PWM mode to provide a variable mark-space ratio switching
waveform to the gate of the NFET. This in turn controls the power in the DC motor.
Timer0 is configured to count the rising edge events on the CLK/GATE pin over a constant
period. This converts the tacho pulse stream output into a count proportional to the motor
speed. This value is then used by the application software executing the control algorithm.
If necessary for other functionality, then the unused IO associated with the timers could be
used as general-purpose DIO.
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IEEE802.15.4 Wireless Microcontroller
+10 V
TACHO
M
1N4007
IRF521
JN517x PWM1
CLK/GATE
TIMER0 CAPTURE
PWM
1 pulse/rev
aaa-021461
Fig 31. Closed loop PWM speed control using JN517x timers
9.10.2 ARM cortex-M3 system tick timer
The JN517x has a system tick timer (SysTick) which is a part of the Cortex-M3. SysTick,
that provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a
flexible control mechanism. A system can use this counter in several different ways,
including:
• As an RTOS tick timer that fires at a programmable rate, for example 100 Hz, and
invokes a SysTick routine each time it fires
• As a high-speed alarm timer using the main processor clock
• As a variable-rate alarm or signal timer. The available duration range depends on the
reference clock used and the dynamic range of the counter
• As a simple counter. Software can use this to measure time to completion and time
used
For further details, refer to JN-UG-3118 Integrated Peripherals API User Guide
JN-UG-3118 on the Wireless Connectivity area of the NXP web site Ref. 2.
In the JN517x, this timer can be clocked from the CPU clock or from a 32 kHz clock. The
32 kHz source can be either high-speed RC oscillator or 32 MHz crystal clock, suitably
divided down. When the high-speed RC oscillator is used as the clock source, the SysTick
clock may not be accurate 32 kHz.
9.10.3 Wake-up timers
Two 41-bit wake-up timers are available in the JN517x driven from the 32 kHz internal
clock. They may run during sleep periods when most of the rest of the device is powered
down, to time sleep periods or other long period timings that may be required by the
application. The wake-up timers do not run during deep sleep and may optionally be
disabled in sleep mode through software control. When a wake-up timer expires, it
typically generates an interrupt; if the device is asleep then the interrupt may be used as
an event to end the sleep period. See Section 10 for further details on how they are used
during sleep periods. Features include:
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• 41-bit down counter
• Optionally runs during sleep periods
• Clocked by 32 kHz system clock; either 32 kHz RC oscillator or 32 kHz clock input
A wake-up timer consists of a 41-bit down counter clocked from the selected 32 kHz
clock. An interrupt or wake-up event can be generated when the counter reaches zero. On
reaching zero, the counter will continue to count down until stopped, which allows the
latency in responding to the interrupt to be measured. If an interrupt or wake-up event is
required, the timer interrupt should be enabled before loading the count value for the
period. Once the count value is loaded and counter started, the counter begins to count
down; the counter can be stopped at any time through software control. The counter will
remain at the value it contained when the timer was stopped and no interrupt will be
generated. The status of the timers can be read to indicate if the timers are running and/or
have expired; this is useful when the timer interrupts are masked. This operation will reset
any expired status flags.
9.10.3.1 32 kHz RC oscillator calibration
The 32 kHz RC oscillator that can be used to time sleep periods is designed to require
very little power to operate and be self-contained, requiring no external timing
components and hence is lower cost. As a consequence of using on-chip resistors and
capacitors, the inherent absolute accuracy and temperature coefficient is lower than that
of a crystal oscillator, but once calibrated the accuracy approaches that of a crystal
oscillator. Sleep time periods should be as close to the desired time as possible in order to
allow the device to wake up in time for important events, for example beacon
transmissions in the IEEE802.15.4 protocol. If the sleep time is accurate, the device can
be programmed to wake up very close to the calculated time of the event and so keep
current consumption to a minimum. If the sleep time is less accurate, it will be necessary
to wake up earlier in order to be certain the event will be captured. If the device wakes
earlier, it will be awake for longer and so reduce battery life. The oscillator has a default
current consumption of around 0.5 A, which can optionally be reduced to 0.375 A, in
order to improve battery life. However, the calibrated accuracy and temperature
coefficient will be worse as a consequence. For detailed electrical specifications, see
Section 14.3.9.
In order to allow sleep time periods to be as close to the desired length as possible, the
true frequency of the RC oscillator needs to be determined to better than the initial 30 %
accuracy. The calibration factor can then be used to calculate the true number of nominal
32 kHz periods needed to make up a particular sleep time. A calibration reference
counter, clocked from the 16 MHz peripheral system clock, is provided to allow
comparisons to be made between the 32 kHz RC clock and the 16 MHz clock when the
JN517x is awake and running from the 32 MHz crystal.
Wake-up Timer0 counts for a set number of 32 kHz clock periods during which time the
reference counter runs. When the wake-up timer reaches zero the reference counter is
stopped, allowing software to read the number of 16 MHz clock ticks generated during the
time represented by the number of 32 kHz ticks programmed in the wake-up timer. The
true period of the 32 kHz clock can thus be determined and used when programming a
wake-up timer to achieve a better accuracy and hence more accurate sleep periods.
For an RC oscillator running at exactly 32000 Hz, the value returned by the calibration
procedure should be 10000, for a calibration period of twenty 32000 Hz clock periods. If
the oscillator is running faster than 32000 Hz the count will be less than 10000, if running
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slower the value will be higher. For a calibration count of 9000, indicating that the RC
oscillator period is running at approximately 35 kHz, to time for a period of 2 seconds the
timer should be loaded with 71,111 ((10000/9000) (32000 2)) rather than 64000.
9.11 Pulse counters
Two 16-bit counters are provided that can increment during all modes of operation
(including sleep). The first, PC0, increments from pulses received on DIO1 or DIO13. The
other pulse counter, PC1 operates from DIO5 or DIO14 depending upon the configuration.
This is enabled under software control. The pulses can be de-bounced using the 32 kHz
clock to guard against false counting on slow or noisy edges. Increments occur from a
configurable rising or falling edge on the respective DIO input.
Each counter has an associated 16-bit reference that is loaded by the user. An interrupt
(and wake-up event if asleep) may be generated when a counter reaches its
pre-configured reference value. The 2 counters may optionally be cascaded together to
provide a single 32-bit counter, linked to any of the four DIOs. The counters do not
saturate at 65535, but naturally roll-over to 0. Additionally, the pulse counting continues
when the reference value is reached without software interaction so that pulses are not
missed even if there is a long delay before an interrupt is serviced or during the wake-up
process.
The system can work with signals up to 100 kHz, with no debounce, or from 5.3 kHz to
1.7 kHz with debounce. When using debounce the 32 kHz clock must be active, so for
minimum sleep currents the debounce mode should not be used.
9.12 Serial communications
The JN517x has two Universal Asynchronous Receiver/Transmitter (UART) serial
communication interfaces. These provide similar operating features to the industry
standard 16550A device operating in FIFO mode. The interfaces perform serial-to-parallel
conversion on incoming serial data and parallel-to-serial conversion on outgoing data
from the CPU to external devices. In both directions, a configurable FIFO buffer (with a
default depth of 16-byte) allows the CPU to read and write multiple characters on each
transaction. This means that the CPU is freed from handling data on a
character-by-character basis, with the associated high processor overhead. The UARTs
have the following features:
• Emulates behavior of industry standard NS16450 and NS16550A UARTs
• Configurable transmit and receive FIFO buffers (with default depths of 16 bytes for
each), with direct access to fill levels of each. Adds/deletes standard start, stop and
parity bits to/from the serial data
• Independently controlled transmit, receive, status and data sent interrupts
• Optional modem flow control signals CTS and RTS on UART0
• Fully programmable data formats: baud rate, start, stop and parity settings
• False start-bit detection, parity, framing and FIFO overrun error detect and break
indication
• Internal diagnostic capabilities: loopback controls for communications link fault
isolation
• Flow control by software or automatically by hardware
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IEEE802.15.4 Wireless Microcontroller
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Fig 32. UART block diagram
The serial interfaces contain programmable fields that can be used to set number of data
bits (5, 6, 7 or 8), even, odd, set-at-1, set-at-0 or no-parity detection and generation of
single or multiple stop bit (for 5-bit data, multiple is 1.5 stop bits; for 6 data bits or 7 data
bits or 8 data bits, multiple is 2 bits).
The baud rate is programmable up to 1 Mbits/s and standard 4.8 kbits/s, 9.6 kbits/s,
19.2 kbits/s, 38.4 kbits/s.
For applications requiring hardware flow control, UART0 provides two control signals:
Clear-To-Send (CTS) and Request-To-Send (RTS). CTS is an indication sent by an
external device to the UART that it is ready to receive data. RTS is an indication sent by
the UART to the external device that it is ready to receive data. RTS is controlled from
software activities, while the value of CTS can be read. Monitoring and control of CTS and
RTS are software activity, normally performed as part of interrupt processing. The signals
do not control parts of the UART hardware, but simply indicate to software the state of the
UART external interfaces. Alternatively, the automatic flow control mode can be used, in
which the hardware controls the value of the generated RTS (negated if the receive FIFO
fill level is greater than a programmable threshold of 8 bytes, 11 bytes, 13 bytes or 15
bytes), and only transmits data when the incoming CTS is asserted.
Software can read characters, one byte at a time, from the receive FIFO and can also
write to the transmit FIFO, one byte at a time. The transmit and receive FIFOs can be
cleared and reset independently of each other. The status of the transmit FIFO can be
checked to see if it is empty and if there is a character being transmitted. The status of the
receive FIFO can also be checked, indicating if a condition such as parity error, framing
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IEEE802.15.4 Wireless Microcontroller
error or break indication has occurred. It also shows if an overrun error has occurred
(receive buffer full and another character arrives) and if there is data held in the receive
FIFO.
UART0 and UART1 can both be configured to use standard or alternative DIO lines, as
shown in Table 8. Additionally, UART0 can be configured to be used in 2-wire mode
(where CTS0 and RTS0 are not configured), and UART1 can be configured in 1-wire
mode (where RXD1 is not configured). These freed up DIO pins can then be used for
other purposes.
Table 8.
Signal
UART I/O
DIO assignment
Standard pins
DIO6
Alternative pins
CTS0
RTS0
RXD0
TXD0
RXD1
TXD1
-
DIO11
-
DIO4
DIO10, DIO13
DIO9, DIO12
DIO6
DIO5
DIO2
DIO3
DIO11
Remark: With the automatic flow control threshold set to 15, the hardware flow control
within the UART’s block negates RTS when the receive FIFO is about to become full. In
some instances, it has been observed that remote devices that are transmitting data do
not respond quickly enough to the de-asserted RTS and continue to transmit data. In
these instances, the data will be lost in a receive FIFO overflow
9.12.1 Interrupts
Interrupt generation can be controlled for the UART’s block and is divided into four
categories:
• Received Data Available: set when data in the RX FIFO queue reaches a particular
level (the trigger level can be configured as 1, 4, 8 or 14) or if no character has been
received for 4-character times.
• Transmit FIFO Empty: set when the last character from the TX FIFO is read and starts
to be transmitted
• Receiver Line Status: set when one of the following occurs
a. Parity Error - the character at the head of the receive FIFO has been received with
a parity error
b. Overrun Error - the RX FIFO is full and another character has been received at the
receiver shift register
c. Framing Error - the character at the head of the receive FIFO does not have a valid
stop bit
d. Break Interrupt – occurs when the RXD line has been held low for an entire
character
• Modem Status: generated when the CTS (Clear To Send) input control line changes.
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9.12.2 UART application
The following example shows the UART0 connected to a 9-pin connector compatible with
a PC. As the JN517x device pins do not provide the RS232 line voltage, a level shifter is
used.
PC COM
port
pin
signal
1
5
1
2
3
4
5
6
7
8
9
CD
RD
JN517x
6
9
TD
DTR
SG
DSR
RTS
CTS
RI
TXD
CTS
RXD
RTS
RS232
LEVEL
SHIFTER
UART0
aaa-021456
Fig 33. JN517x serial communication link
9.13 JTAG test interface
The JN517x includes a JTAG interface for the purposes of software debugging when used
in conjunction with the LCPXpresso for NXP development environment.
For further details, refer to SDK Installation and User Guide JN-UG-3109 on the Wireless
Connectivity area of the NXP web site Ref. 2.
The JTAG interface does not support boundary scan testing. It is recommended that the
JN517x is not connected as part of the board scan chain.
9.14 2-wire serial interface (I2C-bus)
The JN517x includes industry standard I2C-bus 2-wire synchronous Serial Interface
operates as a Master (MSIF) or Slave (SSIF) that provides a simple and efficient method
of data exchange between devices. The system uses a serial data line (SDA) and a serial
clock line (SCL) to perform bidirectional data transfers and includes the following features:
Common to both master and slave:
• Compatible with both I2C-bus standard
• Support for 7 and 10-bit addressing modes
• Pulse suppression on signal inputs (60 ns guaranteed, 125 ns typical)
• True open-drain support on one set of DIOs
• Receive and transmit FIFO of depth of 8
• Bus monitor mode
• Fail-safe operation on DIO4 and DIO5
Master only:
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• Multi-master operation
• Software programmable clock frequency
• Supports Slave clock stretching
• Software programmable acknowledge bit
• Interrupt or polling driven data-transfers
Slave only:
• Read data flow control using clock stretching
• Read data preloaded or provided as required
The serial interface is accessed, depending upon the configuration, through DIO4 and
DIO5 which have true open-drain mode or DIO2 and DIO3. This is enabled under
software control. The following table details which DIO is used for the Serial Interface
depending upon the configuration.
Table 9.
Signal
2-wire serial interface I/O
DIO assignment
Standard pins
DIO4
Alternative pins
DIO3
SCL
SDA
DIO5
DIO2
9.14.1 Connecting devices
The clock and data lines, SCL and SDA, are alternate functions of DIO4 and DIO5
respectively. The serial interface function of these pins is selected when the interface is
enabled. They are both bidirectional lines, connected internally to the positive supply
voltage via weak (50 k) programmable pull-up resistors. However, it is recommended
that external 4.7 k pull-ups be used for reliable operation at high bus speeds, as shown
in Figure 34. When the bus is free, both lines are HIGH. The output stages of devices
connected to the bus must have an open-drain or open-collector in order to perform the
wired-AND function. The number of devices connected to the bus is solely dependent on
the bus capacitance limit of 400 pF.
DIO4 and DIO5 support fail-safe operation of the I2C-bus system bus, i.e., if the VDD
supply is removed from the JN517x then rest of I2C-bus at system level is not affected.
However when alternate pins DIO2 and DIO3 are used as the I2C-bus interface the
fail-safe operation is not guaranteed as these DIOs do not have true open-drain output
stages.
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VDD
JN517x
pull-up
resistors
R
R
P
P
SCL
DIO4
I2C-bus
SDA
DIO5
D1_IN
CLK1_IN
D2_IN
CLK2_IN
D1_OUT
CLK1_OUT
D2_OUT
CLK2_OUT
DEVICE 1
DEVICE 2
aaa-0121462
Fig 34. Connection details
9.14.2 Clock stretching
Slave devices can use clock stretching to slow down the read transfer bit rate. After the
master has driven SCL low, the slave can drive SCL low for the required period and then
release it. If the slave’s SCL low period is greater than the master’s low period the
resulting SCL bus signal low period is stretched thus inserting wait states, see
Section 9.14.4 for further details.
clock held low
by slave
SCL
SCL
SCL
master SCL
slave SCL
system SCL
aaa-015455
Fig 35. Clock stretching
9.14.3 Master interface
When operating as a master, it provides the clock signal and a separately programmable
SCL low and high period to determine the clock rate and shape, allowing operation up to
400 kbit/s.Data transfer is controlled from the processor bus interface by populating the
TX FIFO or managing the RX FIFO, with the I2C-bus controller taking care of when start,
stop, read, write and acknowledge control should be generated. To use the master device
as a receiver, one just needs to fill the TX_FIFO with a start condition and a valid slave
address (LSB = 1: read operation), and then with as many dummy bytes (i.e. any byte) as
the number of bytes requested from the slave device. A ‘stop’ must always be issued
together with a dummy byte in the TX_FIFO to indicate the slave no longer needs to send
data. The data received on the master side is stored in the RX_FIFO.
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Regardless of the direction of the communication in master mode the first thing that must
be done is to set the I2C-bus clock frequency, by programming both the
Clock_Divisor_High and Clock_Divisor_Low registers.
Then the programming depends on the function required for the device:
9.14.3.1 Master transmitter
1. The user has to write the TX_FIFO register with a slave address byte (with the LSB
set to 0 = write operation) and a start command bit, so that an I2C-bus transfer can be
initiated. The data bytes to be sent must then be loaded into the TX_FIFO register
(start and stop commands bits should be cleared to ‘0’). The matching slave device
will acknowledge the slave address and then each data byte so that the transaction
can continue.
2. If the TX_FIFO is empty, the master will automatically stretch the clock of the previous
byte (after acknowledge) until a new byte is written to the TX_FIFO as can be seen in
Figure 36. This stretching after acknowledge is the case for the address + R/W byte
(first) as well as for all data bytes that follow.
TX_FIFO empty:
Master stretches
the clock
One or several bytes
have been written to
TX_FIFO
7
8
Ack
1
2
SCL
SDA
Acknowledge
by Slave
MTDR
interrupt out.
Master transmits again
aaa-015456
Fig 36. TX_FIFO in the middle of a transaction
3. With the LAST data byte to be sent the user must set the stop bit to generate a STOP
condition and the slave should acknowledge the byte. For a RESTART to be issued
both start and stop bits should remain cleared at this point.
4. If a STOP has been produced, a new transaction can be initiated by jumping back to
step 1 of the master receiver or transmitter mode. Otherwise for the RESTART case,
the start bit has to be programmed together with the slave address of the next
transaction (start bit set).
The next action will be step 2 of the master receiver or Transmitter mode, depending on
the slave address direction bit. Table 10 is an example of master transmitter writing data
to TX_FIFO.
Table 10. I2C-bus TX_FIFO master transmitter writing data example
Instruction code
0x148
Description
master issues a START + slave address 24h (write operation)
0x025
data bytes 25h”, 13h will be sent to the slave” interrupt
-
0x013
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Table 10. I2C-bus TX_FIFO master transmitter writing data example …continued
Instruction code Description
0x1DC
0x001
0x2AA
master issues a RESTART + slave address 6Eh (write)
data bytes 01h, AAh will be sent to the slave
master issues a STOP
9.14.3.2 Master receiver
1. The user has to write the TX_FIFO register with a slave address byte (with the LSB
set to 1 = read operation) and a start command bit, so that an I2C-bus transfer can be
initiated. The slave will acknowledge if it recognizes its address, and start transmitting
data.
2. For each data byte requested by the master, a dummy byte (i.e. the value of the data
byte can be anything from 0x00 to 0xFF) must be loaded into the TX_FIFO, so that
the master acknowledges the data bytes it receives. Please note that the
acknowledge bit is generated automatically; no specific programming is required for it.
The received (acknowledged) data bytes will be stored in the RX_FIFO (address
0x000), from where they can be fetched by the bus system interface. If the RX_FIFO
happens to be full (interrupt RX_FIFO_FULL) in the middle of a transaction, the
master will automatically stretch the clock before the acknowledge of the last byte that
is stored, until some room is made in the RX_FIFO, refer to Figure 37. The data is
actually written into the RX_FIFO on the 8th clock cycle, so it can be read by software
even if the clock is currently stretched in the Ack cycle (9th clock) due to
RX_FIFO_Full.
RX_FIFO full:
Master stretches
the clock
One or several bytes
have been fetched from
the RX_FIFO
6
7
8
Ack
1
2
SCL
SDA
RFF
interrupt out.
Acknowledge
by Master
Slave transmits again
aaa-015457
Fig 37. RX_FIFO full in the middle of a transaction
3. When the LAST data byte has to be received, the user must set the stop bit with the
last dummy byte to generate a STOP condition. In this case, the master will NOT
Acknowledge the byte, so that the slave releases the data line and the STOP can be
issued by the master
If the TX_FIFO is empty, the master will automatically stretch the clock. If the
TX_FIFO becomes empty, the clock will be stretched after the acknowledgement has
been sent. This behavior is identical to the master transmitter as shown in Figure 36.
However when the TX_FIFO is empty after sending a dummy byte (in order to receive
a byte from the slave) the clock will be stretched between the 8th cycle and the Ack
cycle, until at least one new byte is written to the TX_FIFO. This is shown in
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Figure 38.
TX_FIFO empty:
Master stretches
the clock
Slv_add byte 0x1xx
have been written to
TX_FIFO
6
7
8
Ack
SCL
SDA
Slave transmits
MTDR
interrupt out.
NAck
RESTART condition.
from Master (Slave aborts transfer)
aaa-015458
Fig 38. TX_FIFO empty just before RESTART condition in master slave case
The master transmitter has to stretch the clock between the 8th and the 9th pulse when
TX_FIFO is empty, since it does not know whether it should send a NAck (next byte that
is programmed contains a restart) or an Ack (next byte is a normal dummy data byte).
Although the clock is stretched in the Ack cycle until the next dummy byte is written into
the TX_FIFO, the current data can already be read from the RX_FIFO, since the data is
written into the RX_FIFO on the 8th clock pulse. This implies that data can be read from
a slave on a byte by byte basis even when the TX_FIFO is empty.
4. If a STOP has been produced, a new transaction can be initiated by jumping back to
step 1 of the master receiver or transmitter mode. Otherwise for the RESTART case,
the start bit has to be programmed together with the slave address of the next
transaction. The previous byte will then not be acknowledged and the restart
produced. The next action will be then step 2 of the master receiver or transmitter
mode, depending on the slave address direction bit. When the master loses
arbitration, the data already received in the RX_FIFO is invalid. To prevent new slave
I2C-bus data from being written into the RX_FIFO while it still contains this invalid
data, the RX_FIFO_block signal is set (bit 10 of I2C_Status register). When the
RX_FIFO is accessed as a slave receiver after it has lost arbitration (as a master) and
the RX_FIFO was not cleared (emptied) the clock will be stretched, until the RX_FIFO
has been emptied. See Section 9.14.4.1 for more information.
Table 11. I2C-bus RX_FIFO master receiver reading data example
Instruction code
0x149
Description
master issues a START + slave address 24h (read operation)
0x0xx
the presence of the 3 dummy bytes indicates that the master expects 3
data bytes from the slave
0x0xx
0x2xx
-
master issues a STOP
9.14.4 Slave interface
When operating as a slave, the first thing that needs to be done is to set the addressing
mode (either 10-bit or 7-bit).
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As soon as the slave sees a start condition on the bus, it will read the first byte (if 7-bit
slave address mode selected) or the first 2 bytes (if 10-bit slave address mode selected).
If the address received matches the address programmed into the slave by the user, it will
acknowledge the slave address, and enter respectively the Receiver or the Transmitter
mode, according to the slave address first byte LSB, respectively 0 or 1.
9.14.4.1 Slave receiver
All the received bytes are stored in the RX_FIFO and all bytes are acknowledged. The
slave cannot generate a NAck.
Remark: the generation of the acknowledge is automatic and no extra programming is
required.
If the RX_FIFO happens to be full (interrupt RX_FIFO_FULL) in the middle of a
transaction, the slave will automatically stretch the clock after the acknowledge of the last
byte stored, until some room is made in the RX_FIFO as shown in Figure 39.
RX_FIFO full:
Slave stretches
the clock
One or several bytes
have been fetched from
the RX_FIFO
7
8
Ack
1
2
SCL
SDA
Acknowledge
by Slave
RFF
interrupt out.
Master transmits again
aaa-015459
Fig 39. Slave receiver: RX_FIFO in middle of a transaction
The transaction is aborted only when a STOP or a RESTART is detected on the bus.
After the slave has been addressed in receiver mode, the RX_FIFO must be emptied
before the device is addressed again after a STOP or RESTART. This will be notified
externally via interrupt SRSD (Int_Status register bit 4), set when the slave receiver sees
a STOP or a RESTART on the bus. The RX_FIFO is then automatically blocked
(I2C_Status register bit 10 set) and must be emptied (read), before clearing the interrupt.
Only then can the slave be involved in a new transfer. If the slave is addressed again in
receiver mode and the RX_FIFO is not empty, the slave will stretch the clock after
acknowledging its address, until the RX_FIFO is completely emptied. This mechanism is
present to prevent multiple messages from being entered into the RX_FIFO, since the
slave cannot differentiate 2 distinct messages - START and STOP information is not
stored.
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empty
RX_FIFO
+ clear int
SRSD
interrupt
SRSD still pending
≥ stretch clock
7
8
Ack
1
2
8
Ack
1
SCL
SDA
Master transmits
STOP + START
Master sends
slave address + write bit
Master transmits
NoAck
from slave
Slave acknowledges
and takes over the SDA line
aaa-015460
Fig 40. Example of use of the SRSD interrupt (STOP case)
9.14.4.2 Slave transmitter
The slave transmitter data must be written to the TXS_FIFO. Each data byte must be
acknowledged by the master to continue the transaction.
If the TXS_FIFO is empty (interrupt STDR -Int_Status register bit 8- set), the slave will
automatically stretch the clock of the previous byte (after acknowledge) until some new
byte is loaded in the TXS_FIFO. See Figure 41.
TX/TXS_FIFO empty:
slave stretches
the clock
one or several bytes
have been written to
the TX/TXS_FIFO
7
8
Ack
1
2
SCL
SDA
acknowledge
by master
STDR
interrupt out
slave transmits again
aaa-016452
Fig 41. TXS_FIFO empty in the middle of a transaction
A transaction is aborted only when the master does not acknowledge a data byte, after
which the slave releases the data line. A STOP or a RESTART is then issued by the
master.
After the slave has been addressed in transmitter mode, the TXS_FIFO must be emptied
before the device is addressed again. This is notified externally via interrupt STSD
(Int_Status register bit 3), set when the slave transmitter sees a STOP or a RESTART on
the bus. The TXS_FIFO is then automatically blocked (I2C_Status register bit 11 set) and
must be flushed by software before clearing the interrupt. This blocking mechanism is
used to prevent unwanted data from remaining in the TXS_FIFO after the STOP or
RESTART on the bus. If the slave is addressed again in transmitter mode and the
TXS_FIFO has not been flushed, the slave will stretch the clock after acknowledging its
address, until the TXS_FIFO is flushed and filled up again with correct new data.
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flush TX/TXS_FIFO
clear int and fill
TX/TXS_FIFO
STSD
interrupt
TX/TXS_FIFO not flushed
≥ stretch clock
7
8
Ack
1
2
8
Ack
1
SCL
SDA
Master transmits
RESTART
Master sends
slave address + read bit
Slave transmits
NoAck
from Master
(slave aborts transfer)
Slave acknowledges
and takes over the SDA line
aaa-015462
Fig 42. Example of use of the STSD interrupt (RESTART case)
9.14.5 Particular cases on I2C-bus
9.14.5.1 I2C-bus error
In a protocol violation on the I2C-bus, i.e., an unexpected START or STOP in the middle of
a transfer, the I2C-bus Error interrupt is set. On detection of an unexpected stop condition,
the device goes to the IDLE state and releases SDA and SCL. In case of an unexpected
restart condition, the device releases SDA and SCL checks whether it is addressed as a
slave.
9.14.5.2 Arbitration lost
When arbitration loss occurs, the Transmitter Arbitration Failure interrupt (TAF: bit 1 of the
Int_Status register) is automatically set. This means that the data bytes stored in the
TX_FIFO and the RX_FIFO are not valid, since the transfer was interrupted. The
TX_FIFO must be flushed (I2C_Control register bit 3) before clearing the interrupt. On
detection of an arbitration loss, the master will immediately release the I2C-bus (IDLE
state).
Likewise, the data in the RX_FIFO is invalid and must be read by the system to empty the
RX_FIFO. Until this is done, access to the RX_FIFO from I2C-bus is blocked by clock
stretching as described in Section 9.14.3.
9.14.5.3 NAck from slave receiver
If a master transmitter receives a NAck from the addressed slave, the master will
automatically generate a STOP and break off the transfer. The user must manually flush
the TX_FIFO before clearing the interrupt.
Software can add data to the TX_FIFO, since there is no blocking from the system bus,
however this data must be flushed again later to start normal master operation again.
9.15 Random number generator
A random number generator is provided which creates a 16-bit random number each time
it is invoked. Consecutive calls can be made to build up any length of random number.
Each call takes approximately 0.25 ms to complete. Alternatively, continuous generation
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mode can be used where a new number is generated approximately every 0.25 ms. In
either mode of operation, an interrupt can be generated to indicate when the number is
available, or a status bit can be polled.
The random bits are generated by sampling the state of the 32 MHz clock every 32 kHz
system clock edge. As these clocks are asynchronous to each other, each sampled bit is
unpredictable and hence random.
9.16 Analog peripherals
The JN517x contains a number of analog peripherals allowing the direct connection of a
wide range of external sensors and switches.
chip boundary
supply voltage
(V
)
DDD
Vref
Vref select
ADC0
VREF/ADC1
ADC
ADC2
ADC3
ADC4
ADC5
temp
sensor
COMP1P
COMP1M
comparator 1
processor bus
aaa-015463
Fig 43. Analog peripherals
In order to provide good isolation from digital noise, the analog peripherals and radio are
powered by the radio regulator, which is supplied from the analog supply VDDA and
referenced to analog ground VSSA
.
A reference signal Vref for the ADC can be selected between an internal band gap
reference or an external voltage reference supplied to the VREF pin. ADC input 1 cannot
be used if an external reference is required, as this uses the same pin as VREF. The
ADC4, ADC3, ADC5 and ADC2 use the same pins as DIO0, DIO1, DIO2 and DIO3
respectively. These pins can only be used for the ADC if they are not required for any of
their alternative functions. Similarly, the comparator inputs are shared with DIO17 and
DIO18. If used for their analog functions, these DIOs must be put into a passive state by
setting them to Inputs with their pull-ups disabled.
The ADC is clocked from a common clock source derived from the 16 MHz clock
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9.16.1 Analog to Digital Converter
The 10-bit ADC uses a successive approximation design to perform high accuracy
conversions as typically required in wireless sensor network applications. It has eight
multiplexed single-ended input channels: six available externally, one connected to an
internal temperature sensor, and one connected to an internal supply monitoring circuit.
9.16.1.1 Operation
The input range of the ADC can be set between 40 mV to either the reference voltage or
twice the reference voltage. The reference can be either taken from the internal voltage
reference or from the external voltage applied to the VREF pin. For example, an external
reference of 1.2 V supplied to VREF may be used to set the ADC range between 40 mV
and 2.4 V.
Table 12. ADC maximum input range
VREF
1.2 V
1.6 V
1.2 V
1.6 V
Gain setting
Maximum input range Supply voltage range (VDD)
0
0
1
1
1.2 V
1.6 V
2.4 V
3.2 V
2.2 V to 3.6 V
2.2 V to 3.6 V
2.6 V to 3.6 V
3.4 V to 3.6 V
The input clock to the ADC is 16 MHz and can be divided down to 2 MHz, 1 MHz, 500 kHz
and 250 kHz. During an ADC conversion, the selected input channel is sampled for a fixed
period and then held. This sampling period is defined as a number of ADC clock periods
and can be programmed to 2, 4, 6 or 8. The conversion rate is ((3 sample period) + 13)
clock periods. For example, for 500 kHz conversion with sample period of 2 will be (3 2)
+ 13 = 19 clock periods, 38 s or 26.32 kHz. The ADC can be operated in either a single
conversion mode or alternatively a new conversion can be started as soon as the previous
one has completed, to give continuous conversions.
If the source resistance of the input voltage is 1 k or less, then the default sampling time
of 2 clock periods should be used. The input to the ADC can be modeled as a resistor of
5 k (typ.) and 10 k (max.) to represent the on-resistance of the switches and the
sampling capacitor 8 pF. The sampling time required can then be calculated, by adding
the sensor source resistance to the switch resistance, multiplying by the capacitance
giving a time constant. Assuming normal exponential RC charging, the number of time
constants required to give an acceptable error can be calculated, seven time constants
gives an error of 0.091 %, so for 10-bit accuracy, seven time constants should be the
target. For a source with zero resistance, seven time constants are 640 ns, hence the
smallest sampling window of 2 clock periods can be used.
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ꢆꢀS)
DDDꢀꢁꢁꢂꢃꢉꢉ
Fig 44. ADC input equivalent circuit
The ADC sampling period, input range and mode (single shot or continuous) are
controlled through software.
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When the ADC conversion is complete, an interrupt is generated. Alternatively the
conversion status can be polled. When operating in continuous mode, it is recommended
that the interrupt is used to signal the end of a conversion, since conversion times may
range from 9.5 s to 148 s. Polling over this period would be wasteful of processor
bandwidth.
To facilitate averaging of the ADC value, which is a common practice in microcontrollers,
a dedicated accumulator has been added, the user can define the accumulation to occur
over 2, 4, 8 or 16 samples. The end of conversion interrupt can be modified to occur at the
end of the chosen accumulation period, alternatively polling can still be used. Software
can then be used to apply the appropriate rounding and shifting to generate the average
value, as well as setting up the accumulation function.
For detailed electrical specifications, see Section 14.3.7.
9.16.1.2 Supply monitor
The internal supply monitor allows the voltage on the analog supply pin VDDA to be
measured. This is achieved with a potential divider that reduces the voltage by a factor of
0.666, allowing it to fall inside the input range of the ADC when set with an input range
twice the internal voltage reference. The resistor chain that performs the voltage reduction
is disabled until the measurement is made to avoid a continuous drain on the supply.
9.16.1.3 Temperature sensor
The on-chip temperature sensor can be used either to provide an absolute measure of the
device temperature or to detect changes in the ambient temperature. In common with
most on-chip temperature sensors, it is not trimmed and so the absolute accuracy
variation is large; the user may wish to calibrate the sensor prior to use. The sensor forces
a constant current through a forward biased diode to provide a voltage output proportional
to the chip die temperature which can then be measured using the ADC. The measured
voltage has a linear relationship to temperature as described in Section 14.3.13.
Because this sensor is on-chip, any measurements taken must account for the thermal
time constants. For example, if the device just came out of sleep or deep sleep mode the
user application should wait until the temperature has stabilized before taking a
measurement.
9.16.1.4 ADC sample buffer mode
In this mode, the ADC operates with a Direct Memory Access (DMA) engine as follows:
• ADC sampling is triggered at a configurable rate using dedicated Timer ADC
• ADC samples are automatically stored in a buffer located in RAM using a DMA
mechanism
• ADC inputs may be multiplexed between different analog sources
The 10-bit ADC data samples are transferred into the buffer in RAM as 16-bit words. The
maximum number of 16-bit words that may allocated in RAM for ADC sample storage is
2047.
The buffer may be configured to automatically wrap around to the start when full.
Interrupts may be configured to indicate when the buffer is half-full, full and has
overflowed.
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The CPU may perform other tasks while the data transfer and storage is being managed
independently by the DMA engine - the CPU only needs to configure the ADC sample
buffer mode and deal with the stored samples in the buffer when an interrupt occurs.
ADC sample buffer mode allows up to 8 analog inputs to be multiplexed in combination.
These inputs comprise 6 external inputs (ADC0 to 5, corresponding to IO pins), an
on-chip temperature sensor and an internal voltage monitor. Samples from all the selected
inputs will be produced on each timer trigger and stored in consecutive RAM locations.
9.16.2 Comparator
The JN517x contains one analog comparator, COMP1, that is designed to have true
rail-to-rail inputs and operate over the full voltage range of the analog supply VDDA. The
hysteresis level can be set to a nominal value of 0 mV, 10 mV, 20 mV or 40 mV. The
source of the negative input signal for the comparator can be set to the internal voltage
reference, the negative external pin (COMP1M, which uses the same pin as DIO18) or the
positive external pin (COMP1P, on the same pin as DIO17). The source of the positive
input signal can be COMP1P or COMP1M. DIO17 and DIO18 cannot be used if the
external comparator inputs are needed. The comparator output is routed to an internal
register and can be polled, or can be used to generate interrupts. The comparator can be
disabled to reduce power consumption. DIO17 and DIO18 should be set to inputs with
pull-ups disabled, when using the comparator.
The comparator also has a low-power mode where the response time of the comparator is
slower than the normal mode, but the current required is greatly reduced. These figures
are specified in Section 14.3.8. It is the only mode that may be used during sleep, where a
transition of the comparator output will wake the device. The wake-up action and the
configuration for which edge of the comparator output is active are controlled through
software. In sleep mode, the negative input signal source must be configured to be driven
from the external pins.
9.16.3 Digital monitor for ADC output
The JN517x contains one digital monitor function at the output of the ADC. The digital
monitor can be configured to compare the ADC output against programmable upper
threshold (DC_UT) and lower threshold (DC_LT) and raise an interrupt on enabled trigger
conditions. The output of the monitor can also be brought out on DIO7. There are four
trigger conditions which can be selected:
• Less than: TRUE when ADC_VAL < DC_LT
• More than: TRUE when ADC_VAL > DC_UT
• Inside range: TRUE when DC_LT ADC_VAL DC_UT
• Outside range: TRUE when (ADC_VAL < DC_LT) OR (ADC_VAL > DC_UT)
10. Power management and sleep modes
10.1 Operating modes
After the main supply source is selected, 3 operating modes are provided in the JN517x
that enable the system power consumption to be controlled carefully to maximize battery
life.
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• Active processing mode
• Sleep mode
• Deep sleep mode
The variation in power consumption of the 3 modes is a result of having a series of power
domains within the chip that may be selectively powered ON or OFF.
10.1.1 Power domains
The JN517x has the following power domains:
• VDD supply domain: supplies the wake-up timers and controller, DIO blocks,
Comparator, SVM and BOR together with the Fast RC, 32 kHz RC and crystal
oscillator. This domain is driven from the external supply (battery) and is always
powered. The wake-up timers and controller, and the 32 kHz RC and crystal oscillator
may be powered ON or OFF in sleep mode through software control.
• Digital logic domain: supplies the digital peripherals, CPU, Flash when in active
processing mode, baseband controller, modem and encryption processor. It is
powered OFF during sleep or deep sleep mode.
• RAM domain: supplies the RAM when in active processing mode. Also supplies the
RAM during sleep mode to retain the memory contents. It may be powered ON or
OFF for sleep mode through software control.
• Radio domain: supplies the radio interface, ADCs and temperature sensor. It is
powered during transmit and receive and when the analog peripherals are enabled. It
is controlled by the baseband processor and is powered OFF during sleep or deep
sleep mode.
The current consumption figures for the different modes of operation of the device is given
in Section 14.1.
10.2 Active processing mode
Active processing mode in the JN517x is where all of the application processing takes
place. By default, the CPU will execute at the selected clock speed executing application
firmware. All of the peripherals are available to the application, as are options to actively
enable or disable them to control power consumption; see specific peripheral sections for
details.
While in active processing mode there is the option to doze the CPU but keep the rest of
the chip active; this is particularly useful for radio transmit and receive operations, where
the CPU operation is not required therefore saving power.
10.2.1 CPU doze
While in doze mode, CPU operation is stopped but the chip remains powered and the
digital peripherals continue to run. Doze mode is entered through software and is
terminated by any interrupt request. Once the interrupt service routine has been executed,
normal program execution resumes. Doze mode uses more power than sleep and deep
sleep modes but requires less time to restart and can therefore be used as a low-power
alternative to an idle loop.
While in CPU doze, the CPU is not drawing current, therefore the total device current is
reduced.
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10.3 Sleep mode
The JN517x enters sleep mode through software control. In this mode most of the internal
chip functions are shut down to save power, however the state of DIO pins are retained,
including the output values and pull-up enables, and this therefore preserves any interface
to the outside world.
When entering into sleep mode, there is an option to retain the RAM contents throughout
the sleep period. If the wake-up timers are not to be used for a wake-up event and the
application does not require them to run continually, then power can be saved by
switching off the 32 kHz oscillator if selected as the 32 kHz system clock through software
control. The oscillator is restarted when a wake-up event occurs.
Whilst in sleep mode, one of 4 possible events can cause a wake-up to occur: transitions
on DIO inputs, expiry of wake-up timers, pulse counters maturing or comparator events. If
any of these events occur, and the relevant interrupt is enabled, then an interrupt is
generated that will cause a wake-up from sleep. It is possible for multiple wake-up
sources to trigger an event at the same instant and only one of them will be accountable
for the wake-up period. It is therefore necessary in software to remove all other pending
wake-up events prior to requesting entry back into sleep mode; otherwise, the device will
reawaken immediately.
When wake-up occurs, a similar sequence of events to the reset process described in
Section 9.5.1 happens, including the checking of the supply voltage by the Supply Voltage
Monitor (Section 9.5.4). The high-speed RC oscillator is started up, once stable the power
to the CPU sub-system is enabled and the reset is removed. Software determines that this
is a reset from sleep and so commences with the wake-up process. If RAM contents were
held through sleep, wake-up is quicker as the software does not have to initialize RAM
contents meaning the application can recommence more quickly. See Section 14.3.5 for
wake-up timings.
10.3.1 Wake-up timer event
The JN517x contains two 41-bit wake-up timers that are counters clocked from the 32 kHz
oscillator, and can be programmed to generate a wake-up event. Following a wake-up
event, the timers continue to run. These timers are described in Section 9.10.3.
Timer events can be generated from both of the timers; one is intended for use by the
802.15.4 protocol, the other being available for use by the application running on the
CPU. These timers are available to run at any time, even during sleep mode.
10.3.2 DIO event
Any DIO pin when used as an input has the capability, by detecting a transition, to
generate a wake-up event. Once this feature has been enabled, the type of transition can
be specified (rising or falling edge). Even when groups of DIO lines are configured as
alternative functions such as the UARTs or Timers, any input line in the group can still be
used to provide a wake-up event. This means that an external device communicating over
the UART can wake up a sleeping device by asserting its RTS signal pin (which is the
CTS input of the JN517x).
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10.3.3 Comparator event
The comparator can generate a wake-up interrupt when a change in the relative levels of
the positive and negative inputs occurs. The ability to wake up when continuously
monitoring analog signals is useful in ultra-low power applications. For example, the
JN517x can remain in sleep mode until the voltage drops below a threshold and then be
woken up to deal with the alarm condition; the comparator has a low current mode to
facilitate this.
10.3.4 Pulse counter
The JN517x contains two 16-bit pulse counters that can be programmed to generate a
wake-up event. Following the wake-up event the counters will continue to operate and
therefore no pulse will be missed during the wake-up process. These counters are
described in Section 9.11.To minimize sleep current it is possible to disable the 32 kHz
RC oscillator and still use the pulse counters to cause a wake-up event, provided
debounce mode is not required.
10.4 Deep sleep mode
Deep sleep mode gives the lowest power consumption. All switchable power domains are
off and most functions in the VDD supply power domain are stopped, including the 32 kHz
RC oscillator. However, the Brown-Out Reset remains active as well as all the DIO cells.
This mode can be exited by a hardware reset on the RESET_N pin, or an enabled DIO
wake-up event.
10.5 Flicker control
FLICK_CTRL feature is dedicated to lighting application in a bulb. It allows either to do a
OR or NOR function from RFRX and RFTX to be outputted on one of DIO. Aim of this
feature is to compensate the variation of current of the IC depending of the mode (RX/TX)
when using Lighting application.
11. Limiting values
Table 13. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDDA
Parameter
Conditions
Min
Max
Unit
V
analog supply voltage
digital supply voltage
regulated supply voltage
voltage on pin XTAL_OUT
voltage on pin XTAL_IN
voltage on pin RF_IO
voltage on pin VREF
voltage on pin ADCX
voltage on pin IBIAS
digital input/output voltage
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
+3.6
VDDD
+3.6
V
[1]
[1]
[1]
[1]
VDD(regd)
VXTAL_OUT
VXTAL_IN
VRF_IO
VVREF
on pins VB_xx
+1.98
V
VB_xx + 0.3
VB_xx + 0.3
VB_xx + 0.3
VDDA + 0.3
VDDA + 0.3
VDDA + 0.3
VDDD + 0.3
V
V
V
V
[2]
[3]
VADCx
V
VIBIAS
V
VIO(dig)
on pins DIOx
V
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Table 13. Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Tstg
Parameter
Conditions
Min
Max
Unit
C
V
storage temperature
electrostatic discharge voltage
40
+150
2000
1000
[4]
[5]
VESD
HBM
CDM
-
-
V
[1] With xxx = SYNTH or VCO or RF2 or RF1 or DIG.
[2] With x = 0 or 1.
[3] With x = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 17 or 18.
[4] Testing for HBM discharge is performed as specified in JEDEC Standard JS-001.
[5] Testing for CDM discharge is performed as specified in JEDEC Standard JESD22-C101.
12. Recommended operating conditions
Table 14. Operating conditions
Symbol
VDDA
Parameter
Conditions
Min
Max
3.6
Unit
[1]
analog supply voltage
digital supply voltage
ambient temperature
2
V
VDDD
2
3.6
V
Tamb
standard range
40
+125
C
[1] To reach the maximum TX power, 2.8 V is the minimum.
13. Thermal characteristics
Table 15. Thermal characteristics
Symbol
Rth(j-a)
Rth(j-c)
Parameter
Conditions
Min
Typ
29.9
19
Max
Unit
thermal resistance from junction to ambient
thermal resistance from junction to case
maximum junction temperature
-
-
-
-
K/W
K/W
C
-
Tj(max)
-
130
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14. Characteristics
14.1 DC current
Table 16. Active processing
VDD = 2 V to 3.6 V; Tamb = 40C to +125 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
[1]
IDD
supply current
CPU in doze mode; analog and digital
with radio in receive mode; maximum input
level at 10 dBm; high-performance mode
-
-
14.8
12.7
-
-
mA
mA
with radio in receive mode; maximum input
level at 2 dBm; low-power mode
[2]
[2]
with radio in transmit mode 10 dBm
-
-
-
-
22.5
19.6
14
-
-
-
-
mA
mA
mA
mA
with radio in transmit mode 8.5 dBm
with radio in transmit mode 3 dBm
without radio
CPU processing at:
32 MHz
2
[3]
-
-
-
-
-
-
-
2.62
1.54
0.89
0.49
0.28
0.15
390
-
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
A
16 MHz
8 MHz
4 MHz
2 MHz
1 MHz
[4]
[5]
IDD(ADC)
IDD(comp)
ADC supply current
[5]
comparator supply
current
operating mode
low-power mode
-
-
-
-
-
70
-
-
-
-
-
A
A
A
A
A
0.62
60
[5]
[5]
[5]
IDD(UART)
IDD(tmr)
UART supply current per UART
timer supply current per timer
54
IDD(sintf)
serial interface supply SPI-bus supply current
current
40
[1] Doze mode = CPU is not clocked.
[2] To reach the maximum TX power, 2.8 V is the minimum.
[3] Digital consumption only. When in CPU doze, the current related to CPU speed is not consumed. This value should be added to the
CPU in doze mode supply current value.
[4] Temperature sensor and battery measurements require ADC.
[5] These numbers should be added to IDD if the feature is being used.
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Table 17. Sleep mode
VDD = 2 V to 3.6 V; Tamb = 40C to +125 C; unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ
Max Unit
[1]
[1]
IDD(IO)
I/O supply current
analog and digital supply current; with IO
and 1 RC oscillator timer wake-up;
-
0.61
-
A
T
amb = 25 °C
IDD(xtal)
crystal oscillator supply
current
for 32 kHz internal RC oscillator
HIGH current
-
-
-
-
0.76
0.40
0.6
-
-
-
-
A
A
A
A
LOW current
[2]
Iret(RAM)
RAM retention current
Tamb = 25 C
[1][2][3]
IDD(comp) comparator supply current low-power mode
0.62
[1] Waiting on IO event.
[2] RAM and comparator supply currents should be added to IDD(IO) if the feature is being used.
[3] Reduced response time.
Table 18. Deep sleep mode
VDD = 2 V to 3.6 V; Tamb = 40C to +125 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
100
Max
Unit
[1]
IDD
supply current
analog and digital supply current; deep
-
-
nA
sleep mode; measured at 25 C
[1] Waiting on chip RESET or IO event.
14.2 IO characteristics
Table 19. IO characteristics
VDD = 2 V to 3.6 V; Tamb = 40C to +125 C; unless otherwise specified.
Symbol
Parameter
internal pull-up resistance on pins DIOx[1]
Conditions
Min
40
Typ Max
Unit
Rpu(int)(DIO)
50
60
k
k
k
k
Rpu(int)(RESET_N) internal pull-up resistance on pin RESET_N VDD = 3.6 V
300
400
650
750
425 550
500 700
830 1100
VDD = 3.0 V
VDD = 2.2 V
VDD = 2.0 V
950 1350 k
Digital voltages
IO
VIH
HIGH-level input voltage
LOW-level input voltage
input hysteresis voltage
0.7VD
D
-
-
VDD
V
VIL
0.3
0.27V
V
DD
Vhys(i)
200
310 400
mV
Output on pins DIOx[1]
VOH
HIGH-level output voltage
6.8 mA load
6.8 mA load
VDD -
0.4
VDD
0.4
V
V
VOL
LOW-level output voltage
0
-
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Table 19. IO characteristics …continued
VDD = 2 V to 3.6 V; Tamb = 40C to +125 C; unless otherwise specified.
Symbol
Currents
ILIL
Parameter
Conditions
Min
Typ Max
Unit
LOW-level input leakage current
HIGH-level input leakage current
VDD = 3.6 V; Tamb = 25 C
VDD = 3.6 V; Tamb = 25 C
-
-
2
2
-
-
nA
nA
ILIH
[1] With x = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 17 or 18.
14.3 AC characteristics
14.3.1 Reset and Supply Voltage Monitor
Vth(POR)
V
DD
internal RESET
t
stab
aaa-017254
Fig 45. Internal Power-On Reset without showing Brown-Out
t
rst
RESET_N
V
rst
internal RESET
t
stab
aaa-017255
Fig 46. Externally applied reset
Table 20. Externally applied reset
Symbol Parameter
Conditions
Min
Typ
Max
Unit
[1]
[2]
trst
reset time
external reset pulse width to
initiate reset sequence
1
-
-
s
Vrst
reset voltage
external threshold voltage
0.7VDD
-
-
V
Vth(POR)
power-on reset threshold voltage rise time > 10 ms
rising
falling
-
-
1.44
1.41
-
-
V
V
spike
spike rejection
depth of pulse to trigger reset
1 s square wave
-
-
-
-
1.2
1.3
180
6
-
-
-
-
V
10 s triangular wave
V
[3]
tstab
IDD
stabilization time
supply current
reset
chip current when held in reset
s
A
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Table 20. Externally applied reset …continued
Symbol Parameter
Irst(bo) brownout reset current
Vth threshold voltage
Conditions
Min
Typ
Max
Unit
-
80
-
nA
supply threshold voltage
monitor; configurable in eight
levels
1.86
1.92
2.02
2.11
2.21
2.30
2.59
2.88
1.94
2.00
2.10
2.20
2.30
2.40
2.70
3.00
2.00
2.06
2.16
2.27
2.37
2.47
2.78
3.09
V
V
V
V
V
V
V
V
Vhys
hysteresis voltage
supply voltage monitor;
corresponding to the eight
threshold levels
-
-
-
-
-
-
-
-
37
38
45
52
58
65
82
100
-
-
-
-
-
-
-
-
mV
mV
mV
mV
mV
mV
mV
mV
[1] Assumes internal pull-up resistor value of 100 k worst case and 5 pF external capacitance.
[2] Minimum voltage to avoid being reset.
[3] Time from release of reset to start of executing of bootloader code from internal Flash. An extra 15 s is incurred if the BOR circuit has
been activated (e.g. if the supply voltage has been ramped up from 0 V).
V
+ V
hys
th
V
th
V
th(POR)
th(POR)
V
V
DDD
internal SVM
internal BOReset
aaa-017274
Fig 47. Brown-Out Reset followed by Supply Voltage Monitor trigger
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14.3.2 SPI-bus master timing
(1)
SPISELx
t
su(S)
t
h(S)
SPICLK
(mode = 0, 1)
T
clk
SPICLK
(mode = 2, 3)
t
h(D)
SPIMISO
(mode = 0, 2)
t
t
h(D)
su(D)
SPIMISO
(mode = 1, 3)
t
t
su(D)
d(Q)
SPIMOSI
(mode = 1, 3)
t
d(Q)
SPIMOSI
(mode = 0, 2)
aaa-017275
(1) With x = 0, 1 or 2.
Fig 48. SPI-bus master timing
Table 21. SPI-bus master timing
Symbol
Tclk
Parameter
Conditions
Min
Typ
Max
Unit
clock period
62.5
-
-
ns
tsu(D)
data input set-up time
for SPI-bus clock on pin 23 DO0
3.3 V
16.7
18.2
21
-
-
-
-
-
-
ns
ns
ns
2.8 V
2.0 V
for SPI-bus clock on pin 36 DIO11
3.3 V
2.8 V
2.0 V
20.2
23.3
25.3
0
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
-
th(D)
td(Q)
tsu(S)
th(S)
data input hold time
data output delay time
chip select set-up time
chip select hold time
-
on SPIMOSI
-
15
-
60
30
0
SPICLK = 16 MHz
-
SPICLK < 16 MHz; mode = 0 or 2
SPICLK < 16 MHz; mode = 1 or 3
-
60
-
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14.3.3 SPI-bus slave timing
SPISSEL
T
clk
t
idle
t
t
h(S)
su(S)
SPISCLK
t
h(D)
t
su(D)
SPISMOSI
t
t
d(C-Q)
d(S-Q)
SPISMISO
aaa-017276
Fig 49. SPI-bus slave timing
Table 22. SPI-bus slave timing
Symbol Parameter
Conditions
Min
125
125
10
Typ
Max
Unit
ns
Tclk
clock period
-
-
-
-
-
-
tidle
idle time
-
ns
tsu(D)
th(D)
td(C-Q)
data input set-up time
data input hold time
-
ns
10
-
ns
clock to data output
delay time
SPISCLK falling edge to SPISMISO output
delay time
-
30
ns
td(S-Q)
tsu(S)
th(S)
chip select to data output SPISSEL falling edge to SPISMISO output
-
-
-
-
30
-
ns
ns
ns
delay time
delay time
chip select set-up time
SPISSEL falling edge to SPISCLK rising edge
delay time
30
30
chip select hold time
SPISCLK falling edge to SPISSEL rising edge
delay time
-
14.3.4 I2C-bus interface
SDA
SCL
t
r
t
r
t
t
t
w(spike)
t
f
t
SU;DAT
HD;STA
BUF
t
LOW
t
t
t
t
t
SU;STO
HD;STA HD;DAT
f
SU;STA
t
S
Sr
P
S
HIGH
aaa-015465
Fig 50. I2C-bus interface timing
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Table 23. I2C-bus interface
Symbol Parameter
Conditions
Standard mode
Min Max
100
Fast mode
Min Max
Unit
fclk
clock frequency
SCL; DIO4; pin 21
0
4
0
400
-
kHz
[1]
tHD;STA
hold time (repeated)
START condition
-
-
-
-
0.6
s
tLOW
LOW period of the
SCL clock
4.7
4
1.3
0.6
0.6
-
-
-
s
s
s
tHIGH
tSU;STA
HIGH period of the
SCL clock
set-up time for a
repeated START
condition
4.7
tSU;DAT
tHD;DAT
tr
data set-up time
data hold time
rise time
data setup time SDA
data hold time SDA
rise time SDA and SCL
0.25
0[2]
-
-
0.1
0[2]
-
-
s
s
ns
-
[3]
[3]
1000
20 + 0.1 300
Cb
tf
fall time
fall time SDA and SCL
-
300
20 + 0.1 300
Cb
ns
s
s
tSU;STO
tBUF
set-up time for STOP
condition
4
-
-
0.6
-
bus free time
between a STOP
and START
condition
4.7
1.3
-
tw(spike)
Cb
spike pulse width
pulse width of spikes that will be
suppressed by input filters
-
60
400
-
-
60
400
-
ns
pF
V
capacitive load for
each bus line
-
-
VnL
noise margin at the noise margin at the LOW level for
0.1VDD
0.1VDD
LOW level
each connected device (including
hysteresis)
VnH
noise margin at the noise margin at the HIGH level for
0.2VDD
-
0.2VDD
-
V
HIGH level
each connected device (including
hysteresis)
[1] After this period, the first clock pulse is generated.
[2] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the CLK signal) to bridge
the undefined region of the falling edge of CLK.
[3] Following the I2C-bus specifications.
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14.3.5 Wake-up timings
Table 24. Wake-up timings
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tstartup
start-up time
CPU start up time; time for crystal to stabilize
ready to run CPU; reached oscillator amplitude
threshold. Default bias current
-
0.87
-
ms
radio start-up time; time for crystal to stabilize
ready for radio activity
-
1.10
-
ms
from reset RESET_N pin, BOR or SVM
-
-
310
300
-
-
s
s
twake
wake-up time
from deep sleep mode or sleep mode without
RAM retention
from sleep mode with RAM retention
from CPU Doze mode
-
-
210
7
-
-
s
s
14.3.6 Band gap reference
Table 25. Band gap reference
VDD = 2 V to 3.6 V; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDA(bg)
band gap analog
supply voltage
1.198 1.235 1.260
V
14.3.7 Analog to Digital Converters
Table 26. Analog to Digital Converters
VDD = 3 V; Vref = 1.2 V; Tamb = -40 C to +125 C; unless otherwise specified.
Symbol
Vi
Parameter
Conditions
Min
Typ
-
Max
Unit
[1]
[2]
input voltage
reference voltage
switchable
0.04
2Vref
V
Vref
internal
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
external; allowable range into VREF pin
1.2
400
1.6
1.8
0.5
10
20
10
20
V
IADCx
INL
current on pins ADCx[3]
integral non-linearity
A
LSB
LSB
LSB
mV
mV
mV
mV
Tamb = 40 C to +85C
Tamb = 40 C to +125C
DNL
EO
differential non-linearity
offset error
0 to Vref range
0 to 2 Vref range
0 to Vref range
EG
gain error
0 to 2 Vref range
[4]
fclk(int)
internal clock frequency 16 MHz input clock
16
32
64
-
1
-
MHz
MHz
MHz
s
-
0.5
0.25
-
-
-
-
tconv
Ci(a)
conversion time
programmable
9.5
-
148
-
analog input capacitance in series with 5 k resistor
8
pF
[1] See Section 9.16.1.1.
[2] See Section 14.3.6.
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[3] With x = 1, 2, 3, 4, 5 or 6.
[4] Number of internal clock periods to sample input (programmable at 2, 4, 6 or 8).
14.3.8 Comparator
Table 27. Comparator
VDD = 2 V to 3.6 V; Tamb = 40 °C to +125C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
90
Max
Unit
ns
[1]
[2]
[3]
tresp
response time
operating mode
low-power mode
-
-
-
-
-
-
2.2
130
ns
tres(tot)
Vhys
total response time
hysteresis voltage
operating mode; including delay to interrupt
controller
ns
programmable in 3 steps
-
10
20
40
-
-
mV
mV
mV
V
-
-
-
-
[4]
Vref
reference voltage
-
-
VI(cm)
common-mode input
voltage
0
-
VDD
V
II
input current
operating mode
low-power mode
-
-
73
-
-
A
A
0.8
[1] 250 mV overdrive; 10 pF load.
[2] 250 mV overdrive; no digital delay.
[3] Digital delay can be up to a maximum of two 16 MHz clock periods.
[4] See Section 14.3.6.
14.3.9 32 kHz RC oscillator
Table 28. 32 kHz RC oscillator
VDD = 2 V to 3.6 V; Tamb = 40C to +125C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
[1]
fxtal
crystal frequency
accuracy
32 kHz clock uncalibrated accuracy; without
temperature and voltage variation
32 21% 32
32 +
53%
kHz
calibration done in operating mode; calibrated
32 kHz accuracy; for a 1 s sleep period
calibrating over 20 x 32 kHz clocks periods
-
-
300
-
ppm
ppm
calibration done in low-power mode; calibrated
32 kHz accuracy; for a 1 s sleep period
calibrating over 20 x 32 kHz clocks periods
600
-
[1] Measured at 3 V and 25 °C.
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14.3.10 32 kHz crystal oscillator
Table 29. 32 kHz crystal oscillator
VDD = 2 V to 3.6 V; Tamb = 40C to +125C; unless otherwise specified.
Symbol Parameter
IDD(xtal) crystal oscillator supply current of cell and counter-logic
tstartup start-up time
Conditions
Min
Typ
0.6
0.6
Max
Unit
A
s
[1]
[2]
-
-
-
-
[1] This is sensitive to the ESR of the crystal, VDD and total capacitance at each pin.
[2] Assuming crystal with ESR of less than 40 , CL = 9 pF and external capacitances = 15 pF (VDD / 2 mV(p-p).
When external 32 kHz oscillator is used, external capacitances of 15 pF are implemented.
Total external capacitance needs to be 2 CL, allowing for stray capacitance from chip,
package and PCB (CL = 9 pF).
14.3.11 32 MHz crystal oscillator
Table 30. 32 MHz crystal oscillator
VDD = 2 V to 3.6 V; Tamb = 40C to +125C; unless otherwise specified.
Symbol Parameter Conditions
Min
Typ
275
0.87
Max
Unit
A
[1]
[2]
IDD(xtal)
tstartup
crystal oscillator supply current of cell and counter-logic
start-up time
-
-
-
-
ms
[1] Excluding band gap ref.
[2] Assuming crystal with ESR of less than 40 , CL = 9 pF and external capacitances = 12 pF (VDD / 2 mV(p-p).
When external 32 MHz oscillator is used, external capacitances of 12 pF are
implemented. Total external capacitance needs to be 2 CL, allowing for stray
capacitance from chip, package and PCB (CL = 9 pF).
14.3.12 High-speed RC oscillator
Table 31. High-speed RC oscillator
VDD = 2 V to 3.6 V; Tamb = 40C to +125C; unless otherwise specified.
Symbol Parameter
IDD(xtal)
fosc
Conditions
Min
Typ
Max
Unit
crystal oscillator supply current of cell
-
145
-
A
oscillator frequency
uncalibrated
calibrated
26.1 16% 26.1
32.1 4% 32.1
26.1 18% MHz
32.1 + 5%
-
MHz
tstartup
start-up time
-
2.4
s
14.3.13 Temperature sensor
Table 32. Temperature sensor
VDD = 2 V to 3.6 V; Tamb = 40C to +125C; unless otherwise specified.
Symbol
Tsen
Parameter
Conditions
Min
Typ
Max
Unit
sensor temperature
sensor gain
40
-
+125
°C
Gsen
-
-
1.66
7
-
-
mV/°C
°C
Tsen
sensor temperature
accuracy
[1]
Vo
output voltage
sensor voltage
540
-
-
840
-
mV
mV
Vsen
at VDD = 3.0 V and Tamb = 25 °C
720
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[1] Includes absolute variation due to manufacturing and temperature.
14.3.14 Non-volatile memory
Table 33. Non-volatile memory
VDD = 2 V to 3.6 V; Tamb = 40C to +125C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
100
1000
100
1.0
1.8
1.1
-
Max
Unit
kCycle
kCycle
ms
[1]
[2]
Nendu
endurance
Flash; program/erase
10
-
-
-
-
-
-
-
EEPROM; program/erase
Flash; one sector
100
ter
erase time
-
tprog
ter
tprog
tret
programming time
erase time
Flash; per page of 256 bytes
EEPROM; one 64-byte page
EEPROM; between 1 byte and 64 bytes
powered; Flash and EEPROM
-
ms
-
ms
programming time
retention time
-
ms
10
year
[1] See Section 9.3.2.
[2] See Section 9.3.4.
14.3.15 Radio transceiver
This JN517x meets all the requirements of the IEEE802.15.4 standard over 2.0 V to 3.6 V
and offers the improved RF characteristics shown in Table 34. All RF characteristics are
measured single ended.
This part also meets the following regulatory body approvals, when used with NXP’s
Module Reference Designs. Compliant with FCC part 15 rules, IC Canada and ETSI ETS
300-328, refer to the JN517x Module Reference Design package on the Wireless
Connectivity area of the NXP web site Ref. 2.
The PCB schematic and layout rules detailed in Section 15 must be followed. Failure to do
so will likely result in the JN517x failing to meet the performance specification detailed
herein and worst case may result in device not functioning in the end application.
Table 34. RF port characteristics
Single-ended; Impedance = 50 [1]; VDD = 2 V to 3.6 V; Tamb = 40C to +125C; unless otherwise specified.
Symbol
frange
Parameter
Conditions
Min
Typ
Max
Unit
frequency range
2.4
-
2.485 GHz
-
VESD
electrostatic discharge
voltage
pin 13
HBM
CDM
-
-
-
-
2
-
-
kV
V
500
[1] With external matching inductors and assuming PCB layout as inSection 15.1.1.
Table 35. Radio transceiver characteristics: +25 C
VDD = 2 V to 3.6 V; unless otherwise specified.
Symbol
Receiver
SRX
Parameter
Conditions
Min
Typ
Max
Unit
receiver sensitivity
nominal for 1 % PER, as per 802.15.4
-
96
93.5 dBm
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Table 35. Radio transceiver characteristics: +25 C …continued
VDD = 2 V to 3.6 V; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Pi(RX)(max) maximum receiver input 1 % PER, measured as sensitivity; supply
-
10
-
dBm
power
current at 14.8 mA; high-performance mode
1 % PER, measured as sensitivity; supply
current at 12.7 mA; low-power mode
-
2
-
dBm
ch
channel rejection
1 % PER, with wanted signal 3 dB, above sensitivity as per 802.15.4
modulated interferer[1][2]
1 channel
+1 channel
2 channel
+2 channel
co-channel
CW interferer[1][2]
1 channel
+1 channel
2 channel
+2 channel
-
-
-
-
-
19
34
40
44
7
-
-
-
-
-
dBc
dBc
dBc
dBc
dBc
-
-
-
-
-
25
50
57
60
43
-
-
-
-
-
dBc
dBc
dBc
dBc
dBc
[1]
[1]
ib
in-band rejection
1 % PER with wanted signal 3 dB above
sensitivity; 2.4 GHz to 2.4835 GHz;
modulated interferers at 3 channel
separation
oob
out-of-band rejection
1 % PER with wanted signal 3 dB above
sensitivity
all frequencies except wanted/2 which is
8 dB lower
-
45
-
dBc
3G frequency at 2.1 GHz
LTE frequency at 2.5 GHz
-
-
5
-
-
dBm
dBm
18
Psp(RX)
receiver spurious power measured conducted into 50
30 MHz to 1 GHz
-
-
-
-
-
-
70
70
55
dBm
dBm
dBm
1 GHz to 12 GHz
PL(lo)
IMP
local oscillator leakage
power
[1]
intermodulation
protection
1 % PER at with wanted signal 3 dB above
sensitivity; modulated interferers at 3 and 6
channel separation
-
46
-
-
dB
dB
RSSI
RSSI variation
95 dBm to 10 dBm; available through
4
+4
JN517x Integrated Peripherals API
Transmitter
Po
[3]
[4]
output power
PA = 5 and Att. 2.5 dB OFF
- 10
42
-
-
dBm
dB
Po(cr)
control range output
power
in 6 major steps and then 4 fine steps
-
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Table 35. Radio transceiver characteristics: +25 C …continued
VDD = 2 V to 3.6 V; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Psp(TX)
transmitter spurious
power
measured conducted into 50
30 MHz to 1 GHz
-
-
-
-
65
36
dBm
dBm
1 GHz to 12.5 GHz (harmonic H2)
exceptions
1.8 GHz to 1.9 GHz
-
-
-
-
-
65
65
-
dBm
dBm
%
5.15 GHz to 5.3 GHz
at maximum output power
at maximum output power
-
EVM
error vector magnitude
8
3
EVMoffset
error vector magnitude
offset
4.5
%
[5]
[5]
PSD
power spectral density
relative density at greater than 3.5 MHz
offset
-
-
38
32
20
dBc
absolute density at greater than 3.5 MHz
offset
-
dBm
[1] Blocker rejection is defined as the value, when 1 % PER is seen with the wanted signal 3 dB above sensitivity, as per IEE802.15.4.
[2] Channels 11, 17, 24 low/high values reversed.
[3] To reach the maximum TX power, 2.8 V is the minimum on VDDA
[4] Up to an extra 2.5 dB of attenuation is available if required.
[5] See IEEE802.15.4.
.
Table 36. Radio transceiver characteristics: 40 C
VDD = 2 V to 3.6 V; unless otherwise specified.
Symbol
Receiver
SRX
Parameter
Conditions
Min
Typ
Max
Unit
receiver sensitivity
nominal for 1 % PER, as per 802.15.4
-
-
96.5
-
-
dBm
dBm
Pi(RX)(max) maximum receiver input 1 % PER, measured as sensitivity; supply
10
power
current at 14.8 mA; high-performance mode
1 % PER, measured as sensitivity; supply
current at 12.7 mA; low-power mode
-
2
-
dBm
ch
channel rejection
1 % PER, with wanted signal 3 dB, above sensitivity as per 802.15.4
modulated interferer[1][2]
1 channel
+1 channel
2 channel
+2 channel
co-channel
-
-
-
-
-
-
19
34
40
44
7
43
-
-
-
-
-
-
dBc
dBc
dBc
dBc
dBc
dBc
[1]
[1]
ib
in-band rejection
1 % PER with wanted signal 3 dB above
sensitivity; 2.4 GHz to 2.4835 GHz;
modulated interferers at 3 channel
separation
oob
out-of-band rejection
1 % PER with wanted signal 3 dB above
sensitivity; all frequencies except wanted/2
which is 8 dB lower
-
45
-
dBc
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Table 36. Radio transceiver characteristics: 40 C …continued
VDD = 2 V to 3.6 V; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Psp(RX)
receiver spurious power measured conducted into 50
30 MHz to 1 GHz
-
-
-
-
-
-
70
70
54
dBm
dBm
dBm
1 GHz to 12 GHz
PL(lo)
IMP
local oscillator leakage
power
[1]
intermodulation
protection
1 % PER at with wanted signal 3 dB above
sensitivity; modulated interferers at 3 and 6
channel separation
-
-
45
-
-
dB
dB
RSSI
RSSI variation
output power
95 dBm to 10 dBm; available through
JN517x Integrated Peripherals API
4
Transmitter
Po
[3]
[4]
PA = 5 and Att. 2.5 dB OFF
- 10
-
-
dBm
dB
Po(cr)
control range output
power
in 6 major steps and then 4 fine steps
-
42
Psp(TX)
transmitter spurious
power
measured conducted into 50
30 MHz to 1 GHz
-
-
-
-
65
36
dBm
dBm
1 GHz to 12.5 GHz (harmonic H2)
exceptions
1.8 GHz to 1.9 GHz
-
-
-
-
-
65
dBm
dBm
%
5.15 GHz to 5.3 GHz
-
65
EVM
error vector magnitude
at maximum output power
at maximum output power
8
3
-
-
EVMoffset
error vector magnitude
offset
%
[5]
[5]
PSD
power spectral density
relative density at greater than 3.5 MHz
offset
-
-
38
32
-
-
dBc
absolute density at greater than 3.5 MHz
offset
dBm
[1] Blocker rejection is defined as the value, when 1 % PER is seen with the wanted signal 3 dB above sensitivity, as per IEE802.15.4.
[2] Channels 11, 17, 24 low/high values reversed.
[3] To reach the maximum TX power, 2.8 V is the minimum on VDDA
[4] Up to an extra 2.5 dB of attenuation is available if required.
[5] See IEEE802.15.4.
.
Table 37. Radio transceiver characteristics: +125 C
VDD = 2 V to 3.6 V; unless otherwise specified.
Symbol
Receiver
SRX
Parameter
Conditions
Min
Typ
Max
Unit
receiver sensitivity
nominal for 1 % PER, as per 802.15.4
-
-
94
-
-
dBm
dBm
Pi(RX)(max) maximum receiver input 1 % PER, measured as sensitivity; supply
5
power
current at 14.8 mA; high-performance mode
1 % PER, measured as sensitivity; supply
current at 12.7 mA; low-power mode
-
10
-
dBm
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Table 37. Radio transceiver characteristics: +125 C …continued
VDD = 2 V to 3.6 V; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
ch
channel rejection
1 % PER, with wanted signal 3 dB, above sensitivity as per 802.15.4
modulated interferer[1][2]
1 channel
+1 channel
2 channel
+2 channel
co-channel
-
-
-
-
-
-
18
31
38
42
7
41
-
-
-
-
-
-
dBc
dBc
dBc
dBc
dBc
dBc
[1]
[1]
ib
in-band rejection
1 % PER with wanted signal 3 dB above
sensitivity; 2.4 GHz to 2.4835 GHz;
modulated interferers at 3 channel
separation
oob
out-of-band rejection
1 % PER with wanted signal 3 dB above
sensitivity; all frequencies except wanted/2
which is 8 dB lower
-
42
-
dBc
Psp(RX)
receiver spurious power measured conducted into 50
30 MHz to 1 GHz
-
-
-
-
-
-
70
70
56
dBm
dBm
dBm
1 GHz to 12 GHz
PL(lo)
IMP
local oscillator leakage
power
[1]
intermodulation
protection
1 % PER at with wanted signal 3 dB above
sensitivity; modulated interferers at 3 and 6
channel separation
-
-
45
-
-
dB
dB
RSSI
RSSI variation
output power
95 dBm to 10 dBm; available through
JN517x Integrated Peripherals API
4
Transmitter
Po
[3]
[4]
PA = 5 and Att. 2.5 dB OFF
- 10
-
-
dBm
dB
Po(cr)
control range output
power
in 6 major steps and then 4 fine steps
-
42
Psp(TX)
transmitter spurious
power
measured conducted into 50
30 MHz to 1 GHz
-
-
-
-
65
36
dBm
dBm
1 GHz to 12.5 GHz (harmonic H2)
exceptions
1.8 GHz to 1.9 GHz
-
-
-
-
-
65
dBm
dBm
%
5.15 GHz to 5.3 GHz
-
65
EVM
error vector magnitude
at maximum output power
at maximum output power
8
3
-
-
EVMoffset
error vector magnitude
offset
%
[5]
[5]
PSD
power spectral density
relative density at greater than 3.5 MHz
offset
-
-
38
32
-
-
dBc
absolute density at greater than 3.5 MHz
offset
dBm
[1] Blocker rejection is defined as the value, when 1 % PER is seen with the wanted signal 3 dB above sensitivity, as per IEE802.15.4.
[2] Channels 11, 17, 24 low/high values reversed.
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[3] To reach the maximum TX power, 2.8 V is the minimum on VDDA
[4] Up to an extra 2.5 dB of attenuation is available if required.
[5] See IEEE802.15.4.
.
15
10
5
Major steps
(PA = 5)
(PA = 4)
0
-5
(PA = 3)
(PA = 2)
-10
-15
-20
-25
-30
-35
(PA = 1)
(PA = 0)
Att 2.5 dB ON
Att 2.5 dB OFF
aaa-018591
At VDD = 3 V and Tamb = 25 °C on channel 17. In complete temperature range and over all
channels, min and max values equal nominal value 1 dB.
Fig 51. Typical control range output power
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aaa-023977
11
Tx output power
(dBm)
9
7
5
3
PA5 boost
3
PA5
PA4
1
2
2.2
2.4
2.6
2.8
3.2
V
3.4
3.6
supply voltage (V)
CC
Fig 52. Typical transmit output power versus voltage
aaa-018592
-94
Sensitivity
-95
-96
-97
-40
-20
0
20
40
60
80
100
120
140
Temp (°C)
Fig 53. Typical receiver sensitivity versus temperature
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aaa-021249
20
Max input
power
(dBm)
sum of high perf
poly (sum of high perf)
10
0
-10
-20
sum of low power
poly (sum of low power)
25
55
65
75
85
95 105 115 125
Temp (°C)
Fig 54. Maximum input level
15. Application information
15.1 JN517x module reference designs
For customers wishing to integrate the JN517x device directly into their system, NXP
provides a range of Module Reference Designs.
To ensure the correct performance, it is strongly recommended that where possible the
design details provided by the reference designs, are used in their exact form for all end
designs, this includes component values, pad dimensions, track layouts etc. In order to
minimize all risks, it is recommended that the entire layout of the appropriate reference
module, if possible, be replicated in the end design.
For full details, contact technical support.
15.1.1 Schematic diagrams
Schematic diagrams of the JN517x reference module is shown in Figure 55.
JN517X
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C13
n.c.
n.c. n.c.
100 nF
IC1
V
DIO15
DIO17
DDD
V
1
2
30
29
28
27
26
25
24
23
22
21
DD
DIO10
DIO9
DIO8
DIO7
DIO6
C9
100 nF
UART0
DIO18
C14
3
RESET_N
XTAL_OUT
XTAL_IN
VB_SYNTH
VB_VCO
4
12 pF
Y1
5
32 MHz
C8
6
(1)
12 pF
DO1
7
(2)
VSSA (paddle)
DO0
C7
100 nF
8
V
DDA
DIO5
DIO4
9
C5
10 nF
IBIAS
10
C16
10 μF
C6
100 nF
V
DD
R1
43 kΩ
1%
C3
100 nF
C4
47 pF
L2
3 nH
To coaxial socket
C2
1.8 pF
L1
or integrated antenna
4.3 nH
50 ohms line
C1
1.8 pF
aaa-018140
In that configuration, an external low ohmic supply voltage shall be delivered to VDDA and VDDD pins. VDDA and VDDD voltages
shall be minimum 2.0 V and maximum 3.6 V, the supply source shall be connected directly to the device pins without any serial
resistor.
To ease the layout implementation and improve the GND plane pins 31,32 and 34 can be connected to GND.
(1) The JN517x will enter UART programming mode if SPIMISO (DO1) pin 24 is low after RESET.
(2) The JN517x will enter JTAG programming mode if SPICLK (DO0) pin 23 is low after RESET.
Fig 55. JN517x module reference design using low voltage supply
Table 38. Components
Component Function
Value
1 pF
Remarks
C1
C2
C3
C4
C5
C6
C7
C8
C9
RF matching capacitor
COG type
[1]
AC coupling
1.8 pF
100 nF
47 pF
10 nF
COG type
VB RF decoupling
VB RF decoupling
VB VCO decoupling
locate less than 5 mm from IC1 pin 12 and IC1 pin 14
locate less than 5 mm from IC1 pin 12 and IC1 pin 14
locate less than 5 mm from IC1 pin 8
locate less than 5 mm from IC1 pin 9
locate less than 5 mm from IC1 pin 7
adjacent to pin 6 and Y1 pin 3
adjacent to IC1 pin 30
analog power decoupling 100 nF
VB synth decoupling 100 nF
crystal load capacitance 12 pF 5 % COG
digital power decoupling 100 nF
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Table 38. Components …continued
Component Function
Value
Remarks
C13
C14
C16
L1
VB Dig decoupling
100 nF
locate less than 5 mm from IC1 pin 35
adjacent to pin 5 and Y1 pin 1
crystal load capacitance 12 pF 5 % COG
power source decoupling 10 F
[1]
[1]
RF matching inductor
4.3 nH
Murata LQP15MN4N3B02 can be used up to 85 °C;
Murata LQG15MN4N3B02 can be used up to 125 °C
L2
load inductor
3 nH
Murata LQP15MN3N0B02 can be used up to 85 °C;
Murata LQG15MN3N0B02 can be used up to 125 °C
R1
Y1
IBIAS resistor
crystal
43 k 1%
32 MHz; CL = 9 pF
AEL X32M000000S039 or
NDK NX3225SA EXS00A-CS08207 or NX2016SA
32 MHz EXS00A-CS07977 or
Murata XR16GD32M000KYQ01R0 (2016) or
Epson Toyocom X1E000021016700
[1] Must be copied directly from the reference design.
The paddle should be connected directly to ground. Any pads that require connection to
ground should do so by connecting directly to the paddle.
15.1.2 Application diagram with Pi filter
Extra pi filter is recommended on RF path to insure a successful FCC certification
regarding H2 spurs. This is the implemented solution for the NXP modules available on
the market.
IBIAS
R1
43 kꢀ
1 %
C3
100 nF
C4
47 pF
L2
1.5 nH
To coaxial socket
C2
1.8 pF
L4
L1
or integrated antenna
2.7 nH
3.9 nH
50 ohms line
C18
1.2 pF
C1
1.2 pF
aaa-022076
Fig 56. Application diagram with Pi filter
Table 39. Components
Component Function
Value
1.2 pF
1.8 pF
100 nF
Remarks
COG type
COG type
[1]
[1]
C1
C2
C3
RF matching capacitor
AC coupling
VB RF decoupling
locate less than 5 mm from U1 pin 12 and U1 pin 14
JN517X
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Table 39. Components …continued
Component Function
Value
47 pF
1.2 pF
3.9 nH
Remarks
C4
VB RF decoupling
locate less than 5 mm from U1 pin 12 and U1 pin 14
COG type
C18
L1
RF filtering capacitor
RF matching inductor
[1]
[1]
[1]
MuRata LQP15MN3N9B02 can be used up to 85 °C;
MuRata LQG15MN3N9B02 can be used up to 125 °C
L2
L4
R1
load inductor
1.5 nH
MuRata LQP15MN1N5B02 can be used up to 85 °C;
MuRata LQG15MN1N5B02 can be used up to 125 °C
filtering inductor
IBIAS resistor
2.7 nH
MuRata LQP15MN2N7B02 can be used up to 85 °C;
MuRata LQG15MN2N7B02 can be used up to 125 °C
43 k 1%
[1] Must be copied directly from the reference design.
15.1.3 PCB design and reflow profile
PCB and land pattern designs are key to the reliability of any electronic circuit design.
The Institute for Interconnecting and Packaging Electronic Circuits (IPC) defines a
number of standards for electronic devices. One of these is the "Surface Mount Design
and Land Pattern Standard" IPC-SM-782 commonly referred to as “IPC782". This
specification defines the physical packaging characteristics and land patterns for a range
of surface-mounted devices. IPC782 is also a useful reference document for general
surface mount design techniques, containing sections on design requirements, reliability
and testability. NXP strongly recommends that this be referred to when designing the
PCB.
NXP also provides an Application Note AN10366, “HVQFN application information”, which
describes the reflow soldering process, refer also to Section 18.
15.1.4 Moisture sensitivity level (MSL)
If there is moisture trapped inside a package, and the package is exposed to a reflow
temperature profile, the moisture may turn into steam, which expands rapidly. This may
cause damage to the inside of the package (delamination), and it may result in a cracked
semiconductor package body (the popcorn effect). A package’s MSL depends on the
package characteristics and on the temperature it is exposed to during reflow soldering,
refer also to Section 18.
Depending on the damage after this test, an MSL of 1 (not sensitive to moisture) to 6 (very
sensitive to moisture) is attached to the semiconductor package.
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16. Footprint information for reflow soldering
Footprint information for reflow soldering of HVQFN40 package
SOT618-8
Hx
Gx
D
0.105
0.125
C
nSPx
SPx
nSPy
SPy
Hy
Gy
SLy By Ay
SPx tot
X
SLx
Bx
Ax
0.29
0.24
0.85 0.9
solder land
solder land plus solder paste
occupied area
nSPx nSPy
detail X
solder paste deposit
Dimensions in mm
3
3
Recommended stencil thickness: 0.1 mm
P
Ax
Ay
Bx
By
C
D
Gx
6.3
Gy
6.3
Hx
Hy
SLx
4.7
SLy
4.7
SPx
0.7
SPy
0.7
SPx tot SPy tot
0.5
7.0
7.0
5.2
5.2
0.9
0.29
7.25
7.25
2.7
2.7
15-04-29
15-04-30
Issue date
sot618-8_fr
Fig 57. Reflow soldering information for the HVQFN40 package
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17. Package outline
HVQFN40: plastic thermal enhanced very thin quad flat package; no leads;
40 terminals; body 6 x 6 x 0.85 mm
SOT618-8
D
B
A
terminal 1
index area
E
A
A
1
c
detail X
e
1
1/2 e
C
v
w
C
C
A
B
e
y
y
b
C
1
11
20
L
21
10
e
E
h
e
2
1/2 e
1
30
terminal 1
index area
40
31
X
D
h
0
2.5
scale
5 mm
v
Dimensions
Unit
(1)
(1)
(1)
A
A
1
b
c
D
D
E
E
e
e
e
L
w
y
y
1
h
h
1
2
max 1.00 0.05 0.30
6.1 4.85 6.1 4.85
0.5
mm nom 0.85 0.02 0.21 0.2 6.0 4.70 6.0 4.70 0.5 4.5 4.5 0.4 0.1 0.05 0.05 0.1
min 0.80 0.00 0.18
5.9 4.55 5.9 4.55
0.3
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
sot618-8_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
- - -
13-11-19
14-01-16
SOT618-8
MO-220
Fig 58. Package outline SOT618-8 HVQFN40
JN517X
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18. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
18.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
18.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering
18.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
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18.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 59) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder
paste characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 40 and 41
Table 40. SnPb eutectic process (from J-STD-020D)
Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350
235
350
220
< 2.5
2.5
220
220
Table 41. Lead-free process (from J-STD-020D)
Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350
260
350 to 2000
> 2000
260
< 1.6
260
250
245
1.6 to 2.5
> 2.5
260
245
250
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 59.
JN517X
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maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 59. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
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19. Abbreviations
Table 42. Abbreviations
Acronym
ADC
ADE
ADO
AES
AGC
API
Description
Analog to Digital Converter
Antenna diversity Even
Antenna diversity Odd
Advanced Encryption Standard
Automatic Gain Control
Application Program Interface
Analog Peripheral Timer
Bill Of Material
APT
BOM
BOR
CCA
CCM
CDM
CLK
CPU
CRC
CSMA/CA
CTS
CW
Brown-Out Reset
Clear Channel Assessment
Counter with CBC-MAC
Charged Device Model
CLocK
Central Processing Unit
Cyclic redundancy Check
Carrier Sense Multiple Access with Collision Avoidance
Clear-To-Send
Continuous Wave
DC
Direct current
DIO
Digital Input Output
DMA
DO
Direct memory Access
Digital Output
ED
Energy Detection
EEPROM
ESR
FIFO
GP
Electrically-Erasable Programmable Read Only Memory
Equivalent Series Resistance
First In First Out
General Purpose
GPIO
HBM
HS
General Purpose Input Output
Human Body Model
High Speed
HVQFN
ID
Heatsink Very-thin Quad Flat No-Leads
IDentification
IF
Intermediate frequency
Input Output
IO
IoT
Internet of Things
IPC
Interconnecting and Packaging Electronic Circuits
Joint Test Action Group
Low Noise Amplifier
JTAG
LNA
LQI
Link Quality Indication
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Table 42. Abbreviations …continued
Acronym
Description
LSB
Low Significant Bit
MAC
MSB
MSIF
MSL
Media Access Control
Most Significant Bit
Master Serial InterFace
Moisture sensitivity level
Not ACKnowledge
NACK
NFET
NRZ
Negative Field Effect Transistor
Non-Return-to-Zero
Nested Vector Interrupt Controller
On-Off Key
NVIC
OOK
OTA
Over-The-Air
OTP
One Time Programmable
Power Amplifier
PA
PAN
Personal Area Network
Printed-Circuit Board
Persistent Data Manager
PHYsical
PCB
PDM
PHY
PLL
Phase-Locked Loop
Power-On Reset
POR
PPF
Palladium Pre Plated
Pulse Width Modulation
Random Access Memory
Radio Frequency
PWM
RAM
RF
RoHS
RSSI
RTS
Restriction of Hazardous Substances
Receive Signal Strength Indication
Request-To-Send
RTOS
RTZ
Real-Time Operating System
Return-To-Zero
RX
Received
SCL
Serial CLock
SDA
Serial DatA
SDK
Software Developer’s Kit
System Management bus
Surface Mount Devices
Single-Pole Double-Throw
Serial Peripheral Interface -bus
Slave Transmitter Stop Detect
Slave Serial InterFace
Supply Voltage Monitor
SYNTHesizer
SMbus
SMDs
SPDT
SPI-bus
STSD
SSIF
SVM
SYNTH
SysTick
System Tick timer
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Table 42. Abbreviations …continued
Acronym
Description
TAF
Transmitter Arbitration Failure
Tightly-Coupled Memory
Transmit
TCM
TX
UART
VCO
VTOR
Universal Asynchronous Receiver Transmitter
Voltage Controlled Oscillator
Vector Table Offset Register
20. References
[1] IEEE Std 802.15.4-2011 IEEE Standard for Information Technology Part
15.4 — Wireless Medium Access Control (MAC) and Physical Layer (PHY)
Specifications for Low-Rate Wireless Personal Area Networks (LR-WPANs).
[2] Wireless Connectivity —
http://www.nxp.com/products/wireless-connectivity:WIRELESS-CONNECTIVITY
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21. Revision history
Table 43. Revision history
Document ID
JN517x v3.0
JN517x v2.0
JN517x v1.0
Release date
Data sheet status
Product data sheet
Product data sheet
Product data sheet
Change notice
Supersedes
JN517x v2.0
JN517x v1.0
-
20171107
20161108
20160805
-
-
-
JN517X
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22. Legal information
22.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use — NXP Semiconductors products are not designed,
22.2 Definitions
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
22.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
JN517X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet
Rev. 3.0 — 7 November 2017
95 of 100
JN517x
NXP Semiconductors
IEEE802.15.4 Wireless Microcontroller
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
22.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
I2C-bus — logo is a trademark of NXP Semiconductors N.V.
ICODE and I-CODE — are trademarks of NXP Semiconductors N.V.
23. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
JN517X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet
Rev. 3.0 — 7 November 2017
96 of 100
JN517x
NXP Semiconductors
IEEE802.15.4 Wireless Microcontroller
24. Tables
Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .5
Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .8
Table 3. Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . .25
Table 4. SPI-bus master I/O . . . . . . . . . . . . . . . . . . . . . .35
Table 5. SPI-bus configurations . . . . . . . . . . . . . . . . . . .36
Table 6. SPI-bus slave I/O . . . . . . . . . . . . . . . . . . . . . . .37
Table 7. Timer and PWM I/O . . . . . . . . . . . . . . . . . . . . .39
Table 8. UART I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Table 9. 2-wire serial interface I/O . . . . . . . . . . . . . . . . .49
Table 10. I2C-bus TX_FIFO master transmitter writing data
example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Table 11. I2C-bus RX_FIFO master receiver reading data
example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Table 12. ADC maximum input range. . . . . . . . . . . . . . . .58
Table 13. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .63
Table 14. Operating conditions . . . . . . . . . . . . . . . . . . . .64
Table 15. Thermal characteristics . . . . . . . . . . . . . . . . . .64
Table 16. Active processing . . . . . . . . . . . . . . . . . . . . . . .65
Table 17. Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Table 18. Deep sleep mode . . . . . . . . . . . . . . . . . . . . . . .66
Table 19. IO characteristics . . . . . . . . . . . . . . . . . . . . . . .66
Table 20. Externally applied reset . . . . . . . . . . . . . . . . . .67
Table 21. SPI-bus master timing . . . . . . . . . . . . . . . . . . .69
Table 22. SPI-bus slave timing . . . . . . . . . . . . . . . . . . . .70
Table 23. I2C-bus interface . . . . . . . . . . . . . . . . . . . . . . .71
Table 24. Wake-up timings . . . . . . . . . . . . . . . . . . . . . . .72
Table 25. Band gap reference . . . . . . . . . . . . . . . . . . . . .72
Table 26. Analog to Digital Converters . . . . . . . . . . . . . .72
Table 27. Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Table 28. 32 kHz RC oscillator . . . . . . . . . . . . . . . . . . . .73
Table 29. 32 kHz crystal oscillator . . . . . . . . . . . . . . . . . .74
Table 30. 32 MHz crystal oscillator . . . . . . . . . . . . . . . . .74
Table 31. High-speed RC oscillator . . . . . . . . . . . . . . . . .74
Table 32. Temperature sensor . . . . . . . . . . . . . . . . . . . . .74
Table 33. Non-volatile memory . . . . . . . . . . . . . . . . . . . .75
Table 34. RF port characteristics . . . . . . . . . . . . . . . . . . .75
Table 35. Radio transceiver characteristics: +25 °C . . . .75
Table 36. Radio transceiver characteristics: -40 °C . . . . .77
Table 37. Radio transceiver characteristics: +125 °C . . .78
Table 38. Components . . . . . . . . . . . . . . . . . . . . . . . . . .83
Table 39. Components . . . . . . . . . . . . . . . . . . . . . . . . . .84
Table 40. SnPb eutectic process (from J-STD-020D) . . .89
Table 41. Lead-free process (from J-STD-020D) . . . . . .89
Table 42. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .91
Table 43. Revision history . . . . . . . . . . . . . . . . . . . . . . . .94
JN517X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet
Rev. 3.0 — 7 November 2017
97 of 100
JN517x
NXP Semiconductors
IEEE802.15.4 Wireless Microcontroller
25. Figures
Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Fig 2. Functional block diagram. . . . . . . . . . . . . . . . . . . .6
Fig 3. Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . .7
Fig 4. Analog IO cell. . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Fig 5. DIO (other than DIO4 and DIO5) pin equivalent
schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Fig 6. DIO4 and DIO5 pin equivalent schematic . . . . . .14
Fig 7. JN517x memory map. . . . . . . . . . . . . . . . . . . . . .16
Fig 8. Connecting external serial memory . . . . . . . . . . .18
Fig 9. System and CPU clocks . . . . . . . . . . . . . . . . . . .19
Fig 10. 32 MHz crystal oscillator connections . . . . . . . . .20
Fig 11. 32 kHz crystal oscillator connections. . . . . . . . . .21
Fig 12. Internal Power-On Reset . . . . . . . . . . . . . . . . . . .22
Fig 13. External reset generation. . . . . . . . . . . . . . . . . . .23
Fig 14. External reset. . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Fig 15. Radio architecture . . . . . . . . . . . . . . . . . . . . . . . .26
Fig 16. External radio components . . . . . . . . . . . . . . . . .27
Fig 17. Simple antenna diversity implementation using
external RF switch . . . . . . . . . . . . . . . . . . . . . . . .28
Fig 18. Antenna diversity ADO signal for TX with
Fig 47. Brown-Out Reset followed by Supply Voltage
Monitor trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Fig 48. SPI-bus master timing. . . . . . . . . . . . . . . . . . . . . 69
Fig 49. SPI-bus slave timing . . . . . . . . . . . . . . . . . . . . . . 70
Fig 50. I2C-bus interface timing. . . . . . . . . . . . . . . . . . . . 70
Fig 51. Typical control range output power . . . . . . . . . . . 80
Fig 52. Typical transmit output power versus voltage . . . 81
Fig 53. Typical receiver sensitivity versus temperature. . 81
Fig 54. Maximum input level . . . . . . . . . . . . . . . . . . . . . . 82
Fig 55. JN517x module reference design using low voltage
supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Fig 56. Application diagram with Pi filter . . . . . . . . . . . . . 84
Fig 57. Reflow soldering information for the HVQFN40
package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Fig 58. Package outline SOT618-8 HVQFN40 . . . . . . . . 87
Fig 59. Temperature profiles for large and small
components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
acknowledgement . . . . . . . . . . . . . . . . . . . . . . . .29
Fig 19. Modem architecture . . . . . . . . . . . . . . . . . . . . . . .29
Fig 20. Energy detect value versus receive power level .30
Fig 21. Baseband processor . . . . . . . . . . . . . . . . . . . . . .31
Fig 22. Security coprocessor architecture . . . . . . . . . . . .32
Fig 23. SPI-bus block diagram. . . . . . . . . . . . . . . . . . . . .34
Fig 24. Typical JN517x SPI-bus peripheral connection . .35
Fig 25. Example SPI-bus waveforms: reading from Flash
device using mode 0 . . . . . . . . . . . . . . . . . . . . . .37
Fig 26. Timer unit block diagram . . . . . . . . . . . . . . . . . . .39
Fig 27. PWM output timings. . . . . . . . . . . . . . . . . . . . . . .40
Fig 28. Capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Fig 29. Return-To-Zero mode in operation. . . . . . . . . . . .42
Fig 30. Non-Return-to-Zero mode . . . . . . . . . . . . . . . . . .42
Fig 31. Closed loop PWM speed control using JN517x
timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Fig 32. UART block diagram . . . . . . . . . . . . . . . . . . . . . .46
Fig 33. JN517x serial communication link . . . . . . . . . . . .48
Fig 34. Connection details . . . . . . . . . . . . . . . . . . . . . . . .50
Fig 35. Clock stretching . . . . . . . . . . . . . . . . . . . . . . . . . .50
Fig 36. TX_FIFO in the middle of a transaction . . . . . . . .51
Fig 37. RX_FIFO full in the middle of a transaction . . . . .52
Fig 38. TX_FIFO empty just before RESTART condition in
master slave case . . . . . . . . . . . . . . . . . . . . . . . .53
Fig 39. Slave receiver: RX_FIFO in middle of a transaction
54
Fig 40. Example of use of the SRSD interrupt (STOP case)
55
Fig 41. TXS_FIFO empty in the middle of a transaction .55
Fig 42. Example of use of the STSD interrupt (RESTART
case) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Fig 43. Analog peripherals . . . . . . . . . . . . . . . . . . . . . . . .57
Fig 44. ADC input equivalent circuit. . . . . . . . . . . . . . . . .58
Fig 45. Internal Power-On Reset without showing
Brown-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Fig 46. Externally applied reset . . . . . . . . . . . . . . . . . . . .67
JN517X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet
Rev. 3.0 — 7 November 2017
98 of 100
JN517x
NXP Semiconductors
IEEE802.15.4 Wireless Microcontroller
26. Contents
1
General description . . . . . . . . . . . . . . . . . . . . . . 1
9.5.5
9.6
9.6.1
9.7
Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . 24
Nested Vector Interrupt controller (NVIC) . . . 24
Interrupts sources . . . . . . . . . . . . . . . . . . . . . 25
Wireless transceiver. . . . . . . . . . . . . . . . . . . . 25
Radio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Radio external components . . . . . . . . . . . . . . 27
Antenna diversity . . . . . . . . . . . . . . . . . . . . . . 28
Modem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Baseband processor . . . . . . . . . . . . . . . . . . . 30
Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Auto acknowledge . . . . . . . . . . . . . . . . . . . . . 32
Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Security coprocessor . . . . . . . . . . . . . . . . . . . 32
Digital Input Output . . . . . . . . . . . . . . . . . . . . 32
Serial Peripheral Interface-bus (SPI-bus) . . . 34
SPI-bus master . . . . . . . . . . . . . . . . . . . . . . . 34
SPI-bus slave. . . . . . . . . . . . . . . . . . . . . . . . . 37
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Peripheral timer/counters. . . . . . . . . . . . . . . . 38
2
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Benefits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Radio features . . . . . . . . . . . . . . . . . . . . . . . . . 2
Microcontroller features . . . . . . . . . . . . . . . . . . 2
2.1
2.2
2.3
9.7.1
9.7.1.1
9.7.1.2
9.7.2
9.7.3
9.7.3.1
9.7.3.2
9.7.3.3
9.7.3.4
9.7.4
9.8
3
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
4
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Wireless transceiver . . . . . . . . . . . . . . . . . . . . . 3
CPU and memory . . . . . . . . . . . . . . . . . . . . . . . 4
Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4.1
4.2
4.3
5
6
7
Ordering information. . . . . . . . . . . . . . . . . . . . . 5
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 6
8
8.1
8.2
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
Pinning information. . . . . . . . . . . . . . . . . . . . . . 7
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power supplies . . . . . . . . . . . . . . . . . . . . . . . . 12
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
32 MHz oscillator . . . . . . . . . . . . . . . . . . . . . . 12
Radio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Analog peripherals . . . . . . . . . . . . . . . . . . . . . 13
Digital Input Output (DIO) . . . . . . . . . . . . . . . . 13
9.9
9.9.1
9.9.2
9.10
9.10.1
9.10.1.1 Pulse Width Modulation mode . . . . . . . . . . . . 40
9.10.1.2 Capture mode . . . . . . . . . . . . . . . . . . . . . . . . 40
9.10.1.3 Counter/timer mode . . . . . . . . . . . . . . . . . . . . 41
9.10.1.4 Delta-sigma mode . . . . . . . . . . . . . . . . . . . . . 41
9.10.1.5 Example timer/counter application. . . . . . . . . 42
9
9.1
9.2
9.3
Functional description . . . . . . . . . . . . . . . . . . 15
CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Emulation and debugging. . . . . . . . . . . . . . . . 15
Memory organization . . . . . . . . . . . . . . . . . . . 15
Flash. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
OTP configuration memory. . . . . . . . . . . . . . . 17
EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
External memory. . . . . . . . . . . . . . . . . . . . . . . 17
Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
System clocks. . . . . . . . . . . . . . . . . . . . . . . . . 18
High-speed (32 MHz) system clock . . . . . . . . 18
32 MHz crystal oscillator. . . . . . . . . . . . . . . . . 19
High-speed RC oscillator . . . . . . . . . . . . . . . . 20
Low-speed (32 kHz) system clock . . . . . . . . . 20
32 kHz RC oscillator . . . . . . . . . . . . . . . . . . . . 20
32 kHz External clock . . . . . . . . . . . . . . . . . . . 21
32 kHz crystal oscillator . . . . . . . . . . . . . . . . . 21
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Internal Power-On Reset/Brown-out Reset (BOR)
22
9.10.2
9.10.3
ARM cortex-M3 system tick timer. . . . . . . . . . 43
Wake-up timers . . . . . . . . . . . . . . . . . . . . . . . 43
9.10.3.1 32 kHz RC oscillator calibration . . . . . . . . . . . 44
9.11
9.12
9.12.1
9.12.2
9.13
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.3.6
9.4
9.4.1
9.4.1.1
9.4.1.2
9.4.2
9.4.2.1
9.4.2.2
9.4.2.3
9.5
Pulse counters . . . . . . . . . . . . . . . . . . . . . . . . 45
Serial communications. . . . . . . . . . . . . . . . . . 45
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
UART application . . . . . . . . . . . . . . . . . . . . . . 48
JTAG test interface. . . . . . . . . . . . . . . . . . . . . 48
2-wire serial interface (I2C-bus) . . . . . . . . . . . 48
Connecting devices . . . . . . . . . . . . . . . . . . . . 49
Clock stretching . . . . . . . . . . . . . . . . . . . . . . . 50
Master interface . . . . . . . . . . . . . . . . . . . . . . . 50
9.14
9.14.1
9.14.2
9.14.3
9.14.3.1 Master transmitter . . . . . . . . . . . . . . . . . . . . . 51
9.14.3.2 Master receiver . . . . . . . . . . . . . . . . . . . . . . . 52
9.14.4
9.14.4.1 Slave receiver . . . . . . . . . . . . . . . . . . . . . . . . 54
9.14.4.2 Slave transmitter . . . . . . . . . . . . . . . . . . . . . . 55
Slave interface . . . . . . . . . . . . . . . . . . . . . . . . 54
9.14.5
Particular cases on I2C-bus . . . . . . . . . . . . . . 56
9.14.5.1 I2C-bus error. . . . . . . . . . . . . . . . . . . . . . . . . . 56
9.14.5.2 Arbitration lost . . . . . . . . . . . . . . . . . . . . . . . . 56
9.14.5.3 NAck from slave receiver . . . . . . . . . . . . . . . . 56
9.5.1
9.5.2
9.5.3
9.5.4
External reset . . . . . . . . . . . . . . . . . . . . . . . . . 23
Software reset. . . . . . . . . . . . . . . . . . . . . . . . . 23
Supply Voltage Monitor. . . . . . . . . . . . . . . . . . 23
9.15
9.16
Random number generator . . . . . . . . . . . . . . 56
Analog peripherals . . . . . . . . . . . . . . . . . . . . . 57
continued >>
JN517X
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet
Rev. 3.0 — 7 November 2017
99 of 100
JN517x
NXP Semiconductors
IEEE802.15.4 Wireless Microcontroller
9.16.1
Analog to Digital Converter. . . . . . . . . . . . . . . 58
18
Soldering of SMD packages. . . . . . . . . . . . . . 88
Introduction to soldering. . . . . . . . . . . . . . . . . 88
Wave and reflow soldering. . . . . . . . . . . . . . . 88
Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 88
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 89
9.16.1.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
9.16.1.2 Supply monitor . . . . . . . . . . . . . . . . . . . . . . . . 59
9.16.1.3 Temperature sensor . . . . . . . . . . . . . . . . . . . . 59
9.16.1.4 ADC sample buffer mode . . . . . . . . . . . . . . . . 59
18.1
18.2
18.3
18.4
9.16.2
9.16.3
Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Digital monitor for ADC output . . . . . . . . . . . . 60
19
20
21
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 91
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Revision history . . . . . . . . . . . . . . . . . . . . . . . 94
10
10.1
10.1.1
10.2
10.2.1
10.3
10.3.1
10.3.2
10.3.3
10.3.4
10.4
Power management and sleep modes. . . . . . 60
Operating modes . . . . . . . . . . . . . . . . . . . . . . 60
Power domains. . . . . . . . . . . . . . . . . . . . . . . . 61
Active processing mode . . . . . . . . . . . . . . . . . 61
CPU doze . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Wake-up timer event. . . . . . . . . . . . . . . . . . . . 62
DIO event . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Comparator event. . . . . . . . . . . . . . . . . . . . . . 63
Pulse counter . . . . . . . . . . . . . . . . . . . . . . . . . 63
Deep sleep mode . . . . . . . . . . . . . . . . . . . . . . 63
Flicker control . . . . . . . . . . . . . . . . . . . . . . . . . 63
22
Legal information . . . . . . . . . . . . . . . . . . . . . . 95
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 95
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 96
22.1
22.2
22.3
22.4
23
24
25
26
Contact information . . . . . . . . . . . . . . . . . . . . 96
Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
10.5
11
12
13
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 63
Recommended operating conditions. . . . . . . 64
Thermal characteristics. . . . . . . . . . . . . . . . . . 64
14
14.1
14.2
14.3
14.3.1
14.3.2
14.3.3
14.3.4
14.3.5
14.3.6
14.3.7
14.3.8
14.3.9
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 65
DC current . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
IO characteristics . . . . . . . . . . . . . . . . . . . . . . 66
AC characteristics. . . . . . . . . . . . . . . . . . . . . . 67
Reset and Supply Voltage Monitor . . . . . . . . . 67
SPI-bus master timing . . . . . . . . . . . . . . . . . . 69
SPI-bus slave timing. . . . . . . . . . . . . . . . . . . . 70
I2C-bus interface. . . . . . . . . . . . . . . . . . . . . . . 70
Wake-up timings. . . . . . . . . . . . . . . . . . . . . . . 72
Band gap reference . . . . . . . . . . . . . . . . . . . . 72
Analog to Digital Converters . . . . . . . . . . . . . . 72
Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . 73
32 kHz RC oscillator . . . . . . . . . . . . . . . . . . . . 73
14.3.10 32 kHz crystal oscillator . . . . . . . . . . . . . . . . . 74
14.3.11 32 MHz crystal oscillator. . . . . . . . . . . . . . . . . 74
14.3.12 High-speed RC oscillator . . . . . . . . . . . . . . . . 74
14.3.13 Temperature sensor . . . . . . . . . . . . . . . . . . . . 74
14.3.14 Non-volatile memory. . . . . . . . . . . . . . . . . . . . 75
14.3.15 Radio transceiver . . . . . . . . . . . . . . . . . . . . . . 75
15
15.1
15.1.1
15.1.2
15.1.3
15.1.4
Application information. . . . . . . . . . . . . . . . . . 82
JN517x module reference designs . . . . . . . . . 82
Schematic diagrams . . . . . . . . . . . . . . . . . . . . 82
Application diagram with Pi filter. . . . . . . . . . . 84
PCB design and reflow profile . . . . . . . . . . . . 85
Moisture sensitivity level (MSL) . . . . . . . . . . . 85
16
17
Footprint information for reflow soldering . . 86
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 87
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2017.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 7 November 2017
Document identifier: JN517X
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