K32L2A31VLH1A_技术文档

NXP Semiconductors

K32L2Ax

Data Sheet: Technical Data

Rev. 3, 02/2021

K32 L2A Microcontroller with 512

K32L2A41VLL1A

K32L2A31VLL1A

K32L2A41VLH1A

K32L2A31VLH1A

KB Flash and 128 KB SRAM

72 MHz Cortex-M0+ based Microcontroller

Supports ultra-low-power Arm based microcontroller with crystal-

less USB feature, large flash and RAM, evolutionary low-power

peripherals and security features. This is an ideal solution for

Sensor Hub applications, Smart Energy, Internet of Things, and

Edge and Concentrator. This device offers:

• 128 KB SRAM for data processing and connectivity stack

• Ultra low dynamic and static power consumption with smart

peripherals for low power applications

• Advanced LPI2C and LPSPI supporting asynchronous

DMA master data transition

100 LQFP

64 LQFP

• FlexIO for flexible and high performance interfaces

• Crypto acceleration with AES/DES/3DES/MD5/SHA and

TRNG

14x14 mm P 0.5 mm 10x10 mm P 0.5 mm

• USB FS 2.0 device operation without need of external

crystal

• USB FS OTG controller, capable of USB host or device operation

Core

• Arm^®Cortex^®-M0+ cores up to 72 MHz in Normal

mode and 96 MHz in High Speed mode

Communication interfaces

• Three 16-bit Low Power Serial Peripheral Interface

(LPSPI) modules

• One EMVSIM module supporting EMV version 4.3,

ISO7816

• Three LPUART modules

• Three LPI2C modules supporting up to 5 Mbit/s

• One FlexIO module emulating UART, SPI, camera

interface, and Motorola 68K/Intel 8080 bus

• USB FS 2.0 device operation without need of

external crystal

Memories

• Up to 512 KB program flash memory

• 128 KB SRAM

• 32 KB ROM with built-in bootloader

System peripherals

• 8-channel DMA controller

• Independent clocked Watchdog

• Low-leakage wakeup unit

• SWD debug interface and Micro Trace Buffer

• Bit Manipulation Engine

• USB FS OTG controller, capable of USB host or

device operation

Analog Modules

• Memory Mapped Divide and Square Root module

(MMDVSQ)

• Cyclic Redundancy Check (CRC) module

• Nested Vector Interrupt Controller (NVIC) supports 32

interrupt vectors

• 16-bit, 24-channel SAR ADC with internal voltage

reference

• Two High-speed analog comparators each

containing a 6-bit DAC and programmable reference

input

• Additional peripheral interrupt support via Interrupt

Multiplexer (INTMUX)

• One 12-bit DAC

• 1.2 V and 2.1 V voltage references (Vref)

Clocks

Timers

• One 6-channel Timer/PWM module

NXP reserves the right to change the production detail specifications as may be

required to permit improvements in the design of its products.

• System Clock Generator module that includes the

following clock sources:

• Two 2-channel Timer/PWM modules

• Two low-power timers

• 48 to 60 MHz high accuracy fast internal

reference clock (FIRC)

• Two periodic interrupt timers

• Secure Real time clock

• 32–40 kHz, or 3–32 MHz crystal oscillator

• 1 kHz LPO clock

• 2/8 MHz slow internal reference clock (SIRC)

• Peripheral Clock Control (PCC) module that

supports asynchronous clocking and clock divide

options for peripherals

• 56-bit software time stamp timer at 1 MHz

Security and integrity modules

• 80-bit unique identification number per chip

• CAU supports acceleration of the DES, 3DES, AES,

MD5, SHA-1, and SHA-256 algorithms

• True Random Number Generator (TRNG)

Human-machine interface

Operating Characteristics

• General-purpose input/output up to 97

• Low-power hardware touch sensor interface (TSI)

• Voltage range: 1.71 to 3.6 V

• Temperature range: –40 to 105 °C

Related Resources

Type

Selector

Description

Resource

Solution Advisor

The NXP Solution Advisor is a web-based tool that features interactive

application wizards and a dynamic product selector.

Guide

Reference

Manual

The Reference Manual contains a comprehensive description of the

structure and function (operation) of a device.

K32L2AxRM¹

Data Sheet

The Data Sheet includes electrical characteristics and signal

connections.

This document¹

Chip Errata

The chip mask set Errata provides additional or corrective information for K32L2A41VLL1A_1N52N ¹

a particular device mask set.

Package

drawing

Package dimensions are provided in package drawings.

• 64-LQFP: 98ASS23234W¹

• 100-LQFP:

98ASS23308W¹

1. To find the associated resource, go to http://www.nxp.com and perform a search using this term.

2

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

NXP Semiconductors

Table of Contents

1

2

Ordering information............................................................5

6.4 Voltage and current operating ratings........................35

Overview............................................................................. 5

2.1 System features.........................................................6

7

General............................................................................... 35

7.1 AC electrical characteristics.......................................35

7.2 Nonswitching electrical specifications........................36

2.1.1

2.1.2

2.1.3

2.1.4

2.1.5

2.1.6

2.1.7

2.1.8

2.1.9

Arm Cortex-M0+ core.................................. 6

NVIC............................................................ 7

AWIC........................................................... 7

Memory........................................................8

Reset and boot............................................ 8

Clock options............................................... 11

Security........................................................13

Power management.....................................14

LLWU...........................................................16

7.2.1

Voltage and current operating

requirements................................................36

LVD, HVD, and POR operating

7.2.2

requirements................................................37

Voltage and current operating behaviors.....38

Power mode transition operating behaviors 39

Power consumption operating behaviors.....40

EMC radiated emissions operating

7.2.3

7.2.4

7.2.5

7.2.6

2.1.10 Debug controller.......................................... 18

behaviors..................................................... 48

Designing with radiated emissions in mind..49

Capacitance attributes.................................49

2.2 Peripheral features.....................................................18

7.2.7

7.2.8

2.2.1

2.2.2

2.2.3

2.2.4

2.2.5

2.2.6

2.2.7

16-bit SAR ADC...........................................18

Crossbar Switch Lite (AXBS-Lite)................18

Bit Manipulation Engine2 (BME2)................19

Cryptographic Acceleration Unit (CAU)....... 19

Comparator (CMP)...................................... 19

12-bit DAC................................................... 20

Direct Memory Access Multiplexer

7.3 Switching specifications.............................................49

7.3.1

7.3.2

Device clock specifications..........................49

General switching specifications..................50

7.4 Thermal specifications............................................... 52

7.4.1

7.4.2

Thermal operating requirements..................52

Thermal attributes........................................52

(DMAMUX).................................................. 20

EMVSIM.......................................................20

Flexible I/O (FlexIO).....................................20

8

Peripheral operating requirements and behaviors.............. 53

8.1 Core modules.............................................................53

2.2.8

2.2.9

8.1.1

SWD electricals .......................................... 53

2.2.10 General-Purpose Input/Output (GPIO)........ 21

2.2.11 Low Power Inter-Integrated Circuit (LPI2C).21

2.2.12 The Low Power Periodic Interrupt Timer

8.2 System modules........................................................ 54

8.3 Clock modules........................................................... 54

8.3.1

System Clock Generation (SCG)

(LPIT)...........................................................21

specifications............................................... 54

Oscillator electrical specifications................57

2.2.13 Low Power Serial Peripheral Interface

8.3.2

(LPSPI)........................................................ 22

8.4 Memories and memory interfaces..............................59

8.4.1 Flash electrical specifications...................... 59

2.2.14 Low-Power Timer (LPTMR).........................22

2.2.15 Low Power Universal Asynchronous

8.5 Security and integrity modules...................................61

8.6 Analog........................................................................61

Receiver/Transmitter (LPUART)..................22

2.2.16 Peripheral Clock Control (PCC)...................23

2.2.17 Real Time Clock (RTC)................................23

2.2.18 Timer/PWM Module (TPM)..........................23

2.2.19 Touch Sensing Input (TSI)...........................23

2.2.20 Universal Serial Bus (USB) FS....................24

2.2.21 Voltage Reference (VREF)..........................24

2.2.22 Watchdog (WDOG)......................................25

Memory Map....................................................................... 25

Pinouts and Packaging....................................................... 27

4.1 Signal Multiplexing and Pin Assignments.................. 27

4.2 K32 L2A Pinouts........................................................ 31

Dimensions..........................................................................33

5.1 Obtaining package dimensions..................................33

Ratings................................................................................ 34

6.1 Thermal handling ratings........................................... 34

6.2 Moisture handling ratings...........................................34

6.3 ESD handling ratings................................................. 34

8.6.1

8.6.2

8.6.3

ADC electrical specifications....................... 61

Voltage reference electrical specifications...66

CMP and 6-bit DAC electrical

specifications............................................... 67

12-bit DAC electrical characteristics............69

8.6.4

8.7 Timers........................................................................72

8.8 Communication interfaces......................................... 72

3

4

8.8.1

8.8.2

8.8.3

8.8.4

8.8.5

8.8.6

EMV SIM specifications...............................72

USB electrical specifications........................77

USB VREG electrical specifications............ 78

LPSPI switching specifications.................... 78

LPI2C...........................................................83

LPUART.......................................................83

5

6

8.9 Human-machine interfaces (HMI)..............................84

8.9.1 TSI electrical specifications......................... 84

9

Design considerations.........................................................84

9.1 Hardware design considerations................................84

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

3

NXP Semiconductors

9.1.1

9.1.2

9.1.3

9.1.4

9.1.5

Printed circuit board recommendations.........84

Power delivery system.................................. 85

Analog design............................................... 85

Digital design.................................................86

Crystal oscillator............................................90

10 Part identification...................................................................92

10.1 Description...................................................................92

10.2 Format......................................................................... 93

10.3 Fields...........................................................................93

10.4 Example.......................................................................93

11 Revision History.................................................................... 94

9.2 Software considerations.............................................. 92

4

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

NXP Semiconductors

Ordering information

1 Ordering information

Table 1. Ordering information

Part number

Memory

(Flash/

SRAM)

Core

CPU frequency

(MHz)

Crypto

Serial

interfaces

Packages

K32L2A41VLL1A

512 KB

Flash/128 KB

SRAM

Single Cortex-

M0+

Up to 72 (normal),

96 (HSRUN)

Yes

3xLPI2C,

3xLPUART,

3xLPSPI,

EVMSIM,

FlexIO, FS USB

LQFP100

LQFP64

K32L2A31VLL1A

K32L2A41VLH1A

K32L2A31VLH1A

256 KB

Flash/128 KB

SRAM

Single Cortex-

M0+

Up to 72 (normal),

96 (HSRUN)

Yes

3xLPI2C,

3xLPUART,

3xLPSPI,

EVMSIM,

FlexIO, FS USB

512 KB

Flash/128 KB

SRAM

Single Cortex-

M0+

Up to 72 (normal),

96 (HSRUN)

3xLPI2C,

3xLPUART,

3xLPSPI,

EVMSIM,

FlexIO, FS USB

256 KB

Flash/128 KB

SRAM

Single Cortex-

M0+

Up to 72 (normal),

96 (HSRUN)

3xLPI2C,

3xLPUART,

3xLPSPI,

EVMSIM,

FlexIO, FS USB

2 Overview

The following figure shows the block diagram of this device.

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

5

NXP Semiconductors

Overview

WDOG

Reset

Timer

SPI

UART

Clocks/

Oscillators

SMC

XTAL

OSC

ANALOG

Temp

SCG

TSTMR

0

TPM

2

LPTMR WDOG LPSPI

LPUART

2

PMC

CRC

0

2

ADC

Inputs

TSI0

TSI

I2C

ADC0

DAC0

CMP0

CMP1

FIRC

PLL

SIRC

Monitor

PCC

LPI2C

2

DAC

Outputs

VREF

LPO1K

LPIT

0

LLWU

0

SCG

SRTC

RCM

SIM

TRG

MUX

Reference

Inputs

RGPIO

MSCM

GPIO

DMA0

8-channel

USB

MCM

s2

s1

USBVREG

DMA

CAU

DMAMux

•

m1

Requests

0

Core

SRAM

128KB

DVSQ

IO Port

Cortex-M0+

Platform

AXBS

m0

MTB

DWT

CTI

Cortex-M0+

ROM

32KB

s0

s3

System

m2

SYSTICK NVIC

SWD

SWD-DP

Interrupts

FTFA

DBG

CTI

MPU

AWIC

MDM-AP

AHB-AP0

FLASH 0

256KB

FMC

FLASH 1

256KB

M0+ DBG

AIPS1

AHB

EMVSIM

TPM

0/1

TRNG

Timer

SPI

USB

SRAM

LPSPI

0/1

PortA

PortB

PortC

Port A

Port B

Port C

PCC

LPUART

0/1

UART

I2C

AIPS0

TRG

MUX

LPI2C

0/1

FlexIO

8/16-bit

Parallel I/F

FlexIO0

LPTMR

1

Timer

PortD

PortE

Port D

Port E

USB

USB0

LEGEND:

Synchronizer

Bus Components

Platform Domain

CM0+ Platform

Analog Domain

AHB32

S

AIPS0 IPBUS

AIPS1 IPBUS

Core Memory-

Mapped Module

DAP Reference

sec

exsc

Memory protection

Gaskets

Other Module such

as test/analog

Figure 1. Block diagram

2.1 System features

6

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

NXP Semiconductors

Overview

2.1.1 Arm Cortex-M0+ core

The enhanced Arm Cortex M0+ is the member of the Cortex-M series of processors

targeting microcontroller cores focused on very cost sensitive, low power

applications. It has a single 32-bit AMBA AHB-Lite interface and includes an NVIC

component. It also has hardware debug functionality including support for simple

program trace capability. The processor supports the Armv6-M instruction set

(Thumb) architecture including all but three 16-bit Thumb opcodes (52 total) plus

seven 32-bit instructions. It is upward compatible with other Cortex-M profile

processors.

2.1.2 NVIC

The Nested Vectored Interrupt Controller supports nested interrupts and 4 priority

levels for interrupts. In the NVIC, each source in the IPR registers contains two bits. It

also differs in number of interrupt sources and supports 32 interrupt vectors.

The Cortex-M family uses a number of methods to improve interrupt latency to up to

15 clock cycles for Cortex-M0+. It also can be used to wake the MCU core from Wait

and VLPW modes.

2.1.3 AWIC

The asynchronous wake-up interrupt controller (AWIC) is used to detect

asynchronous wake-up events in Stop mode and signal to clock control logic to

resume system clocking. After clock restarts, the NVIC observes the pending interrupt

and performs the normal interrupt or event processing. The AWIC can be used to

wake MCU core from Stop and VLPS modes.

Wake-up sources are listed as below:

Table 2. AWIC stop wake-up sources

Wake-up source

Available system resets

Low-voltage detect

Low-voltage warning

Pin interrupts

Description

RESET pin when LPO is its clock source

Power management controller—functional in Stop mode

Port control module—any enabled pin interrupt is capable of waking the system

The ADC is functional when using internal clock source

Interrupt in normal or trigger mode

ADC

CMP

Table continues on the next page...

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

7

NXP Semiconductors

Overview

Table 2. AWIC stop wake-up sources (continued)

Wake-up source

Description

LPI²C

LPUART

RTC

Any enabled interrupt can be a source as long as the module remains clocked

Alarm or seconds interrupt

TSI

Any enabled interrupt can be a source as long as the module remains clocked

NMI_b pin

NMI

TPM

Any enabled interrupt can be a source as long as the module remains clocked

Wake-up

LPTMR

LPSPI

LPIT

FlexIO

USB

2.1.4 Memory

This device has the following features:

• 128 KB SRAM that can be accessed by bus masters through the cross-bar switch.

• Peripherals (LPUART, LPI2C, LPSPI , USB) supported by the ROM Bootloader.

The program flash memory contains a 16-byte flash configuration field that stores

default protection settings and security information. The page size of program flash

is 1 KB.

The protection setting can protect 32 regions of the program flash memory from

unintended erase or program operations.

The security circuitry prevents unauthorized access to RAM or flash contents from

debug port.

• System register file

This device contains a 32-byte register file that is powered in all power modes.

Also, it retains contents during low-voltage detect (LVD) events and is only reset

during a power-on reset.

2.1.5 Reset and boot

The following table lists all the reset sources supported by this device.

8

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

NXP Semiconductors

Overview

Table 3. Reset sources

Reset sources

POR reset

Description

• Power-on reset (POR)

External global system resets

• External pin reset (PIN)

• Low-voltage detect (LVD)

• Low leakage wakeup (LLWU) reset

• Clock monitor reset sources

• Stop mode acknowledge error (SACKERR)

Internal Core-generated resets

Debug reset

• Watchdog timer reset

• Software reset (SW)

• Lockup reset (LOCKUP)

• MDM DAP system reset request

• Debug resets

The CM0+ core adds support for a programmable Vector Table Offset Register

(VTOR) to relocate the exception vector table after reset. This device supports booting

from internal flash and RAM.

The Flash Option (FOPT) register in the Flash Memory module (FTFA_FOPT) allows

the user to customize the operation of the MCU at boot time. The register contains

read-only bits that are loaded from the NVM's option byte in the flash configuration

field. Below is boot flow chart for this device.

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

9

NXP Semiconductors

Overview

Enter Boot

Sequence

RESET =0

-Flash Init Complete

SCG is enabled

-RESET released

-Core clock enabled

-System released

from reset

Required Clocks

are enabled

Set up

-Stack Pointer,

-Program Counter

-Link Register

Flash Controller

is initialized

NVM option is read

and stored in

FTFA_FOPT

[BOOTPIN_OPT]

Yes

NMI/BOOTCFG0

= 0?

No

= 0?

Is

CPU boots

from ROM

Yes

LBOOT

programmed

for alternate

divider?

No

Yes

CPU begins

execution at reset

vector residing

in flash

Is NMI enabled

in FTFA_FOPT?

No

Is

Yes

No

FAST_INIT

cleared?

Or

CPU begins

execution at NMI

Interrupt Handler

Yes

Slower Clock

Faster Clock

is used

for Flash init

Figure 2. Boot flow chart

The blank chip is default to boot from ROM and remaps the vector table to ROM base

address, otherwise, it remaps to flash address.

10

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

NXP Semiconductors

Overview

2.1.6 Clock options

The SCG provides four clock sources that are then distributed and optionally divided

to the CPU, memory and various peripherals.

The four clock sources available to the SCG are:

• SOSC – output of the external oscillator (a crystal or externally applied clock

input)

• SIRC – output of the slow (2/8 Mhz) internal RC oscillator

• FIRC – output of the fast ( 48-60 MHZ) internal RC oscillator

• SPLL – output of the PLL, which is multiple of the SOSC or FIRC clock source.

The following diagram shows the clock sources and clock trees.

Core

SPLL

PLL

(VCO/2)

DIVCORE_CLK

DIVSLOW_CLK

DIVCORE

DIVSLOW

DMA

SOSC

FIRC

SIRC

SPLLDIV1_CLK

SOSCDIV1_CLK

FIRCDIV1_CLK

SIRCDIV1_CLK

USB

Functional

Clock

DIV1

USB

Peripheral

Functional

Clocks

SPLLDIV3_CLK

SOSCDIV3_CLK

FIRCDIV3_CLK

SIRCDIV3_CLK

DIV3

Peripherals

DIV2

PCC

SCG

Figure 3. Clock distribution

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

11

NXP Semiconductors

Overview

The SCG module supplies peripheral interface and functional clocks to the PCC,

depending on the peripheral. The peripheral interface clock can be either the

DIVCORE_CLK or the DIVSLOW_CLK, depending on the peripheral. The peripheral

functional clocks and the peripheral interface clocks for each module/peripheral are

detailed in table below.

Table 4. Peripheral Clocks

Source Module

Module Reset

Bus Interface

Clock

Bus Interface

Clock Gating

Control

Peripheral

Functional Clock

PCCn Functional

Clock Divider

System

Coretex M0+ Core Chip Reset

controller

DIVCORE_CLK

DMA controller

Chip Reset

DIVCORE_CLK

DIVSLOW_CLK

Yes

DMA channel

multiplexer

(DMAMUX)

AXBS

AIPS

Chip Reset

DIVCORE_CLK

DIVSLOW_CLK

INTMUX

LLWU

Chip Reset not

VLLS

LPO

SCG

PCC

Chip Reset

DIVSLOW_CLK

PORT multiplex

control

Yes

SIM

Chip Reset

POR

DIVSLOW_CLK

Power

Management

Controller (PMC)

System Mode

Controller (SMC)

Chip Reset not

VLLS

DIVSLOW_CLK

Reset Control

Module (RCM)

POR/LVD/VLLS

LPO

Security/Integrity

WDOG¹

Chip Reset

DIVSLOW_CLK

LPO, ERCLK,

SIRC

TRNG

CAU

Chip Reset

DIVSLOW_CLK

DIVCORE_CLK

DIVSLOW_CLK

Yes

CRC

Memory

Flash Memory Unit Early Reset

DIVSLOW_CLK

DIVCORE_CLK

Flash Memory

Controller

Chip Reset

Table continues on the next page...

12

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

NXP Semiconductors

Overview

Table 4. Peripheral Clocks (continued)

Source Module

Module Reset

Bus Interface

Clock

Bus Interface

Clock Gating

Control

Peripheral

Functional Clock

PCCn Functional

Clock Divider

SRAM

Chip Reset

DIVCORE_CLK

DIVSLOW_CLK

System Register

File

POR

Analog

TSI

Chip Reset not

VLLS

DIVSLOW_CLK

Yes

ADC

Chip Reset

DIVSLOW_CLK

Yes

SCG DIV3

VREF

DAC

CMP

Timers

TPM

Chip Reset

DIVSLOW_CLK

Yes

SCG DIV3

LPO, ERCLK²,

SIRC,

LPIT

Low-Power Timer POR/LVD

(LPTMR)³

OSC32KCLK

Real-time Clock

(RTC)⁴

POR

DIVSLOW_CLK

Yes

OSC32KCLK, LPO

TSTMR

Chip Reset

SIRCLK @ 1 MHz

Communications

USB

Chip Reset

DIVCORE_CLK⁵

Yes

SCG DIV1,

3-bit Divide, 1-bit

Fraction ⁷

USB_CLKIN ⁶

LPSPI

Chip Reset

DIVSLOW_CLK

DIVCORE_CLK

Yes

SCG DIV3

LPI2C

LPUART

EMVSIM

FlexIO

GPIO controller

1. Watchdog clock sources are selected by WDOGx_CS[CLK]

2. ERCLK is either from an external pin or from the SCG Internal OSC (SOSC) and configured with the

SCG_SOSCCFG[EREFS] bit.

3. LPTMR clock sources are selected by LPTMR_PSR[PCS]

4. RTC clock sources are selected by RTC_CR[LPOS]

5. For the USB FS OTG controller to operate, the minimum required DIVCORE_CLK is 24 MHz (half of USB functional

clock)

6. An additional external clock USB_CLKIN, can also selected via PCCUSB0FS, and device's PORTx MUX field

7. Additional 3bit Divide field and 1-bit Fractional field reside in PCCUSB0FS register

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

13

NXP Semiconductors

Overview

2.1.7 Security

This device implements security based on the mode selected from the flash module.

The device security provides:

• Security of the flash and MCU via SEC bit

• Backdoor Key and NXP Backdoor key access support

• Disable access to the debugger via the SWD interface-bit unique identification

number, which is programmed in factory and loaded to SIM register after power-on

reset.

2.1.8 Power management

The System Mode Controller (SMC) provides multiple power options to allow the user

to optimize power consumption for the level of functionality needed.

Depending on the stop requirements of the user application, a variety of stop modes are

available that provide state retention, partial power-down or full power-down of certain

logic and/or memory. I/O states are held in all modes of operation. The following table

compares the various power modes available.

For each run mode, there is a corresponding Wait and Stop mode. Wait modes are

similar to Arm Sleep modes. Stop modes (VLPS, STOP) are similar to Arm Sleep Deep

mode. The Very Low Power Run (VLPR) operating mode can drastically reduce

runtime power when the maximum bus frequency is not required to handle the

application needs.

The three primary modes of operation are Run, Wait, and Stop. The WFI instruction

invokes both Wait and Stop modes for the chip. The primary modes are augmented in a

number of ways to provide lower power based on application needs.

Table 5. Chip power modes

Chip mode

Description

Core mode

Normal

recovery

method

RUN (Normal

Run)

• Default mode out of reset

• On-chip voltage regulator is on.

Run

High Speed Run

Sleep

—

HRUN (High Allows maximum performance of chip.

Speed Run) • On-chip voltage regulator is on.

—

WAIT (Normal Allows peripherals to function while the core is in Sleep mode,

Wait) - via WFI reducing power.

Interrupt

• NVIC remains sensitive to interrupts

• Peripherals continue to be clocked.

Table continues on the next page...

14

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

NXP Semiconductors

Overview

Table 5. Chip power modes (continued)

Chip mode

Description

Core mode

Normal

recovery

method

STOP (Normal Places chip in static state. Lowest power mode that retains all

Stop) - via WFI registers while maintaining LVD protection.

• NVIC is disabled.

Sleep Deep

Interrupt

• AWIC is used to wake up from interrupt.

• Peripheral clocks are stopped.

VLPR (Very

Low-Power

Run)

On-chip voltage regulator is in a low-power mode that supplies only

enough power to run the chip at a reduced frequency.

• Reduced frequency Flash access mode (1 MHz)

• LVD off

Run

—

• In BLPI clock mode, only the fast internal reference oscillator is

available to provide a low power nominal 4 MHz source for the

core with the nominal bus and flash clock required to be <800

kHz

• Alternatively, BLPE clock mode can be used with an external

clock or the crystal oscillator providing the clock source.

VLPW (Very Same as VLPR but with the core in Sleep mode to further reduce

Sleep

Interrupt

Low-Power

Wait) -via WFI

power.

• NVIC remains sensitive to interrupts (FCLK = ON).

• On-chip voltage regulator is in a low-power mode that supplies

only enough power to run the chip at a reduced frequency.

VLPS (Very

Low-Power

Places chip in static state with LVD operation off. Lowest power mode

with ADC and pin interrupts functional.

Sleep Deep

Stop)-via WFI

• Peripheral clocks are stopped, but OSC, LPTMR,LPUART,

RTC, CMP, TSI can be used.

• TPM and UART can optionally be enabled if their clock source

is enabled.

• NVIC is disabled (FCLK = OFF); AWIC is used to wake up from

interrupt.

• On-chip voltage regulator is in a low-power mode that supplies

only enough power to run the chip at a reduced frequency.

• All SRAM is operating (content retained and I/O states held).

LLS3 (Low-

Leakage Stop3)

State retention power mode

Sleep Deep

Wake-up

Interrupt¹

• Most peripherals are in state retention mode (with clocks

stopped), but OSC, LLWU,LPTMR, RTC, CMP, TSI can be

used.

• NVIC is disabled; LLWU is used to wake up.

NOTE:

The LLWU interrupt must not be masked

by the interrupt controller to avoid a

scenario where the system does not fully

exit stop mode on an LLS recovery

• All SRAM is operating (content retained and I/O states held).

LLS2 (Low-

Leakage Stop2)

State retention power mode

Sleep Deep

Wake-up

Interrupt¹

• Most peripherals are in state retention mode (with clocks

stopped), but OSC, LLWU,LPTMR, RTC, CMP, TSI can be

used.

• NVIC is disabled; LLWU is used to wake up.

NOTE:

The LLWU interrupt must not be masked

by the interrupt controller to avoid a

Table continues on the next page...

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

15

NXP Semiconductors

Overview

Table 5. Chip power modes (continued)

Chip mode

Description

Core mode

Normal

recovery

method

scenario where the system does not fully

exit stop mode on an LLS recovery

• 64 KB SRAM retained, internal logic and I/O states are

retained.

VLLS3 (Very

Low-Leakage

Stop3)

• Most peripherals are disabled (with clocks stopped), but OSC,

LLWU, LPTMR, RTC, CMP, TSI can be used.

• NVIC is disabled; LLWU is used to wake up.

• SRAM_U and SRAM_L remain powered on (content retained

and I/O states held).

Sleep Deep

Wake-up

Reset^-1

VLLS2 (Very

Low-Leakage

Stop2)

• Most peripherals are disabled (with clocks stopped), but OSC,

LLWU, LPTMR, RTC, CMP, TSI can be used.

• NVIC is disabled; LLWU is used to wake up.

• 64K of SRAM_U remains powered on (content retained and I/O

states held).

Wake-up

Reset^-1

VLLS1 (Very

Low-Leakage

Stop1)

• Most peripherals are disabled (with clocks stopped), but OSC,

LLWU, LPTMR, RTC, CMP, TSI can be used.

• NVIC is disabled; LLWU is used to wake up.

• All of SRAM_U and SRAM_L are powered off.

• The 32-byte system register file remains powered for customer-

critical data

Wake-up

Reset^-1

• The 16-byte system register file remains powered for customer-

critical data

VLLS0 (Very

Low-Leakage

Stop 0)

• Most peripherals are disabled (with clocks stopped), but LLWU,

LPTMR, RTC, TSI can be used.

• NVIC is disabled; LLWU is used to wake up.

• All of SRAM_U and SRAM_L are powered off.

• The 32-byte system register file remains powered for customer-

critical data

Sleep Deep

Wake-up

Reset^-1

• The 16-byte system register file remains powered for customer-

critical data

• LPO disabled, optional POR brown-out detection

1. Resumes Normal Run mode operation by executing the LLWU interrupt service routine.

2.1.9 LLWU

The device uses the following internal peripheral and external pin inputs as wakeup

sources to the LLWU module. LLWU_Px are external pin inputs, and

LLWU_M0IFM7IF are connections to the internal peripheral interrupt flags.

NOTE

In addition to the LLWU wakeup sources, the device also

wakes from low power modes when NMI or RESET pins are

enabled and the respective pin is asserted.

16

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

NXP Semiconductors

Overview

Table 6. LLWU Wakeup Sources

IRQ

LLWU_P0

Module source or pin name

PTE1

PTE2

LLWU_P1

LLWU_P2

PTE4

LLWU_P3

PTA4

LLWU_P4

PTA13

LLWU_P5

PTB0

LLWU_P6

PTC1

LLWU_P7

PTC3

LLWU_P8

PTC4

LLWU_P9

PTC5

LLWU_P10

LLWU_P11

LLWU_P12

LLWU_P13

LLWU_P14

LLWU_P15

LLWU_P16

LLWU_P17

LLWU_P18

LLWU_P19

LLWU_P20

LLWU_P21

LLWU_P22

LLWU_P23

LLWU_P24

LLWU_P25

LLWU_P26

LLWU_P27

LLWU_P28

LLWU_P29 - LLWU_P31

LLWU_M0IF

LLWU_M1IF

LLWU_M2IF

LLWU_M3IF

LLWU_M4IF

LLWU_M5IF

LLWU_M6IF

LLWU_M7IF

PTC6

PTC11

PTD0

PTD2

PTD4

PTD6

PTE6

Reserved

PTE17

PTE18

PTE25

PTA10

PTA11

PTD8

PTD11

VREGIN

USB0_DM

USB0_DP

Reserved

LPTMR0

CMP0

CMP1

LPTMR1 asynchronous interrupt

TSI0

RTC Alarm

Reserved

RTC Seconds

Table continues on the next page...

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

17

NXP Semiconductors

Overview

Table 6. LLWU Wakeup Sources

(continued)

IRQ

Module source or pin name

LPTMR0 asynchronous DMA

LPTMR1 asynchronous DMA

TSI asynchronous DMA

LPTMR0 trigger

LLWU_M0DR

LLWU_M3DR

LLWU_M4DR

LLWU_M6DR

LLWU_M7DR

LPTMR1 trigger

2.1.10 Debug controller

The debug system of this device is based on the Arm CoreSight™ architecture, and is

configured to provide the maximum flexibility as allowed by the restrictions of the

pinout and other available resources.

The MCU has a single M0+ CPU available for customer application use.

Debug provides register and memory accessibility from the external debugger interface,

basic run/halt control, plus 2 breakpoints and 2 watchpoints. Additionally, it supports

Arm's Micro Trace Buffer (MTB) capability to provide simple program trace. Only one

debug interface is supported: Serial Wire Debug (SWD). The SWD interface provides

the capability for debugger tools to interface to the CPU.

2.2 Peripheral features

2.2.1 16-bit SAR ADC

This device contains one 16-bit successive approximation ADC. The ADC supports

both software and hardware triggers.

The number of ADC channels present on the device is determined by the pinout of the

specific device package.

2.2.2 Crossbar Switch Lite (AXBS-Lite)

The information found here provides information on the layout, configuration, and

programming of the crossbar switch.

18

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

NXP Semiconductors

Overview

The crossbar switch connects bus masters and bus slaves using a crossbar switch

structure. This structure allows up to four bus masters to access different bus slaves

simultaneously, while providing arbitration among the bus masters when they access

the same slave.

2.2.3 Bit Manipulation Engine2 (BME2)

The key features of the BME2 include:

• Lightweight implementation of decorated storage for selected address spaces

• Additional access semantics encoded into the reference address

• Resides between crossbar switch slave port(s) and their associated peripheral

bridge bus controller(s)

• Two-stage pipeline design matching the AHB system bus protocol

• Combinationally passes non-decorated accesses to peripheral bridge bus

controllers

• Conversion of decorated loads and stores from processor core into atomic

readmodify- writes

• Decorated loads support unsigned bit field extracts, load-and-{set,clear} 1-bit

operations

• Decorated stores support bit field inserts, logical AND, OR, and XOR operations

• Support for byte, halfword and word-sized decorated operations

• Supports minimum signal toggling on AHB output bus to reduce power

dissipation

2.2.4 Cryptographic Acceleration Unit (CAU)

The CAU provides security encrypt/decrypt acceleration to allow users to share secure

data with external devices via a serial communication port (such as an LPUART

module). The CAU clock source is the CPU/platform clock.

There is 1 CAU module, which is connected to the Core PPB.

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

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NXP Semiconductors

Overview

2.2.5 Comparator (CMP)

The device includes two high-speed comparators each with two 8-input multiplexers for

both the inverting and non-inverting inputs of the comparator. Each CMP input channel

connects to both muxes. Two of the channels are connected to internal sources, leaving

resources to support up to 6 input pins. See the channel assignment table for a summary

of CMP input connections for this device.

The CMPs also include one 6-bit DAC with a 64-tap resistor ladder network, which

provides a selectable voltage reference for applications where voltage reference is

needed for an internal connection to the CMP.

The CMPs can be optionally on in all modes except VLLS0.

2.2.6 12-bit DAC

The 12-bit digital-to-analog converter (DAC) is a low-power, general-purpose DAC.

The output of the DAC can be placed on an external pin or set as one of the inputs to

the analog comparator, op-amps, or ADC.

This device contains one 12-bit digital-to-analog converter (DAC) with programmable

reference generator output. The DAC includes a 16-word FIFO for DMA support.

2.2.7 Direct Memory Access Multiplexer (DMAMUX)

DMAMUX0 is a DMA request mux that allows up to 63 DMA request signals to be

mapped to any of the 8 DMA channels of DMA0. Because of the mux, there is no hard

correlation between any of the DMA request sources and a specific DMA channel.

Some of the modules support asynchronous DMA operation.

2.2.8 EMVSIM

The EMVSIM (Euro/Mastercard/Visa/SIM Serial Interface Module) is a standalone ISO

7816 module that is connected to the AIPS0 Peripheral Bridge. The EMVSIM module’s

clock source is the CPU/platform clock.

20

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

NXP Semiconductors

Overview

2.2.9 Flexible I/O (FlexIO)

The FlexIO is a highly configurable module providing a wide range of functionality

including:

• Emulation of a variety of serial/parallel communication protocols

• Flexible 16-bit timers with support for a variety of trigger, reset, enable and

disable conditions

• Programmable logic blocks allowing the implementation of digital logic functions

on-chip and configurable interaction of internal and external modules

• Programmable state machine for offloading basic system control functions from

CPU

2.2.10 General-Purpose Input/Output (GPIO)

The general-purpose input and output (GPIO) module is accessible via the peripheral

bus and also communicates to the processor core via a zero wait state interface

(IOPORT) for maximum pin performance. The GPIO registers support 8-bit, 16-bit or

32-bit accesses.

The device includes pins PTB0, PTB1, PTC3, PTC4, PTD4, PTD5, PTD6, and PTD7

with high current drive capability. These pins can be used to drive LED or power

MOSFETs directly. The high drive capability applies to all functions which are

multiplexed on these pins.

2.2.11 Low Power Inter-Integrated Circuit (LPI2C)

The LPI2C is a low power Inter-Integrated Circuit (I2C) module that supports an

efficient interface to an I2C bus as a master and/or a slave. The LPI2C can continue

operating in stop modes provided an appropriate clock is available and is designed for

low CPU overhead with DMA offloading of FIFO register accesses. The LPI2C

implements logic support for standard-mode, fast-mode, fast-mode plus and ultra-fast

modes of operation.

This device has three LPI2C modules. The LPI2C module provides a low power IIC

module that can operate in low power stop modes if required. Each of the three LPI2C

modules will have a 4 word (32-bit) FIFO for transmit and receive of messages.

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

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NXP Semiconductors

Overview

2.2.12 The Low Power Periodic Interrupt Timer (LPIT)

LPIT is a multi-channel timer module generating independent pre-trigger and trigger

outputs. These timer channels can operate individually or can be chained together. The

LPIT can operate in low power modes if configured to do so. The pre-trigger and

trigger outputs can be used to trigger other modules on the device.

The LPIT generates periodic trigger events to the DMA channel mux. The LPIT to the

DMAMUX trigger is configured in the TRGMUX.

2.2.13 Low Power Serial Peripheral Interface (LPSPI)

The LPSPI is a low power Serial Peripheral Interface (SPI) module that supports an

efficient interface to an SPI bus as a master and/or a slave. The LPSPI can continue

operating in stop modes provided an appropriate clock is available and is designed for

low CPU overhead with DMA offloading of FIFO register accesses.

The LPSPI supports the following features:

• Word size = 32 bits

• Command/transmit FIFO of 4 words.

• Receive FIFO of 4 words.

• Host request input can be used to control the start time of an SPI bus transfer.

2.2.14 Low-Power Timer (LPTMR)

The low-power timer (LPTMR) can be configured to operate as a time counter with

optional prescaler, or as a pulse counter with optional glitch filter, across all power

modes, including the low-leakage modes. It can also continue operating through most

system reset events, allowing it to be used as a time of day counter.

This device has two low-power timers: LPTMR0 and LPTMR1. Both allow operation

during all power modes. LPTMR0 is accessed via AIPS0. LPTMR1 is accessed via

AIPS1.

2.2.15 Low Power Universal Asynchronous Receiver/Transmitter

(LPUART)

The LPUART modules support the basic UART with DMA interface function and x4 to

x32 oversampling of baud-rate. This module supports LIN slave operation.

22

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

NXP Semiconductors

Overview

The module can remain functional in VLPS mode provided the clock it is using

remains enabled.

2.2.16 Peripheral Clock Control (PCC)

The device deploys two Peripheral Clock Control modules that allow clock gating,

and clock source selection to each peripheral. Each AIPS bridge has its own

corresponding PCC module. In addition to this clock, there are optional peripheral

clock sources that may be asynchronous to the CPU/Platform clock: SCGIRCLK,

SCGFIRCLK, SCGPCLK, SCGFCLK, LPO, OSCCLK, SCGSPCLK.

2.2.17 Real Time Clock (RTC)

The RTC module features include:

• 32-bit seconds counter with roll-over protection and 32-bit alarm

• 16-bit prescaler with compensation that can correct errors between 0.12 ppm and

3906 ppm

• Option to increment prescaler using the LPO (prescaler increments by 32 every

clock edge)

• Register write protection

• Lock register requires POR or software reset to enable write access

• Configurable 1, 2, 4, 8, 16, 32, 64 or 128 Hz square wave output with optional

interrupt

The device has one secure RTC. The RTC module is accessed via AIPS0 peripheral

bridge.

2.2.18 Timer/PWM Module (TPM)

The TPM (Timer/PWM Module) is a 2- to 8-channel timer which supports input

capture, output compare, and the generation of PWM signals to control electric motor

and power management applications.

This device contains 3 low-power Timer/PWM modules (TPM), which can all be

functional in Stop/VLPS mode. In Stop/VLPS mode, the clock source is either

external or internal.

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

23

NXP Semiconductors

Overview

2.2.19 Touch Sensing Input (TSI)

The TSI module provides capacitive touch sensing detection with high sensitivity and

enhanced robustness.

This device includes one TSI module containing the channels as shown in the following

table. In Stop, VLPS, LLS, and VLLSx modes, any one channel can be enabled to be

the wake-up source. TSI hardware trigger is from the LPTMR0.

2.2.20 Universal Serial Bus (USB) FS

The USB FS subsystem includes these components:

• Dual-role USB OTG-capable (On-The-Go) controller that supports a full-speed

(FS) device or FS/LS host. The module complies with the USB 2.0 specification.

• USB transceiver that includes internal 15 kΩ pulldowns on the D+ and D- lines for

host mode functionality and a 1.5 kΩ pullup on the D+ line for device mode

functionality.

• A 3.3 V regulator.

• Status detection and wakeup functions for USB data pins, VBUS pin, and OTG ID

pin.

• IRC48 with clock recovery block to eliminate the 48MHz crystal. This is available

for USB device mode only.

NOTE

USB OTG is not functional in VLPx, VLLSx, and any Stop

modes.

NOTE

For the USB FS OTG controller to operate, the minimum

system clock frequency is 20 MHz.

2.2.21 Voltage Reference (VREF)

The VREF can be used in applications to provide a reference voltage to external

devices, or used internally in the device as a reference to analog peripherals (such as the

ADC, DAC, or CMP). The Voltage Reference (VREF) can supply an accurate voltage

output that can be trimmed in 0.5 mV steps (for 1.2 V output) or 1.5 mV steps (for 2.1

V output). The voltage reference has 3 operating modes that provide different levels of

supply rejection and power consumption.

24

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NXP Semiconductors

Memory Map

This device includes a voltage reference (VREF) to supply an accurate 1.2 V or 2.1 V

voltage output.

2.2.22 Watchdog (WDOG)

The multiple clock inputs for the WDOG are:

• 1 kHz clock

• bus clock

• 8 MHz or 2 MHz internal reference clock

• external crystal

3 Memory Map

This device contains various memories and memory-mapped peripherals which are

located in a 4 GB memory space. The following table lists the system memory and

peripheral addresses.

Table 7. Memory Map

Type

START ADDRESS

0x0000_0000

END ADDRESS

0x0007_FFFF

Function

Program Flash

Code

0x0008_0000

0x1C00_0000

0x1C00_8000

0x1D00_0000

0x1D02_0000

0x1D04_0000

0x1D20_0000

0x1D22_0000

0x1D24_0000

0x1FFF_8000

0x1FFF_A000

0x2000_0000

0x2001_2000

0x2001_8000

0x2D00_0000

0x2D02_0000

0x2D04_0000

0x2D10_0000

0x1CFF_FFFF

0x1C00_7FFF

0x1CFF_FFFF

0x1D01_FFFF

0x1D03_FFFF

0x1D1F_FFFF

0x1D21_FFFF

0x1D23_FFFF

0x1FFF_7FFF

0x1FFF_9FFF

0x1FFF_FFFF

0x2001_1FFF

0x2001_7FFF

0x2CFF_FFFF

0x2D01_FFFF

0x2D03_FFFF

0x2D0F_FFFF

0x2D10_7FFF

Reserved

Boot ROM

Reserved

SRAM

Reserved

Table continues on the next page...

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

25

NXP Semiconductors

Memory Map

Table 7. Memory Map (continued)

Type

START ADDRESS

0x2D10_4000

END ADDRESS

0x2D1F_FFFF

Function

Reserved

AIPS0

0x2D20_0000

0x2D22_0000

0x2D24_0000

0x2D30_0000

0x2D30_4000

0x4000_0000

0x4008_0000

0x4010_0000

0x4108_0000

0x4110_0000

0x4118_0000

0x4120_0000

0x4400_0000

0x2D21_FFFF

0x2D23_FFFF

0x2D2F_FFFF

0x2D30_7FFF

0x3FFF_FFFF

0x4007_FFFF

0x400F_FFFF

0x4107_FFFF

0x410F_FFFF

0x4117_FFFF

0x411F_FFFF

0x43FF_FFFF

0x5FFF_FFFF

Peripheral

AIPS1

USB SRAM

Reserved

BME (AIPS0 and AIPS1)

(448 MB)

External RAM

0x6000_0000

0xE000_0000

0xE100_0000

0xE200_0000

0xE300_0000

0xE400_0000

0xE500_0000

0xE600_0000

0xE700_0000

0xE800_0000

0xE900_0000

0xEA00_0000

0xEB00_0000

0xEC00_0000

0xF000_0000

0xF010_0000

0xF100_0000

0xF110_0000

0xF120_0000

0xF800_0000

0xF810_0000

0xF900_0000

0xF910_0000

0xDFFF_FFFF

0xE0FF_FFFF

0xE1FF_FFFF

0xE2FF_FFFF

0xE3FF_FFFF

0xE4FF_FFFF

0xE5FF_FFFF

0xE6FF_FFFF

0xE7FF_FFFF

0xE8FF_FFFF

0xE9FF_FFFF

0xEAFF_FFFF

0xEBFF_FFFF

0xEFFF_FFFF

0xF00F_FFFF

0xF0FF_FFFF

0xF10F_FFFF

0xF11F_FFFF

0xF7FF_FFFF

0xF80F_FFFF

0xF8FF_FFFF

0xF90F_FFFF

0xFFFF_FFFF

Reserved

PPB - Arm SYS Modules

System

PPB - Arm DBG Modules

PPB - NXP Modules

Reserved

PPB

Reserved

SYS IOPORT

Reserved

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Pinouts and Packaging

4 Pinouts and Packaging

4.1 Signal Multiplexing and Pin Assignments

The following table shows the signals available on each pin and the locations of these

pins on the devices supported by this document. The Port Control Module is

responsible for selecting which ALT function is available on each pin.

NOTE

• A pull-up resistor (typically 4.7 KΩ) must be connected

to the EMVSIM0_IO pin if this pin is configured as

EMV SIM function.

• PTB0/1, PTC3/4, PTD4/5/6/7 have both high drive and

normal/low drive capability. PTD4, PTD5, PTD6,

PTD7, PTE20, PTE21, PTE22, PTE23 are also fast pins.

When a high bit rate is required on the communication

interface pins, it is recommended to use fast pins. In

case of high bus loading, the high drive strength of high

drive pins must be enabled by setting the corresponding

PORTx_PCRn[DSE] bit.

• RESET_b pin is open drain with internal pullup device

and passive analog filter when configured as RESET pin

(default state after POR). When this pin is configured to

other shared functions, the passive analog filter is

disabled.

• NMI0_b pin has pullup device enabled and passive

analog filter disabled after POR.

• SWD_DIO pin has pullup device enabled after POR.

SWD_CLK has pulldown device enabled after POR.

100

LQFP LQFP

64

Pin Name

Default

ADC0_SE16

ADC0_SE17

ADC0_SE18

ADC0_SE19

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

1

2

3

4

1

2

PTE0

ADC0_SE16

ADC0_SE17

ADC0_SE18

ADC0_SE19

PTE0/

RTC_CLKOUT

LPSPI1_SIN

LPUART1_TX

LPUART1_RX

CMP0_OUT

LPI2C1_SDA

LPI2C1_SCL

LPI2C1_SDAS

LPI2C1_SCLS

PTE1/

LLWU_P0

PTE1/

LLWU_P0

LPSPI1_

SOUT

—

PTE2/

LLWU_P1

PTE2/

LLWU_P1

LPSPI1_SCK

LPUART1_

CTS_b

PTE3

LPSPI1_SIN

LPUART1_

RTS_b

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NXP Semiconductors

Pinouts and Packaging

100

64

Pin Name

Default

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

LQFP LQFP

5

—

PTE4/

DISABLED

PTE4/

LPSPI1_PCS0

LLWU_P2

6

7

—

PTE5

DISABLED

PTE5

LPSPI1_PCS1

LPSPI1_PCS2

PTE6/

LLWU_P16

PTE6/

LLWU_P16

USB_SOF_

OUT

8

3

4

VDD

VSS

9

VSS

10

11

12

13

14

5

USB0_DP

USB0_DM

VOUT33

VREGIN

PTE16

USB0_DP

USB0_DM

VOUT33

VREGIN

USB0_DP

USB0_DM

VOUT33

VREGIN

6

7

8

—

ADC0_DP1/

ADC0_SE1

ADC0_DP1/

ADC0_SE1

PTE16

LPSPI0_PCS0 LPUART2_TX

TPM0_CLKIN

LPSPI1_PCS3 FXIO0_D0

15

—

PTE17/

LLWU_P19

ADC0_DM1/

ADC0_SE5a

ADC0_DM1/

ADC0_SE5a

PTE17/

LLWU_P19

LPSPI0_SCK

LPUART2_RX TPM1_CLKIN

LPTMR0_

ALT3/

FXIO0_D1

LPTMR1_

ALT3

16

17

18

19

20

21

—

9

PTE18/

LLWU_P20

ADC0_DP2/

ADC0_SE2

ADC0_DP2/

ADC0_SE2

PTE18/

LLWU_P20

LPSPI0_

SOUT

LPUART2_

CTS_b

LPI2C0_SDA

LPI2C0_SCL

LPUART0_TX

LPUART0_RX

LPUART2_TX

LPUART2_RX

FXIO0_D2

FXIO0_D3

FXIO0_D4

FXIO0_D5

FXIO0_D6

FXIO0_D7

PTE19

PTE20

PTE21

PTE22

PTE23

VDDA

ADC0_DM2/

ADC0_SE6a

ADC0_DM2/

ADC0_SE6a

PTE19

PTE20

PTE21

PTE22

PTE23

LPSPI0_SIN

LPUART2_

RTS_b

ADC0_DP0/

ADC0_SE0

ADC0_DP0/

ADC0_SE0

LPSPI2_SCK

TPM1_CH0

TPM1_CH1

TPM2_CH0

10

11

12

ADC0_DM0/

ADC0_SE4a

ADC0_DM0/

ADC0_SE4a

LPSPI2_

SOUT

ADC0_DP3/

ADC0_SE3

ADC0_DP3/

ADC0_SE3

LPSPI2_SIN

ADC0_DM3/

ADC0_SE7a

ADC0_DM3/

ADC0_SE7a

LPSPI2_PCS0 TPM2_CH1

22

23

13

14

VDDA

VREFH/

VREF_OUT

24

25

26

15

16

17

VREFL

VSSA

VREFL

VSSA

VREFL

VSSA

PTE29

CMP1_IN5/

CMP0_IN5/

ADC0_SE4b

CMP1_IN5/

CMP0_IN5/

ADC0_SE4b

PTE29

PTE30

EMVSIM0_

CLK

TPM0_CH2

TPM0_CH3

TPM0_CLKIN

TPM1_CLKIN

27

18

PTE30

DAC0_OUT/

CMP1_IN3/

ADC0_SE23/

CMP0_IN4

DAC0_OUT/

CMP1_IN3/

ADC0_SE23/

CMP0_IN4

EMVSIM0_

RST

28

19

PTE31

DISABLED

PTE31

EMVSIM0_

VCCEN

TPM0_CH4

TPM2_CLKIN

LPI2C0_

HREQ

29

30

—

VSS

VDD

VSS

VDD

VSS

VDD

28

NXP Semiconductors

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

Pinouts and Packaging

100

64

Pin Name

Default

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

LQFP LQFP

31

32

20

21

PTE24

ADC0_SE20

ADC0_SE21

ADC0_SE20

ADC0_SE21

PTE24

EMVSIM0_IO

TPM0_CH0

LPI2C0_SCL

LPI2C0_SDA

PTE25/

EMVSIM0_PD TPM0_CH1

LLWU_P21

33

34

—

PTE26

DISABLED

SWD_CLK

PTE26/

RTC_CLKOUT

TPM0_CH5

LPI2C0_SCLS

LPI2C0_SDAS

USB_CLKIN

SWD_CLK

22

PTA0

TSI0_CH1

PTA0

LPUART0_

CTS_b

TPM0_CH5

35

36

37

23

24

25

PTA1

PTA2

PTA3

TSI0_CH2

TSI0_CH3

SWD_DIO

TSI0_CH2

TSI0_CH3

TSI0_CH4

PTA1

PTA2

PTA3

LPUART0_RX TPM2_CH0

LPUART0_TX

LPI2C1_SCL

TPM2_CH1

TPM0_CH0

LPUART0_

RTS_b

SWD_DIO

NMI0_b

38

39

26

27

PTA4/

LLWU_P3

NMI0_b

TSI0_CH5

PTA4/

LLWU_P3

LPI2C1_SDA

USB_CLKIN

TPM0_CH1

TPM0_CH2

TPM0_CH3

PTA5

DISABLED

PTA5

LPI2C2_

HREQ

40

41

42

43

—

28

29

PTA6

PTA7

PTA12

DISABLED

PTA6

PTA7

PTA12

LPSPI0_PCS3 TPM0_CH4

TPM1_CH0

LPI2C2_SDAS

LPI2C2_SCL

LPI2C2_SDA

PTA13/

TPM1_CH1

LLWU_P4

44

45

46

—

PTA14

PTA15

PTA16

DISABLED

PTA14

PTA15

PTA16

LPSPI0_PCS0 LPUART0_TX

LPI2C2_SCL

LPSPI0_SCK

LPUART0_RX

LPSPI0_

SOUT

LPUART0_

CTS_b

47

—

PTA17

ADC0_SE22

PTA17

LPSPI0_SIN

LPUART0_

RTS_b

48

49

50

51

30

31

32

33

VDD

VSS

PTA18

PTA19

EXTAL0

XTAL0

EXTAL0

XTAL0

PTA18

PTA19

LPUART1_RX TPM0_CLKIN

LPUART1_TX

TPM1_CLKIN

LPTMR0_

ALT1/

LPTMR1_

ALT1

52

53

34

35

PTA20

RESET_b

PTA20

LPI2C0_SCLS

LPI2C0_SCL

TPM2_CLKIN

RESET_b

PTB0/

LLWU_P5

ADC0_SE8/

TSI0_CH0

ADC0_SE8/

TSI0_CH0

PTB0/

LLWU_P5

TPM1_CH0

TPM1_CH1

TPM2_CH0

TPM2_CH1

FXIO0_D8

FXIO0_D9

FXIO0_D10

FXIO0_D11

54

55

56

36

37

38

PTB1

PTB2

PTB3

ADC0_SE9/

TSI0_CH6

ADC0_SE9/

TSI0_CH6

PTB1

PTB2

PTB3

LPI2C0_SDA

LPI2C0_SCL

LPI2C0_SDA

ADC0_SE12/

TSI0_CH7

ADC0_SE12/

TSI0_CH7

LPUART0_

RTS_b

ADC0_SE13/

TSI0_CH8

ADC0_SE13/

TSI0_CH8

LPSPI1_PCS3 LPUART0_

CTS_b

57

58

—

PTB7

PTB8

DISABLED

PTB7

PTB8

LPSPI1_PCS1

LPSPI1_PCS0

FXIO0_D12

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

29

NXP Semiconductors

Pinouts and Packaging

100

64

Pin Name

Default

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

LQFP LQFP

59

60

61

62

—

39

PTB9

DISABLED

TSI0_CH9

PTB9

LPSPI1_SCK

LPSPI1_PCS0

LPSPI1_SCK

FXIO0_D13

FXIO0_D14

FXIO0_D15

PTB10

PTB11

PTB16

PTB10

PTB11

PTB16

TPM2_CLKIN

TSI0_CH9

LPSPI1_

SOUT

LPUART0_RX TPM0_CLKIN

LPSPI2_PCS3 FXIO0_D16

63

64

40

41

PTB17

PTB18

TSI0_CH10

TSI0_CH11

TSI0_CH10

TSI0_CH11

PTB17

PTB18

LPSPI1_SIN

LPUART0_TX

TPM2_CH0

TPM1_CLKIN

LPSPI2_PCS2 FXIO0_D17

LPI2C1_

HREQ

FXIO0_D18

65

66

67

68

42

—

PTB19

PTB20

PTB21

PTB22

TSI0_CH12

DISABLED

TSI0_CH12

PTB19

PTB20

PTB21

PTB22

TPM2_CH1

LPSPI2_PCS1 FXIO0_D19

CMP0_OUT

LPSPI2_PCS0

LPSPI2_SCK

CMP1_OUT

LPSPI2_

SOUT

69

70

—

PTB23

PTC0

DISABLED

PTB23

PTC0

LPSPI2_SIN

43

ADC0_SE14/

TSI0_CH13

ADC0_SE14/

TSI0_CH13

LPSPI2_PCS1

USB_SOF_

OUT

CMP0_OUT

71

72

44

45

PTC1/

LLWU_P6

ADC0_SE15/

TSI0_CH14

ADC0_SE15/

TSI0_CH14

PTC1/

LLWU_P6

LPI2C1_SCL

LPI2C1_SDA

LPUART1_

RTS_b

TPM0_CH0

PTC2

ADC0_SE11/

CMP1_IN0/

TSI0_CH15

ADC0_SE11/

CMP1_IN0/

TSI0_CH15

PTC2

LPUART1_

CTS_b

TPM0_CH1

73

46

PTC3/

CMP1_IN1

PTC3/

LPSPI0_PCS1 LPUART1_RX TPM0_CH2

CLKOUT

LLWU_P7

74

75

76

47

48

49

VSS

VDD

VSS

VDD

PTC4/

LLWU_P8

DISABLED

PTC4/

LLWU_P8

LPSPI0_PCS0 LPUART1_TX

TPM0_CH3

CMP1_OUT

CMP0_OUT

77

50

PTC5/

LLWU_P9

DISABLED

PTC5/

LLWU_P9

LPSPI0_SCK

LPTMR0_

ALT2/

LPTMR1_

ALT2

78

79

51

52

PTC6/

LLWU_P10

CMP0_IN0

CMP0_IN1

CMP0_IN0

CMP0_IN1

PTC6/

LLWU_P10

LPSPI0_

SOUT

PTC7

LPSPI0_SIN

USB_SOF_

OUT

FXIO0_D20

80

81

82

83

53

54

55

56

PTC8

PTC9

PTC10

CMP0_IN2

CMP0_IN3

DISABLED

CMP0_IN2

CMP0_IN3

PTC8

PTC9

PTC10

LPI2C0_SCL

LPI2C0_SDA

LPI2C1_SCL

LPI2C1_SDA

TPM0_CH4

TPM0_CH5

FXIO0_D21

FXIO0_D22

FXIO0_D23

PTC11/

LLWU_P11

84

85

86

—

PTC12

PTC13

PTC14

DISABLED

PTC12

PTC13

PTC14

LPI2C1_SCLS

LPI2C1_SDAS

TPM0_CLKIN

TPM1_CLKIN

EMVSIM0_

CLK

30

NXP Semiconductors

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

Pinouts and Packaging

100

64

Pin Name

Default

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

LQFP LQFP

87

—

PTC15

DISABLED

PTC15

EMVSIM0_

RST

88

89

90

—

VSS

VDD

PTC16

DISABLED

PTC16

EMVSIM0_

VCCEN

91

92

93

—

57

PTC17

PTC18

DISABLED

PTC17

PTC18

EMVSIM0_IO

LPSPI0_PCS3

EMVSIM0_PD LPSPI0_PCS2

PTD0/

LLWU_P12

PTD0/

LLWU_P12

LPSPI0_PCS0 LPUART2_

RTS_b

TPM0_CH0

TPM0_CH1

FXIO0_D0

FXIO0_D1

FXIO0_D2

94

95

58

59

PTD1

ADC0_SE5b

DISABLED

ADC0_SE5b

PTD1

LPSPI0_SCK

LPUART2_

CTS_b

PTD2/

LLWU_P13

PTD2/

LLWU_P13

LPSPI0_

SOUT

LPUART2_RX TPM0_CH2

96

97

60

61

PTD3

DISABLED

PTD3

LPSPI0_SIN

LPUART2_TX

TPM0_CH3

FXIO0_D3

FXIO0_D4

PTD4/

LLWU_P14

PTD4/

LLWU_P14

LPSPI1_PCS0 LPUART2_RX TPM0_CH4

LPUART0_

RTS_b

98

99

62

63

64

PTD5

ADC0_SE6b

ADC0_SE7b

DISABLED

ADC0_SE6b

ADC0_SE7b

PTD5

LPSPI1_SCK

LPUART2_TX

LPUART0_RX

LPUART0_TX

TPM0_CH5

LPUART0_

CTS_b

FXIO0_D5

FXIO0_D6

FXIO0_D7

PTD6/

LLWU_P15

PTD6/

LLWU_P15

LPSPI1_

SOUT

100

PTD7

LPSPI1_SIN

4.2 K32 L2A Pinouts

The below figure shows the pinout diagram for the devices supported by this

document. Many signals may be multiplexed onto a single pin. To determine what

signals can be used on which pin, see the previous section.

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

31

NXP Semiconductors

Pinouts and Packaging

1

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

PTE0

PTE1/LLWU_P0

PTE2/LLWU_P1

PTE3

VDD

2

VSS

3

PTC3/LLWU_P7

PTC2

4

5

PTC1/LLWU_P6

PTC0

PTE4/LLWU_P2

PTE5

6

7

PTB23

PTB22

PTB21

PTB20

PTB19

PTB18

PTB17

PTB16

PTB11

PTE6/LLWU_P16

VDD

8

9

VSS

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

USB0_DP

USB0_DM

VOUT33

VREGIN

PTE16

PTE17/LLWU_P19

PTE18/LLWU_P20

PTE19

PTB10

PTB9

PTB8

PTE20

PTB7

PTE21

PTB3

PTE22

PTB2

PTE23

PTB1

VDDA

PTB0/LLWU_P5

PTA20

VREFH/VREF_OUT

VREFL

PTA19

VSSA

Figure 4. 100 LQFP Pinout Diagram

32

NXP Semiconductors

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

Dimensions

PTE0

PTE1/LLWU_P0

VDD

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

VDD

VSS

2

3

PTC3/LLWU_P7

PTC2

VSS

4

USB0_DP

USB0_DM

VOUT33

VREGIN

5

PTC1/LLWU_P6

PTC0

6

7

PTB19

8

PTB18

PTE20

9

PTB17

PTE21

10

11

12

13

14

15

16

PTB16

PTE22

PTB3

PTE23

PTB2

VDDA

PTB1

VREFH/VREF_OUT

VREFL

PTB0/LLWU_P5

PTA20

VSSA

PTA19

Figure 5. 64 LQFP Pinout Diagram

5 Dimensions

5.1 Obtaining package dimensions

Package dimensions are provided in package drawings.

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

33

NXP Semiconductors

Ratings

To find a package drawing, go to nxp.com and perform a keyword search for the

drawing’s document number:

If you want the drawing for this package

64-pin LQFP

Then use this document number

98ASS23234W

98ASS23308W

100-pin LQFP

6 Ratings

6.1 Thermal handling ratings

Table 8. Thermal handling ratings

Symbol

T_STG

Description

Min.

Max.

150

Unit

°C

Notes

Storage temperature

–55

1

2

T_SDR

Solder temperature, lead-free

—

260

°C

1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.

2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

6.2 Moisture handling ratings

Table 9. Moisture handling ratings

Symbol

Description

Min.

Max.

Unit

Notes

MSL

Moisture sensitivity level

—

3

—

1

1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

6.3 ESD handling ratings

Table 10. ESD handling ratings

Symbol

V_HBM

Description

Min.

–2000

–500

Max.

+2000

+500

Unit

V

Notes

Electrostatic discharge voltage, human body model

1

2

V_CDM

Electrostatic discharge voltage, charged-device

model

V

Table continues on the next page...

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

34

NXP Semiconductors

General

Table 10. ESD handling ratings (continued)

Symbol

Description

Min.

Max.

Unit

Notes

I_LAT

Latch-up current at ambient temperature of 105 °C

–100

+100

mA

3

1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human

Body Model (HBM).

2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for

Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.

3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.

6.4 Voltage and current operating ratings

Table 11. Voltage and current operating ratings

Symbol

V_DD

I_DD

Description

Min.

–0.3

—

Max.

3.8

Unit

V

Digital supply voltage

Digital supply current

IO pin input voltage

120

mA

V

V_IO

–0.3

–25

V_DD+ 0.3

25

I_D

Instantaneous maximum current single pin limit (applies to

all port pins)

mA

V_DDA

Analog supply voltage

USB_DP input voltage

USB_DM input voltage

USB regulator input

V_DD– 0.3

–0.3

V_DD+ 0.3

3.63

V

V_{USB_DP}

V_{USB_DM}

V_REGIN

–0.3

3.63

–0.3

6.0

7 General

7.1 AC electrical characteristics

Unless otherwise specified, propagation delays are measured from the 50% to the 50%

point, and rise and fall times are measured at the 20% and 80% points, as shown in the

following figure.

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

35

NXP Semiconductors

General

High

Low

V_IH

80%

50%

20%

Input Signal

Midpoint1

V_IL

Fall Time

Rise Time

The midpoint is V_IL+ (V_IH- V_IL) / 2

Figure 6. Input signal measurement reference

All digital I/O switching characteristics, unless otherwise specified, assume that the

output pins have the following characteristics.

• C_L=30 pF loads

• Slew rate disabled

• Normal drive strength

7.2 Nonswitching electrical specifications

7.2.1 Voltage and current operating requirements

Table 12. Voltage and current operating requirements

Symbol

V_DD

Description

Min.

1.71

–0.1

Max.

3.6

Unit

V

Notes

Supply voltage

V_DDA

Analog supply voltage

3.6

V

V_DD– V_DDAV_DD-to-V_DDAdifferential voltage

V_SS– V_SSAV_SS-to-V_SSAdifferential voltage

0.1

V

0.1

V

V_IH

Input high voltage

• 2.7 V ≤ V_DD≤ 3.6 V

• 1.71 V ≤ V_DD≤ 2.7 V

0.7 × V_DD

—

V

0.75 × V_DD

V_IL

Input low voltage

• 2.7 V ≤ V_DD≤ 3.6 V

• 1.71 V ≤ V_DD≤ 2.7 V

—

0.35 × V_DD

0.3 × V_DD

V

V_HYS

I_ICIO

Input hysteresis

0.06 × V_DD

-5

—

V

IO pin negative DC injection current — single pin

• V_IN< V_SS-0.3V

1

mA

Table continues on the next page...

36

NXP Semiconductors

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

General

Notes

Table 12. Voltage and current operating requirements (continued)

Symbol

Description

Min.

Max.

Unit

I_ICcont

Contiguous pin DC injection current —regional limit,

includes sum of negative injection currents of 16

contiguous pins

-25

—

mA

• Negative current injection

V_ODPU

V_RAM

Open drain pullup voltage level

V_DD

1.2

V_DD

—

V

2

V_DDvoltage required to retain RAM

1. All I/O pins are internally clamped to V_SSthrough a ESD protection diode. There is no diode connection to V_DD. If V_IN

greater than V_{IO_MIN}(= V_SS-0.3 V) is observed, then there is no need to provide current limiting resistors at the pads. If

this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting

resistor is calculated as R = (V_{IO_MIN}- V_IN)/|I_ICIO|.

2. Open drain outputs must be pulled to V_DD

.

7.2.2 LVD, HVD, and POR operating requirements

Table 13. V_DDsupply LVD, HVD, and POR operating requirements

Symbol Description

Min.

0.8

Typ.

1.1

Max.

1.5

Unit

V

Notes

—

V_POR

Falling V_DDPOR detect voltage

V_LVDH

Falling low-voltage detect threshold — high

range (LVDV = 01)

2.48

2.56

2.64

V

—

Low-voltage warning thresholds — high range

• Level 1 falling (LVWV = 00)

1

V_LVW1H

V_LVW2H

V_LVW3H

V_LVW4H

2.62

2.72

2.82

2.92

—

2.70

2.80

2.90

3.00

60

2.78

2.88

2.98

3.08

—

V

• Level 2 falling (LVWV = 01)

• Level 3 falling (LVWV = 10)

V

• Level 4 falling (LVWV = 11)

V

V_HYSH

V_LVDL

Low-voltage inhibit reset/recover hysteresis —

high range

mV

—

1

Falling low-voltage detect threshold — low

range (LVDV=00)

1.54

1.60

1.66

V

Low-voltage warning thresholds — low range

• Level 1 falling (LVWV = 00)

V_LVW1L

V_LVW2L

V_LVW3L

V_LVW4L

1.74

1.84

1.94

2.04

—

1.80

1.90

2.00

2.10

40

1.86

1.96

2.06

2.16

—

V

• Level 2 falling (LVWV = 01)

• Level 3 falling (LVWV = 10)

V

• Level 4 falling (LVWV = 11)

V

V_HYSL

Low-voltage inhibit reset/recover hysteresis —

low range

mV

—

V_BG

t_LPO

Bandgap voltage reference

0.97

900

1.00

1.03

V

—

Internal low power oscillator period — factory

trimmed

1000

1100

μs

Table continues on the next page...

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

37

NXP Semiconductors

General

Table 13. V_DDsupply LVD, HVD, and POR operating requirements (continued)

Symbol Description

Min.

Typ.

Max.

Unit

Notes

V_HVDL

V_HVDH

V_HYSH

High voltage detect threshold — low range

(HVDV=0) — Rising

3.4

3.5

3.6

V

2

High voltage detect threshold — low range

(HVDV=0) — Falling

3.35

3.65

3.6

—

3.45

3.75

3.7

50

3.55

3.85

3.8

—

High voltage detect threshold — high range

(HVDV=1) — Rising

V

2

High voltage detect threshold — high range

(HVDV=1) — Falling

High voltage detect hysteresis — low range

(HVDV=0)

mV

—

High voltage detect hysteresis — high range

(HVDV=1)

—

50

—

1. Rising thresholds are falling threshold + hysteresis voltage

2. The selection of high voltage detect trip voltage is controlled by PMC_HVDSC1[HVDV].

7.2.3 Voltage and current operating behaviors

Table 14. Voltage and current operating behaviors

Symbol Description

V_OHOutput high voltage — Normal drive pad

Min.

Typ.

Max.

Unit

Notes

1

• 2.7 V ≤ V_DD≤ 3.6 V, I_OH= –5 mA

• 1.71 V ≤ V_DD≤ 2.7 V, I_OH= –2.5 mA

V_DD– 0.5

—

V

V_OH

Output high voltage — High drive pad

• 2.7 V ≤ V_DD≤ 3.6 V, I_OH= –20 mA

• 1.71 V ≤ V_DD≤ 2.7 V, I_OH= –10 mA

1

V_DD– 0.5

—

V

I_OHT

V_OL

Output high current total for all ports

Output low voltage — Normal drive pad

• 2.7 V ≤ V_DD≤ 3.6 V, I_OL= 5 mA

• 1.71 V ≤ V_DD≤ 2.7 V, I_OL= 2.5 mA

100

mA

1

—

0.5

V

V_OL

Output low voltage — High drive pad

• 2.7 V ≤ V_DD≤ 3.6 V, I_OL= 20 mA

• 1.71 V ≤ V_DD≤ 2.7 V, I_OL= 10 mA

—

0.5

100

1

V

I_OLT

I_IN

Output low current total for all ports

mA

μA

Input leakage current (per pin) for full

temperature range

2

I_IN

Input leakage current (per pin) at 25 °C

—

0.025

μA

Table continues on the next page...

38

NXP Semiconductors

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

General

Table 14. Voltage and current operating behaviors (continued)

Symbol Description

Min.

Typ.

Max.

Unit

Notes

I_IN

Input leakage current (total all pins) for full

—

41

μA

2

temperature range

I_OZ

Hi-Z (off-state) leakage current (per pin)

Internal pullup resistors

—

1

μA

kΩ

R_PU

20

50

3

1. PTB0, PTB1, PTC3, PTC4, PTD4, PTD5, PTD6 and PTD7 I/O have both high drive and normal drive capability

selected by the associated PORTx_PCRn[DSE] control bit. All other GPIOs are normal drive only. PTD4, PTD5,

PTD6, PTD7, PTE20, PTE21, PTE22, and PTE23 are also fast pins.

2. Measured at V_DD= 3.6 V

3. Measured at V_DDsupply voltage = V_DDmin and Vinput = V_SS

7.2.4 Power mode transition operating behaviors

All specifications in the following table assume this clock configuration in Run mode:

• CPU and system clocks = 48 MHz

• Bus and flash clock = 24 MHz

• SCG configured in FIRC mode; peripheral functional clocks from

FIRCDIV3_CLK and USB clock from FIRCDIV1_CLK

Table 15. Power mode transition operating behaviors

Symbol Description

Min.

Typ.

Max.

Unit

Notes

t_PORAfter a POR event, amount of time from the

—

300

μs

1

point V_DDreaches 1.8 V to execution of the first

instruction across the operating temperature

range of the chip.

• VLLS0 → RUN

• VLLS1 → RUN

• VLLS2 → RUN

• VLLS3 → RUN

• LLS3 → RUN

• LLS2 → RUN

—

188

125

5.5

193

130

6.1

μs

5.5

6.1

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K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

39

NXP Semiconductors

General

Table 15. Power mode transition operating behaviors (continued)

Symbol Description

• VLPS → RUN

Min.

Typ.

Max.

Unit

Notes

—

5.5

6.1

μs

• STOP → RUN

—

5.5

6.1

μs

1. Normal boot (FTFA_FOPT[LPBOOT]=11).

7.2.5 Power consumption operating behaviors

NOTE

The values in the following table are based on

characterization data with a few samples.

NOTE

The actual power consumption measured in the related

condition, with certain peripherals running, is the sum of

related low power current consumption of the device listed in

Table 16 and the related low power mode peripheral adders in

Table 17.

NOTE

The maximum values represent characterized results

equivalent to the mean plus three times the standard deviation

(mean + 3σ).

Table 16. Power consumption operating behaviors

Symbol

Description

Min.

Typ.

Max.

Unit

Notes

I_DDA

Analog supply current

—

See note

mA

1

2

I_{DD_HSRUN}High speed run mode current at 96 MHz

- all peripheral clocks disabled, code

executing from flash, while(1) loop

• at 1.8 V

• at 3.0 V

—

12.6

12.8

17.4

17.6

mA

I_{DD_HSRUN}High speed run mode current at 96 MHz

- all peripheral clocks enabled, code

3

executing from flash, while(1) loop

• at 1.8 V

• at 3.0 V

—

15.5

15.7

20.4

20.6

mA

Table continues on the next page...

40

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

NXP Semiconductors

General

Table 16. Power consumption operating behaviors (continued)

Symbol

Description

Min.

Typ.

Max.

Unit

Notes

I_{DD_RUN}

Run mode current at 72 MHz - all

peripheral clocks disabled, code

executing from flash, while(1) loop

4

5

6

7

• at 1.8 V

• at 3.0 V

—

9.4

9.6

13.6

13.8

mA

I_{DD_RUN}

Run mode current at 48 Mhz - all

peripheral clocks disabled, code

executing from flash, while(1) loop

—

7.3

7.4

11.4

11.5

mA

• at 1.8 V

• at 3.0 V

Run mode current at 72 MHz - all

peripheral clocks enabled, code

executing from flash, while(1) loop

—

11.6

11.7

15.9

16.0

mA

• at 1.8 V

• at 3.0 V

Run mode current at 48 Mhz - all

peripheral clocks enabled, code

executing from flash, while(1) loop

—

8.9

9.1

13.1

13.3

mA

• at 1.8 V

• at 3.0 V

I_{DD_WAIT}

I_{DD_VLPR}

Wait mode high frequency current at 72

MHz, at 3.0 V - all peripheral clocks

disabled, while(1) loop

—

7.0

9.0

mA

μA

4

5

Wait mode current at 3.0 V at 48 Mhz —

all peripheral clocks disabled, while(1)

loop

5.7

10.4

Very-low-power run mode current at 3.0

V — all peripheral clocks enabled at 4

MHz, while(1) loop

483.7

557.6

400.3

415.2

285.9

1011.7

1720.2

926.5

941.1

1145.6

8

Very-low-power run mode current at 3.0

V — all peripheral clocks enabled at 8

MHz, while(1) loop

9

Very-low-power run mode current at 3.0

V — all peripheral clocks disabled at 4

MHz, while(1) loop

10

11

10

Very-low-power run mode current at 3.0

V — all peripheral clocks disabled at 8

MHz, while(1) loop

I_{DD_VLPW}Very-low-power wait mode current at

3.0 V — all peripheral clocks disabled at

4 MHz, while(1) loop

Table continues on the next page...

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

41

NXP Semiconductors

General

Table 16. Power consumption operating behaviors (continued)

Symbol

Description

Min.

Typ.

Max.

Unit

Notes

I_{DD_VLPW}Very-low-power wait mode current at

3.0 V — all peripheral clocks disabled at

8 MHz, while(1) loop

—

415.6

1498.7

μA

11

I_{DD_STOP}

Stop mode current at 3.0 V

• -40 to 25 °C

—

264.5

287.0

325.3

374.7

496.7

320.5

356.1

445.4

590.8

952.3

μA

• at 50 °C

• at 70 °C

• at 85 °C

• at 105 °C

I_{DD_VLPS}

Very-low-power stop mode current at

3.0 V

—

4.2

16.4

35.9

μA

• -40 to 25 °C

11.0

24.0

44.0

93.4

• at 50 °C

• at 70 °C

• at 85 °C

• at 105 °C

84.5

156.2

300.2

I_{DD_LLS2}

Low-leakage stop mode 2 current at 3.0

V

—

2.7

4.7

5.4

μA

• -40 to 25 °C

10.6

22.7

49.0

88.6

• at 50 °C

• at 70 °C

• at 85 °C

• at 105 °C

8.6

14.7

30.4

I_{DD_LLS3}

Low-leakage stop mode 3 current at 3.0

V

—

3.0

5.9

14.5

32.0

65.2

122.0

μA

• -40 to 25 °C

• at 50 °C

• at 70 °C

• at 85 °C

• at 105 °C

11.4

19.7

40.9

I_{DD_VLLS3}Very-low-leakage stop mode 3 current

at 3.0 V

—

2.2

4.6

5.1

μA

• -40 to 25 °C

• at 50 °C

• at 70 °C

• at 85 °C

• at 105 °C

10.9

24.4

44.8

91.0

9.0

15.9

33.1

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42

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

NXP Semiconductors

General

Table 16. Power consumption operating behaviors (continued)

Symbol

Description

Min.

Typ.

Max.

Unit

Notes

I_{DD_VLLS2}Very-low-leakage stop mode 2 current

at 3.0 V

—

1.8

3.3

3.4

6.8

μA

• -40 to 25 °C

• at 50 °C

• at 70 °C

• at 85 °C

• at 105 °C

6.1

14.5

26.4

54.4

10.4

21.6

I_{DD_VLLS1}Very-low-leakage stop mode 1 current

at 3.0V

—

0.65

1.1

2.1

3.6

8.5

0.88

1.6

μA

• -40 to 25 °C

• at 50 °C

• at 70 °C

• at 85 °C

• at 105 °C

3.3

21.0

32.2

I_{DD_VLLS0}Very-low-leakage stop mode 0 current

(SMC_STOPCTRL[PORPO] = 0) at 3.0

V

—

372.0

768.6

1734

3291

8025

598

1331

3038

20575

27560

nA

• -40 to 25 °C

• at 50 °C

• at 70 °C

• at 85 °C

• at 105 °C

I_{DD_VLLS0}Very-low-leakage stop mode 0 current

12

(SMC_STOPCTRL[PORPO] = 1) at 3.0

V

—

94.1

480.9

1416

2970

7642

311

1024

2760

19574

27325

nA

• -40 to 25 °C

• at 50 °C

• at 70 °C

• at 85 °C

• at 105 °C

1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device.

See each module's specification for its supply current.

2. 96 MHz core and system clock (DIVCORE_CLK), 24 MHz bus/slow clock(DIVSLOW_CLK), and 24 MHz flash clock.

SCG configured as System PLL mode (SCG_HCCR[SCS]=0110), PLL clock source is SOSC from external 8 MHz

crystal. All peripheral functional clocks disabled by clearing all xxDIV3, xxDIV2, and xxDIV1 in SCG_SOSCDIV and

SCG_SPLLDIV registers. FIRC and SIRC disabled by clearing SCG_FIRCCSR[FIRCEN] and

SCG_SIRCCSR[SIRCEN].

3. 96 MHz core and system clock (DIVCORE_CLK), 24 MHz bus/slow clock(DIVSLOW_CLK), and 24 MHz flash clock.

SCG configured as System PLL mode (SCG_HCCR[SCS]=0110), PLL clock source is SOSC from external 8 MHz

crystal. All peripheral functional clocks except USB = 24 MHz from SPLLDIV3_CLK. USB functional clock = 48 MHz

from SPLLDIV1_CLK. FIRC and SIRC disabled by clearing SCG_FIRCCSR[FIRCEN] and SCG_SIRCCSR[SIRCEN].

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

43

NXP Semiconductors

General

4. 72 MHz core and system clock (DIVCORE_CLK), 24 MHz bus/slow clock(DIVSLOW_CLK), and 24 MHz flash clock.

SCG configured as System PLL mode (SCG_RCCR[SCS]=0110), PLL clock source is SOSC from external 8 MHz

crystal. All peripheral functional clocks disabled by clearing all xxDIV3, xxDIV2, and xxDIV1 in SCG_SOSCDIV and

SCG_SPLLDIV registers. FIRC and SIRC disabled by clearing SCG_FIRCCSR[FIRCEN] and SCG_SIRCCSR[SIRCEN].

5. 48 MHz core and system clock (DIVCORE_CLK), 24 MHz bus/slow clock(DIVSLOW_CLK), and 24 MHz flash clock.

SCG configured as FIRC 48 MHz mode (SCG_RCCR[SCS]=0011). All peripheral functional clocks disabled by clearing

all xxDIV3, xxDIV2, and xxDIV1 in SCG_FIRCDIV register. PLL, SOSC, and SIRC disabled by clearing

SCG_SPLLCSR[SPLLEN], SCG_SOSCCSR[SOSCEN], and SCG_SIRCCSR[SIRCEN].

6. 72 MHz core and system clock (DIVCORE_CLK), 24 MHz bus/slow clock(DIVSLOW_CLK), and 24 MHz flash clock.

SCG configured as System PLL mode (SCG_RCCR[SCS]=0110), PLL clock source is SOSC from external 8 MHz

crystal. All peripheral functional clocks except USB = 24 MHz from SPLLDIV3_CLK. USB functional clock = 48 MHz

from SPLLDIV1_CLK. FIRC and SIRC disabled by clearing SCG_FIRCCSR[FIRCEN] and SCG_SIRCCSR[SIRCEN].

7. 48 MHz core and system clock (DIVCORE_CLK), 24 MHz bus/slow clock(DIVSLOW_CLK), and 24 MHz flash clock.

SCG configured as FIRC 48 MHz mode (SCG_RCCR[SCS]=0011). All peripheral functional clocks except USB = 24

MHz from FIRCDIV3_CLK. USB functional clock = 48 MHz from FIRCDIV1_CLK. PLL, SOSC, and SIRC disabled by

clearing SCG_SPLLCSR[SPLLEN], SCG_SOSCCSR[SOSCEN], and SCG_SIRCCSR[SIRCEN].

8. 4 MHz core and system clock (DIVCORE_CLK), 1 MHz bus/slow clock(DIVSLOW_CLK), and 1 MHz flash clock. SCG

configured as SIRC 8 MHz mode (SCG_VCCR[SCS]=0010). All peripheral functional clocks except USB = 1M Hz from

SIRCDIV3_CLK. USB clock disabled. PLL, SOSC, and FIRC disabled by clearing SCG_SPLLCSR[SPLLEN],

SCG_SOSCCSR[SOSCEN], and SCG_FIRCCSR[FIRCEN].

9. 8 MHz core and system clock (DIVCORE_CLK), 1 MHz bus/slow clock(DIVSLOW_CLK), and 1 MHz flash clock. SCG

configured as SIRC 8 MHz mode (SCG_VCCR[SCS]=0010). All peripheral functional clocks except USB = 1M Hz from

SIRCDIV3_CLK. USB clock disabled. PLL, SOSC, and FIRC disabled by clearing SCG_SPLLCSR[SPLLEN],

SCG_SOSCCSR[SOSCEN], and SCG_FIRCCSR[FIRCEN].

10. 4 MHz core and system clock (DIVCORE_CLK), 1 MHz bus/slow clock(DIVSLOW_CLK), and 1 MHz flash clock. SCG

configured as SIRC 8 MHz mode (SCG_VCCR[SCS]=0010). All peripheral functional clocks disabled by clearing all

xxDIV3, xxDIV2, and xxDIV1 in SCG_SIRCDIV register. PLL, SOSC, and FIRC disabled by clearing

SCG_SPLLCSR[SPLLEN], SCG_SOSCCSR[SOSCEN], and SCG_FIRCCSR[FIRCEN].

11. 8 MHz core and system clock (DIVCORE_CLK), 1 MHz bus/slow clock(DIVSLOW_CLK), and 1 MHz flash clock. SCG

configured as SIRC 8 MHz mode (SCG_VCCR[SCS]=0010). All peripheral functional clocks disabled by clearing all

xxDIV3, xxDIV2, and xxDIV1 in SCG_SIRCDIV register. PLL, SOSC, and FIRC disabled by clearing

SCG_SPLLCSR[SPLLEN], SCG_SOSCCSR[SOSCEN], and SCG_FIRCCSR[FIRCEN].

12. No brownout

Table 17. Low power mode peripheral adders — typical value

Symbol

Description

Temperature (°C)

Unit

-40

25

50

70

85

105

I_EREFSTEN8MHz

External 8 MHz crystal clock adder with 402.9 462.1 477.5

System OSC. Measured by entering

VLPS mode with the crystal enabled

(SCG_SOSCCFG[RANGE] = 10,

492

506.2 530.4

uA

SCG_SOSCCFG[HGO] = 0,

SCG_SOSCCFG[EREFS] = 1, and

SC2P/SC4P/SC8P = 0).

I_{EREFSTEN32KHz}

External 32 kHz crystal clock adder with

System OSC by means of

SCG_SOSCCFG[RANGE] = 01,

SCG_SOSCCFG[HGO] = 0,

SCG_SOSCCFG[EREFS] = 1, and

SC2P/SC4P/SC8P = 0. Measured by

entering all the following modes with the

crystal enabled:

• VLLS1

nA

373.9 539.2 612.3 644.9 523.7 1000

568.4 552.6 650.8 757.9 995.6 1400

582.8 565.0 615.5 797.1 968.5 1700

• VLLS3

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K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

44

NXP Semiconductors

General

Table 17. Low power mode peripheral adders — typical value (continued)

Symbol

Description

Temperature (°C)

50 70

Unit

-40

25

85

105

• LLS3

• VLPS

• STOP

472.4 635.2 776.9 425.6 1500 2800

528.0 534.1 636.6 9600 20300 40900

I_LPTMR

LPTMR peripheral adder measured by

placing the device in VLLS1 mode with

LPTMR enabled using LPO clock.

151.0

18.8

7.7

21.8

19.9

7.6

174.0 31.0

nA

µA

I_CMP

CMP peripheral adder measured by

placing the device in VLLS1 mode with

CMP enabled using the 6-bit DAC and a

single external input for compare.

19.6

20.0

20.4

20.5

Includes 6-bit DAC power consumption.

I_RTC

RTC peripheral adder measured by

placing the device in VLLS1 mode and

the RTC ALARM set for 1 minute.

Includes selected clock source power

consumption.

• OSC32KCLK (32KHz external

crystal)

• LPO (internal 1K Hz Low Power

Oscillator)

116.0 1400 1400 1500 1500 120.0

nA

35.0

1400 1400 1600 1400 120.0

I_LPUART

LPUART peripheral adder measured by

placing the device in STOP mode with

selected clock source waiting for RX

data at 115200 baud rate. Includes

selected clock source power

consumption.

85.7

41.2

89.4

43.5

87.3

38.7

88.4

36.8

85.3

39.6

86.6

37.0

µA

• Slow IRC clock from SCG (8 MHz

internal reference clock)

• OSCERCLK (8 MHz external

crystal)

I_LPSPI

LPSPI peripheral adder measured by

placing the device in VLPS mode with

selected clock source, LPSPI is

configured as master mode with bit rate

of 4 Mbps. Includes selected clock

source power consumption.

69.4

66.7

65.9

66.1

65.8

66.0

µA

• Slow IRC clock from SCG (8 MHz

internal reference clock)

• OSCERCLK (8 MHz external

crystal)

431.9 489.9 503.5 518.6 533.0 557.0

I_TPM

TPM peripheral adder measured by

placing the device in STOP mode with

selected clock source configured for

output compare generating 100 Hz

clock signal. No load is placed on the

I/O generating the clock signal. Includes

selected clock source and I/O switching

currents.

µA

80.7

35.5

84.2

37.2

84.2

37.3

84.4

37.1

84.8

37.7

86.3

37.7

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K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

45

NXP Semiconductors

General

Table 17. Low power mode peripheral adders — typical value (continued)

Symbol

Description

Temperature (°C)

Unit

-40

25

50

70

85

105

• Slow IRC clock from SCG (8 MHz

internal reference clock)

• OSCERCLK (8 MHz external

crystal)

I_LPI2C

LPI2C peripheral adder measured by

placing the device in VLPS mode with

selected clock source, LPI2C is

configured as master, and bit rate is

400 Kbps. Includes selected clock

source power consumption.

• Slow IRC clock from SCG (8 MHz

internal reference clock)

µA

69.7

66.7

66.9

67.6

68.2

582.9 597.9 610.8 623.8 637.0 660.2

• OSCERCLK (8 MHz external

crystal)

I_BG

Bandgap adder when BGEN bit is set

and device is placed in VLPS mode.

• Bandgap buffer disabled

µA

96.8

95.4

96.4

98.2

98.5

137.5 129.6 133.0 135.5 136.9 139.6

372.9 380.5 384.0 388.3 392.2 394.6

• Bandgap buffer enabled

I_ADC

ADC peripheral adder combining the

measured values at V_DDand V_DDAby

placing the device in STOP mode. ADC

is configured for low power mode using

the ADC asynchronous clock (ADACK)

and continuous conversions.

I_WDOG

WDOG peripheral adder measured by

placing the device in STOP mode,

WDOG is configured to time out at 1

second. Includes selected clock source

power consumption.

µA

68.8

11.2

56.0

68.5

10.1

57.1

69.2

10.1

58.6

69.9

10.2

58.5

71.7

10.5

58.6

72.6

10.7

60.0

• Slow IRC clock from SCG (8 MHz

internal reference clock)

• OSCERCLK (8 MHz external

crystal)

• LPO (internal 1 kHz Lower Power

Oscillator)

I_{SIRC_8MHz}

SIRC adder when SIRC is configured to 67.2

8 MHz. Measured by entering VLPS

mode with 8 MHz IRC enabled, and

63.0

21.2

63.3

21.4

63.2

21.5

63.3

21.7

63.6

21.4

µA

SIRCDIV1, SIRCDIV2, SIRCDIV3 =000.

I_{SIRC_2MHz}

SIRC adder when SIRC is configured to 22.3

2 MHz. Measured by entering STOP or

VLPS mode with 2 MHz IRC enabled,

and SIRCDIV1, SIRCDIV2, SIRCDIV3

=000.

46

NXP Semiconductors

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

General

7.2.5.1 Diagram: Typical IDD_RUN operating behavior

The following data was measured under these conditions:

• SCG is configured as SPLL mode with SOSC as the clock source for RUN mode

current measurement, and as SIRC mode for VLPR mode current measurement

• USB regulator disabled

• No GPIOs toggled

• Code execution from flash with cache enabled

• For the ALLOFF curve, all peripheral clocks are disabled except FTFA

• For the ALLON curve, all peripheral clocks are enabled as specified in notes of

Power consumption operating behaviors.

Figure 7. Run mode supply current vs. core frequency

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

47

NXP Semiconductors

General

Figure 8. VLPR mode supply current vs. core frequency

7.2.6 EMC radiated emissions operating behaviors

Table 18. EMC radiated emissions operating behaviors

Symbol

Description

Frequency

band

Typ.

Unit

Notes

(MHz)

V_RE1

V_RE2

Radiated emissions voltage, band 1

Radiated emissions voltage, band 2

Radiated emissions voltage, band 3

Radiated emissions voltage, band 4

IEC level

0.15–50

50–150

18

21

24

L

dBμV

—

1, 2

V_RE3

150–500

500–1000

0.15–1000

V_RE4

V_{RE_IEC}

2, 3

1. Determined according to IEC Standard 61967-2 (and SAE J1752/3), Integrated Circuits - Measurement of

Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and Wideband

TEM Cell Method. Measurements were made while the microcontroller was running basic application code. The reported

emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the

measured orientations in each frequency range.

48

NXP Semiconductors

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

General

2. V_DD= 3.3 V, V_REGIN= 5V, T_A= 25 °C, f_OSC= 8 MHz (crystal), f_{SYS_CORE}= 96 MHz, f_BUS= 24 MHz

3. IEC/SAE level maximum: L≤24dB mV

7.2.7 Designing with radiated emissions in mind

To find application notes that provide guidance on designing your system to minimize

interference from radiated emissions:

1. Go to www.nxp.com.

2. Perform a keyword search for “EMC design.”

7.2.8 Capacitance attributes

Table 19. Capacitance attributes

Symbol

Description

Min.

Max.

Unit

C_IN

Input capacitance

—

7

pF

7.3 Switching specifications

7.3.1 Device clock specifications

Table 20. Device clock specifications

Symbol

Description

Min.

Max.

Unit

Run mode¹

Normal run mode

f_SYS

System and core clock (DIVCORE_CLK)

—

96

72

MHz High speed run

mode

MHz Normal speed run

mode

—

8

MHz VLPR mode

f_BUS

Bus clock/Slow clock (DIVSLOW_CLK)

Flash clock

24

MHz High speed run

mode and Normal

speed run mode

—

1

MHz VLPR mode

f_FLASH

24

MHz High speed run

mode and Normal

speed run mode

—

1

MHz VLPR mode

KHz All modes

f_LLWU

f_RCM

LLWU clock

RCM clock

Table continues on the next page...

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

49

NXP Semiconductors

General

Table 20. Device clock specifications (continued)

Symbol

Description

Min.

Max.

Unit

Run mode¹

f_WDOG, f_TSIWDOG clock, TSI clock

—

24

MHz High speed run

mode and Normal

speed run mode

—

1

24²

MHz VLPR mode

f_ADC

ADC clock

MHz High speed run

mode and Normal

speed run mode

—

8

32.768

1

MHz VLPR mode

KHz All modes

MHz All modes

f_RTC

f_TSTMR

RTC clock

TSTMR clock

LPTMR clock

f_LPTMR

24

f_TPM, f_LPIT

f_LPSPI, f_LPI2C

,

TPM clock, LPIT clock, LPSPI clock, LPI2C clock,

, LPUART clock, EMVSIM clock, FlexIO clock

96

MHz High speed run

mode

f_LPUART

f_EMVSIM

f_FLEXIO

,

—

72

MHz Normal speed run

mode

—

8

MHz VLPR mode

f_USB

USB clock

48

MHz High speed run

mode and Normal

speed run mode

—

0

MHz VLPR mode

f_ERCLK

External reference clock

48

MHz High speed run

mode and Normal

speed run mode

16

32

MHz VLPR mode

f_{osc_hi_2}

Oscillator crystal or resonator frequency — high

frequency mode (high range)

(SCG_SOSCCFG[RANGE]=11)

—

MHz High speed run

mode and Normal

speed run mode

—

16

96

MHz VLPR mode

f_CAU, f_GPIOCAU clock, GPIO clock

MHz High speed run

mode

—

72

8

MHz Normal speed run

mode

MHz VLPR mode

1. Normal run mode, High speed run mode, and VLPR mode.

2. See ADC electrical specifications

7.3.2 General switching specifications

These general-purpose specifications apply to all signals configured for GPIO, LPI2C,

and LPUART signals.

50

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

NXP Semiconductors

General

Table 21. General switching specifications

Description

Min.

Max.

Unit

Notes

GPIO pin interrupt pulse width (digital glitch filter disabled)

— Synchronous path

1.5

—

Bus clock

cycles

1

GPIO pin interrupt pulse width (digital glitch filter disabled,

analog filter enabled) — Asynchronous path

100

50

—

ns

GPIO pin interrupt pulse width (digital glitch filter disabled,

analog filter disabled) — Asynchronous path

External RESET and NMI pin interrupt pulse width —

Asynchronous path

100

16

2

GPIO pin interrupt pulse width — Asynchronous path

Port rise/fall time

Normal drive pins

3

• 2.7 ≤ VDD ≤ 3.6 V

• Fast slew rate

—

3

ns

10.5

• Slow slew rate

• 1.71 ≤ VDD ≤ 2.7 V

• Fast slew rate

—

4

17

• Slow slew rate

High drive pins

4

Normal/low drive enabled

• 2.7 ≤ VDD ≤ 3.6 V

• Fast slew rate

—

2.5

ns

10.5

• Slow slew rate

• 1.71 ≤ VDD ≤ 2.7 V

• Fast slew rate

—

4

17

• Slow slew rate

High drive enabled

• 2.7 ≤ VDD ≤ 3.6 V

• Fast slew rate

—

2

11

• Slow slew rate

• 1.71 ≤ VDD ≤ 2.7 V

• Fast slew rate

—

2.5

17

• Slow slew rate

Normal drive fast pins

5

• 2.7 ≤ VDD ≤ 3.6 V

• Fast slew rate

—

0.5

10

ns

• Slow slew rate

• 1.71 ≤ VDD ≤ 2.7 V

• Fast slew rate

—

0.75

19

• Slow slew rate

High drive fast pins

6

Normal/low drive enabled

• 2.7 ≤ VDD ≤ 3.6 V

—

0.5

ns

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

51

NXP Semiconductors

General

Table 21. General switching specifications

Description

Min.

Max.

Unit

Notes

• Fast slew rate

—

11

• Slow slew rate

• 1.71 ≤ VDD ≤ 2.7 V

• Fast slew rate

—

1

19

• Slow slew rate

High drive enabled

• 2.7 ≤ VDD ≤ 3.6 V

• Fast slew rate

—

2

13

• Slow slew rate

• 1.71 ≤ VDD ≤ 2.7 V

• Fast slew rate

—

4

21

• Slow slew rate

1. The synchronous and asynchronous timing must be met.

2. This is the shortest pulse that is guaranteed to be recognized.

3. For high drive pins with high drive enabled, load is 75pF; other pins load (normal/low drive) is 25pF. Fast slew rate is

enabled by clearing PORTx_PCRn[SRE].

4. High drive pins are PTB0,PTB1, PTC3, and PTC4. High drive capability is enabled by setting PORTx_PCRn[DSE].

5. Normal drive fast pins are PTE20, PTE21, PTE22, and PTE23.

6. High drive fast pins are PTD4, PTD5, PTD6, and PTD7. High drive capability is enabled by setting PORTx_PCRn[DSE].

NOTE

Only PTA4, PTA20, and PTB19 pins have analog/passive

filter.

7.4 Thermal specifications

7.4.1 Thermal operating requirements

Table 22. Thermal operating requirements

Symbol

T_J

Description

Min.

–40

Max.

125

Unit

°C

Notes

Die junction temperature

Ambient temperature

T_A

105

°C

1

1. Maximum T_Acan be exceeded only if the user ensures that T_Jdoes not exceed the maximum. The simplest method to

determine T_Jis: T_J= T_A+ R_θJA× chip power dissipation.

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NXP Semiconductors

Peripheral operating requirements and behaviors

7.4.2 Thermal attributes

Table 23. Thermal attributes

Board type¹

Symbol

Description

100 LQFP 64 LQFP

Unit

Notes

Four-layer (2s2p)

R_θJA

Thermal resistance, junction to

ambient (natural convection)

51

44

°C/W

Four-layer (2s2p)

Ψ_JT

Thermal characterization

4

1.2

°C/W

2

parameter, junction to package top

outside center (natural convection)

1. Thermal test board meets JEDEC specification for this package (JESD51-9).

2. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental

Conditions—Natural Convection (Still Air).

8 Peripheral operating requirements and behaviors

8.1 Core modules

8.1.1 SWD electricals

Table 24. SWD full voltage range electricals

Symbol

Description

Min.

Max.

Unit

Operating voltage

1.71

3.6

V

J1

SWD_CLK frequency of operation

• Serial wire debug

0

25

—

MHz

ns

J2

J3

SWD_CLK cycle period

SWD_CLK clock pulse width

• Serial wire debug

1/J1

20

—

ns

J4

J9

SWD_CLK rise and fall times

—

10

0

3

ns

SWD_DIO input data setup time to SWD_CLK rise

SWD_DIO input data hold time after SWD_CLK rise

SWD_CLK high to SWD_DIO data valid

SWD_CLK high to SWD_DIO high-Z

—

32

—

J10

J11

J12

—

5

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

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NXP Semiconductors

Peripheral operating requirements and behaviors

J2

J4

J3

SWD_CLK (input)

J4

Figure 9. Serial wire clock input timing

SWD_CLK

SWD_DIO

J9

J10

Input data valid

J11

Output data valid

J12

J11

Output data valid

Figure 10. Serial wire data timing

8.2 System modules

There are no specifications necessary for the device's system modules.

8.3 Clock modules

8.3.1 System Clock Generation (SCG) specifications

54

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

NXP Semiconductors

Peripheral operating requirements and behaviors

8.3.1.1 Fast IRC (FIRC) specifications

Table 25. Fast IRC (FIRC) specifications

Symbol

Description

Min.

1.71

Typ.

Max.

3.6

Unit

V

Notes

V_{dd_firc}

Supply voltage

—

F_{firc_target}IRC target frequency (nominal)

Trim range = 00

—

MHz

1

48

52

56

60

Trim range = 01

Trim range = 10

Trim range = 11

Δf_{firc_ol_lv}Open loop total deviation of FIRC frequency at low

voltage (VDD=1.71V-1.89V) over full temperature

• Regulator disable

2

—

0.5

1.5

%F_{firc_targ}

et

(SCG_FIRCCSR[FIRCREGOFF]=1)

• Regulator enable

(SCG_FIRCCSR[FIRCREGOFF]=0)

Δf_{firc_ol_hv}Open loop total deviation of FIRC frequency at high

%F_{firc_targ}2, 3

voltage (VDD=1.89V-3.6V) over full temperature

et

Regulator enable

(SCG_FIRCCSR[FIRCREGOFF]=0)

Δf_{firc_cl}

Fine Trim Resolution

—

0.1

%F_{firc_targ}

et

J_{cyc_firc}

T_{st_firc}

I_{dd_firc}

Period Jitter (RMS)

Startup time

—

35

2

150

3

ps

μs

4

Current consumption:

• 48 MHz

—

350

360

380

400

420

460

500

μA

• 52 MHz

• 56 MHz

• 60 MHz

1. FIRC trim range is programmable via SCG_FIRCCFG[RANGE].

2. For temperatures -40 to 85 °C, the maximum value is 1%, characterized on a few samples of different slots. This

value is not guaranteed by production.

3. Closed loop operation of the FIRC is only usable for USB device operation; it is not usable for USB host operation. It is

enabled by configuring for USB Device, selecting FIRC as USB clock source, and enabling the clock recover function

(USBn_CLK_RECOVER_CTRL[CLOCK_RECOVER_EN]=1, SCG_FIRCCSR[FIRCREGOFF]=0).

4. FIRC startup time is defined as the time between clock enablement and clock availability for system use.

8.3.1.2 Slow IRC (SIRC) specifications

Table 26. Slow IRC specifications

Symbol

Description

Min.

Typ.

Max.

Unit

Notes

I_{DD_sirc2M}Supply current in 2 MHz mode

—

14

17

μA

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NXP Semiconductors

Peripheral operating requirements and behaviors

Table 26. Slow IRC specifications

(continued)

Symbol

Description

Min.

—

Typ.

25

2

Max.

35

Unit

μA

Notes

I_{DD_sirc8M}Supply current in 8 MHz mode

f_sirc

Output frequency

—

MHz

1

2

—

8

—

Δf_sirc

Total deviation of trimmed frequency over voltage

and temperature

%f_sirc

—

3

4

• 0 to 105 °C

• -40 to 0 °C

Δf_{sirc_t}

Total deviation of trimmed frequency over

temperature @V_DD=3.3V

2

3

—

3

%f_sirc

T_{su_sirc}

J_{cyc_sirc}

Startup time

12.5

μs

ps

Period jitter (RMS)

• f_sirc= 2 MHz

• f_sirc= 8 Mhz

—

350

100

—

1. Selection of output frequency for Slow IRC between 2 MHz and 8 MHz is controlled by SCG_ SIRCCFG[RANGE].

2. Maximum deviation occurs at cold temperature (-40 °C) and hot temperature (105 °C).

3. This specification was obtained using a NXP developed PCB. Jitter is dependent on the noise characteristics of each

PCB and results will vary.

8.3.1.3 System PLL specifications

Table 27. System PLL Specifications

Symbol

f_{pll_ref}

Description

Min.

8

Typ.

—

Max.

16

Unit

MHz

Notes

PLL reference frequency range

VCO output frequency

PLL output frequency

f_{vcoclk_2x}

f_vcoclk

I_pll

180

90

—

288

144

—

PLL operating current — VCO @ 180 MHz (f _{osc_hi_2}

= 10 MHz , f _{pll_ref}= 10 MHz ,VDIV multiplier = 18)

1

—

1.1

2.0

—

mA

PLL operating current — VCO @ 288 MHz (f _{osc_hi_2}

= 32 MHz , f _{pll_ref}= 8 MHz ,VDIV multiplier = 36)

J_{cyc_pll}

PLL period jitter (RMS)

• f_vco= 180 MHz

2

—

120

80

—

ps

• f_vco= 288 MHz

J_{acc_pll}

PLL accumilated jitter over 1 μs (RMS)

• f_vco= 180 MHz

—

600

300

—

• f_vco= 288 MHz

D_unl

Lock exit frequency tolerance

Lock detector detection time

4.47

—

5.97

150 × 10^-6

%

s

t_{pll_lock}

—

3

56

NXP Semiconductors

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

Peripheral operating requirements and behaviors

Table 27. System PLL Specifications

Symbol

Description

Min.

Typ.

Max.

Unit

Notes

+ 1075(1/

f _{pll_ref}

)

1. Excludes any oscillator currents that are also consuming power while PLL is in operation.

2. This specification was obtained using an NXP developed PCB. PLL jitter is dependent on the noise characteristics of

each PCB and results will vary.

3. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL

disabled to PLL enabled. If a crystal/resonator is being used as the reference, this specification assumes it is already

running.

8.3.2 Oscillator electrical specifications

8.3.2.1 Oscillator DC electrical specifications

Table 28. Oscillator DC electrical specifications

Symbol Description

V_DDSupply voltage

Min.

Typ.

Max.

Unit

Notes

1.71

—

3.6

V

I_DDOSCSupply current — low-power mode (HGO=0)

1

• 32 kHz

—

500

200

300

950

1.2

—

nA

μA

mA

• 4 MHz

• 8 MHz (RANGE=01)

• 16 MHz

• 24 MHz

• 32 MHz

1.5

I_DDOSCSupply current — high gain mode (HGO=1)

1

• 32 kHz

—

25

400

500

2.5

3

—

μA

• 4 MHz

• 8 MHz (RANGE=01)

• 16 MHz

μA

mA

• 24 MHz

• 32 MHz

4

C_x

C_y

R_F

EXTAL load capacitance

XTAL load capacitance

—

2, 3

2, 4

Feedback resistor — low-frequency, low-power

mode (HGO=0)

MΩ

Feedback resistor — low-frequency, high-gain

mode (HGO=1)

—

10

—

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NXP Semiconductors

Peripheral operating requirements and behaviors

Table 28. Oscillator DC electrical specifications (continued)

Symbol Description

Min.

Typ.

Max.

Unit

Notes

Feedback resistor — high-frequency, low-

—

MΩ

power mode (HGO=0)

Feedback resistor — high-frequency, high-gain

mode (HGO=1)

—

1

—

MΩ

kΩ

R_S

Series resistor — low-frequency, low-power

mode (HGO=0)

Series resistor — low-frequency, high-gain

mode (HGO=1)

200

—

Series resistor — high-frequency, low-power

mode (HGO=0)

Series resistor — high-frequency, high-gain

mode (HGO=1)

—

0

—

kΩ

V

5

V_pp

Peak-to-peak amplitude of oscillation (oscillator

mode) — low-frequency, low-power mode

(HGO=0)

0.6

Peak-to-peak amplitude of oscillation (oscillator

mode) — low-frequency, high-gain mode

(HGO=1)

—

V_DD

1.0

—

V

Peak-to-peak amplitude of oscillation (oscillator

mode) — high-frequency, low-power mode

(HGO=0)

Peak-to-peak amplitude of oscillation (oscillator

mode) — high-frequency, high-gain mode

(HGO=1)

V_DD

1. V_DD=3.3 V, Temperature =25 °C

2. See crystal or resonator manufacturer's recommendation

3. C_x,C_ycan be provided by using the integrated capacitors when the low frequency oscillator (RANGE = 00) is used. For

all other cases external capacitors must be used.

4. When low power mode is selected, R_Fis integrated and must not be attached externally.

5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to

any other devices.

8.3.2.2 Oscillator frequency specifications

Table 29. Oscillator frequency specifications

Symbol Description

Min.

Typ.

Max.

Unit

Notes

f_{osc_lo}Oscillator crystal or resonator frequency — low-

32

—

40

kHz

frequency range

(SCG_SOSCCFG[RANGE]=01)

f_{osc_hi_1}Oscillator crystal or resonator frequency —

medium frequency range

1

—

8

MHz

(SCG_SOSCCFG[RANGE]=10)

Table continues on the next page...

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NXP Semiconductors

Peripheral operating requirements and behaviors

Table 29. Oscillator frequency specifications (continued)

Symbol Description

Min.

Typ.

Max.

Unit

Notes

f_{osc_hi_2}Oscillator crystal or resonator frequency — high

frequency range

8

—

32

MHz

(SCG_SOSCCFG[RANGE]=11)

f_{ec_extal}Input clock frequency (external clock mode)

t_{dc_extal}Input clock duty cycle (external clock mode)

—

40

—

50

48

60

—

MHz

%

1, 2

t_cst

Crystal startup time — 32 kHz low-frequency,

low-power mode (HGO=0)

750

ms

3, 4, 5

Crystal startup time — 32 kHz low-frequency,

high-gain mode (HGO=1)

—

250

0.6

—

ms

Crystal startup time — 8 MHz medium

frequency (SCG_SOSCCFG[RANGE]=11), low-

power mode (HGO=0)

Crystal startup time — 8 MHz medium

frequency (SCG_SOSCCFG[RANGE]=10),

high-gain mode (HGO=1)

—

1

—

ms

1. Other frequency limits may apply when external clock is being used as a reference for the PLL.

2. When transitioning to system PLL mode, restrict the frequency of the input clock so that, when it is divided by

PREDIV, it remains within the limits of the PLL reference input clock frequency.

3. Proper PC board layout procedures must be followed to achieve specifications.

4. Crystal startup time is defined as the time between the oscillator being enabled and the SCG_SOSCCSR[SOSCVLD]

being set.

5. Crystal startup time is dependent on external crystal and/or resonator and loading capacitance as well as series

resistance.

8.4 Memories and memory interfaces

8.4.1 Flash electrical specifications

This section describes the electrical characteristics of the flash memory module.

8.4.1.1 Flash timing specifications — program and erase

The following specifications represent the amount of time the internal charge pumps

are active and do not include command overhead.

Table 30. Flash program/erase timing specifications

Symbol Description

Min.

—

Typ.

7.5

13

Max.

18

Unit

μs

Notes

t_hvpgm4Longword Program high-voltage time

t_hversscrSector Erase high-voltage time

—

1

—

113

ms

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NXP Semiconductors

Peripheral operating requirements and behaviors

Table 30. Flash program/erase timing specifications (continued)

Symbol Description

Min.

—

Typ.

52

Max.

452

Unit

ms

Notes

t_hversblk128kErase Block high-voltage time for 128 KB

1

t_hversall

Erase All high-voltage time

—

104

904

ms

1. Maximum time based on expectations at cycling end-of-life.

8.4.1.2 Flash timing specifications — commands

Table 31. Flash command timing specifications

Symbol Description

Read 1s Block execution time

• 128 KB program flash

Min.

Typ.

Max.

Unit

Notes

1

t_rd1blk128k

—

1.7

ms

t_rd1sec1kRead 1s Section execution time (flash sector)

—

65

60

45

μs

1

t_pgmchk

t_rdrsrc

Program Check execution time

Read Resource execution time

Program Longword execution time

Erase Flash Block execution time

• 128 KB program flash

30

1

t_pgm4

145

—

2

t_ersblk128k

—

88

600

ms

t_ersscr

t_rd1all

Erase Flash Sector execution time

Read 1s All Blocks execution time

Read Once execution time

—

14

—

114

1.8

25

ms

μs

2

1

t_rdonce

—

1

t_pgmonceProgram Once execution time

65

175

—

μs

—

2

t_ersall

Erase All Blocks execution time

1300

30

ms

μs

t_vfykey

Verify Backdoor Access Key execution time

1

1. Assumes 25 MHz flash clock frequency.

2. Maximum times for erase parameters based on expectations at cycling end-of-life.

8.4.1.3 Flash high voltage current behaviors

Table 32. Flash high voltage current behaviors

Symbol

Description

Min.

Typ.

Max.

Unit

I_{DD_PGM}

Average current adder during high voltage

flash programming operation

—

2.5

6.0

mA

I_{DD_ERS}

Average current adder during high voltage

flash erase operation

—

1.5

4.0

mA

60

NXP Semiconductors

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

Peripheral operating requirements and behaviors

8.4.1.4 Reliability specifications

Table 33. Flash reliability specifications

Symbol Description

Min.

5

Typ.¹

Max.

—

Unit

years

cycles

Notes

—

t_nvmretp10kData retention after up to 10 K cycles

t_nvmretp1kData retention after up to 1 K cycles

n_nvmcycpCycling endurance

50

20

100

50 K

—

10 K

—

2

1. Typical data retention values are based on measured response accelerated at high temperature and derated to a

constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in

Engineering Bulletin EB619.

2. Cycling endurance represents number of program/erase cycles at –40 °C ≤ T_j≤ 125 °C.

8.5 Security and integrity modules

There are no specifications necessary for the device's security and integrity modules.

8.6 Analog

8.6.1 ADC electrical specifications

8.6.1.1 16-bit ADC operating conditions

Table 34. 16-bit ADC operating conditions

Symbol Description

V_DDASupply voltage

ΔV_DDASupply voltage

Conditions

Min.

1.71

Typ.¹

Max.

3.6

Unit

V

Notes

Absolute

—

2

Delta to V_DD(V_DD– V_DDA

)

-100

0

+100

mV

V

ΔV_SSA

Ground voltage Delta to V_SS(V_SS– V_SSA

)

-100

0

2

V_ADIN

Input voltage

• 16-bit differential mode

• All other modes

• 16-bit mode

VREFL

—

31/32 ×

VREFH

—

VREFL

—

VREFH

C_ADIN

Input

—

8

4

10

5

pF

—

capacitance

• 8-bit / 10-bit / 12-bit

modes

R_ADIN

R_AS

Input series

resistance

—

2

5

kΩ

—

Analog source

resistance

16-bit modes

3, 4

—

0.5

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Peripheral operating requirements and behaviors

Table 34. 16-bit ADC operating conditions (continued)

Symbol Description

Conditions

• f_ADCK> 8 MHz

Min.

Typ.¹

Max.

Unit

Notes

—

1

kΩ

• f_ADCK= 4–8 MHz

• f_ADCK< 4 MHz

—

2

kΩ

13-bit / 12-bit modes

• f_ADCK> 16 MHz

• f_ADCK> 8 MHz

• f_ADCK= 4–8 MHz

• f_ADCK< 4 MHz

—

0.5

1

kΩ

2

5

11-bit / 10-bit modes

• f_ADCK> 8 MHz

• f_ADCK= 4–8 MHz

• f_ADCK< 4MHz

—

2

5

kΩ

10

9-bit / 8-bit modes

• f_ADCK> 8 MHz

• f_ADCK< 8 MHz

—

5

kΩ

10

f_ADCK

ADC conversion ≤ 13-bit mode

1.0

2.0

—

24.0

12.0

MHz

5

6

clock frequency

16-bit mode

C_rate

ADC conversion ≤ 13-bit modes

rate

No ADC hardware averaging

20.000

37.037

—

1200

ksps

Continuous conversions

enabled, subsequent

conversion time

C_rate

ADC conversion 16-bit mode

6

rate

No ADC hardware averaging

461.467

Continuous conversions

enabled, subsequent

conversion time

1. Typical values assume V_DDA= 3.0 V, Temp = 25 °C, f_ADCK= 1.0 MHz, unless otherwise stated. Typical values are for

reference only, and are not tested in production.

2. DC potential difference.

3. Assumes ADLSMP=0

4. This resistance is external to the MCU. To achieve the best results, the analog source resistance must be kept as low as

possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The R_AS

C_AStime constant should be kept to < 1 ns.

*

5. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.

6. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.

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Peripheral operating requirements and behaviors

SIMPLIFIED

INPUT PIN EQUIVALENT

CIRCUIT

ZADIN

SIMPLIFIED

CHANNEL SELECT

CIRCUIT

Pad

leakage

ZAS

ADC SAR

ENGINE

RAS

RADIN

VADIN

CAS

VAS

RADIN

INPUT PIN

CADIN

Figure 11. ADC input impedance equivalency diagram

8.6.1.2 16-bit ADC electrical characteristics

Table 35. 16-bit ADC characteristics (V_REFH= V_DDA, V_REFL= V_SSA

)

Symbol Description

Conditions¹

Min.

0.215

1.2

Typ.²

Max.

1.7

3.9

6.1

7.3

9.5

Unit

Notes

I_{DDA_ADC}Supply current

—

mA

3

ADC asynchronous

clock source

• ADLPC = 1, ADHSC = 0

• ADLPC = 1, ADHSC = 1

• ADLPC = 0, ADHSC = 0

• ADLPC = 0, ADHSC = 1

2.4

4.0

5.2

6.2

MHz

t_ADACK= 1/

f_ADACK

2.4

f_ADACK

3.0

4.4

Sample Time

See Reference Manual chapter for sample times

TUE

DNL

Total unadjusted

error

• 12-bit modes

• <12-bit modes

—

4

6.8

2.1

LSB⁴

5

1.4

Differential non-

linearity

• 12-bit modes

• <12-bit modes

—

0.7

0.2

–1.1 to

+1.9

–0.3 to

0.5

INL

Integral non-linearity

• 12-bit modes

—

1.0

–2.7 to

+1.9

LSB⁴

5

Table continues on the next page...

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Peripheral operating requirements and behaviors

Table 35. 16-bit ADC characteristics (V_REFH= V_DDA, V_REFL= V_SSA) (continued)

Symbol Description

Conditions¹

Min.

Typ.²

Max.

Unit

Notes

—

0.5

–0.7 to

+0.5

• <12-bit modes

5

E_FS

E_Q

Full-scale error

• 12-bit modes

• <12-bit modes

• 16-bit modes

• ≤13-bit modes

—

–4

–1.4

–1 to 0

—

–5.4

–1.8

—

LSB⁴

V_ADIN= V_DDA

Quantization error

0.5

ENOB Effective number of 16-bit differential mode

6

bits

12.8

11.9

14.5

13.8

—

bits

• Avg = 32

• Avg = 4

16-bit single-ended mode

• Avg = 32

12.2

11.4

13.9

13.1

—

bits

dB

• Avg = 4

Signal-to-noise plus See ENOB

SINAD

6.02 × ENOB + 1.76

distortion

THD

Total harmonic

distortion

16-bit differential mode

• Avg = 32

7

dB

—

-94

-85

—

16-bit single-ended mode

• Avg = 32

—

SFDR Spurious free

dynamic range

16-bit differential mode

• Avg = 32

—

dB

82

78

95

90

16-bit single-ended mode

• Avg = 32

E_IL

Input leakage error

I_In× R_AS

mV

I_In= leakage

current

(refer to the

MCU's

voltage and

current

operating

ratings)

Temp sensor slope Across the full temperature

range of the device

1.55

706

1.62

716

1.69

726

mV/°C

mV

8

V_TEMP25Temp sensor

voltage

25 °C

8

1. All accuracy numbers assume the ADC is calibrated with V_REFH= V_DDA

2. Typical values assume V_DDA= 3.0 V, Temp = 25 °C, f_ADCK= 2.0 MHz unless otherwise stated. Typical values are for

reference only and are not tested in production.

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Peripheral operating requirements and behaviors

3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low

power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with

1 MHz ADC conversion clock speed.

4. 1 LSB = (V_REFH- V_REFL)/2^N

5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)

6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz.

7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.

8. ADC conversion clock < 3 MHz

Typical ADC 16-bit Differential ENOB vs ADC Clock

100Hz, 90% FS Sine Input

15.00

14.70

14.40

14.10

13.80

13.50

13.20

12.90

12.60

Hardware Averaging Disabled

Averaging of 4 samples

12.30

12.00

Averaging of 8 samples

Averaging of 32 samples

1

2

3

4

5

6

7

8

9

10

11

12

ADC Clock Frequency (MHz)

Figure 12. Typical ENOB vs. ADC_CLK for 16-bit differential mode

Typical ADC 16-bit Single-Ended ENOB vs ADC Clock

100Hz, 90% FS Sine Input

14.00

13.75

13.50

13.25

13.00

12.75

12.50

12.25

12.00

11.75

11.50

11.25

Averaging of 4 samples

Averaging of 32 samples

11.00

1

2

3

4

5

6

7

8

9

10

11

12

ADC Clock Frequency (MHz)

Figure 13. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

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Peripheral operating requirements and behaviors

8.6.2 Voltage reference electrical specifications

Table 36. VREF full-range operating requirements

Symbol

Description

Min.

Max.

3.6

Unit

V

Notes

—

V_DDA

Supply voltage for 1.2V output

Supply voltage for 2.1V output

Temperature

2.4

3.6

V

—

T_A

C_L

Operating temperature

range of the device

°C

—

Output load capacitance

100

nF

1, 2

1. C_Lmust be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external

reference.

2. The load capacitance should not exceed +/-25% of the nominal specified C_Lvalue over the operating temperature range

of the device.

Table 37. VREF full-range operating behaviors

Symbol Description

Min.

1.190

2.092

1.188

2.087

—

Typ.

1.195

2.1

Max.

1.2

Unit

V

Notes

V_outVoltage reference output with factory trim at

1

nominal V_DDAand temperature=25°C

2.108

1.202

2.113

—

V

V_out

Voltage reference 1.2 V output— factory trim

Voltage reference 2.1 V output — factory trim

Voltage reference trim step for 1.2 V output

Voltage reference trim step for 2.1 V output

Aging coefficient

1.195

2.1

V

1

V

V_step

0.5

mV

uV/yr

µA

mV

µs

1

—

1.5

—

1

Ac

I_bg

I_lp

—

400

80

—

1

Bandgap only current

—

60

Low-power buffer current

—

180

480

0.2

360

960

—

1

I_hp

High-power buffer current

—

1

ΔV_LOADLoad regulation — current is 1.0 mA

—

1, 2

—

1

T_stup

Buffer startup time

—

100

2

V_vdrift

Voltage drift for 1.2 V output (Vmax -Vmin

across the full voltage range)

—

0.5

mV

Voltage drift for 2.1 V output (Vmax -Vmin

across the full voltage range)

—

0.9

2

3.5

15

26

mV

V_tdrift

Temperature drift for 1.2 V output (Vmax -Vmin

across the full temperature range)

3

Temperature drift for 2.1 V output (Vmax -Vmin

across the full temperature range)

3.5

1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register for V_outselection

of 1.2 V or 2.1 V.

2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load

3. To get best performance of VREF temperature drift, VREF_SC[ICOMPEN] must be set.

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Peripheral operating requirements and behaviors

Table 38. VREF limited-range operating requirements

Symbol

Description

Temperature

Min.

Max.

50

Unit

Notes

T_A

0

°C

—

Table 39. VREF limited-range operating behaviors

Symbol

V_out

Description

Min.

1.173

2.088

Max.

1.225

2.115

Unit

V

Notes

—

Voltage reference output 1.2 V with factory trim

Voltage reference output 2.1 V with factory trim

V_out

V

—

8.6.3 CMP and 6-bit DAC electrical specifications

Table 40. Comparator and 6-bit DAC electrical specifications

Symbol

V_DD

Description

Min.

1.71

—

Typ.

—

Max.

3.6

Unit

V

Supply voltage

I_DDHS

I_DDLS

V_AIN

Supply current, high-speed mode (EN=1, PMODE=1)

Supply current, low-speed mode (EN=1, PMODE=0)

Analog input voltage

—

200

20

μA

V

—

V_SS– 0.3

—

V_DD

20

V_AIO

Analog input offset voltage

Analog comparator hysteresis¹

• CR0[HYSTCTR] = 00

—

mV

V_H

—

5

—

mV

10

20

30

• CR0[HYSTCTR] = 01

• CR0[HYSTCTR] = 10

• CR0[HYSTCTR] = 11

V_CMPOh

V_CMPOl

t_DHS

Output high

V_DD– 0.5

—

50

250

—

7

—

0.5

200

600

40

V

Output low

Propagation delay, high-speed mode (EN=1, PMODE=1)

Propagation delay, low-speed mode (EN=1, PMODE=0)

Analog comparator initialization delay²

6-bit DAC current adder (enabled)

6-bit DAC integral non-linearity

20

ns

t_DLS

80

ns

—

μs

I_DAC6b

INL

—

μA

LSB³

LSB

–0.5

–0.3

—

0.5

0.3

DNL

6-bit DAC differential non-linearity

1. Typical hysteresis is measured with input voltage range limited to 0.6 to V_DD–0.6 V.

2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to

CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and

CMP_MUXCR[MSEL]) and the comparator output settling to a stable level.

3. 1 LSB = V_reference/64

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Peripheral operating requirements and behaviors

0.08

0.07

0.06

0.05

0.04

0.03

HYSTCTR

Setting

00

01

10

11

0.02

0.01

0

0.1

0.4

0.7

1

1.3

1.6

1.9

2.2

2.5

2.8

3.1

Vin level (V)

Figure 14. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)

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Peripheral operating requirements and behaviors

0.18

0.16

0.14

0.12

HYSTCTR

Setting

0.1

00

01

10

11

0.08

0.06

0.04

0.02

0

0.1

0.4

0.7

1

1.3

1.6

1.9

2.2

2.5

2.8

3.1

Vin level (V)

Figure 15. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)

8.6.4 12-bit DAC electrical characteristics

8.6.4.1 12-bit DAC operating requirements

Table 41. 12-bit DAC operating requirements

Symbol

V_DDA

V_DACR

C_L

Desciption

Min.

Max.

3.6

100

1

Unit

V

Notes

Supply voltage

Reference voltage

Output load capacitance

Output load current

1.13

—

V

1

2

pF

mA

I_L

—

1. The DAC reference can be selected to be V_DDAor V_{REF_OUT}

.

2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC.

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Peripheral operating requirements and behaviors

8.6.4.2 12-bit DAC operating behaviors

Table 42. 12-bit DAC operating behaviors

Symbol Description

Min.

Typ.

Max.

Unit

Notes

I_{DDA_DACL}Supply current — low-power mode

—

250

μA

P

I_{DDA_DACH}Supply current — high-speed mode

—

100

15

900

200

30

μA

μs

P

t_DACLPFull-scale settling time (0x080 to 0xF7F) —

low-power mode

1

t_DACHPFull-scale settling time (0x080 to 0xF7F) —

high-power mode

t_CCDACLPCode-to-code settling time (0xBF8 to

0xC08) — low-power mode and high-speed

mode

0.7

1

V_dacoutlDAC output voltage range low — high-

speed mode, no load, DAC set to 0x000

—

100

mV

V_dacouthDAC output voltage range high — high-

speed mode, no load, DAC set to 0xFFF

V_DACR

−100

V_DACR

INL

DNL

Integral non-linearity error — high speed

mode

—

8

1

LSB

2

3

4

Differential non-linearity error — V_DACR> 2

V

Differential non-linearity error — V_DACR

VREF_OUT

=

V_OFFSETOffset error

E_GGain error

PSRR Power supply rejection ratio, V_DDA≥ 2.4 V

—

60

—

0.4

0.1

0.8

0.6

90

%FSR

dB

5

—

T_CO

T_GE

Rop

SR

Temperature coefficient offset voltage

Temperature coefficient gain error

Output resistance (load = 3 kΩ)

Slew rate -80h→ F7Fh→ 80h

3.7

—

μV/C

%FSR/C

Ω

6

0.000421

—

250

V/μs

• High power (SP_HP

)

1.2

1.7

—

• Low power (SP_LP

3dB bandwidth

)

0.05

0.12

BW

kHz

• High power (SP_HP

• Low power (SP_LP

)

550

40

—

)

1. Settling within 1 LSB

2. The INL is measured for 0 + 100 mV to V_DACR−100 mV

3. The DNL is measured for 0 + 100 mV to V_DACR−100 mV

4. The DNL is measured for 0 + 100 mV to V_DACR−100 mV with V_DDA> 2.4 V

5. Calculated by a best fit curve from V_SS+ 100 mV to V_DACR− 100 mV

6. V_DDA= 3.0 V, reference select set for V_DDA(DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set

to 0x800, temperature range is across the full range of the device

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Peripheral operating requirements and behaviors

8

6

4

2

0

-2

-4

-6

-8

0

500

1000

1500

2000

2500

3000

3500

4000

Digital Code

Figure 16. Typical INL error vs. digital code

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

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Peripheral operating requirements and behaviors

1.499

1.4985

1.498

1.4975

1.497

1.4965

1.496

55

85

25

105

125

-40

Temperature °C

Figure 17. Offset at half scale vs. temperature

8.7 Timers

See General switching specifications.

8.8 Communication interfaces

8.8.1 EMV SIM specifications

Each EMV SIM module interface consists of a total of five pins.

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Peripheral operating requirements and behaviors

The interface is designed to be used with synchronous Smart cards, meaning the EMV

SIM module provides the clock used by the Smart card. The clock frequency is

typically 372 times the Tx/Rx data rate.

There is no timing relationship between the clock and the data. The clock that the

EMV SIM module provides to the Smart card is used by the Smart card to recover the

clock from the data in the same manner as standard UART data exchanges. All five

signals of the EMV SIM module are asynchronous with each other.

There are no required timing relationships between signals in normal mode. The smart

card is initiated by the interface device; the Smart card responds with Answer to

Reset. Although the EMV SIM interface has no defined requirements, the ISO/IEC

7816 defines reset and power-down sequences (for detailed information see ISO/IEC

7816).

SI10

EMVSIMn_PD

EMVSIMn_RST

SI7

EMVSIMn_CLK

SI8

EMVSIMn_IO

SI9

EMVSIMn_VCCEN

Figure 18. EMV SIM Clock Timing Diagram

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Peripheral operating requirements and behaviors

The following table defines the general timing requirements for the EMV SIM

interface.

Table 43. Timing Specifications, High Drive Strength

ID

Parameter

Symbol

Min

Max

Unit

MHz

SI EMV SIM clock frequency (EMVSIMn_CLK)¹

1

SI EMV SIM clock rise time (EMVSIMn_CLK)²

2

SI EMV SIM clock fall time (EMVSIMn_CLK)²

3

S_freq

S_rise

S_fall

1

5

—

20

—

0.08 × (1/Sfreq)

ns

μs

0.08 × (1/Sfreq)

SI EMV SIM input transition time (EMVSIMn_IO,

4

Si EMV SIM I/O rise time / fall time (EMVSIMn_IO)³

5

Si EMV SIM RST rise time / fall time (EMVSIMn_RST)⁴

6

S_tran

Tr/Tf

25

EMVSIMn_PD)

0.8

1. 50% duty cycle clock,

2. With C = 50 pF

3. With Cin = 30 pF, Cout = 30 pF,

4. With Cin = 30 pF,

8.8.1.1 EMV SIM Reset Sequences

Smart cards may have internal reset, or active low reset. The following subset describes

the reset sequences in these two cases.

8.8.1.1.1 Smart Cards with Internal Reset

Following figure shows the reset sequence for Smart cards with internal reset. The reset

sequence comprises the following steps:

• After power-up, the clock signal is enabled on EMVSIMn_CLK (time T0)

• After 200 clock cycles, EMVSIMn_IO must be asserted.

• The card must send a response on EMVSIMn_IO acknowledging the reset between

400–40000 clock cycles after T0.

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Peripheral operating requirements and behaviors

EMVSIMn_VCCEN

EMVSIMn_CLK

EMVSIMn_IO

RESPONSE

1

2

T0

Figure 19. Internal Reset Card Reset Sequence

The following table defines the general timing requirements for the SIM interface.

Table 44. Timing Specifications, Internal Reset Card Reset Sequence

Ref

Min

Max

Units

1

—

200

EMVSIMx_CLK

clock cycles

2

400

40,000

EMVSIMx_CLK

clock cycles

8.8.1.1.2 Smart Cards with Active Low Reset

Following figure shows the reset sequence for Smart cards with active low reset. The

reset sequence comprises the following steps::

• After power-up, the clock signal is enabled on EMVSIMn_CLK (time T0)

• After 200 clock cycles, EMVSIMn_IO must be asserted.

• EMVSIMn_RST must remain low for at least 40,000 clock cycles after T0 (no

response is to be received on RX during those 40,000 clock cycles)

• EMVSIMn_RST is asserted (at time T1)

• EMVSIMn_RST must remain asserted for at least 40,000 clock cycles after T1,

and a response must be received on EMVSIMn_IO between 400 and 40,000 clock

cycles after T1.

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Peripheral operating requirements and behaviors

EMVSIMn_VCCEN

EMVSIMn_RST

EMVSIMn_CLK

RESPONSE

EMVSIMn_IO

2

1

3

T0

T1

Figure 20. Active-Low-Reset Smart Card Reset Sequence

The following table defines the general timing requirements for the EMVSIM

interface..

Table 45. Timing Specifications, Internal Reset Card Reset Sequence

Ref No

Min

—

Max

200

Units

1

2

3

EMVSIMx_CLK clock cycles

400

40,000

—

40,000

8.8.1.2 EMVSIM Power-Down Sequence

Following figure shows the EMV SIM interface power-down AC timing diagram.Table

46 table shows the timing requirements for parameters (SI7–SI10) shown in the figure.

The power-down sequence for the EMV SIM interface is as follows:

• EMVSIMn_SIMPD port detects the removal of the Smart Card

• EMVSIMn_RST is negated

• EMVSIMn_CLK is negated

• EMVSIM_IO is negated

• EMVSIMx_VCCENy is negated

Each of the above steps requires one OSC32KCLK period (usually 32 kHz, also known

as rtcclk in below figure). Power-down may be initiated by a Smart card removal

detection; or it may be launched by the processor.

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Peripheral operating requirements and behaviors

SI10

EMVSIMn_PD

EMVSIMn_RST

SI7

EMVSIMn_CLK

EMVSIMn_IO

SI8

SI9

EMVSIMn_VCCEN

Figure 21. Smart Card Interface Power Down AC Timing

Table 46. Timing Requirements for Power-down Sequence

Ref No

Parameter

Symbol

Min

Max

Units

SI7

EMVSIM reset to SIM clock stop S_rst2clk

0.9 × 1/

Frtcclk¹

1.1 × 1/Frtcclk

μs

SI8

SI9

EMVSIM reset to SIM Tx data

low

S_rst2dat

S_rst2ven

S_pd2rst

1.8 × 1/

Frtcclk

2.2 × 1/Frtcclk

3.3 × 1/Frtcclk

1.1 × 1/Frtcclk

μs

EMVSIM reset to SIM voltage

enable low

2.7 × 1/

Frtcclk

SI10

EMVSIM presence detect to

SIM reset low

0.9 × 1/

Frtcclk

1. Frtcclk is OSC32KCLK, and this clock must be enabled during the power down sequence.

NOTE

Same timing is also followed when auto power down is

initiated. See Reference Manual for reference.

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Peripheral operating requirements and behaviors

8.8.2 USB electrical specifications

The USB electricals for the USB On-the-Go module conform to the standards

documented by the Universal Serial Bus Implementers Forum. For the most up-to-date

standards, visit usb.org.

NOTE

The Fast IRC do not meet the USB jitter specifications for

certification for Host mode operation.

8.8.3 USB VREG electrical specifications

Table 47. USB VREG electrical specifications

Symbol Description

Min.

2.7

—

Typ.¹

Max.

5.5

Unit

V

Notes

VREGIN Input supply voltage

—

I_DDon

I_DDstby

I_DDoff

Quiescent current — Run mode, load current

equal zero, input supply (VREGIN) > 3.6 V

125

186

μA

Quiescent current — Standby mode, load

current equal zero

—

1.1

10

μA

Quiescent current — Shutdown mode

—

650

—

4

nA

μA

• VREGIN = 5.0 V and temperature=25 °C

• Across operating voltage and temperature

I_LOADrunMaximum load current — Run mode

I_LOADstbyMaximum load current — Standby mode

—

120

1

mA

V_Reg33outRegulator output voltage — Input supply

(VREGIN) > 3.6 V

• Run mode

3

3.3

2.8

—

3.6

V

• Standby mode

2.1

V_Reg33outRegulator output voltage — Input supply

(VREGIN) < 3.6 V, pass-through mode

2

C_OUT

ESR

External output capacitor

1.76

1

2.2

—

8.16

100

μF

External output capacitor equivalent series

resistance

mΩ

I_LIM

Short circuit current

—

290

—

mA

1. Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated.

2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to I_Load

.

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Peripheral operating requirements and behaviors

8.8.4 LPSPI switching specifications

The Low Power Serial Peripheral Interface (LPSPI) provides a synchronous serial bus

with master and slave operations. Many of the transfer attributes are programmable.

The following tables provide timing characteristics for classic SPI timing modes.

All timing is shown with respect to 20% V_DDand 80% V_DDthresholds, unless noted,

as well as input signal transitions of 3 ns and a 30 pF maximum load on all LPSPI

pins.

NOTE

• Slew rate disabled pads are those pins with

PORTx_PCRn[SRE] bit cleared. Slew rate enabled pads

are those pins with PORTx_PCRn[SRE] bit set.

• To achieve high bit rate, it is recommended to use fast

pins (PTE20, PTE21, PTE22, PTE23, PTD4, PTD5,

PTD6, and PTD7) and/or high drive pins (PTC3, PTC4,

PTD4, PTD5, PTD6, and PTD7).

Table 48. LPSPI master mode timing on slew rate disabled pads

Num.

Symbol Description

Min.

Max.

Unit

Hz

Note

1

2

f_op

Frequency of operation

f_periph/2048

2 x t_periph

f_periph/2

1

2

t_SPSCK

SPSCK period

2048 x

t_periph

ns

3

4

5

t_Lead

t_Lag

Enable lead time

Enable lag time

1/2

—

t_SPSCK

ns

—

t_WSPSCKClock (SPSCK) high or low time

t_periph- 30

1024 x

t_periph

6

7

t_SU

t_HI

Data setup time (inputs)

Data hold time (inputs)

Data valid (after SPSCK edge)

Data hold time (outputs)

Rise time input

18

0

—

ns

—

15

8

t_v

—

0

9

t_HO

t_RI

—

10

—

t_periph- 25

t_FI

Fall time input

11

t_RO

t_FO

Rise time output

—

25

ns

—

Fall time output

1. f_periphis the LPSPI peripheral functional clock.

2. t_periph= 1/f_periph

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Peripheral operating requirements and behaviors

Table 49. LPSPI master mode timing on slew rate enabled pads

Num.

Symbol Description

Min.

Max.

Unit

Hz

Note

1

2

f_op

Frequency of operation

f_periph/2048

2 x t_periph

f_periph/2

1

2

t_SPSCK

SPSCK period

2048 x

t_periph

ns

3

4

5

t_Lead

t_Lag

Enable lead time

Enable lag time

1/2

—

t_SPSCK

ns

—

t_WSPSCKClock (SPSCK) high or low time

t_periph- 30

1024 x

t_periph

6

7

t_SU

t_HI

Data setup time (inputs)

Data hold time (inputs)

Data valid (after SPSCK edge)

Data hold time (outputs)

Rise time input

96

0

—

ns

—

52

8

t_v

—

0

9

t_HO

t_RI

—

10

—

t_periph- 25

t_FI

Fall time input

11

t_RO

t_FO

Rise time output

—

36

ns

—

Fall time output

1. f_periphis the LPSPI peripheral functional clock

2. t_periph= 1/f_periph

1

SS

(OUTPUT)

3

2

10

11

4

SPSCK

(CPOL=0)

(OUTPUT)

5

SPSCK

(CPOL=1)

(OUTPUT)

6

7

MISO

(INPUT)

2

BIT 6 . . . 1

8

MSB IN

LSB IN

9

MOSI

(OUTPUT)

2

BIT 6 . . . 1

MSB OUT

LSB OUT

1. If configured as an output.

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

Figure 22. LPSPI master mode timing (CPHA = 0)

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Peripheral operating requirements and behaviors

1

SS

(OUTPUT)

2

10

11

4

3

SPSCK

(CPOL=0)

(OUTPUT)

5

SPSCK

(CPOL=1)

(OUTPUT)

6

7

MISO

(INPUT)

2

BIT 6 . . . 1

LSB IN

MSB IN

9

8

MOSI

(OUTPUT)

2

PORT DATA

BIT 6 . . . 1

MASTER MSB OUT

PORT DATA

MASTER LSB OUT

1.If configured as output

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

Figure 23. LPSPI master mode timing (CPHA = 1)

Table 50. LPSPI slave mode timing on slew rate disabled pads

Num.

1

Symbol Description

Min.

Max.

f_periph/4

—

Unit

Hz

Note

1

f_op

t_SPSCK

t_Lead

t_Lag

Frequency of operation

0

2

SPSCK period

Enable lead time

Enable lag time

4 x t_periph

ns

2

3

1

—

t_periph

ns

—

3

4

1

—

5

t_WSPSCKClock (SPSCK) high or low time

t_periph- 30

—

6

t_SU

t_HI

t_a

Data setup time (inputs)

Data hold time (inputs)

Slave access time

2.5

3.5

—

0

—

ns

7

—

ns

8

t_periph

31

ns

9

t_dis

t_v

Slave MISO disable time

Data valid (after SPSCK edge)

Data hold time (outputs)

Rise time input

ns

4

10

11

12

ns

—

t_HO

t_RI

t_FI

—

ns

—

t_periph- 25

ns

Fall time input

13

t_RO

t_FO

Rise time output

—

25

ns

—

Fall time output

1. f_periphis the LPSPI peripheral functional clock

2. t_periph= 1/f_periph

3. Time to data active from high-impedance state

4. Hold time to high-impedance state

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Peripheral operating requirements and behaviors

Table 51. LPSPI slave mode timing on slew rate enabled pads

Num.

1

Symbol Description

Min.

Max.

f_periph/4

—

Unit

Hz

Note

1

f_op

t_SPSCK

t_Lead

t_Lag

Frequency of operation

0

2

SPSCK period

Enable lead time

Enable lag time

4 x t_periph

ns

2

3

1

—

t_periph

ns

—

3

4

1

—

5

t_WSPSCKClock (SPSCK) high or low time

t_periph- 30

—

6

t_SU

t_HI

t_a

Data setup time (inputs)

Data hold time (inputs)

Slave access time

2

7

—

ns

7

—

ns

8

—

0

t_periph

122

ns

9

t_dis

t_v

Slave MISO disable time

Data valid (after SPSCK edge)

Data hold time (outputs)

Rise time input

ns

4

10

11

12

ns

—

t_HO

t_RI

t_FI

—

ns

—

t_periph- 25

ns

Fall time input

13

t_RO

t_FO

Rise time output

—

36

ns

—

Fall time output

1. f_periphis the LPSPI peripheral functional clock

2. t_periph= 1/f_periph

3. Time to data active from high-impedance state

4. Hold time to high-impedance state

SS

(INPUT)

2

12

13

4

SPSCK

(CPOL=0)

(INPUT)

5

3

SPSCK

(CPOL=1)

(INPUT)

9

8

10

11

see

note

SEE

NOTE

MISO

(OUTPUT)

BIT 6 . . . 1

SLAVE MSB

7

SLAVE LSB OUT

6

MOSI

(INPUT)

LSB IN

MSB IN

BIT 6 . . . 1

NOTE: Not defined

Figure 24. LPSPI slave mode timing (CPHA = 0)

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Peripheral operating requirements and behaviors

SS

(INPUT)

4

2

12

13

3

SPSCK

(CPOL=0)

(INPUT)

5

13

SPSCK

(CPOL=1)

(INPUT)

11

9

10

SLAVE MSB OUT

see

note

MISO

(OUTPUT)

BIT 6 . . . 1

SLAVE LSB OUT

8

6

7

MOSI

(INPUT)

MSB IN

LSB IN

NOTE: Not defined

Figure 25. LPSPI slave mode timing (CPHA = 1)

8.8.5 LPI²C

Table 52. LPI²C specifications

Symbol Description

Min.

Max.

100

Unit

Notes

1

f_SCL

SCL clock frequency

Standard mode (Sm)

Fast mode (Fm)

0

kHz

400

1, 2

1, 3

1, 4

1, 5

Fast mode Plus (Fm+)

Ultra Fast mode (UFm)

High speed mode (Hs-mode)

1000

5000

3400

1. See General switching specifications, measured at room temperature.

2. Measured with the maximum bus loading of 400pF at 3.3V VDD with pull-up Rp = 580Ω on normal drive pins or 350Ω

on high drive pins, and at 1.8V VDD with Rp = 880Ω. For all other cases, select appropriate Rp per I2C Bus

Specification and the pin drive capability.

3. Fm+ is only supported on high drive pin with high drive enabled. It is measured with the maximum bus loading of

400pF at 3.3V VDD with Rp = 350Ω. For all other cases, select appropriate Rp per I2C Bus Specification and the pin

drive capability.

4. UFm is only supported on high drive pin with high drive enabled and push-pull output only mode. It is measured at

3.3V VDD with the maximum bus loading of 400pF. For 1.8V VDD, the maximum speed is 4Mbps.

5. Hs-mode is only supported in slave mode and on the high drive pins with high drive enabled.

8.8.6 LPUART

See General switching specifications.

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Design considerations

8.9 Human-machine interfaces (HMI)

8.9.1 TSI electrical specifications

Table 53. TSI electrical specifications

Symbol

TSI_RUNF

TSI_RUNV

Description

Min.

—

Typ.

100

—

Max.

—

Unit

µA

Fixed power consumption in run mode

Variable power consumption in run mode

(depends on oscillator's current selection)

1.0

128

µA

TSI_EN

TSI_DIS

Power consumption in enable mode

Power consumption in disable mode

TSI analog enable time

—

100

1.2

66

—

µA

µs

pF

V

TSI_TEN

—

TSI_CREF

TSI_DVOLT

TSI reference capacitor

—

1.0

—

Voltage variation of VP & VM around nominal

values

0.19

1.03

9 Design considerations

9.1 Hardware design considerations

This device contains protective circuitry to guard against damage due to high static

voltage or electric fields. However, take normal precautions to avoid application of any

voltages higher than maximum-rated voltages to this high-impedance circuit.

9.1.1 Printed circuit board recommendations

• Place connectors or cables on one edge of the board and do not place digital circuits

between connectors.

• Drivers and filters for I/O functions must be placed as close to the connectors as

possible. Connect TVS devices at the connector to a good ground. Connect filter

capacitors at the connector to a good ground.

• Physically isolate analog circuits from digital circuits if possible.

• Place input filter capacitors as close to the MCU as possible.

• For best EMC performance, route signals as transmission lines; use a ground plane

directly under LQFP/MAPBGA packages.

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Design considerations

9.1.2 Power delivery system

Consider the following items in the power delivery system:

• Use a plane for ground.

• Use a plane for MCU VDD supply if possible.

• Always route ground first, as a plane or continuous surface, and never as

sequential segments.

• Route power next, as a plane or traces that are parallel to ground traces.

• Place bulk capacitance, 10 μF or more, at the entrance of the power plane.

• Place bypass capacitors for MCU power domain as close as possible to each

VDD/VSS pair, including VDDA/VSSA and VREFH/VREFL.

• The minimum bypass requirement is to place 0.1 μF capacitors positioned as near

as possible to the package supply pins.

• The VREG_IN voltage range is 2.7 V to 5.5 V. Typically, 5.0V is applied here. If

USB module is used, this pin must be powered to make the USB transceiver also

powered. It is recommended to include a filter circuit with one bulk capacitor (no

less than 2.2 μF) and one 0.1 μF capacitor to VREG_IN at this pin to improve

USB performance. Total capacitors on VBUS should be less than 10 μF.

• Take special care to minimize noise levels on the VREFH/VREFL inputs. An

option is to use the internal reference voltage (output 1.2 V or 2.1 V typically) as

the ADC reference.

NOTE

The internal reference voltage output (VREF_OUT) is

bonded to the VREFH pin. When the VREF_OUT output is

used, a 0.1 μF capacitor is required as a filter. Do not

connect any other supply voltage to the pin that has

VREF_OUT activated.

9.1.3 Analog design

Each ADC input must have an RC filter as shown in the following figure. The

maximum value of R must be smaller than RAS max if high resolution is required.

The value of C must be chosen to ensure that the RC time constant is very small

compared to the sample period. See AN4373: Cookbook for SAR ADC

Measurements for how to select proper RC values.

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Design considerations

MCU

1

2

Input signal

ADCx

R

C

Figure 26. RC circuit for ADC input

High voltage measurement circuits require voltage division, current limiting, and

overvoltage protection as shown the following figure. The voltage divider formed by R1

– R4 must yield a voltage less than or equal to VREFH. Typically, VREFH is

connected to VDDA. The current must be limited to less than the negative injection

current limit. Since the ADC pins do not have diodes to VDD, external clamp diodes

must be included to protect against transient over-voltages.

MCU

R1

R2

R3

VDD

1

2

R5

1

2

ADCx

High voltage input

R4

1

2

C

BAT54SW

Figure 27. High voltage measurement with an ADC input

9.1.4 Digital design

Ensure that all I/O pins cannot get pulled above VDD (Max I/O is VDD+0.3V).

CAUTION

Do not provide power to I/O pins prior to VDD, especially the

RESET_b pin.

• High drive pins

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Design considerations

PTB0, PTB1, PTC3, PTC4, PTD4, PTD5, PTD6 and PTD7 I/O have both high

drive and normal drive capability selected by the associated PTx_PCRn[DSE]

control bit. All other GPIOs are normal drive only. When in high drive mode, the

sink/source current for a high drive pin can reach 20 mA. However, the total

current flowing into the MCU VDD must not exceed maximum limit of IDD.

• Fast pins

PTE20, PTE21, PTE22, PTE23, PTD4, PTD5, PTD6, PTD7 can support fast slew

rate of 0.5 ns and are used for high speed communications. It is set/cleared by

PTx_PCRn[SRE].

• Default I/O state

Most of digital pins are disabled (in high impedance state) after power up, so a

pull-up/down is needed to a determined level for some applications. Please refer

to the Signal Multiplexing and Pin Assignments chapter to know the default IO

state for a dedicate pin.

• RESET_b pin

The RESET_b pin is an open-drain I/O pin that has an internal pullup resistor. An

external RC circuit is recommended to filter noise as shown in the following

figure. The resistor value must be in the range of 4.7 kΩ to 10 kΩ; the

recommended capacitance value is 0.1 μF. The RESET_b pin also has a selectable

digital filter to reject spurious noise.

VDD

MCU

10k

RESET_b

0.1uF

Figure 28. Reset circuit

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NXP Semiconductors

Design considerations

When an external supervisor chip is connected to the RESET_b pin, a series

resistor must be used to avoid damaging the supervisor chip or the RESET_b pin,

as shown in the following figure. The series resistor value (RS below) must be in

the range of 100 Ω to 1 kΩ depending on the external reset chip drive strength. The

supervisor chip must have an active high, open-drain output.

VDD

Supervisor Chip

MCU

10k

1

2

OUT

RESET_b

RS

Active high,

open drain

0.1uF

Figure 29. Reset signal connection to external reset chip

• NMI pin

Do not add a pull-down resistor or capacitor on the NMI_b pin, because a low level

on this pin will trigger non-maskable interrupt. When this pin is enabled as the NMI

function, an external pull-up resistor (10 kΩ) as shown in the following figure is

recommended for robustness.

If the NMI_b pin is used as an I/O pin, use the following two ways to disable NMI

function:

a. Define NMI interrupt handler in which NMI pin function is remapped to other

pin mux function

b. Disable NMI function by programming flash configuration byte at 0x40d for

FOPT, change FOPT[NMI_DIS] bit to zero. It will not take effect until next

reset.

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K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

Design considerations

VDD

MCU

10k

NMI_b

Figure 30. NMI pin biasing

• Debug interface

This MCU uses the standard Arm SWD interface protocol as shown in the

following figure. While pull-up or pull-down resistors are not required

(SWD_DIO has an internal pull-up and SWD_CLK has an internal pull-down),

external 10 kΩ pull resistors are recommended for system robustness. The

RESET_b pin recommendations mentioned above must also be considered.

VDD

10k

VDD

J1

SWD_DIO

SWD_CLK

1

3

5

7

9

2

4

6

8

RESET_b

10k

10

0.1uF

HDR_5X2

Figure 31. SWD debug interface

• Low leakage stop mode wakeup

Select low leakage wakeup pins (LLWU_Px) to wake the MCU from one of the

low leakage stop modes (LLS/VLLSx). See K32 L2A Signal Multiplexing and

Pin Assignments chapter for pin selection.

• Unused pin

Unused GPIO pins must be left floating (no electrical connections) with the MUX

field of the pin’s PORTx_PCRn register equal to 000. This disables the digital

input path to the MCU.

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NXP Semiconductors

Design considerations

If the USB module is not used, leave the USB data pins (USB0_DP, USB0_DM)

floating.

• EMVSIM

When using EMVSIM, a typical 4.7 KΩ pull up resistor should be added on the

EMVSIM_IO pin.

P3V3

R103

4.7K

EMVSIM HEADER

JP1

1

2

3

EMVSIM_CLK

PTC14

EMVSIM_RST

EMVSIM_VCCEN

EMVSIM_IO

4

5

6

7

PTC15

PTC16

PTC17

PTC18

EMVSIM_PD

HDR TH 1X7

GND

Figure 32. EMVSIM interface

• Pull up resistor for getting correct power consumption result

Connect the pull up resistor to VDD_MCU for the pins like RESET and NMI. For

other pull up resistor, do not use VDD_MCU.

9.1.5 Crystal oscillator

When using an external crystal or ceramic resonator as the frequency reference for the

MCU clock system, refer to the following table and diagrams.

The feedback resistor, RF, is incorporated internally with the low power oscillators. An

external feedback is required when using high gain (HGO=1) mode. In harsh EMC

environment, it is recommended to use high gain mode. For low frequency (32 to 40

kHz), switching between high gain and low power is not supported.

The series resistor, RS, is used to limit current to external crystal or resonator to avoid

overdrive, and is required in high gain (HGO=1) mode when the crystal or resonator

frequency is below 2 MHz. The low power oscillator (HGO=0) must not have any

series resistor RS.

Internal load capacitors (Cx, Cy) are provided in the low frequency (32.786kHz) mode.

Use the SCxP bits in the SCG_SOSCCFG register to adjust the load capacitance for the

crystal. Typically, values of 10 pf to 16 pF are sufficient for 32.768 kHz crystals that

have a 12.5 pF CL specification. The internal load capacitor selection must not be used

for high frequency crystals and resonators. See crystal or resonator manufacturer's

recommendation for parameters about load capacitance and RF.

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Design considerations

Table 54. External crystal/resonator connections

Oscillator mode

Diagram

Low frequency (32 kHz-40 kHz), low power

Low frequency (32 kHz-40 kHz), high gain

High/Medium frequency (1-32 MHz), low power

High/Medium frequency (1-32MHz), high gain

Diagram 1

Diagram 2, Diagram 4

Diagram 3

Diagram 4

OSCILLATOR

EXTAL

XTAL

1

2

CRYSTAL

Figure 33. Crystal connection – Diagram 1

OSCILLATOR

EXTAL

XTAL

1

2

RF

RS

1

2

CRYSTAL

Figure 34. Crystal connection – Diagram 2

OSCILLATOR

EXTAL

OSCILLATOR

EXTAL

XTAL

1

2

1

3

CRYSTAL

Cx

Cy

RESONATOR

Figure 35. Crystal connection – Diagram 3

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NXP Semiconductors

Part identification

OSCILLATOR

EXTAL

OSCILLATOR

EXTAL

XTAL

1

2

1

2

RF

RS

1

2

1

3

CRYSTAL

Cx

Cy

RESONATOR

Figure 36. Crystal connection – Diagram 4

9.2 Software considerations

All K32L2A MCUs are supported by comprehensive NXP and third-party hardware and

software enablement solutions, which can reduce development costs and time to market.

Featured software and tools are listed below.

Evaluation and Prototyping Hardware

• NXP Freedom Development Platform: http://www.nxp.com/freedom

• Tower System Development Platform: http://www.nxp.com/tower

IDEs for Kinetis MCUs

• MCUXpresso Integrated Development Environment (IDE)：https://www.nxp.com/

design/software/development-software/mcuxpresso-software-and-tools-/

mcuxpresso-integrated-development-environment-ide:MCUXpresso-IDE

Run-time Software

• K32 L2A SDK: http://mcuxpresso.nxp.com

• MQX RTOS: http://www.nxp.com/mqx

For all other partner-developed software and tools, visit http://www.nxp.com/partners.

10 Part identification

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Part identification

10.1 Description

Part numbers for the chip have fields that identify the specific part. You can use the

values of these fields to determine the specific part you have received.

10.2 Format

Part numbers for this device have the following format:

B PS C FS SPF T PG FR S PT

10.3 Fields

This table lists the possible values for each field in the part number (not all

combinations are valid):

Table 55. Part number fields descriptions

Field

Description

Values

B

Brand

• K32

• L2

PS

C

Product Series

Core

• A= Sub-family A

• B= Sub-family B

FS

Flash size

• 1 = 64 KB

• 2 = 128 KB

• 3 = 256 KB

• 4 = 512 KB

SPF

Special Feature

• 0 = Dual core

• 1 = Single core

T

Temperature range (°C)

Package

• V = –40 to 105

PG

• LH = 64 LQFP

• LL = 100 LQFP

FR

S

Fequency (MHz)

Silicon revision

• 1 = 0 - 72 MHz

• A = Initial Mask Set

• B = 1st Major Spin

PT

Packaging Type

• R = Std Reel

10.4 Example

This is an example part number:

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Revision History

K32L2A41VLL1A

11 Revision History

The following table provides a revision history for this document.

Table 56. Revision History

Rev. No.

Date

Substantial Changes

Initial release

0

1

08/2019

12/2019

• In the features section:

• Under clocks, updated SIRC to "2/8 MHz slow internal reference clock (SIRC)".

• Removed "Bluetooth, Wi-Fi connectivity".

• Added a new bullet stating "USB FS OTG controller, capable of USB host or

device operation".

• In the Fields section:

• Updated Special Feature values.

• Removed "T=Tray" from packaging type.

2

3

01/2020

02/2021

• Added section Dimensions.

• In section Pinouts and Packaging, the default values of PTA1, PTA2, and PTA4/

LLWU_P3 updated to TSI0_CH2, TSI0_CH3, and NMI0_b respectively.

• In section Fast IRC (FIRC) specifications :

• In the Open loop total deviation of FIRC frequency at low voltage

(VDD=1.71V-1.89V) over full temperature specification, maximum regulator

disable value updated to 1.5.

• In the Open loop total deviation of FIRC frequency at high voltage

(VDD=1.89V-3.6V) over full temperature specification, maximum value updated

to 1.5.

• Added footnote stating "For temperatures -40 to 85 °C, the maximum value is

1%, characterized on a few samples of different slots. This value is not

guaranteed by production.".

• Updated "Freescale" to "NXP" throughout the document.

• In section 16-bit ADC operating conditions, updated the link of the ADC calculator tool

in the table footnotes.

• In section Software considerations, updated "Kinetis Design Studio IDE" to

"MCUXpresso Integrated Development Environment (IDE)". The associated link is

also updated.

94

NXP Semiconductors

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

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Date of release: 02/2021

Document identifier: K32L2Ax


型号：	K32L2A31VLH1A
厂家：	NXP
描述：	K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM 微控制器静态存储器
文件：	总96页 (文件大小：1141K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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