KMC11FC0CPU4 [NXP]
8-BIT, 4MHz, MICROCONTROLLER;
| 型号： | KMC11FC0CPU4 |
| 厂家： | 
NXP |
| 描述： | 8-BIT, 4MHz, MICROCONTROLLER 时钟 外围集成电路 |
| 文件： | 总74页 (文件大小：513K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Order this document
by MC68HC11FTS/D
MOTOROLA
SEMICONDUCTOR
TECHNICAL DATA
MC68HC11F1
MC68HC11FC0
Technical Summary
8-Bit Microcontroller
1 Introduction
The MC68HC11F1 is a high-performance member of the M68HC11 family of microcontroller units
(MCUs). High-speed expanded systems required the development of this chip with its extra input/output
(I/O) ports, an increase in static RAM (one Kbyte), internal chip-select functions, and a non-multiplexed
bus which reduces the need for external interface logic. The timer, serial I/O, and analog-to-digital (A/
D) converter enable functions similar to those found in the MC68HC11E9.
The MC68HC11FC0 is a low cost, high-speed derivative of the MC68HC11F1. It does not have
EEPROM or an analog-to-digital converter. The MC68HC11FC0 can operate at bus speeds as high as
six MHz.
This document provides a brief overview of the structure, features, control registers, packaging infor-
mation and availability of the MC68HC11F1 and MC68HC11FC0. For detailed information on
M68HC11 subsystems, programming and the instruction set, refer to the M68HC11 Reference Manual
(M68HC11RM/AD).
1.1 Features
• MC68HC11 CPU
• 512 Bytes of On-Chip Electrically Erasable Programmable ROM (EEPROM) with Block Protect
(MC68HC11F1 only)
• 1024 Bytes of On-Chip RAM (All Saved During Standby)
• Enhanced 16-Bit Timer System
— 3 Input Capture (IC) Functions
— 4 Output Compare (OC) Functions
— 4th IC or 5th OC (Software Selectable)
• On-Board Chip-Selects with Clock Stretching
• Real-Time Interrupt Circuit
• 8-Bit Pulse Accumulator
• Synchronous Serial Peripheral Interface (SPI)
• Asynchronous Nonreturn to Zero (NRZ) Serial Communication Interface (SCI)
• Power saving STOP and WAIT Modes
• Eight-Channel 8-Bit A/D Converter (MC68HC11F1 only)
• Computer Operating Properly (COP) Watchdog System and Clock Monitor
• Bus Speeds of up to 6 MHz for the MC68HC11FC0 and up to 5 MHz for the MC68HC11F1
• 68-Pin PLCC (MC68HC11F1 only), 64-Pin QFP (MC68HC11FC0 only), and 80-pin TQFP pack-
age options
This document contains information on a new product. Specifications and information herein are subject to change without notice.
M
© MOTOROLA INC., 1997
1.2 Ordering Information
The following devices all have 1024 bytes of RAM. In addition, the MC68HC11F1 devices have 512
bytes of EEPROM. None of the devices contain on-chip ROM.
Table 1 MC68HC11F1 Standard Device Ordering Information
Package
Temperature
Frequency
5 MHz
2 MHz
3 MHz
4 MHz
5 MHz
2 MHz
3 MHz
4 MHz
2 MHz
3 MHz
4 MHz
5 MHz
2 MHz
3 MHz
4 MHz
5 MHz
2 MHz
3 MHz
4 MHz
2 MHz
3 MHz
4 MHz
MC Order Number
MC68HC11F1PU5
MC68HC11F1CPU2
MC68HC11F1CPU3
MC68HC11F1CPU4
MC68HC11F1CPU5
MC68HC11F1VPU2
MC68HC11F1VPU3
MC68HC11F1VPU4
MC68HC11F1MPU2
MC68HC11F1MPU3
MC68HC11F1MPU4
MC68HC11F1FN5
MC68HC11F1CFN2
MC68HC11F1CFN3
MC68HC11F1CFN4
MC68HC11F1CFN5
MC68HC11F1VFN2
MC68HC11F1VFN3
MC68HC11F1VFN4
MC68HC11F1MFN2
MC68HC11F1MFN3
MC68HC11F1MFN4
0° to +70°
-40° to +85°C
80-Pin Thin Quad Flat Pack
(TQFP)
(14 mm X 14 mm,
1.4 mm thick)
– 40° to + 105° C
– 40° to + 125° C
0° to +70°
– 40° to + 85° C
68-Pin PLCC
– 40° to + 105° C
– 40° to + 125° C
Table 2 MC68HC11F1 Extended Voltage (3.0 to 5.5 V) Device Ordering Information
Package
Temperature
0° to +70°C
Frequency
3 MHz
MC Order Number
MC68L11F1FN3
68-Pin Plastic Leaded Chip
Carrier (PLCC)
–40° to +85°C
0° to +70°C
3 MHz
MC68L11F1CFN3
MC68L11F1PU3
MC68L11F1CPU3
3 MHz
80-Pin Thin Quad Flat Pack
(TQFP)
–40° to +85°C
3 MHz
MOTOROLA
2
MC68HC11F1/FC0
MC68HC11FTS/D
Table 3 MC68HC11FC0 Standard Device Ordering Information
Package
Temperature
–40° to +85°C
0° to 70° C
Frequency
4 MHz
MC Order Number
MC68HC11FC0CFU4
MC68HC11FC0CFU5
MC68HC11FC0FU6
MC68HC11FC0CPU4
MC68HC11FC0CPU5
MC68HC11FC0PU6
64-Pin Quad Flat Pack
(QFP)
5 MHz
6 MHz
4 MHz
–40° to +85°C
0° to 70° C
80-Pin Thin Quad Flat Pack
(TQFP)
5 MHz
6 MHz
Table 4 MC68HC11FC0 Extended Voltage (3.0 to 5.5 V) Device Ordering Information
Package
Temperature
Frequency
3 MHz
MC Order Number
MC68L11FC0FU3
MC68L11FC0FU4
MC68L11FC0PU3
MC68L11FC0PU4
64-Pin Quad Flat Pack
(QFP)
4 MHz
–0° to +70°C
3 MHz
80-Pin Thin Quad Flat Pack
(TQFP)
4 MHz
MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
3
TABLE OF CONTENTS
Section
Page
1
Introduction
1
1.1
1.2
1.3
Features ......................................................................................................................................1
Ordering Information ...................................................................................................................2
Block Diagrams ..........................................................................................................................6
2
Pin Assignments and Signal Descriptions
MC68HC11F1 Pin Assignments ..................................................................................................8
MC68HC11FC0 Pin Assignments .............................................................................................10
Pin Descriptions ........................................................................................................................12
8
2.1
2.2
2.3
3
Control Registers
14
3.1
3.2
MC68HC11F1 Control Registers ...............................................................................................14
MC68HC11FC0 Control Registers ............................................................................................16
4
Operating Modes and System Initialization
Operating Modes .......................................................................................................................18
Memory Maps ............................................................................................................................19
System Initialization Registers ..................................................................................................20
18
4.1
4.2
4.3
5
Resets and Interrupts
25
5.1
5.2
Interrupt Sources .......................................................................................................................25
Reset and Interrupt Registers ...................................................................................................26
6
Electrically Erasable Programmable ROM
29
6.1
6.2
6.3
6.4
EEPROM Operation ..................................................................................................................29
EEPROM Registers ...................................................................................................................29
EEPROM Programming and Erasure ........................................................................................31
CONFIG Register Programming ...............................................................................................32
7
Parallel Input/Output
33
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
Port A ........................................................................................................................................33
Port B ........................................................................................................................................33
Port C ........................................................................................................................................33
Port D ........................................................................................................................................33
Port E ........................................................................................................................................33
Port F .........................................................................................................................................33
Port G ........................................................................................................................................34
Parallel I/O Registers ................................................................................................................34
8
Chip-Selects
38
8.1
8.2
Chip-Select Operation ...............................................................................................................38
Chip-Select Registers ................................................................................................................38
9
Serial Communications Interface (SCI)
42
9.1
9.2
SCI Block Diagrams ..................................................................................................................42
SCI Registers ............................................................................................................................44
10
Serial Peripheral Interface
49
10.1 SPI Block Diagram ....................................................................................................................49
10.2 SPI Registers ............................................................................................................................50
11
Analog-to-Digital Converter
11.1 Input Pins ..................................................................................................................................54
11.2 Conversion Sequence ...............................................................................................................54
11.3 A/D Registers ............................................................................................................................55
53
12
13
Main Timer
57
12.1 Timer Operation ........................................................................................................................57
12.2 Timer Registers .........................................................................................................................59
Pulse Accumulator
64
13.1 Pulse Accumulator Block Diagram ............................................................................................64
13.2 Pulse Accumulator Registers ....................................................................................................64
MOTOROLA
4
MC68HC11F1/FC0
MC68HC11FTS/D
REGISTER INDEX
Register
Address
Page
ADCTL ................ A/D Control/Status.........................................................$1030 ..........................55
BAUD .................. Baud Rate......................................................................$102B ..........................44
BPROT................ Block Protect..................................................................$1035 ..........................29
CFORC ............... Timer Force Compare....................................................$100B ..........................59
CONFIG .............. EEPROM Mapping, COP, EEPROM Enables...............$103F ............. 24, 28, 30
COPRST ............. Arm/Reset COP Timer Circuitry.....................................$103A ..........................27
CSCTL ................ Chip-Select Control........................................................$105D ..........................39
CSGADR............. General-Purpose Chip-Select Address Register ........... $105E .........................40
CSGSIZ............... General-Purpose Chip-Select Size Register ................$105F ..........................40
CSSTRH ............. Clock Stretching.............................................................$105C ..........................38
DDRA.................. Port A Data Register......................................................$1001 ..........................34
DDRC.................. Data Direction Register for Port C .................................$1007 ..........................35
DDRD.................. Data Direction Register for Port D .................................$1009 ..........................36
DDRG.................. Data Direction Register for Port G.................................$1003 ..........................35
HPRIO................. Highest Priority Interrupt and Miscellaneous ................$103C ................... 20, 27
INIT ..................... RAM and I/O Mapping ...................................................$103D ................... 21, 22
OC1D .................. Output Compare 1 Data ................................................$100D ..........................59
OC1M.................. Output Compare 1 Mask ...............................................$100C ..........................59
OPT2................... System Configuration Option Register 2 .......................$1038 ............. 22, 36, 52
OPTION .............. System Configuration Options.......................................$1039 ............. 23, 26, 56
PACNT................ Pulse Accumulator Count ..............................................$1027 ..........................66
PACTL................. Pulse Accumulator Control ...........................................$1026 ................... 63, 65
PORTA................ Port A Data ....................................................................$1000 ..........................34
PORTB................ Port B Data ....................................................................$1004 ..........................35
PORTC................ Port C Data....................................................................$1006 ..........................35
PORTD................ Port D Data....................................................................$1008 ..........................36
PORTE................ Port E Data ....................................................................$100A ..........................36
PORTF................ Port F Data ....................................................................$1005 ..........................35
PORTG ............... Port G Data....................................................................$1002 ..........................34
PPROG ............... EEPROM Programming Control....................................$103B ..........................30
SCCR1................ SCI Control 1 ................................................................$102C ..........................46
SCCR2................ SCI Control 2 ................................................................$102D ..........................46
SCDR.................. Serial Communications Data Register...........................$102F ..........................48
SCSR .................. SCI Status......................................................................$102E ..........................47
SPCR .................. Serial Peripheral Control ...............................................$1028 ..........................50
SPDR .................. SPI Data .......................................................................$102A ..........................51
SPSR .................. Serial Peripheral Status.................................................$1029 ..........................51
TCNT................... Timer Count ..................................................................$100E, $100F ..............59
TCTL1 ................. Timer Control 1..............................................................$1020 ..........................60
TCTL2 ................. Timer Control 2..............................................................$1021 ..........................61
TEST1................. Factory Test ..................................................................$103E ..........................24
TFLG1................. Timer Interrupt Flag 1 ...................................................$1023 ..........................61
TFLG2................. Timer Interrupt Flag 2 ...................................................$1025 ................... 62, 65
TI4O5 .................. Timer Input Capture 4/Output Compare 5 ....................$101E, $101F ..............60
TIC1–TIC3........... Timer Input Capture ......................................................$1010–$1015 ..............60
TMSK1 ................ Timer Interrupt Mask 1 ..................................................$1022 ..........................61
TMSK2 ................ Timer Interrupt Mask 2 ..................................................$1024 ................... 62, 64
TOC1–TOC4....... Timer Output Compare .................................................$1016–$101D ..............60
MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
5
1.3 Block Diagrams
MODB/
VSTBY
MODA/
LIR
E
VDD VSS
XTAL
EXTAL IRQ XIRQ RESET
4XOUT
OSCILLATOR
MODE
CONTROL
CLOCK
LOGIC
INTERRUPT
LOGIC
POWER
VRH
VRL
PULSE
ACCUMULATOR
A/D
CONVERTER
COP
PAI/0C1
PA7
AN7
PE7
OC2/OC1
OC3/OC1
OC4/OC1
IC4/OC5/OC1
IC3
PA6
PA5
PA4
PA3
PA2
PA1
PA0
AN6
AN5
AN4
AN3
AN2
AN1
AN0
PE6
PE5
PE4
PE3
PE2
PE1
PE0
TIMER
SYSTEM
IC2
IC1
PERIODIC INTERRUPT
512 BYTES EEPROM
PG7
PG6
PG5
PG4
PG3
PG2
PG1
PG0
CSPROG
CSGEN
CSIO1
CSIO2
1024 BYTES STATIC RAM
CHIP
SELECTS
CPU
CORE
RxD
TxD
PD0
PD1
SCI
ADDRESS BUS
DATA BUS
MISO
MOSI
SCK
SS
PD2
PD3
PD4
PD5
SPI
PORT C
DDRC
PORT B
PORT F
Figure 1 MC68HC11F1 Block Diagram
MOTOROLA
6
MC68HC11F1/FC0
MC68HC11FTS/D
MODB /
VSTBY
MODA /
LIR
VDD VSS
DS
E
4XOUT XTAL
EXTAL IRQ XIRQ RESET
OSCILLATOR
MODE
CONTROL
CLOCK
LOGIC
INTERRUPT
LOGIC
POWER
PULSE
ACCUMULATOR
COP
PAI/0C1
PA7
PG7
PG6
PG5
PG4
PG3
PG2
PG1
PG0
CSPROG
CSGEN
CSIO1
CSIO2
OC2/OC1
OC3/OC1
OC4/OC1
IC4/OC5/OC1
IC3
PA6
PA5
PA4
PA3
PA2
PA1
PA0
TIMER
SYSTEM
IC2
IC1
CHIP
SELECTS
PERIODIC INTERRUPT
WAIT
RxD
TxD
PD0
PD1
1024 BYTES STATIC RAM
SCI
PE6
PE5
PE4
PE3
PE2
PE1
MISO
MOSI
SCK
SS
PD2
PD3
PD4
PD5
CPU
CORE
SPI
ADDRESS BUS
DATA BUS
PORT C
DDRC
PORT B
PORT F
Figure 2 MC68HC11FC0 Block Diagram
MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
7
2 Pin Assignments and Signal Descriptions
2.1 MC68HC11F1 Pin Assignments
10
11
12
13
14
15
PC1/DATA1
PC2/DATA2
PC3/DATA3
PC4/DATA4
PC5/DATA5
PC6/DATA6
PC7/DATA7
RESET
60
59
58
57
56
55
PE4/AN4
PE0/AN0
PF0/ADDR0
PF1/ADDR1
PF2/ADDR2
PF3/ADDR3
PF4/ADDR4
16
17
18
19
20
21
22
23
24
25
26
54
53
52
51
50
49
48
47
46
45
44
PF5/ADDR5
PF6/ADDR6
PF7/ADDR7
PB0/ADDR8
PB1/ADDR9
PB2/ADDR10
PB3/ADDR11
PB4/ADDR12
PB5/ADDR13
PB6/ADDR14
MC68HC11F1
XIRQ
IRQ
PG7/CSPROG
PG6/CSGEN
PG5/CSIO1
PG4/CSIO2
PG3
PG2
PG1
Figure 3 MC68HC11F1 68-Pin PLCC Pin Assignments
MOTOROLA
8
MC68HC11F1/FC0
MC68HC11FTS/D
1
2
3
4
5
6
7
8
9
60
59
58
57
56
55
54
53
NC
NC
NC
PG1
PB6/ADDR14
PB5/ADDR13
PB4/ADDR12
PB3/ADDR11
PB2/ADDR10
PB1/ADDR9
PB0/ADDR8
PG2
PG3
PG4/CSIO2
PG5/CSIO1
PG6/CSGEN
PG7/CSPROG
IRQ
52
51
50
49
48
47
46
45
44
43
42
41
PF7/ADDR7 10
PF6/ADDR6 11
PF5/ADDR5 12
PF4/ADDR4 13
PF3/ADDR3 14
PF2/ADDR2 15
PF1/ADDR1 16
PF0/ADDR0 17
PE0/AN0 18
XIRQ
MC68HC11F1
RESET
PC7/DATA7
PC6/DATA6
PC5/DATA5
PC4/DATA4
PC3/DATA3
PC2/DATA2
PC1/DATA1
NC
PE4/AN4 19
NC 20
NC
Figure 4 Pin Assignments for the MC68HC11F1 80-Pin QFP
MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
9
2.2 MC68HC11FC0 Pin Assignments
PB6/ADDR14
PB5/ADDR13
PB4/ADDR12
PB3/ADDR11
PB2/ADDR10
PB1/ADDR9
PB0/ADDR8
PF7/ADDR7
PF6/ADDR6
PF5/ADDR5
PF4/ADDR4
PF3/ADDR3
PF2/ADDR2
PF1/ADDR1
PF0/ADDR0
1
2
48 PG2
47 PG3
3
PG4/CSIO2
46
45
44
43
42
41
40
39
38
37
36
35
34
33
4
PG5/CSIO1
PG6/CSGEN
PG7/CSPROG
IRQ
5
6
7
XIRQ
8
MC68HC11FC0
9
RESET
10
11
12
13
14
15
16
PC7/DATA7
PC6/DATA6
PC5/DATA5
PC4/DATA4
PC3/DATA3
PC2/DATA2
PC1/DATA1
V
SS
Figure 5 MC68HC11FC0 64-Pin QFP Pin Assignments
MOTOROLA
10
MC68HC11F1/FC0
MC68HC11FTS/D
NC
NC
1
2
60 NC
59
PG1
PB6/ADDR14
PB5/ADDR13
PB4/ADDR12
PB3/ADDR11
PB2/ADDR10
PB1/ADDR9
PB0/ADDR8
PF7/ADDR7
PF6/ADDR6
PF5/ADDR5
PF4/ADDR4
PF3/ADDR3
PF2/ADDR2
PF1/ADDR1
PF0/ADDR0
3
58 PG2
4
57 PG3
5
56 PG4/CSIO0
55 PG5/CSIO1
54 PG6/CSGEN
53 PG7/CSPROG
52 IRQ
6
7
8
9
XIRQ
10
11
12
13
14
15
16
17
18
51
MC68HC11FC0
50 RESET
49 PC7/DATA7
48 PC6/DATA6
47 PC5/DATA5
46 PC4/DATA4
45 PC3/DATA3
44 PC2/DATA2
43 PC1/DATA1
42 NC
V
SS
PE4 19
NC 20
41
NC
Figure 6 MC68HC11FC0 80-Pin TQFP Pin Assignments
MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
11
2.3 Pin Descriptions
and V
V
DD
SS
V
is the positive power input to the MCU, and V is ground.
SS
DD
RESET
This active-low input initializes the MCU to a known startup state. It also acts as an open-drain
output to indicate that an internal failure has been detected in either the clock monitor or the COP
watchdog circuits.
XTAL and EXTAL
These two pins provide the interface for either a crystal or a CMOS-compatible clock to drive the
internal clock circuitry. The frequency applied to these pins is four times the desired bus
frequency (E clock).
E
This pin provides an output for the E clock, the basic timing reference signal for the bus circuitry.
The address bus is active when E is low, and the data bus is active when E is high.
DS
The data strobe output is the inverted E clock. DS is present on the MC68HC11FC0 only.
WAIT
This input is used to stretch the bus cycle to accomodate slower devices. The MCU samples the
logic level at this pin on the rising edge of E clock. If it is high, the MCU holds the E clock high for
the next four EXTAL clock cycles. If it is low, the E clock responds normally, going low two
EXTAL cycles later. The WAIT pin is present on the MC68HC11FC0 only.
4XOUT
This pin provides a buffered oscillator signal to drive another M68HC11 MCU. The 4XOUT pin is
not present on the 64-pin QFP MC68HC11FC0 package.
IRQ
This active-low input provides a means of generating asynchronous, maskable interrupt requests
for the CPU.
XIRQ
This interrupt request input can be made non-maskable by clearing the X bit in the MCU’s
condition code register.
MODA/LIR and MODB/VSTBY
The logic level applied to the MODA and MODB pins at reset determines the MCU’s opreating
mode (see Table 7 in 4 Operating Modes and System Initialization). After reset, MODA
functions as LIR, an open-drain output that indicates the start of an instruction cycle. MODB
functions as V
, providing a backup battery to maintain the contents of RAM when V falls.
STBY
DD
R/W
In expanded and test modes, R/W indicates the direction of transfers on the external data bus.
V
and V
RL
RH
These pins provide the reference voltage for the analog-to-digital converter. Use bypass
capacitors to minimize noise on these signals. Any noise on V and V will directly affect A/D
RH
RL
accuracy. These pins are not present on the MC68HC11FC0.
MOTOROLA
12
MC68HC11F1/FC0
MC68HC11FTS/D
Port Signals
On the MC68HC11F1, 54 pins are arranged into six 8-bit ports (ports A, B, C, E, F, and G) and
one 6-bit port (port D). On the MC68HC11FC0, either 52 or 49 pins are available, depending on
the package. General-purpose I/O port signals are discussed briefly in the following pragraphs.
For additional information, refer to 7 Parallel Input/Output.
Port A Pins
Port A is an 8-bit general-purpose I/O port (PA[7:0]) with a data register (PORTA) and a data
direction register (DDRA). Port A pins share functions with the 16-bit timer system. Out of reset,
PA[7:0] are general-purpose high-impedance inputs.
Port B Pins
Port B is an 8-bit output-only port. In single-chip modes, port B pins are general-purpose output
pins (PB[7:0]). In expanded modes, port B pins act as the high-order address lines ADDR[15:8].
Port C Pins
Port C is an 8-bit general-purpose I/O port with a data register (PORTC) and a data direction
register (DDRC). In single-chip modes, port C pins are general-purpose I/O pins PC[7:0]. In
expanded modes, port C pins are configured as data bus pins DATA[7:0].
Port D Pins
Port D is a 6-bit general-purpose I/O port with a data register (PORTD) and a data direction
register (DDRD). The six port D lines PD[5:0] can be used for general-purpose I/O or for the serial
communications interface (SCI) or serial peripheral interface (SPI) subsystems.
Port E Pins
Port E is an 8-bit input-only port that is also used as the analog input port for the analog-to-digital
converter. Port E pins that are not used for the A/D system can be used as general-purpose
inputs. However, PORTE should not be read during the sample portion of an A/D conversion
sequence.
NOTE
The A/D system is not available on the MC68HC11FC0. PE7 and PE0 are not
available on the 80-pin MC68HC11FC0. PE7, PE4, and PE0 are not available on
the 64-pin MC68HC11FC0.
Port F Pins
Port F is an 8-bit output-only port. In single-chip mode, port F pins are general-purpose output
pins PF[7:0]. In expanded mode, port F pins act as the low-order address outputs ADDR[7:0].
Port G Pins
Port G is an 8-bit general-purpose I/O port. When enabled, four chip select signals are alternate
functions of PG[7:4].
NOTE
PG[1:0] are not available on the 64-pin MC68HC11FC0.
MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
13
3 Control Registers
The MC68HC11F1 and MC68HC11FC0 control registers determine most of the system’s operating
characteristics. They occupy a 96-byte relocatable memory block. Their names and bit mnemonics are
summarized in the following table. Addresses shown are the default locations out of reset.
3.1 MC68HC11F1 Control Registers
Table 5 MC68HC11F1 Register and Control Bit Assignments
Bit 7
PA7
6
PA6
5
PA5
4
PA4
3
PA3
2
PA2
1
PA1
Bit 0
PA0
$1000
$1001
$1002
$1003
$1004
$1005
$1006
$1007
$1008
$1009
$100A
$100B
$100C
$100D
PORTA
DDA7
PG7
DDA6
PG6
DDA5
PG5
DDA4
PG4
DDA3
PG3
DDA2
PG2
DDG2
PB2
PF2
PC2
DDC2
PD2
DDD2
PE2
0
DDA1
PG1
DDG1
PB1
PF1
PC1
DDC1
PD1
DDD1
PE1
0
DDA0 DDRA
PG0 PORTG
DDG0 DDRG
DDG7
PB7
DDG6
PB6
DDG5
PB5
DDG4
PB4
DDG3
PB3
PB0
PF0
PC0
PORTB
PORTF
PORTC
PF7
PF6
PF5
PF4
PF3
PC7
PC6
PC5
PC4
PC3
DDC7
0
DDC6
0
DDC5
PD5
DDC4
PD4
DDC3
PD3
DDC0 DDRC
PD0 PORTD
DDD0 DDRD
0
0
DDD5
PE5
DDD4
PE4
DDD3
PE3
PE7
PE6
PE0
0
PORTE
CFORC
OC1M
OC1D
FOC1
OC1M7
OC1D7
FOC2
OC1M6
OC1D6
FOC3
OC1M5
OC1D5
FOC4
OC1M4
OC1D4
FOC5
OC1M3
OC1D3
0
0
0
0
0
0
$100E
$100F
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
TCNT (High)
TCNT (Low)
$1010
$1011
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
TIC1 (High)
TIC1 (Low)
$1012
$1013
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
TIC2 (High)
TIC2 (Low)
$1014
$1015
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
TIC3 (High)
TIC3 (Low)
$1016
$1017
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
TOC1 (High)
TOC1 (Low)
$1018
$1019
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
TOC2 (High)
TOC2 (Low)
$101A
$101B
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
TOC3 (High)
TOC3 (Low)
$101C
$101D
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
TOC4 (High)
TOC4 (Low)
$101E
$101F
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
TI4/O5 (High)
TI4/O5 (Low)
$1020
$1021
OM2
OL2
OM3
OL3
OM4
OL4
OM5
OL5
TCTL1
EDG4B
EDG4A
EDG1B
EDG1A
EDG2B
EDG2A
EDG3B
EDG3A TCTL2
MOTOROLA
14
MC68HC11F1/FC0
MC68HC11FTS/D
Table 5 MC68HC11F1 Register and Control Bit Assignments (Continued)
Bit 7
6
5
4
3
2
1
Bit 0
$1022
$1023
OC1I
OC1F
OC2I
OC2F
OC3I
OC3F
OC4I
OC4F
I4/O5I
I4/O5F
IC1I
IC1F
IC2I
IC2F
IC3I
IC3F
TMSK1
TFLG1
$1024
$1025
$1026
$1027
$1028
$1029
$102A
$102B
$102C
$102D
$102E
$102F
$1030
$1031
$1032
$1033
$1034
$1035
$1036
$1037
$1038
$1039
$103A
$103B
$103C
$103D
$103E
$103F
TOI
TOF
0
RTII
PAOVI
PAII
PAIF
PEDGE
4
0
0
PR1
PR0
0
TMSK2
TFLG2
PACTL
PACNT
SPCR
SPSR
RTIF
PAOVF
0
0
0
PAEN
PAMOD
0
I4/05
RTR1
RTR0
Bit 0
SPR0
0
Bit 7
SPIE
SPIF
Bit 7
TCLR
R8
6
5
3
2
1
SPE
DWOM
MSTR
MODF
4
CPOL
CPHA
SPR1
WCOL
0
0
0
0
6
5
3
2
1
Bit 0
SPDR
SCP2
SCP1
SCP0
M
RCKB
SCR2
SCR1
SCR0 BAUD
T8
TCIE
TC
6
0
WAKE
0
0
0
SCCR1
SCCR2
SCSR
SCDR
ADCTL
ADR1
ADR2
ADR3
ADR4
TIE
RIE
ILIE
IDLE
4
TE
RE
RWU
SBK
0
TDRE
Bit 7
CCF
Bit 7
Bit 7
Bit 7
Bit 7
0
RDRF
OR
NF
FE
5
3
2
1
Bit 0
CA
0
SCAN
MULT
4
CD
CC
CB
6
5
5
5
5
0
3
2
1
Bit 0
Bit 0
Bit 0
Bit 0
6
4
3
2
1
6
4
3
3
2
2
1
1
6
4
0
PTCON
BPRT3
BPRT2
BPRT1
BPRT0 BPROT
Reserved
Reserved
GWOM
0
CWOM
0
CLK4X
IRQE
5
LIRDV
DLY
0
CME
3
SPRBYP
FCME
2
0
0
OPT2
CR1
1
CR0
Bit 0
OPTION
COPRST
Bit 7
6
4
ODD
RBOOT
RAM3
TILOP
EE3
EVEN
SMOD
RAM2
0
0
BYTE
IRV
ROW
PSEL3
REG3
DISR
1
ERASE
PSEL2
REG2
FCM
EELAT
PSEL1
REG1
FCOP
1
EEPGM PPROG
PSEL0 HPRIO
REG0 INIT
MDA
RAM1
OCCR
EE1
RAM0
CBYP
EE0
0
TEST1
EE2
NOCOP
EEON CONFIG
Reserved
$1040
to
$105B
Reserved
PSTHB CSSTRH
PSIZB CSCTL
$105C
$105D
$105E
$105F
I01SA
I01EN
GA15
I01AV
I01SB
I01PL
GA14
I02AV
I02SA
I02EN
GA13
0
I02SB
I02PL
GSTHA
GCSPR
GA11
GSTGB
PCSEN
GA10
PSTHA
PSIZA
0
GA12
0
CSGADR
GNPOL
GAVLD
GSIZA
GSIZB
GSIZC CSGSIZ
MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
15
3.2 MC68HC11FC0 Control Registers
Table 6 MC68HC11FC0 Register and Control Bit Assignments
Bit 7
PA7
6
PA6
5
PA5
4
PA4
3
PA3
2
PA2
1
PA1
Bit 0
PA0
$1000
$1001
$1002
$1003
$1004
$1005
$1006
$1007
$1008
$1009
$100A
$100B
$100C
$100D
PORTA
DDA7
PG7
DDA6
PG6
DDA5
PG5
DDA4
PG4
DDA3
PG3
DDA2
PG2
DDG2
PB2
PF2
PC2
DDC2
PD2
DDD2
PE2
0
DDA1
PG1
DDG1
PB1
PF1
PC1
DDC1
PD1
DDD1
PE1
0
DDA0 DDRA
PG0 PORTG
DDG0 DDRG
DDG7
PB7
DDG6
PB6
DDG5
PB5
DDG4
PB4
DDG3
PB3
PB0
PF0
PC0
PORTB
PORTF
PORTC
PF7
PF6
PF5
PF4
PF3
PC7
PC6
PC5
PC4
PC3
DDC7
0
DDC6
0
DDC5
PD5
DDC4
PD4
DDC3
PD3
DDC0 DDRC
PD0 PORTD
DDD0 DDRD
0
0
DDD5
PE5
DDD4
PE4
DDD3
PE3
PE7
PE6
PE0
0
PORTE
CFORC
OC1M
OC1D
FOC1
OC1M7
OC1D7
FOC2
OC1M6
OC1D6
FOC3
OC1M5
OC1D5
FOC4
OC1M4
OC1D4
FOC5
OC1M3
OC1D3
0
0
0
0
0
0
$100E
$100F
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
TCNT (High)
TCNT (Low)
$1010
$1011
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
TIC1 (High)
TIC1 (Low)
$1012
$1013
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
TIC2 (High)
TIC2 (Low)
$1014
$1015
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
TIC3 (High)
TIC3 (Low)
$1016
$1017
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
TOC1 (High)
TOC1 (Low)
$1018
$1019
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
TOC2 (High)
TOC2 (Low)
$101A
$101B
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
TOC3 (High)
TOC3 (Low)
$101C
$101D
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
TOC4 (High)
TOC4 (Low)
$101E
$101F
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
TI4/O5 (High)
TI4/O5 (Low)
$1020
$1021
OM2
OL2
OM3
OL3
OM4
OL4
OM5
OL5
TCTL1
EDG4B
EDG4A
EDG1B
EDG1A
EDG2B
EDG2A
EDG3B
EDG3A TCTL2
$1022
$1023
OC1I
OC1F
OC2I
OC2F
OC3I
OC3F
OC4I
OC4F
I4/O5I
I4/O5F
IC1I
IC1F
IC2I
IC2F
IC3I
IC3F
TMSK1
TFLG1
$1024
$1025
TOI
RTII
PAOVI
PAII
0
0
0
0
PR1
0
PR0
0
TMSK2
TFLG2
TOF
RTIF
PAOVF
PAIF
MOTOROLA
16
MC68HC11F1/FC0
MC68HC11FTS/D
Table 6 MC68HC11FC0 Register and Control Bit Assignments (Continued)
Bit 7
0
6
PAEN
6
5
4
PEDGE
4
3
2
I4/05
2
1
RTR1
1
Bit 0
RTR0
Bit 0
SPR0
0
$1026
$1027
$1028
$1029
$102A
$102B
$102C
$102D
$102E
$102F
PAMOD
0
3
PACTL
PACNT
SPCR
SPSR
SPDR
Bit 7
SPIE
SPIF
Bit 7
TCLR
R8
5
DWOM
0
SPE
WCOL
6
MSTR
MODF
4
CPOL
0
CPHA
0
SPR1
0
5
3
2
1
Bit 0
SCP2
T8
SCP1
0
SCP0
M
RCKB
WAKE
TE
SCR2
0
SCR1
0
SCR0 BAUD
0
SCCR1
SCCR2
SCSR
TIE
TCIE
TC
RIE
RDRF
5
ILIE
IDLE
4
RE
NF
2
RWU
FE
SBK
0
TDRE
Bit 7
OR
3
6
1
Bit 0
SCDR
$1030
to
Reserved
$1037
Reserved
OPT2
$1038
$1039
$103A
$103B
$103C
$103D
$103E
$103F
GWOM
0
CWOM
CLK4X
IRQE
5
LIRDV
DLY
4
0
CME
3
SPRBYP
FCME
2
0
CR1
1
0
0
6
CR0
Bit 0
OPTION
COPRST
Reserved
Bit 7
RBOOT
RAM5
TILOP
0
SMOD
MDA
RAM3
OCCR
0
IRV
RAM2
CBYP
0
PSEL3
RAM1
DISR
0
PSEL2
RAM0
FCM
PSEL1
REG1
FCOP
0
PSEL0 HPRIO
REG0 INIT
RAM4
0
0
0
0
TEST1
NOCOP
CONFIG
Reserved
$1040
to
$105B
Reserved
$105C
$105D
$105E
$105F
I01SA
I01EN
GA15
I01AV
I01SB
I01PL
GA14
I02AV
I02SA
I02EN
GA13
0
I02SB
I02PL
GSTHA
GCSPR
GA11
GSTGB
PCSEN
GA10
PSTHA
PSIZA
0
PSTHB CSSTRH
PSIZB CSCTL
GA12
0
CSGADR
GNPOL
GAVLD
GSIZA
GSIZB
GSIZC CSGSIZ
MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
17
4 Operating Modes and System Initialization
The 16-bit address bus can access 64 Kbytes of memory. Because the MC68HC11F1 and
MC68HC11FC0 are intended to operate principally in expanded mode, there is no internal ROM and
the address bus is non-multiplexed. Both devices include 1 Kbyte of static RAM, a 96-byte control reg-
ister block, and 256 bytes of bootstrap ROM. The MC68HC11F1 also includes 512 bytes of EEPROM.
RAM and registers can be remapped on both the MC68HC11F1 and the MC68HC11FC0. On both the
MC68HC11F1 and the MC68HC11FC0, out of reset RAM resides at $0000 to $03FF and registers re-
side at $1000 to $105F. On the MC68HC11F1, RAM and registers can both be remapped to any 4-
Kbyte boundary. On the MC68HC11FC0, RAM can be remapped to any 1-Kbyte boundary, and regis-
ters can be remapped to any 4-Kbyte boundary in the first 16 Kbytes of address space.
RAM and control register locations are defined by the INIT register, which can be written only once with-
in the first 64 E-clock cycles after a reset in normal modes. It becomes a read-only register thereafter.
If RAM and the control register block are mapped to the same boundary, the register block has priority
of the first 96 bytes.
In expanded and special test modes in the MC68HC11F1, EEPROM is located from $xE00 to $xFFF,
where x represents the value of the four high-order bits of the CONFIG register. EEPROM is enabled
by the EEON bit of the CONFIG register. In single-chip and bootstrap modes, the EEPROM is located
from $FE00 to $FFFF.
4.1 Operating Modes
Bootstrap ROM resides at addresses $BF00–$BFFF, and is only available when the MCU operates in
special bootstrap operating mode. Operating modes are determined by the logic levels applied to the
MODB and MODA pins at reset.
In single-chip mode, the MCU functions as a self-contained microcontroller and has no external address
or data bus. Ports B, C and F are available for general-purpose I/O (GPIO). Ports B and F are outputs
only; each of the port C pins can be configured as input or output.
CAUTION
The MC68HC11FC0 must not be configured to boot in single-chip mode because
it has no internal ROM or EEPROM. Operation of the device in single-chip mode
will result in erratic behavior.
In expanded mode, the MCU can access external memory. Ports B and F provide the address bus, and
port C is the data bus.
Special bootstrap mode is a variation of single chip mode that provides access to the internal bootstrap
ROM. In this mode, the user can download a program into on-chip RAM through the serial communica-
tion interface (SCI).
Special test mode, a variation of expanded mode, is primarily used during Motorola’s internal production
testing, but can support emulation and debugging during program development.
Table 7 shows a summary of operating modes, mode select pins, and control bits in the HPRIO register.
Table 7 Hardware Mode Select Summary
Input Pins
Control Bits in HPRIO (Latched at Reset)
Mode Description
MODB
MODA
RBOOT
SMOD
MDA
1
1
0
0
0
1
0
1
Single Chip
0
0
1
0
0
0
1
1
0
1
0
1
Expanded
Special Bootstrap
Special Test
MOTOROLA
18
MC68HC11F1/FC0
MC68HC11FTS/D
4.2 Memory Maps
x000
$0000 —
$03FF —
—
—
—
—
—
—
1
1024 BYTES RAM
x3FF
y000
EXTERNAL
EXTERNAL
—
—
—
—
—
—
$1000 —
$105F —
2
96-BYTE REGISTER FILE
y05F
EXTERNAL
EXTERNAL
$BFC0
SPECIAL
MODE
INTERRUPT
256 BYTES
BOOTSTRAP
ROM
$BF00 —
$BFFF —
—
—
—
—
—
—
3
VECTORS
$BFFF
4
RESERVED
$FFC0
512
NORMAL
MODE
INTERRUPT
VECTORS
$FFFF
$FE00 —
$FFC0 —
BYTES
5
EEPROM
—
—
—
—
—
—
$FFFF —
SINGLE
CHIP
EXPANDED
SPECIAL
BOOTSTRAP
SPECIAL
TEST
MODA = 0
MODB = 1
MODA = 1
MODB = 1
MODA = 0
MODB = 0
MODA = 1
MODB = 0
NOTES:
1. RAM can be remapped to any 4-Kbyte boundary ($x000). “x” represents the value contained in RAM[3:0] in the
INIT register.
2. The register block can be remapped to any 4-Kbyte boundary ($y000). “y” represents the value contained in
REG[3:0] in the INIT register.
3. Special test mode vectors are externally addressed.
4. In special test mode the address locations $zD00—$zDFF are not externally addressable. “z” represents the val-
ue of bits EE[3:0] in the CONFIG register.
5. EEPROM can be remapped to any 4-Kbyte boundary ($z000). “z” represents the value contained in EE[3:0] in
the CONFIG register.
Figure 7 MC68HC11F1 Memory Map
MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
19
$0000 —
$03FF —
—
—
—
—
—
—
1
1024 BYTES RAM
EXTERNAL
EXTERNAL
—
—
—
—
—
—
$1000 —
$105F —
2
96-BYTE REGISTER FILE
EXTERNAL
EXTERNAL
$BFC0
SPECIAL
MODE
INTERRUPT
256 BYTES
BOOTSTRAP
ROM
$BF00 —
$BFFF —
—
—
—
—
—
—
VECTORS
$BFFF
$FFC0
NORMAL
MODE
INTERRUPT
VECTORS
$FFFF
$FE00 —
$FFC0 —
—
—
—
—
—
—
$FFFF —
SINGLE
CHIP
EXPANDED
SPECIAL
BOOTSTRAP
SPECIAL
TEST
MODA = 0
MODB = 1
MODA = 1
MODB = 1
MODA = 0
MODB = 0
MODA = 1
MODB = 0
NOTES:
1. RAM can be remapped to any 1-Kbyte boundary, depending on the value contained in the RAM field in the INIT
register.
2. The register block can be remapped to $0000, $2000, or $3000, depending on the value contained in REG[1:0]
in the INIT register.
Figure 8 MC68HC11FC0 Memory Map
4.3 System Initialization Registers
HPRIO — Highest Priority Interrupt and Miscellaneous
$x03C
Bit 7
6
5
4
IRV
0
3
2
1
Bit 0
RBOOT
SMOD
MDA
PSEL3
PSEL2
PSEL1
PSEL0
RESET:
0
0
1
0
0
0
1
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Single-Chip
0
Expanded
Bootstrap
1
1
Special Test
MOTOROLA
20
MC68HC11F1/FC0
MC68HC11FTS/D
RBOOT — Read Bootstrap ROM
RBOOT is valid only when SMOD is set to one (special bootstrap or special test mode). RBOOT can
only be written in special modes but can be read anytime.
0 = Boot loader ROM disabled and not in memory map
1 = Boot loader ROM enabled and in memory map at $BF00–$BFFF
SMOD and MDA — Special Mode Select and Mode Select A
The initial value of SMOD is the inverse of the logic level present on the MODB pin at the rising edge
of reset. The initial value of MDA equals the logic level present on the MODA pin at the rising edge of
reset. These two bits can be read at any time. They can be written at any time in special modes. Neither
bit can be written in normal modes. SMOD cannot be set once it has been cleared. Refer to Table 8.
Table 8 Hardware Mode Select Summary
Input Pins
Control Bits in HPRIO (Latched at Reset)
Mode Description
MODB
MODA
RBOOT
SMOD
MDA
1
1
0
0
0
1
0
1
Single Chip
0
0
1
0
0
0
1
1
0
1
0
1
Expanded
Special Bootstrap
Special Test
IRV — Internal Read Visibility
This bit can be read at any time. It can be written at any time in special modes, but only once in normal
modes. In single-chip and bootstrap modes, IRV has no meaning or effect.
0 = Internal reads not visible
1 = Data from internal reads is driven on the external data bus
PSEL[3:0] — See 5.2 Reset and Interrupt Registers, page 27.
INIT — RAM and I/O Mapping (MC68HC11FC0 only)
$x03D
Bit 7
RAM5
0
6
RAM4
0
5
RAM3
0
4
RAM2
0
3
RAM1
0
2
RAM0
0
1
REG1
0
Bit 0
REG0
1
RESET:
The INIT register can be written only once in first 64 cycles out of reset in normal modes, or at any time
in special modes.
NOTE
The register diagram above applies to the MC68HC11FC0 only. A diagram and bit
descriptions of the INIT register in the MC68HC11F1 are provided elsewhere in
this section.
RAM[5:0] — Internal RAM Map Position
These bits determine the upper six bits of the RAM address and allow mapping of the RAM to any one-
Kbyte boundary.
REG[1:0] — Register Block Map Position
These bits determine the location of the register block, as shown in Table 9.
Table 9 Register Block Location
REG[1:0]
0 0
Register Block Address
$0000 – $005F
0 1
$1000 – $105F
1 0
$2000 – $205F
1 1
$3000 – $305F
MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
21
INIT — RAM and I/O Mapping (MC68HC11F1 only)
$x03D
Bit 7
RAM3
0
6
RAM2
0
5
RAM1
0
4
RAM0
0
3
REG3
0
2
REG4
0
1
REG1
0
Bit 0
REG0
1
RESET:
The INIT register can be written only once in first 64 cycles out of reset in normal modes, or at any time
in special modes.
NOTE
The register diagram above applies to the MC68HC11F1 only. A diagram and bit
descriptions of the INIT register in the MC68HC11FC0 are provided elsewhere in
this section.
RAM[3:0] — Internal RAM Map Position
These bits determine the upper four bits of the RAM address and allow mapping of the RAM to any four-
Kbyte boundary. Refer to Table 10.
REG[3:0] — 96-Byte Register Block Map Position
These bits determine bits the upper 4 bits of the register block and allow mapping of the register block
to any four-Kbyte boundary. Refer to Table 10.
Table 10 RAM and Register Mapping
RAM[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Location
REG[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Location
$0000-$03FF
$1000-$13FF
$2000-$23FF
$3000-$33FF
$4000-$43FF
$5000-$53FF
$6000-$63FF
$7000-$73FF
$8000-$83FF
$9000-$93FF
$A000-$A3FF
$B000-$B3FF
$C000-$C3FF
$D000-$D3FF
$E000-$E3FF
$F000-$F3FF
$0000-$005F
$1000-$105F
$2000-$205F
$3000-$305F
$4000-$405F
$5000-$505F
$6000-$605F
$7000-$705F
$8000-$805F
$9000-$905F
$A000-$A05F
$B000-$B05F
$C000-$C05F
$D000-$D05F
$E000-$E05F
$F000-$F05F
OPT2 — System Configuration Option Register 2
$x038
Bit 7
GWOM
0
6
CWOM
0
5
CLK4X
1
4
LIRDV
0
3
—
0
2
1
Bit 0
—
SPRBYP
0
—
0
RESET
0
GWOM — Port G Wired-OR Mode Option
Refer to 7.8 Parallel I/O Registers, page 36.
MOTOROLA
22
MC68HC11F1/FC0
MC68HC11FTS/D
CWOM — Port C Wired-OR Mode Option
Refer to 7.8 Parallel I/O Registers, page 37.
CLK4X — 4XCLK Output Enable
This bit can only be written once after reset in all modes.
0 = 4XOUT clock output is disabled
1 = Buffered oscillator is driven on the 4XOUT clock output
LIRDV — Load Instruction Register Driven
In order to detect consecutive instructions in a high-speed application, LIR can be driven high for one
quarter of an E-clock cycle during each instruction fetch.
0 = LIR signal is not driven high.
1 = LIR signal is driven high.
Bits 3, 1, 0 — Not implemented. Reads always return zero and writes have no effect.
SPRBYP — See 10.2 SPI Registers, page 52.
OPTION — System Configuration Options
$x039
Bit 7
ADPU
0
6
CSEL
0
5
IRQE*
0
4
DLY*
1
3
CME
0
2
FCME*
0
1
CR1*
0
Bit 0
CR0*
0
RESET:
*Can be written only once in first 64 cycles out of reset in normal modes, or at any time in special modes.
ADPU — A/D Power-Up
This bit is implemented on the MC68HC11F1 only. On the MC68HC11FC0, reads always return zero
and writes have no effect.
0 = A/D system disabled
1 = A/D system enabled
CSEL — Clock Select
This bit is implemented on the MC68HC11F1 only. On the MC68HC11FC0, reads always return zero
and writes have no effect.
0 = A/D and EEPROM use system E clock
1 = A/D and EEPROM use internal RC clock
IRQE — IRQ Select Edge Sensitive Only
0 = Low level recognition
1 = Falling edge recognition
DLY — Enable Oscillator Start-Up Delay on Exit from STOP
0 = No stabilization delay on exit from STOP
1 = Stabilization delay of 4064 E-clock cycles is enabled on exit from STOP
CME — Clock Monitor Enable
0 = Clock monitor disabled; slow clocks can be used
1 = Slow or stopped clocks cause clock failure reset
FCME — Force Clock Monitor Enable
0 = Clock monitor circuit follows the state of the CME bit
1 = Clock monitor circuit is enabled until the next reset
In order to use both STOP and the clock monitor, the CME bit should be written to zero prior to executing
a STOP instruction and rewritten to one after recovery from STOP. FCME should be kept cleared if the
user intends to use the STOP instruction.
CR[1:0] — COP Timer Rate Select
Refer to 5.2 Reset and Interrupt Registers, page 27.
MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
23
CONFIG — EEPROM Mapping, COP, EEPROM Enables
$x03F
Bit 7
EE3
U
6
EE2
U
5
EE1
U
4
EE0
U
3
1
1
2
NOCOP
U
1
1
1
Bit 0
EEON
U
RESET
U = Unaffected by reset
Bits 7:3 — See 6.2 EEPROM Registers, page 30. (These bits are implemented on the MC68HC11F1 only.)
NOCOP — COP System Disable
0 = COP enabled (forces reset on time-out)
1 = COP disabled (does not force reset on time-out)
TEST1 — Factory Test
$x03E
Bit 7
6
0
0
5
OCCR
0
4
CBYP
0
3
2
FCM
0
1
FCOP
0
Bit 0
TILOP
DISR
—
0
0
RESET:
0
These bits can only be written in test and bootstrap modes.
TILOP — Test Illegal Opcode
This test mode allows serial testing of all illegal opcodes without servicing an interrupt after each illegal
opcode is fetched.
0 = Normal operation (trap on illegal opcodes)
1 = Inhibit LIR when an illegal opcode is found
Bit 6 — Not implemented. Reads always return zero and writes have no effect.
OCCR — Output Condition Code Register to Timer Port
0 = Normal operation
1 = Condition code bits H, N, Z, V and C are driven on PA[7:3] to allow a test system to monitor
CPU operation
CBYP — Timer Divider Chain Bypass
0 = Normal operation
1 = The 16-bit free-running timer is divided into two 8-bit halves and the prescaler is bypassed. The
system E clock drives both halves directly.
DISR — Disable Resets from COP and Clock Monitor
In test and bootstrap modes, this bit is reset to one to inhibit clock monitor and COP resets. In normal
modes, DISR is reset to zero.
0 = Normal operation
1 = COP and Clock Monitor failure do not generate a system reset
FCM — Force Clock Monitor Failure
0 = Normal operation
1 = Generate an immediate clock monitor failure reset. Note that the CME bit in the OPTION register
must also be set in order to force the reset.
FCOP — Force COP Watchdog Failure
0 = Normal operation
1 = Generate an immediate COP failure reset. Note that the NOCOP bit in the CONFIG register
must be cleared (COP enabled) in order to force the reset.
Bit 0 — Not implemented. Reads always return zero and writes have no effect.
MOTOROLA
24
MC68HC11F1/FC0
MC68HC11FTS/D
5 Resets and Interrupts
There are three sources of reset on the MC68HC11F1 and MC68HC11FC0, each having its own reset
vector:
• RESET pin
• Clock monitor failure
• Computer operating properly (COP) failure
There are 22 interrupt sources serviced by 18 interrupt vectors. (The SCI interrupt vector services five
SCI interrupt sources.) Three of the interrupt vectors are non-maskable:
• Illegal opcode trap
• Software interrupt
• XIRQ pin (pseudo non-maskable interrupt)
The other 19 interrupts, generated mostly by on-chip peripheral systems, are maskable. Maskable in-
terrupts are recognized only if the global interrupt mask bit (I) in the condition code register (CCR) is
clear. Maskable interrupts have a default priority arrangement out of reset. However, any one interrupt
source can be elevated to the highest maskable priority position by writing to the HPRIO register. This
register can be written at any time, provided the I bit in the CCR is set.
In addition to the global I bit, all maskable interrupt sources except the external interrupt (IRQ pin) are
subject to local enable bits in control registers. Each of these interrupt sources also sets a correspond-
ing flag bit in a control register that can be polled by software.
Several of these flags are automatically cleared during the normal course of responding to the interrupt
requests. For example, the RDRF flag is set when a byte has been received in the SCI. The normal
response to an RDRF interrupt request is to read the SCI status register to check for receive errors,
then to read the received data from the SCI data register. It is precisely these two steps that are required
to clear the RDRF flag, so no further instructions are necessary.
5.1 Interrupt Sources
The following table summarizes the interrupt sources, vector addresses, masks, and flag bits.
MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
25
Table 11 Interrupt and Reset Vector Assignments
Vector Address
Interrupt Source
CCR Mask Local Mask
Flag Bit
FFC0, C1
to
FFD4, D5
Reserved
—
—
—
FFD6, D7
SCI Serial System
SCI Transmit Complete
SCI Transmit Data Register Empty
SCI Idle Line Detect
TCIE
TIE
TC
TDRE
IDLE
OR
I Bit
ILIE
SCI Receiver Overrun
SCI Receive Data Register Full
SPI Serial Transfer Complete
Pulse Accumulator Input Edge
Pulse Accumulator Overflow
Timer Overflow
RIE
RIE
RDRF
SPIF
PAIF
PAOVF
TOF
FFD8, D9
FFDA, DB
FFDC, DD
FFDE, DF
FFE0, E1
FFE2, E3
FFE4, E5
FFE6, E7
FFE8, E9
FFEA, EB
FFEC, ED
FFEE, EF
FFF0, F1
FFF2, F3
FFF4, F5
FFF6, F7
FFF8, F9
FFFA, FB
FFFC, FD
FFFE, FF
I Bit
I Bit
SPIE
PAII
I Bit
PAOVI
TOI
I Bit
Timer Input Capture 4/Output Compare 5
Timer Output Compare 4
Timer Output Compare 3
Timer Output Compare 2
Timer Output Compare 1
Timer Input Capture 3
Timer Input Capture 2
Timer Input Capture 1
Real-Time Interrupt
I Bit
I4/O5I
OC4I
OC3I
OC2I
OC1I
IC3I
I4/O5F
OC4F
OC3F
OC2F
OC1F
IC3F
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
IC2I
IC2F
I Bit
IC1I
IC1F
I Bit
RTII
RTIF
None
None
None
None
None
None
None
IRQ
I Bit
None
None
None
None
NOCOP
CME
None
XIRQ Pin
X Bit
None
None
None
None
None
Software Interrupt
Illegal Opcode Trap
COP Failure
Clock Monitor Fail
RESET
5.2 Reset and Interrupt Registers
OPTION — System Configuration Options
$x039
Bit 7
ADPU
0
6
CSEL
0
5
IRQE*
0
4
DLY*
1
3
CME
0
2
FCME*
0
1
Bit 0
CR0*
0
CR1*
0
RESET:
*Can be written only once in first 64 cycles out of reset in normal modes, or at any time in special modes.
Bits [7:6], [4:2]
Refer to 4.3 System Initialization Registers, page 23, and 11.3 A/D Registers, page 56.
IRQE — IRQ Select Edge Sensitive Only
0 = Low level recognition
1 = Falling edge recognition
MOTOROLA
26
MC68HC11F1/FC0
MC68HC11FTS/D
CR[1:0] — COP Timer Rate Select
15
The COP system is driven by a constant frequency of E/2 . CR[1:0] specify an additional divide-by fac-
tor to arrive at the COP time-out rate.
Table 12 COP Watchdog Time-Out Periods
Frequency
1 MHz
2 MHz
3 MHz
4 MHz
5 MHz
6 MHz
Any E
Tolerance
-0/+32.768 ms
-0/+16.384 ms
-0/+10.923 ms
-0/+8.192 ms
-0/+6.554 ms
-0/+5.461 ms
CR[1:0] = 00
32.768 ms
16.384 ms
10.923 ms
8.192 ms
CR[1:0] = 01
131.072 ms
65.536 ms
43.691 ms
32.768 ms
26.214 ms
CR[1:0] = 10
524.288 ms
262.144 ms
174.763 ms
131.072 ms
104.858 ms
CR[1:0] = 11
2.097 s
1.049 s
699.051 ms
524.288 ms
419.430 ms
6.554 ms
5.461 ms
21.845
87.381 ms
349.525 ms
15
15
17
19
21
-0/+2 /E
2
/E
2
/E
2
/E
2
/E
COPRST — Arm/Reset COP Timer Circuitry
$x03A
Bit 7
6
6
0
5
5
0
4
4
0
3
2
2
1
1
Bit 0
7
0
3
0
0
RESET:
0
0
0
Write $55 to COPRST to arm the COP watchdog clearing mechanism. Then write $AA to COPRST to
reset the COP timer. Performing instructions between these two steps is possible provided both steps
are completed in the correct sequence before the timer times out.
HPRIO — Highest Priority I-Bit Interrupt and Miscellaneous
$x03C
Bit 7
6
5
4
3
PSEL3
0
2
PSEL2
1
1
PSEL1
0
Bit 0
PSEL0
1
RBOOT
SMOD
MDA
IRV
RESET:
Bits [7:4] — See 4.3 System Initialization Registers, page 20.
PSEL[3:0] — Interrupt Priority Select Bits
Can be written only while the I bit in the CCR is set (interrupts disabled). These bits select one interrupt
source to have priority over other I-bit related sources.
Table 13 Highest Priority Interrupt Selection
PSEL[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
Interrupt Source Promoted
Timer Overflow
Pulse Accumulator Overflow
Pulse Accumulator Input Edge
SPI Serial Transfer Complete
SCI Serial System
Reserved (Default to IRQ)
IRQ (External Pin)
Real-Time Interrupt
Timer Input Capture 1
Timer Input Capture 2
Timer Input Capture 3
MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
27
Table 13 Highest Priority Interrupt Selection (Continued)
PSEL[3:0]
1011
Interrupt Source Promoted
Timer Output Compare 1
1100
Timer Output Compare 2
1101
Timer Output Compare 3
1110
Timer Output Compare 4
1111
Timer Output Compare 5/Input Capture 4
CONFIG — EEPROM Mapping, COP, EEPROM Enables
$x03F
Bit 7
EE3
U
6
EE2
U
5
EE1
U
4
EE0
U
3
1
1
2
NOCOP
U
1
1
1
Bit 0
EEON
U
RESET
Bits 7:3, 1:0 — See 6.2 EEPROM Registers, page 30.
NOCOP — COP System Disable
0 = COP enabled (forces reset on time-out)
1 = COP disabled (does not force reset on time-out)
MOTOROLA
28
MC68HC11F1/FC0
MC68HC11FTS/D
6 Electrically Erasable Programmable ROM
The MC68HC11F1 has 512 bytes of electrically erasable programmable ROM (EEPROM). A nonvola-
tile, EEPROM-based configuration register (CONFIG) controls whether the EEPROM is present or ab-
sent and determines its position in the memory map. In single-chip and bootstrap modes the EEPROM
is positioned at $FE00–$FFFF. In expanded and special test modes, the EEPROM can be repositioned
to any 4-Kbyte boundary ($xE00–$xFFF).
NOTE
EEPROM is available on the MC68HC11F1 only.
6.1 EEPROM Operation
The EEON bit in CONFIG controls whether the EEPROM is present in the memory map. When
EEON = 1, the EEPROM is enabled. When EEON = 0, the EEPROM is disabled and removed from the
memory map. EEON is forced to one out of reset in single-chip and special bootstrap modes to enable
EEPROM. EEON is forced to zero out of reset in special test mode to remove EEPROM from the mem-
ory map, although test software can turn it back on. In normal expanded mode, EEON is reset to the
value last programmed into CONFIG.
An on-chip charge pump develops the high voltage required for programming and erasing. When the
E-clock frequency is 1 MHz or above, the charge pump is driven by the E-clock. When the E-clock fre-
quency is less than 1 MHz, select the internal RC oscillator to drive the EEPROM charge pump by writ-
ing one to the CSEL bit in the OPTION register. Refer to the discussion of the OPTION register in 4.3
System Initialization Registers, page 23.
6.2 EEPROM Registers
BPROT — Block Protect
$x035
Bit 7
0
6
0
0
5
0
0
4
PTCON
1
3
BPRT3
1
2
BPRT2
1
1
BPRT1
1
Bit 0
BPRT0
1
RESET
0
Bits [7:5] — Not implemented. Reads always return zero and writes have no effect.
PTCON — Protect for CONFIG
0 = CONFIG register can be programmed or erased normally
1 = CONFIG register cannot be programmed or erased
BPRT[3:0] — Block Protect Bits for EEPROM
0 = Protection disabled
1 = Protection enabled
Table 14 Block Protect Bits for EEPROM
Bit Name
BPRT3
BPRT2
PBRT1
BPRT0
Block Protected
$xEE0–xFFF
$xE60–xEDF
$xE20–xE5F
$xE00–xE1F
Block Size
288 Bytes
128 Bytes
64 Bytes
32 Bytes
NOTE
Block protect register bits can be written to zero (protection disabled) only once
within 64 cycles of a reset in normal modes, or at any time in special modes. Block
protect register bits can be written to one (protection enabled) at any time.
MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
29
PPROG — EEPROM Programming Control
$x03B
Bit 7
ODD
0
6
EVEN
0
5
0
0
4
BYTE
0
3
ROW
0
2
ERASE
0
1
EELAT
0
Bit 0
EEPGM
0
RESET
ODD — Program Odd Rows (TEST)
EVEN — Program Even Rows (TEST)
ROW and BYTE — Row Erase Select Bit and Byte Erase Select
The value of these bits determines the manner in which EEPROM is erased. Bit encodings are shown
in 6.2 EEPROM Registers, page 30.
Table 15 ROW and BYTE Encodings
BYTE
ROW
Action
Bulk Erase (All 512 Bytes)
Row Erase (16 Bytes)
Byte Erase
0
0
1
1
0
1
0
1
Byte Erase
ERASE — Erase/Normal Control for EEPROM
0 = Normal read or program mode
1 = Erase mode
EELAT — EEPROM Latch Control
0 = EEPROM address and data bus configured for normal reads
1 = EEPROM address and data bus configured for programming or erasing
EEPGM — EEPROM Program Command
0 = Program or erase voltage to EEPROM array switched off
1 = Program or erase voltage to EEPROM array switched on
CONFIG — EEPROM Mapping, COP, EEPROM Enables
$x03F
Bit 7
EE3
U
6
EE2
U
5
EE1
U
4
EE0
U
3
1
1
2
NOCOP
U
1
1
1
Bit 0
EEON
U
RESET
U = Unaffected by reset.
The CONFIG register is used to assign EEPROM a location in the memory map and to enable or disable
EEPROM operation. Bits in this register are user-programmed except when forced to certain values, as
noted in the following bit descriptions.
EE[3:0] — EEPROM Map Position
EEPROM is located at $xE00 – $xFFF, where x is the value represented by these four bits. In single-
chip and bootstrap modes, EEPROM is forced to $FE00 – $FFFF, regardless of the state of these bits.
On factory-fresh devices, EE[3:0] = $0.
Bit 3 — Not implemented. Reads always return one and writes have no effect.
NOCOP — COP System Disable
0 = COP enabled (forces reset on time-out)
1 = COP disabled (does not force reset on time-out)
MOTOROLA
30
MC68HC11F1/FC0
MC68HC11FTS/D
Bit 1 — Not implemented. Reads always return one and writes have no effect.
EEON — EEPROM Enable
This bit is forced to one in single-chip and bootstrap modes. In test mode, EEON is forced to zero out
of reset. In expanded mode, the EEPROM obeys the state of this bit.
0 = EEPROM is removed from the memory map.
1 = EEPROM is present in the memory map.
Refer to 6.4 CONFIG Register Programming for instructions on programming this register.
6.3 EEPROM Programming and Erasure
Programming and erasing the EEPROM is controlled by the PPROG register, subject to the block pro-
tect (BPROT) register value. To erase the EEPROM, ensure that the proper bits of the BPROT register
are cleared, and then complete the following steps:
1. Write to PPROG with the ERASE and EELAT bits set and the BYTE and ROW bits set or
cleared as appropriate.
2. Write to the appropriate EEPROM address with any data. Row erase ($xE00–$xE0F, $xE10–
$xE1F,... $xFF0–$xFFF) requires a single write to any location in the row. Perform bulk erase
by writing to any location in the array.
3. Write to PPROG with the ERASE, EELAT, and EEPGM bits set and the BYTE and ROW bits
set or cleared as appropriate.
4. Delay for 10 ms (20 ms for low-voltage operation).
5. Clear the EEPGM bit in PPROG to turn off the high voltage.
6. Clear the PPROG register to reconfigure EEPROM address and data buses for normal opera-
tions.
To program the EEPROM, ensure that the proper bits of the BPROT register are cleared, and then com-
plete the following steps:
1. Write to PPROG with the EELAT bit set.
2. Write data to the desired address.
3. Write to PPROG with the EELAT and EEPGM bits set.
4. Delay for 10 ms (20 ms for low-voltage operation).
5. Clear the EEPGM bit in PPROG to turn off the high voltage.
6. Clear the PPROG register to reconfigure EEPROM address and data buses for normal opera-
tions.
6.3.1 Programming a Byte
The following example shows how to program an EEPROM byte. This example assumes that the ap-
propriate bits in BPROT are cleared and that the data to be programmed is present in accumulator A.
PROG
LDAB
STAB
STAA
LDAB
STAB
JSR
#$02
EELAT=1, EEPGM=0
Set EELAT bit
Store data to EEPROM address
EELAT=1, EEPGM=1
Turn on programming voltage
Delay 10 ms
$103B
$FE00
#$03
$103B
DLY10
$103B
CLR
Turn off high voltage and set to READ mode
6.3.2 Bulk Erase
The following example shows how to bulk erase the 512-byte EEPROM. The CONFIG register is not
affected in this example. Note that when the CONFIG register is bulk erased, CONFIG and the 512-byte
array are all erased.
BULKE
LDAB
STAB
#$06
$103B
ERASE=1, EELAT=1, EEPGM=0
Set EELAT bit
MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
31
STAB
LDAB
STAB
JSR
$FE00
#$07
$103B
DLY10
$103B
Store any data to any EEPROM address
EELAT=1, EEPGM=1
Turn on programming voltage
Delay 10 ms
CLR
Turn off high voltage and set to READ mode
6.3.3 Row Erase
The following example shows how to perform a fast erase of large sections of EEPROM. This example
assumes that index register X contains the address of a location in the desired row.
ROWE
LDAB
STAB
STAB
LDAB
STAB
JSR
#$0E
ROW=1, ERASE=1, EELAT=1, EEPGM=0
Set to ROW erase mode
Store any data to any address in ROW
ROW=1, ERASE=1, EELAT=1, EEPGM=1
Turn on high voltage
$103B
$xxxx
#$0F
$103B
DLY10
$103B
Delay 10 ms
Turn off high voltage and set to READ mode
CLR
6.3.4 Byte Erase
The following is an example of how to erase a single byte of EEPROM. This example assumes that in-
dex register X contains the address of the byte to be erased.
BYTEE
LDAB
STAB
STAB
LDAB
STAB
JSR
#$16
$103B
$0,X
BYTE=1, ROW=0, ERASE=1, EELAT=1, EEPGM=0
Set to BYTE erase mode
Store any data to address to be erased
BYTE=1, ROW=0, ERASE=1, EELAT=1, EEPGM=1
Turn on high voltage
#$17
$103B
DLY10
$103B
Delay 10 ms
Turn off high voltage and set to READ mode
CLR
6.4 CONFIG Register Programming
Because the CONFIG register is implemented with EEPROM cells, use EEPROM procedures to erase
and program this register. The procedure for programming is the same as for programming a byte in
the EEPROM array, except that the CONFIG register address is used. CONFIG can be programmed or
erased (including byte erase) while the MCU is operating in any mode, provided that PTCON in BPROT
is clear. To change the value in the CONFIG register, complete the following procedure. Do not initiate
a reset until the procedure is complete. The new value will not take effect until after the next reset se-
quence.
1. Erase the CONFIG register.
2. Program the new value to the CONFIG address.
3. Initiate reset.
MOTOROLA
32
MC68HC11F1/FC0
MC68HC11FTS/D
7 Parallel Input/Output
On the MC68HC11F1, either 54 or 51 pins are available for general-purpose I/O, depending on the
package. These pins are arranged into ports A, B, C, D, E, F, and G. On the MC68HC11FC0, either 52
or 49 pins are available, depending on the package.
I/O functions on some ports (B, C, F, and G) are affected by the mode of operation selected. In the sin-
gle-chip and bootstrap modes, they are configured as parallel I/O data ports. In expanded and test
modes, they are configured as follows:
• Ports B and F are configured as the address bus.
• Port C is configured as the data bus.
• Port G bit 7 is configured as the optional program chip select CSPROG.
In addition, in expanded and test modes the R/W signal is configured as data bus direction control. The
remaining ports (A, D, and E) are unaffected by mode changes.
7.1 Port A
Port A is an eight-bit general-purpose I/O port (PA[7:0]) with a data register (PORTA) and a data direc-
tion register (DDRA). Port A pins are available for shared use among the main timer, pulse accumulator,
and general I/O functions, regardless of mode. Four pins can be used for timer output compare func-
tions (OC), three for input capture (IC), and one as either a fourth IC or a fifth OC.
7.2 Port B
Port B is an eight-bit general-purpose output-only port in single-chip modes. In expanded modes, port
B pins act as high-order address lines ADDR[15:8], and accesses to PORTB (the port B data register)
are mapped externally.
7.3 Port C
Port C is an eight-bit general-purpose I/O port with a data register (PORTC) and a data direction register
(DDRC). In single-chip modes, port C pins are general-purpose I/O pins PC[7:0]. Port C can be config-
ured for wired-OR operation in single-chip modes by setting the CWOM bit in the OPT2 register. In ex-
panded modes, port C is the data bus DATA[7:0], and accesses to PORTC (the port C data register)
are mapped externally.
7.4 Port D
Port D is a six-bit general-purpose I/O port with a data register (PORTD) and a data direction register
(DDRD). In all modes, the six port D lines (PD[5:0]) can be used for general-purpose I/O or for the serial
communications interface (SCI) or serial peripheral interface (SPI) subsystems. Port D can also be con-
figured for wired-OR operation.
7.5 Port E
Port E is an eight-bit input-only port that is also used (on the MC68HC11F1 only) as the analog input
port for the analog-to-digital converter. Port E pins that are not used for the A/D system can be used as
general-purpose inputs. However, PORTE should not be read during the sample portion of an A/D con-
version sequence.
NOTE
PE7 and PE0 are not available on the 80-pin MC68HC11FC0. PE7, PE4, and PE0
are not available on the 64-pin MC68HC11FC0.
7.6 Port F
Port F is an eight-bit output-only port. In single-chip mode, port F pins are general-purpose output pins
PF[7:0]. In expanded mode, port F pins act as low-order address outputs ADDR[7:0].
MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
33
7.7 Port G
Port G is an eight-bit general-purpose I/O port with a data register (PORTG) and a data direction register
(DDRG). When enabled, the upper four lines (PG[7:4] can be used as chip-select outputs in expanded
modes. When any of these pins are not being used for chip selects, they can be used for general-pur-
pose I/O. Port G can be configured for wired-OR operation by setting the GWOM bit in the OPT2 reg-
ister.
NOTE
PG[1:0] are not available on the 64-pin MC68HC11FC0.
7.8 Parallel I/O Registers
Port pin function is mode dependent. Do not confuse pin function with the electrical state of the pin at
reset. Port pins are either driven to a specified logic level or are configured as high impedance inputs.
I/O pins configured as high-impedance inputs have port data that is indeterminate. The contents of the
corresponding latches are dependent upon the electrical state of the pins during reset. In port descrip-
tions, an “I” indicates this condition. Port pins that are driven to a known logic level during reset are
shown with a value of either one or zero. Some control bits are unaffected by reset. Reset states for
these bits are indicated with a “U”.
PORTA — Port A Data Register
$x000
Bit 7
PA7
I
6
PA6
I
5
PA5
I
4
PA4
I
3
PA3
I
2
PA2
I
1
PA1
I
Bit 0
PA0
I
RESET:
Alternate
Function:
PAI
OC2
OC1
OC3
OC1
OC4
OC1
OC5/IC4
OC1
IC1
—
IC2
—
IC3
—
And/or:
OC1
I = Indeterminate value
DDRA — Port A Data Direction Register
$x001
Bit 7
DDA7
0
6
DDA6
0
5
DDA5
0
4
DDA4
0
3
DDA3
0
2
DDA2
0
1
DDA1
0
Bit 0
DDA0
0
RESET:
For DDRx bits, 0 = input and 1 = output.
PORTG — Port G Data Register
$x002
Bit 7
PG7
I
6
PG6
I
5
PG5
I
4
PG4
I
3
PG3
I
2
PG2
I
1
PG1*
I
Bit 0
PG0*
I
RESET:
Alternate
Function:
CSPROG CSGEN
CSIO1
CSIO2
*These bits are not present on the 64-pin QFP version of the MC68HC11FC0.
I = Indeterminate value
MOTOROLA
34
MC68HC11F1/FC0
MC68HC11FTS/D
DDRG — Port G Data Direction Register
$x003
Bit 7
DDG7*
0
6
DDG6
0
5
DDG5
0
4
DDG4
0
3
DDG3
0
2
DDG2
0
1
DDG1
0
Bit 0
DDG0
0
RESET:
* Following reset in expanded and test modes, PG7/CSPRG is configured as a program chip select, forcing the pin
to be an output pin, even though the value of the DDG7 bit remains zero.
For DDRx bits, 0 = input and 1 = output.
PORTB — Port B Data Register
$x004
Bit 7
PB7
0
6
PB6
0
5
PB5
0
4
PB4
0
3
PB3
0
2
PB2
0
1
PB1
0
Bit 0
PB0
0
RESET:
Alternate
Function:
ADDR15 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10
ADDR9
ADDR8
The reset state of port B is mode dependent. In single-chip or bootstrap modes, port B pins are general-
purpose outputs. In expanded and test modes, port B pins are high-order address outputs and PORTB
is not in the memory map.
PORTF — Port F Data Register
$x005
PF7
0
PF6
0
PF5
0
PF4
0
PF3
0
PF2
0
PF1
0
PF0
0
RESET:
Alternate
Function:
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
The reset state of port F is mode dependent. In single-chip or bootstrap modes, port F pins are general-
purpose outputs. In expanded and test modes, port F pins are low-order address outputs and PORTF
is not in the memory map.
PORTC — Port C Data Register
$x006
Bit 7
PC7
I
6
PC6
I
5
PC5
I
4
PC4
I
3
PC3
I
2
PC2
I
1
PC1
I
Bit 0
PC0
I
RESET:
Alternate
Function:
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
The reset state of port C is mode dependent. In single-chip and bootstrap modes, port C pins are high-
impedance inputs. In expanded or test modes, port C pins are data bus inputs/outputs and PORTC is
not in the memory map. The R/W signal is used to control the direction of data transfers.
DDRC — Port C Data Direction Register
$x007
Bit 7
DDC7
0
6
DDC6
0
5
DDC5
0
4
DDC4
0
3
DDC3
0
2
DDC2
0
1
DDC1
0
Bit 0
DDC0
0
RESET:
For DDRx bits, 0 = input and 1 = output.
MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
35
PORTD — Port D Data Register
$x008
Bit 7
6
0
0
5
PD5
I
4
PD4
I
3
PD3
I
2
PD2
I
1
PD1
I
Bit 0
PD0
I
0
0
RESET:
Alternate
Function:
—
—
SS
SCK
MOSI
MISO
TxD
RxD
DDRD — Port D Data Direction Register
$x009
Bit 7
6
0
0
5
DDD5
0
4
DDD4
0
3
DDD3
0
2
DDD2
0
1
DDD1
0
Bit 0
DDD0
0
0
0
RESET:
For DDRx bits, 0 = input and 1 = output.
NOTE
When the SPI system is in slave mode, DDD5 has no meaning or effect. When the
SPI system is in master mode, DDD5 determines whether bit 5 of PORTD is an er-
ror detect input (DDD5 = 0) or a general-purpose output (DDD5 = 1). If the SPI sys-
tem is enabled and expects one or more of bits [4:2] to be inputs, those bits will be
inputs regardless of the state of the associated DDR bits. If one or more of bits [4:2]
are expected to be outputs, those bits will be outputs only if the associated DDR
bits are set.
PORTE — Port E Data
$x00A
Bit 7
6
PE6
U
5
PE5
U
4
PE4
U
3
PE3
U
2
PE2
U
1
PE1
U
Bit 0
1
2
1
PE7
U
PE0
U
RESET:
Alternate
Function
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
NOTES:
1. These bits are not present on the MC68HC11FC0 and will always read zero.
2. This bit is not present on the 64-pin QFP version of the MC68HC11FC0 and will always read zero.
U = Unaffected by rest.
PORTE is an input-only register. Reads return the digital state of the I/O pins, and writes have no effect.
On the MC68HC11F1, port E is shared with the analog-to-digital converter. (The A/D converter is not
present on the MC68HC11FC0.)
OPT2 — System Configuration Option Register 2
$x038
Bit 7
GWOM
0
6
CWOM
0
5
CLK4X
1
4
LIRDV
0
3
—
0
2
SPRBYP
0
1
—
0
Bit 0
—
RESET
0
GWOM — Port G Wired-OR Mode Option
This bit affects all port G pins together.
0 = Port G outputs are normal CMOS outputs
1 = Port G outputs act as open-drain outputs
MOTOROLA
36
MC68HC11F1/FC0
MC68HC11FTS/D
CWOM — Port C Wired-OR Mode Option
This bit affects all port C pins together.
0 = Port C outputs are normal CMOS outputs
1 = Port C outputs act as open-drain outputs
CLK4X — 4XCLK Output Enable
Refer to 4.3 System Initialization Registers, page 23
LIRDV — Load Instruction Register Driven
Refer to 4.3 System Initialization Registers, page 23
Bits 3, 1, 0 — Not implemented. Reads always return zero and writes have no effect.
SPRBYP — Refer to 10.2 SPI Registers, page 52.
MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
37
8 Chip-Selects
Chip selects eliminate the need for additional external components to interface with peripherals in ex-
panded non-multiplexed modes. Chip-select registers control polarity, address block size, base ad-
dress, and clock stretching.
8.1 Chip-Select Operation
There are four programmable chip selects on the MC68HC11F1 and MC68HC11FC0: two for external
I/O (CSIO1 and CSIO2), one for external program space (CSPROG), and one general-purpose chip se-
lect (CSGEN).
CSPROG is active low and becomes active at address valid time. CSPROG is enabled by the PCSEN
bit of the chip-select control register (CSCTL). Its address block size is selected by the PSIZA and
PSIZB bits of CSCTL.
Use the I/O chip selects (CSIO1 and CSIO2) for external I/O devices. These chip-select addresses are
found in the memory map block that contains the status and control registers. CSIO1 is mapped from
$x060 to $x7FF, and CSIO2 is mapped from $x800 to $xFFF, where x represents the REG[3:0] bits of
the INIT register on the MC68HC11F1 or the REG[1:0] bits of the INIT register on the MC68HC11FC0.
Polarity and enable-disable selections are controlled by CSCTL register bits IO1EN, IO1PL, IO2EN, and
IO2PL. The IO1AV and IO2AV bits of the CSGSIZ register determine whether the chip selects are valid
during address or E-clock valid times.
The general-purpose chip select is the most flexible of the four chip selects. Polarity, valid assertion
time, and block size are determined by the GNPOL, GAVLD, GSIZA, GSIZB, and GSIZC bits of the
CSGSIZ register. The starting address is selected with the CSGADR register.
Each of the four chip selects has two associated bits in the chip-select clock stretch register (CSSTRH).
These bits allow clock stretching from zero to three cycles (full E-clock periods) to accommodate slow
device interfaces. Any of the chip selects can be programmed to cause a clock stretch to occur only
during access to addresses that fall within that particular chip select’s address range.
During the stretch period, the E-clock is held high and the bus remains in the state that it is normally in
at the end of E high time. Internally, the clocks continue to run, which maintains the integrity of the timers
and baud-rate generators.
Priority levels are assigned to prevent the four chip selects from conflicting with each other or with in-
ternal memory and registers. There are two sets of priorities controlled by the value of the general-pur-
pose chip-select priority bit (GCSPR) of the CSCTL register. Refer to Table 17.
8.2 Chip-Select Registers
CSSTRH — Clock Stretching
$x05C
Bit 7
IO1SA
0
6
IO1SB
0
5
IO2SA
0
4
IO2SB
0
3
GSTHA
0
2
GSTHB
0
1
PSTHA
0
Bit 0
PSTHB
0
RESET:
IO1SA, IOS1B — I/O Chip-Select 1 Clock Stretch
IO2SA, IO2SB — I/O Chip-Select 2 Clock Stretch
GSTHA, GSTHB — General-Purpose Chip-Select Clock Stretch
PSTHA, PSSTHB — Program Chip-Select Clock Stretch
Each pair of bits selects the number of clock cycles of stretch for the corresponding chip select.
MOTOROLA
38
MC68HC11F1/FC0
MC68HC11FTS/D
Table 16 Chip Select Clock Stretch Control
Clock Stretch
Clock Stretch
Bits A, B
0 0
0 1
1 0
1 1
0 Cycles
1 Cycle
2 Cycles
3 Cycles
CSCTL — Chip-Select Control
$x05D
Bit 7
IO1EN
0
6
IO1PL
0
5
IO2EN
0
4
3
2
PCSEN*
—
1
PSIZA
0
Bit 0
PSIZB
0
IO2PL
0
GCSPR
RESET:
0
* PCSEN is set out of reset in expanded modes and cleared in single-chip modes.
IO1EN — I/O Chip-Select 1 Enable
0 = CSIO1 disabled
1 = CSIO1 enabled
IO1PL — I/O Chip-Select 1 Polarity
0 = CSIO1 active low
1 = CSIO1 active high
IO1EN — I/O Chip-Select 2 Enable
0 = CSIO2 disabled
1 = CSIO2 enabled
IO2PL — I/O Chip-Select 2 Polarity
0 = CSIO2 active low
1 = CSIO2 active high
GCSPR — General-Purpose Chip-Select Priority
0 = Program chip-select has priority over general-purpose chip-select
1 = General-purpose chip-select has priority over program chip-select
Refer to Table 17.
Table 17 Chip Select Priorities
GCSPR = 0
On-Chip Registers
GCSPR = 1
On-Chip Registers
On-Chip RAM
On-Chip RAM
Bootloader ROM
On-Chip EEPROM
I/O Chip Selects
Bootloader ROM
1
1
On-Chip EEPROM
I/O Chip Selects
Program Chip Select
General-Purpose Chip Select
NOTES:
General-Purpose Chip Select
Program Chip Select
1. EEPROM is present on the MC68HC11F1 only.
MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
39
PCSEN — Program Chip-Select Enable
Reset clears PCSEN in single-chip modes and sets PCSEN in expanded modes.
0 = CSPROG disabled
1 = CSPROG enabled
PSIZA, PSIZB — Select Size of Program Chip-Select
Table 18 Program Chip Select Size Control
PSIZA
PSIZB
Size
Address Range
$0000–$FFFF
$8000–$FFFF
$C000–$FFFF
$E000–$FFFF
0
0
1
1
0
1
0
1
64 Kbytes
32 Kbytes
16 Kbytes
8 Kbytes
CSGADR — General-Purpose Chip-Select Address Register
$x05E
Bit 7
GA15
0
6
GA14
0
5
GA13
0
4
GA12
0
3
GA11
0
2
GA10
0
1
Bit 0
—
—
RESET:
0
0
GA[15:10] — General-Purpose Chip-Select Starting Address
These bits determine the starting address of the CSGEN valid address space and correspond to the
high-order address bits ADDR[15:10]. Table 19 illustrates how the block size selected determines
which of this register's bits are valid.
Table 19 General Purpose Chip Select Starting Address
CSGEN Block Size
0 Kbytes
CSGADR Bits Valid
None
1 Kbyte
GA15 – GA10
GA15 – GA11
GA15 – GA12
GA15 – GA13
GA15 – GA14
GA15
2 Kbytes
4 Kbytes
8 Kbytes
16 Kbytes
32 Kbytes
64 Kbytes
None
Bits [1:0] — Not implemented. Reads always return zero and writes have no effect.
CSGSIZ — General-Purpose Chip-Select Size Register
$x05F
Bit 7
IO1AV
0
6
IO2AV
0
5
—
0
4
GNPOL
0
3
GAVLD
0
2
GSIZA
1
1
GSIZB
1
Bit 0
GSIZC
1
RESET:
IO1AV — I/O Chip-Select 1 Address Valid
0 = CSIO1 is valid during E-clock valid time (E-clock high)
1 = CSIO1 is valid during address valid time
IO2AV — I/O Chip-Select 2 Address Valid
0 = CSIO2 is valid during E-clock valid time (E-clock high)
1 = CSIO2 is valid during address valid time
MOTOROLA
40
MC68HC11F1/FC0
MC68HC11FTS/D
Bit 5 — Not implemented. Reads always return zero and writes have no effect.
GNPOL — General-Purpose Chip-Select Polarity
0 = CSGEN is active low
1 = CSGEN is active high
GAVLD — General-Purpose Chip-Select Address Valid
0 = CSGEN is valid during E-clock valid time (E-clock high)
1 = CSGEN is valid during address valid time
GSIZ[A:C] — Block Size for CSGEN
Refer to Table 20 for bit values.
Table 20 General-Purpose Chip Select Size Control
GSIZ[A:C]
000
Address Size
64 Kbytes
001
32 Kbytes
010
16 Kbytes
011
8 Kbytes
100
4 Kbytes
101
2 Kbytes
110
1 Kbyte
111
0 Kbytes (disabled)
MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
41
9 Serial Communications Interface (SCI)
The SCI, a universal asynchronous receiver transmitter (UART) serial communications interface, is one
of two independent serial I/O subsystems in the MC68HC11F1 and MC68HC11FC0. The SCI has a
standard non-return to zero (NRZ) format (one start bit, eight or nine data bits, and one stop bit) and
several selectable baud rates. The transmitter and receiver are independent but use the same data for-
mat and bit rate.
9.1 SCI Block Diagrams
TRANSMITTER
BAUD RATE
CLOCK
(WRITE ONLY)
SCDR Tx BUFFER
DDD1
10 (11) - BIT Tx SHIFT REGISTER
PIN BUFFER
AND CONTROL
PD1
TxD
H
(8)
7
6
5
4
3
2
1
0
L
FORCE PIN
DIRECTION (OUT)
TRANSMITTER
CONTROL LOGIC
SCSR1
SCI STATUS 1
SCCR1
SCI CONTROL 1
TDRE
TIE
TC
TCIE
SCCR2
SCI CONTROL 2
SCI Rx
QUESTS
SCI INTERRUPT
REQUEST
INTERNAL
DATA BUS
Figure 9 SCI Transmitter Block Diagram
MOTOROLA
42
MC68HC11F1/FC0
MC68HC11FTS/D
RECEIVER
BAUD RATE
CLOCK
DDD0
÷16
10 (11) - BIT
Rx SHIFT REGISTER
PD0
RxD
PIN BUFFER
AND CONTROL
DATA
RECOVERY
H
8
7
6
5
4
3
2
1
0
L
ALL
ONES
MSB
DISABLE
DRIVER
RE
WAKEUP
LOGIC
SCCR1
SCI CONTROL 1
SCSR1
SCI STATUS 1
SCDR
Rx BUFFER
(READ ONLY)
RDRF
RIE
IDLE
ILIE
OR
RIE
SCCR2
SCI CONTROL 2
SCI Tx
REQUESTS
SCI INTERRUPT
REQUEST
INTERNAL
DATA BUS
Figure 10 SCI Receiver Block Diagram
MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
43
9.2 SCI Registers
BAUD — Baud Rate
$x02B
Bit 7
6
SCP2
0
5
SCP1
0
4
SCP0
0
3
RCKB
0
2
SCR2
U
1
SCR1
U
Bit 0
SCR0
U
TCLR
RESET:
0
TCLR — Clear Baud Rate Counters (TEST)
Bit 6 — Not implemented. Reads always return zero and writes have no effect.
RCKB — SCI Baud-Rate Clock Check (TEST)
SCP[2:0] — SCI Baud Rate Prescaler Selects
These bits determine the baud rate prescaler frequency. Refer to Table 21 and Figure 11.
SCR[2:0] — SCI Baud Rate Selects
These bits determine the receiver and transmitter baud rate. Refer to Table 22 and Figure 11.
Table 21 Baud Rate Prescaler Selection
1
Prescaler Output
Divide
Internal
Clock By
SCP[2:0]
XTAL =
XTAL =
XTAL = XTAL = XTAL = XTAL = XTAL = XTAL =
4.0 MHz 4.9152 MHz 8.0 MHz 10.0 MHz 12.0 MHz 16.0 MHz 20.0 MHz 24.0 MHz
X00
001
1
3
62500
20833
15625
4800
—
76800
25600
19200
5908
—
125000 156250 187500 250000 312500 375000
41667
31250
9600
—
52083
38400
12019
—
62500
46875
14423
20830
83333
62500
19200
—
104167 125000
X10
4
76800
24038
—
93750
28846
—
X11
13
9
101
NOTES:
1. A blank table cell indicates that an uncommon rate results.
Table 22 Baud Rate Selection
Baud Rate
Divide
Prescaler By
Prescaler
Output =
4800
Prescaler
Output =
9600
Prescaler
Output =
19200
Prescaler
Output =
38400
Prescaler
Output =
76800
SCR[2:0]
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
1
2
4800
2400
1200
600
300
150
75
9600
4800
2400
1200
600
19200
9600
4800
2400
1200
600
38400
19200
9600
4800
2400
1200
600
76800
38400
19200
9600
4800
2400
1200
600
4
8
16
32
64
128
300
150
300
—
75
150
300
The prescaler bits SCP[2:0] determine the highest baud rate, and the SCR[2:0] bits select an additional
binary submultiple (divide by 1, 2, 4,..., through 128) of this highest baud rate. The result of these two
dividers in series is the 16X receiver baud rate clock. The SCR[2:0] bits are not affected by reset and
can be changed at any time. They should not be changed, however, when an SCI transfer is in progress.
MOTOROLA
44
MC68HC11F1/FC0
MC68HC11FTS/D
Figure 11 illustrates the SCI baud rate timing chain. The prescaler select bits determine the highest
baud rate. The rate select bits determine additional divide-by-two stages to arrive at the receiver timing
(RT) clock rate. The baud rate clock is the result of dividing the RT clock by 16.
EXTAL
XTAL
OSCILLATOR
AND
CLOCK GENERATOR
INTERNAL BUS CLOCK (PH2)
(÷4)
÷ 3
÷ 4
÷ 13
÷ 9
E
X00
001
X10
X11
101
SCR[2:0]
0:0:0
÷ 2
÷ 2
÷ 2
÷ 2
÷ 2
÷ 2
÷ 2
0:0:1
0:1:0
0:1:1
1:0:0
1:0:1
1:1:0
1:1:1
SCI Receive Baud Rate (16x)
SCI Transmit Baud Rate (1x)
÷ 16
Figure 11 SCI Baud Rate Generator Block Diagram
MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
45
SCCR1 — SCI Control Register 1
$x02C
Bit 7
R8
U
6
T8
U
5
0
0
4
M
0
3
WAKE
0
2
0
0
1
0
0
Bit 0
0
0
RESET:
U = Unaffected by reset
R8 — Receive Data Bit 8
If M is set, R8 stores the ninth bit of the receive data character.
T8 — Transmit Data Bit 8
If M is set, T8 stores the ninth bit of the transmit data character.
Bit 5 — Not implemented. Reads always return zero and writes have no effect.
M — Mode (Select Character Format)
0 = 1 start bit, 8 data bits, 1 stop bit
1 = 1 start bit, 9 data bits, 1 stop bit
WAKE — Wake Up by Address Mark/Idle
0 = Wake up by IDLE line recognition
1 = Wake up by address mark
Bits [2:0] — Not implemented. Reads always return zero and writes have no effect.
SCCR2 — SCI Control Register 2
$x02D
Bit 7
TIE
0
6
TCIE
0
5
RIE
0
4
ILIE
0
3
TE
0
2
RE
0
1
RWU
0
Bit 0
SBK
0
RESET:
TIE — Transmit Interrupt Enable
0 = TDRE interrupts disabled
1 = SCI interrupt requested when the TDRE flag is set
TCIE — Transmit Complete Interrupt Enable
0 = TC interrupts disabled
1 = SCI interrupt requested when the TC flag is set
RIE — Receiver Interrupt Enable
0 = RDRF and OR interrupts disabled
1 = SCI interrupt requested when the RDRF flag or the OR flag is set
ILIE — Idle Line Interrupt Enable
0 = IDLE interrupts disabled
1 = SCI interrupt requested when IDLE status flag is set
TE — Transmitter Enable
When TE goes from zero to one, one unit of idle character time (logic one) is queued as a preamble.
0 = Transmitter disabled
1 = Transmitter enabled
RE — Receiver Enable
0 = Receiver disabled
1 = Receiver enabled
MOTOROLA
46
MC68HC11F1/FC0
MC68HC11FTS/D
RWU — Receiver Wake Up Control
0 = Normal SCI receiver
1 = Wake up enabled and receiver interrupt inhibited
SBK — Send Break
0 = Break generator off
1 = Break codes generated as long as SBK = 1
SCSR — SCI Status Register
$x02E
Bit 7
TDRE
1
6
TC
1
5
RDRF
0
4
IDLE
0
3
OR
0
2
NF
0
1
FE
0
Bit 0
0
0
RESET:
TDRE — Transmit Data Register Empty Flag
This flag is set when SCDR is empty. Clear the TDRE flag by reading SCSR with TDRE set and then
writing to SCDR.
0 = SCDR is busy
1 = SCDR is empty
TC — Transmit Complete Flag
This flag is set when the transmitter is idle (no data, preamble, or break transmission in progress). Clear
the TC flag by reading SCSR with TC set and then writing to SCDR.
0 = Transmitter is busy
1 = Transmitter is idle
RDRF — Receive Data Register Full Flag
This flag is set if a received character is ready to be read from SCDR. Clear the RDRF flag by reading
SCSR with RDRF set and then reading SCDR.
0 = SCDR empty
1 = SCDR full
IDLE — Idle Line Detected Flag
This flag is set if the RxD line is idle. Once cleared, IDLE is not set again until the RxD line has been
active and becomes idle again. The IDLE flag is inhibited when RWU = 1. Clear IDLE by reading SCSR
with IDLE set and then reading SCDR.
0 = RxD line is active
1 = RxD line is idle
OR — Overrun Error Flag
OR is set if a new character is received before a previously received character is read from SCDR. Clear
OR by reading SCSR with OR set and then reading SCDR.
0 = No overrun detected
1 = Overrun detected
NF — Noise Error Flag
NF is set if majority sample logic detects anything other than a unanimous decision. Clear NF by reading
SCSR with NF set and then reading SCDR.
0 = Unanimous decision
1 = Noise detected
FE — Framing Error
FE is set when a zero is detected where a stop bit was expected. Clear the FE flag by reading SCSR
with FE set and then reading SCDR.
0 = Stop bit detected
1 = Zero detected
MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
47
Bit 0 — Not implemented. Reads always return zero and writes have no effect.
SCDR — Serial Communications Data Register
$x02F
Bit 7
Bit 7
I
6
6
I
5
5
I
4
4
I
3
3
I
2
2
I
1
2
I
Bit 0
Bit 0
I
RESET:
I = Indeterminate value
Reading SCDR retrieves the last byte received in the receive data buffer. Writing to SCDR loads the
transmit data buffer with the next byte to be transmitted.
MOTOROLA
48
MC68HC11F1/FC0
MC68HC11FTS/D
10 Serial Peripheral Interface
The serial peripheral interface (SPI) allows the MCU to communicate synchronously with peripheral de-
vices and other microprocessors. The SPI protocol facilitates rapid exchange of serial data between de-
vices in a control system. The MC68HC11F1 and MC68HC11FC0 can be set up for master or slave
operation. Standard data rates can be as high as one half of the E-clock rate when configured as mas-
ter, and as fast as the E-clock when configured as slave.
The MC68HC11FC0 has an additional control bit that allows the SPI baud rate counter to be bypassed.
This allows a master mode baud rate equal to the E-clock frequency.
10.1 SPI Block Diagram
SPI STATUS REGISTER
DOTTED LINE CONNECTIONS
PRESENT ON MC68HC11FC0 ONLY
SPIE
SPE
DWOM
MSTR
CPHA
CPOL
SPR1
SPR0
SPIE
SPE
SPI
CONTROL
SPI INTERRUPT
REQUEST
MSTR
SS
PD5
SPR0
SPR1
÷2
÷4
INTERNAL
MCU CLOCK
÷16
÷32
M
S
SCK
PD4
CLOCK LOGIC
S
M
MOSI
PD3
SPRBYP
M
S
MSB
LSB
MISO
PD2
8-BIT SHIFT REGISTER
READ DATA BUFFER
Figure 12 SPI Block Diagram
MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
49
10.2 SPI Registers
SPCR — SPI Control Register
$x028
Bit 7
SPIE
0
6
SPE
0
5
DWOM
0
4
MSTR
0
3
CPOL
0
2
CPHA
1
1
SPR1
U
Bit 0
SPR0
U
RESET:
U = Unaffected by reset
SPIE — SPI Interrupt Enable
When SPI interrupts are enabled, a hardware interrupt sequence is requested each time the SPIF or
MODF status flag is set. SPI interrupts are inhibited if this bit is cleared or if the I bit in the condition code
register is one.
0 = SPI interrupt disabled
1 = SPI interrupt enabled
SPE — SPI Enable
When the SPE bit is set, PD[5:2] are dedicated to the SPI function. If the SPI is in master mode and the
DDRD bit 5 is set, then PD5/SS becomes a general-purpose output instead of the SS input.
0 = SPI off
1 = SPI on
DWOM — Port D Wired-OR Mode Option for SPI Pins PD[5:2]
0 = Normal CMOS outputs
1 = Open-drain outputs
MSTR — Master Mode Select
0 = Slave mode
1 = Master mode
CPOL — Clock Polarity
When the clock polarity bit is cleared and data is not being transferred, the SCK pin of the master device
has a steady state low value. When CPOL is set, SCK idles high. Refer to Figure 13.
CPHA — Clock Phase
The clock phase bit, in conjunction with the CPOL bit, controls the clock-data relationship between mas-
ter and slave. The CPHA bit selects one of two clocking protocols. Refer to Figure 13.
SCK CYCLE #
1
2
3
4
5
6
7
8
(FOR REFERENCE)
SCK (CPOL = 0)
SCK (CPOL = 1)
SAMPLE INPUT
(CPHA = 0) DATA OUT
MSB
6
5
4
3
2
1
LSB
SAMPLE INPUT
(CPHA = 1) DATA OUT
MSB
6
5
4
3
2
1
LSB
SS (TO SLAVE)
Figure 13 SPI Data Clock Timing Diagram
MOTOROLA
50
MC68HC11F1/FC0
MC68HC11FTS/D
SPR[1:0] — SPI Clock Rate Selects
These two bits select the SPI clock (SCK) rate when the device is configured as a master. When the
device is configured as a slave, the bits have no effect. Refer to Table 23.
Table 23 SPI Baud Rates
Input
SPR[1:0] = 00
SPR[1:0] = 01
SPR[1:0] = 10
SPR[1:0] = 11
Frequency
1 MHz
2 MHz
3 MHz
4 MHz
5 MHz
6 MHz
Any E
500 kbps
1 Mbps
1.5 Mbps
2 Mbps
2.5 Mbps
3 Mbps
E/2
250 kbps
500 kbps
750 kbps
1 Mbps
62.5 kbps
125 kbps
187.5 kbps
250 kbps
312.5 kbps
375 kbps
E/16
31.25 kbps
62.5 kbps
93.75 kbps
125 kbps
156.25 kbps
187.5 kbps
E/32
1.25 Mbps
1.5 Mbps
E/4
NOTE
The SPRBYP bit in OPT2 on the MC68HC11FC0 allows the SPI baud rate counter
to be bypassed. This permits a maximum master mode baud rate equal to the E-
clock frequency on the MC68HC11FC0. SPRBYP is not present on the
MC68HC11F1.
SPSR — SPI Status Register
$x029
Bit 7
SPIF
0
6
WCOL
0
5
0
0
4
MODF
0
3
0
0
2
0
0
1
0
0
Bit 0
0
0
RESET:
SPIF — SPI Transfer Complete Flag
SPIF is set when an SPI transfer is complete. It is cleared by reading SPSR with SPIF set, followed by
a read or write of SPDR.
WCOL — Write Collision
WCOL is set when SPDR is written while a transfer is in progress. It is cleared by reading SPSR with
WCOL set, followed by a read or write of SPDR.
0 = No write collision
1 = Write collision
Bit 5 — Not Implemented. Reads always return zero and writes have no effect.
MODF — Mode Fault
A mode fault terminates SPI operation. Set when SS is pulled low while MSTR = 1. MODF is cleared
by reading SPSR read with MODF set, followed by a write to SPCR.
0 = No mode fault
1 = Mode fault
Bits [3:0] — Not Implemented. Reads always return zero and writes have no effect.
SPDR — SPI Data Register
$x02A
Bit 7
Bit 7
6
6
5
5
4
4
3
3
2
2
1
1
Bit 0
Bit 0
Incoming SPI data is double buffered. Outgoing SPI data is single buffered.
MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
51
OPT2 — System Configuration Option Register 2
$x038
Bit 7
GWOM
0
6
CWOM
0
5
CLK4X
1
4
LIRDV
0
3
—
0
2
SPRBYP
0
1
—
0
Bit 0
—
RESET
0
Bits [7:4] — See 4.3 System Initialization Registers, page 22.
Bits 3, 1, 0 — Not implemented. Reads always return zero and writes have no effect.
SPRBYP — SPI Baud Rate Counter Bypass
0 = Enable SPI baud rate counter
1 = Bypass SPI baud rate counter
When the SPI baud rate counter is bypassed, the SPI can transmit at a maximum master mode baud
rate equal to the E-clock frequency. SPRBYP is present only on the MC68HC11FC0 and overrides
the setting of SPR[1:0] in SPCR.
MOTOROLA
52
MC68HC11F1/FC0
MC68HC11FTS/D
11 Analog-to-Digital Converter
The MC68HC11F1 analog-to-digital (A/D) converter system uses an all-capacitive charge-redistribution
technique to convert analog signals to digital values. The A/D system is an 8-channel, 8-bit, multiplexed-
input, successive-approximation converter, accurate to ±1 least significant bit (LSB). Because the ca-
pacitive charge redistribution technique used includes a built-in sample-and-hold, no external sample-
and-hold is required.
Dedicated lines V and V provide the reference supply voltage inputs. Systems operating at clock
RH
RL
rates of 750 kHz or below must use an internal RC oscillator. The CSEL bit in the OPTION register se-
lects the clock source for the A/D system. (The CSEL bit is described in 11.3 A/D Registers, page 56.)
A multiplexer allows the single A/D converter to select one of 16 analog signals, as shown in Table 24.
NOTE
The A/D converter is present on the MC68HC11F1 only.
PE0
AN0
V
RH
8-BIT CAPACITIVE DAC
WITH SAMPLE AND HOLD
PE1
AN1
V
RL
PE2
AN2
SUCCESSIVE APPROXIMATION
REGISTER AND CONTROL
PE3
AN3
RESULT
ANALOG
MUX
PE4
AN4
PE5
AN5
INTERNAL
DATA BUS
PE6
AN6
PE7
AN7
ADCTL A/D CONTROL
RESULT REGISTER INTERFACE
ADR1 A/D RESULT 1
ADR2 A/D RESULT 2
ADR3 A/D RESULT 3
ADR4 A/D RESULT 4
EA9 A/D BLOCK
Figure 14 A/D Converter Block Diagram
MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
53
11.1 Input Pins
Port E pins can also be used as digital inputs. Reads of port E pins are not recommended during the
sample portion of an A/D conversion cycle, when the gate signal to the N-channel input gate is on. Be-
cause no P-channel devices are directly connected to either input pins or reference voltage pins, volt-
ages above V
do not cause a latchup problem, although current should be limited according to
DD
maximum ratings. Figure 15 is a functional diagram of an input pin.
DIFFUSION/POLY
COUPLER
ANALOG
INPUT
PIN
*
+ ~20V
– ~0.7V
+ ~12V
– ~0.7V
≤ 4 KΩ
< 2 pF
~ 20 pF
400 nA
JUNCTION
LEAKAGE
DAC
CAPACITANCE
DUMMY N-CHANNEL
OUTPUT DEVICE
INPUT
PROTECTION
DEVICE
V
RL
* THIS ANALOG SWITCH IS CLOSED ONLY DURING THE 12-CYCLE SAMPLE TIME.
Figure 15 Electrical Model of an Analog Input Pin (Sample Mode)
11.2 Conversion Sequence
A/D converter operations are performed in sequences of four conversions each. A conversion sequence
can be repeated continuously or stop after one iteration. The conversion complete flag (CCF) is set after
the fourth conversion in a sequence to show the availability of data in the result registers. Figure 16
shows the timing of a typical sequence. Synchronization is referenced to the system E clock.
E CLOCK
MSB
4
CYCLES
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
2
2
2
2
2
2
2
2
CYC
12 E CYCLES
CYC CYC CYC CYC CYC CYC CYC END
SAMPLE ANALOG INPUT
SUCCESSIVE APPROXIMATION SEQUENCE
CONVERT FIRST
CONVERT SECOND
CHANNEL, UPDATE
ADR2
CONVERT THIRD
CHANNEL, UPDATE
ADR3
CONVERT FOURTH
CHANNEL, UPDATE
ADR4
CHANNEL, UPDATE
ADR1
0
32
64
96
128 — E CYCLES
Figure 16 A/D Conversion Sequence
MOTOROLA
54
MC68HC11F1/FC0
MC68HC11FTS/D
11.3 A/D Registers
ADCTL — A/D Control/Status
$x030
Bit 7
CCF
I
6
0
0
5
SCAN
I
4
MULT
I
3
CD
I
2
CC
I
1
CB
I
Bit 0
CA
I
RESET:
I = Indeterminate value
CCF — Conversions Complete Flag
A read-only status indicator, this bit is set when all four A/D result registers contain valid conversion re-
sults. Each time the ADCTL register is overwritten, this bit is automatically cleared to zero and a con-
version sequence is started. In the continuous mode, CCF is set at the end of the first conversion
sequence.
Bit 6 — Not implemented. Reads always return zero and writes have no effect.
SCAN — Continuous Scan Control
0 = Do four conversions and stop
1 = Convert four channels in selected group continuously
MULT — Multiple Channel/Single Channel Control
0 = Convert single channel selected
1 = Convert four channels in selected group
CD–CA — Channel Select D through A
Refer to Table 24. When a multiple channel mode is selected (MULT = 1), the two least significant chan-
nel select bits (CB and CA) have no meaning and the CD and CC bits specify which group of four chan-
nels is to be converted.
Table 24 A/D Converter Channel Assignments
Channel Select Control Bits
Channel Signal
Result in ADRx if MULT = 1
CD:CC:CB:CA
0000
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
ADR1
ADR2
0001
0010
ADR3
0011
ADR4
0100
ADR1
0101
ADR2
0110
ADR3
0111
ADR4
10XX
1100
Reserved
ADR1–ADR4
ADR1
1
V
RH
1
1101
1110
1111
ADR2
ADR3
ADR4
V
RL
1
(V )/2
RH
1
Reserved
NOTES:
1. Used for factory testing.
MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
55
ADR1 – ADR4 — A/D Results
$x031 – $x034
$x031
$x032
$x033
$x034
Bit 7
Bit 7
Bit 7
Bit 7
6
6
6
6
5
5
5
5
4
4
4
4
3
3
3
3
2
2
2
2
1
1
1
1
Bit 0
ADR1
ADR2
ADR3
ADR4
Bit 0
Bit 0
Bit 0
Each read-only result register holds an eight-bit conversion result. Writes to these registers have no ef-
fect. Data in the A/D converter result registers is valid when the CCF flag in the ADCTL register is set,
indicating a conversion sequence is complete. If conversion results are needed sooner, refer to Figure
16, which shows the A/D conversion sequence diagram.
Table 25 Analog Input to 8-Bit Result Translation Table
Bit 7
50%
6
5
4
3
2
1
Bit 0
1
Percentage
25%
1.250
12.5%
0.625
6.25%
0.3125
3.12%
0.1562
1.56%
0.0781
0.78%
0.0391
0.39%
0.0195
2
Volts
2.500
NOTES:
1. % of V –V
RH RL
2. Volts for V = 0; V
RL RH
= 5.0 V
OPTION — System Configuration Options
$x039
Bit 7
ADPU
0
6
CSEL
0
5
IRQE*
0
4
DLY*
1
3
2
1
Bit 0
CR0*
0
CME
0
FCME*
0
CR1*
RESET:
0
*Can be written only once in first 64 cycles out of reset in normal modes, or at any time in special modes.
ADPU — A/D Power Up
0 = A/D powered down
1 = A/D powered up
CSEL — Clock Select
0 = A/D and EEPROM use system E-Clock
1 = A/D and EEPROM use internal RC clock
Bits [5:0] — Refer to 4.3 System Initialization Registers, page 23.
MOTOROLA
56
MC68HC11F1/FC0
MC68HC11FTS/D
12 Main Timer
The main timer is based on a free-running 16-bit counter with a four-stage programmable prescaler. The
timer drives the three input capture (IC) channels, four output compare (OC) channels, one channel pro-
grammable for either IC or OC, and the pulse accumulator (PA). All of these functions share port A. The
main timer also drives the pulse accumulator, real-time interrupt (RTI), and computer operating properly
(COP) watchdog circuits.
12.1 Timer Operation
The following tables summarize timing periods for various M68HC11 functions derived from the main
timer for several crystal frequencies.
Table 26 Timer Subsystem Count and Overflow Periods
PR[1:0] = 00
TCNT
Overflow
1.000 µs 65.536 ms 4.000 µs 262.144 ms 8.000 µs 524.288 ms 16.000 µs
PR[1:0] = 01
TCNT
Overflow
PR[1:0] = 10
TCNT
Overflow
PR[1:0] = 11
E-Clock
Frequency
TCNT
Overflow
1 Count
1 Count
1 Count
1 Count
1 MHz
2 MHz
3 MHz
4 MHz
5 MHz
6 MHz
Any E
1.049 s
0.500 µs 32.768 ms 2.000 µs 131.072 ms 4.000 µs 262.144 ms 8.000 µs 524.288 ms
0.333 µs 21.845 ms 1.333 µs 87.381 ms 2.667 µs 174.763 ms 5.333 µs 349.525 ms
0.250 µs 16.384 ms 1.000 µs 65.536 ms 2.000 µs 131.072 ms 4.000 µs 262.144 ms
0.200 µs 13.107 ms 0.800 µs 52.429 ms 1.600 µs 104.858 ms 3.200 µs 209.715 ms
0.167 µs 10.923 ms 0.667 µs 43.691 ms 1.333 µs 87.381 ms 2.667 µs 174.763 ms
16
18
19
20
1/E
4/E
8/E
16/E
2
/E
2
/E
2
/E
2 /E
Table 27 Real-Time Interrupt Periods
E-Clock
Frequency
RTR[1:0] = 00
RTR[1:0] = 01
RTR[1:0] = 10
RTR[1:0] = 11
1 MHz
2 MHz
3 MHz
4 MHz
5 MHz
6 MHz
Any E
8.192 ms
4.096 ms
2.731 ms
2.048 ms
1.638 ms
16.384 ms
8.192 ms
5.461 ms
4.096 ms
3.277 ms
32.768 ms
16.384 ms
10.923 ms
8.192 ms
6.554 ms
65.536 ms
32.768 ms
21.845 ms
16.384 ms
13.107 ms
1.366 ms
2.731 ms
5.461 ms
10.923 ms
13
14
15
21
2
/E
2
/E
2
/E
2 /E
Table 28 COP Watchdog Time-Out Periods
E-Clock
Frequency
RTR[1:0] = 00
RTR[1:0] = 01
RTR[1:0] = 10
RTR[1:0] = 11
1 MHz
2 MHz
3 MHz
4 MHz
5 MHz
6 MHz
Any E
32.768 ms
16.384 ms
10.923 ms
8.192 ms
6.554 ms
131.072 ms
65.536 ms
43.691 ms
32.768 ms
26.214 ms
524.288 ms
262.144 ms
174.763 ms
131.072 ms
104.858 ms
2.097 s
1.049 s
699.051 ms
524.288 ms
419.430 ms
5.461 ms
21.845 ms
87.381 ms
349.525 ms
15
17
19
21
2
/E
2
/E
2
/E
2 /E
MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
57
PRESCALER
Divide by
TCNT (HI)
TCNT (LO)
TOI
E CLOCK
9
16-BIT FREE RUNNING
COUNTER
1, 4, 8 or 16
TOF
PR1
PR0
Interrupt
Requests
16-BIT TIMER BUS
To Pulse
Accumulator
OC1I
PORT A
8
7
6
5
4
Pins
OC1F
16-BIT COMPARATOR
=
PA7
OC1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
TOC1 (HI) TOC1 (LO)
FOC1
FOC2
FOC3
FOC4
OC2I
OC3I
OC4I
I4O5I
OC2F
OC3F
OC4F
16-BIT COMPARATOR
=
PA6
OC2/OC1
TOC2 (HI) TOC2 (LO)
16-BIT COMPARATOR
=
PA5
OC3/OC1
TOC3 (HI) TOC3 (LO)
16-BIT COMPARATOR
=
PA4
OC4/OC1
TOC4 (HI) TOC4 (LO)
16-BIT COMPARATOR
=
OC5
I4O5F
IC4
PA3
IC4/OC5
OC1
TI4O5 (HI) TI4O5 (LO)
FOC5
16-BIT LATCH
16-BIT LATCH
CLK
CFORC
IC1I
IC2I
IC3I
I4/O5
3
2
1
PA2
IC1
CLK
IC1F
IC2F
Bit 2
Bit 1
TIC1 (HI) TIC1 (LO)
PA1
IC2
16-BIT LATCH
CLK
TIC2 (HI) TIC2 (LO)
PA0
IC3
16-BIT LATCH
CLK
IC3F
Bit 0
TIC3 (HI) TIC3 (LO)
Port A
TFLG 1
TMSK 1
Pin
Control
(Note 1)
Status
Interrupt
Flags
Enables
IC/OC BLOCK
NOTE: Registers that control port A action include DDRA, OC1M, OC1D, PACTL, TCTL1 and TCTL2.
Figure 17 Main Timer
MOTOROLA
58
MC68HC11F1/FC0
MC68HC11FTS/D
12.2 Timer Registers
CFORC — Timer Force Compare
$x00B
Bit 7
FOC1
0
6
FOC2
0
5
FOC3
0
4
FOC4
0
3
FOC5
0
2
0
0
1
0
0
Bit 0
0
0
RESET:
FOCx — Force Output Compare x Action
0 = Not affected
1 = Output compare x action occurs, but OCxF flag bit is not set
Bits [2:0] — Not implemented. Reads always return zero and writes have no effect.
OC1M — Output Compare 1 Mask
$x00C
Bit 7
OC1M7
0
6
OC1M6
0
5
OC1M5
0
4
OC1M4
0
3
OC1M3
0
2
0
0
1
0
0
Bit 0
0
0
RESET:
Bits set in OC1M allow OC1 to output the corresponding OC1D bits in port A when a successful com-
pare event occurs.
OC1M[7:3] — Output Compare Masks
0 = Control of the corresponding port A pin is disabled
1 = Control of the corresponding port A pin is enabled
Bits [2:0] — Not implemented. Reads always return zero and writes have no effect.
OC1D — Output Compare 1 Data
$x00D
Bit 7
OC1D7
0
6
OC1D6
0
5
OC1D5
0
4
OC1D4
0
3
OC1D3
0
2
0
0
1
0
0
Bit 0
0
0
RESET:
OC1D[7:3] — Output Compare Data
Data in OC1Dx is output to port A bit x on successful OC1 compares if OC1Mx is set.
Bits [2:0] — Not implemented. Reads always return zero and writes have no effect.
TCNT — Timer Count
$x00E, $x00F
$x00E
$x00F
Bit 15
Bit 7
0
14
6
13
5
12
4
11
3
10
2
9
1
0
Bit 8
High
Low
Bit 0
0
RESET:
0
0
0
0
0
The 16-bit read-only TCNT register contains the prescaled value of the 16-bit timer. A full counter read
addresses the most significant byte (MSB) first. A read of this address causes the least significant byte
to be latched into a buffer for the next CPU cycle so that a double-byte read returns the full 16-bit state
of the counter at the time of the MSB read cycle.
MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
59
TIC1–TIC3 — Timer Input Capture
$x010–$x015
$x010
$x011
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
High
Low
Bit 0
$x012
$x013
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
High
Low
$x014
$x015
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
High
Low
TICx registers are not affected by reset.
TOC1–TOC4 — Timer Output Compare
$x016–$x01D
$x016
$x017
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
High
Low
Bit 0
$x018
$x019
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
High
Low
$x01A
$x01B
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
High
Low
$x01C
$x01D
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
High
Low
All TOCx register pairs are reset to ones ($FFFF).
TI4/O5 — Timer Input Capture 4/Output Compare 5
$x01E, $x01F
$x01E
$x01F
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
High
Low
Bit 0
TI4/O5 is reset to ones ($FFFF).
TCTL1 — Timer Control 1
$x020
Bit 7
OM2
0
6
OL2
0
5
OM3
0
4
OL3
0
3
OM4
0
2
OL4
0
1
Bit 0
OL5
0
OM5
0
RESET:
OM2–OM5 — Output Mode
OL2–OL5 — Output Level
Each OMx–OLx bit pair determines the output action taken on the corresponding OCx pin after a suc-
cessful compare, as shown in Table 29. OC5 functions only if the I4/O5 bit in the PACTL register is
cleared.
MOTOROLA
60
MC68HC11F1/FC0
MC68HC11FTS/D
Table 29 Output Compare Actions
OMx
OLx
Action Taken on Successful Compare
Timer disconnected from output pin logic
Toggle OCx output line
0
0
1
1
0
1
0
1
Clear OCx output line to zero
Set OCx output line to one
TCTL2 — Timer Control 2
$x021
Bit 7
EDG4B
0
6
EDG4A
0
5
4
EDG1A
0
3
EDG2B
0
2
EDG2A
0
1
EDG3B
0
Bit 0
EDG3A
0
EDG1B
0
RESET:
EDGxB, EDGxA — Input Capture Edge Control
Each EDGxB, EDGxA pair determines the polarity of the input signal on the corresponding ICx that will
trigger an input capture, as shown in Table 30. IC4 functions only if the I4/O5 bit in the PACTL register
is set.
Table 30 Input Capture Configuration
EDGxB
EDGxA
Configuration
Capture disabled
0
0
1
1
0
1
0
1
Capture on rising edges only
Capture on falling edges only
Capture on any edge
TMSK1 — Timer Interrupt Mask 1
$x022
Bit 7
OC1I
0
6
OC2I
0
5
OC3I
0
4
OC4I
0
3
I4/O5I
0
2
IC1I
0
1
IC2I
0
Bit 0
IC3I
0
RESET:
Bits in TMSK1 correspond bit for bit with flag bits in TFLG1. Each bit that is set in TMSK1 enables the
corresponding interrupt source.
OCxI — Output Compare x Interrupt Enable
If the OCxI enable bit is set when the OCxF flag bit is set, a hardware interrupt sequence is requested.
I4/O5I — Input Capture 4/Output Compare 5 Interrupt Enable
When I4/O5 in PACTL is one, I4/O5I is the input capture 4 interrupt enable bit. When I4/O5 in PACTL
is zero, I4/O5I is the output compare 5 interrupt enable bit.
ICxI — Input Capture x Interrupt Enable
If the ICxI enable bit is set when the ICxF flag bit is set, a hardware interrupt sequence is requested.
TFLG1 — Timer Interrupt Flag 1
$x023
Bit 7
OC1F
0
6
OC2F
0
5
OC3F
0
4
OC4F
0
3
I4/O5F
0
2
IC1F
0
1
IC2F
0
Bit 0
IC3F
0
RESET:
Bits in TFLG1 are cleared by writing a one to the corresponding bit positions.
MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
61
OCxF — Output Compare x Flag
Set each time the counter matches output compare x value.
I4/O5F — Input Capture 4/Output Compare 5 Flag
Set by IC4 or OC5, depending on which function was enabled by I4/O5 of PACTL.
ICxF — Input Capture x Flag
Set each time a selected active edge is detected on the ICx input line.
TMSK2 — Timer Interrupt Mask 2
$x024
Bit 7
TOI
0
6
RTII
0
5
PAOVI
0
4
PAII
0
3
0
0
2
0
0
1
PR1
0
Bit 0
PR0
0
RESET:
Bits [7:4] in TMSK2 correspond bit for bit with flag bits in TFLG2. Setting any of these bits enables the
corresponding interrupt source. TMSK2 can be written only once in the first 64 cycles out of reset in
normal modes, or at any time in special modes.
TOI — Timer Overflow Interrupt Enable
0 = Timer overflow interrupt disabled
1 = Interrupt requested when TOF is set
RTII — Real-Time Interrupt Enable
0 = Real-time interrupt disabled
1 = Interrupt requested when RTIF is set
Bits [5:4] — See 13.2 Pulse Accumulator Registers, page 64.
Bits [3:2] — Not implemented. Reads always return zero and writes have no effect.
PR[1:0] — Timer Prescaler Select
Determines the main timer prescale factor as shown in Table 31. See Table 26 for specific frequencies.
Table 31 Main Timer Prescale Control
PR[1:0]
0 0
Prescaler
1
4
0 1
1 0
8
1 1
16
TFLG2 — Timer Interrupt Flag 2
$x025
Bit 7
TOF
0
6
RTIF
0
5
4
PAIF
0
3
0
0
2
0
0
1
0
0
Bit 0
PAOVF
0
0
0
RESET:
Bits in this register indicate when certain timer system events have occurred. Coupled with the four
high-order bits of TMSK2, the bits of TFLG2 allow the timer subsystem to operate in either a polled or
interrupt driven system. Each bit of TFLG2 corresponds to a bit in TMSK2 in the same position.
Bits in TFLG2 are cleared by writing a one to the corresponding bit positions.
TOF — Timer Overflow Flag
Set when TCNT rolls over from $FFFF to $0000.
MOTOROLA
62
MC68HC11F1/FC0
MC68HC11FTS/D
RTIF — Real-Time Interrupt Flag
Set periodically at a rate based on bits RTR[1:0] in the PACTL register.
Bits [5:4] — See 13.2 Pulse Accumulator Registers, page 65.
Bits [3:0] — Not implemented. Reads always return zero and writes have no effect.
PACTL — Pulse Accumulator Control
$x026
Bit 7
6
PAEN
0
5
PAMOD
0
4
PEDGE
0
3
0
0
2
I4/O5
0
1
RTR1
0
Bit 0
RTR0
0
0
0
RESET:
Bit 7 — Not implemented. Reads always return zero and writes have no effect.
Bits [6:4] — See 13.2 Pulse Accumulator Registers, page 65.
Bit 3 — Not implemented. Reads always return zero and writes have no effect.
I4/O5 — Configure TI4/O5 Register for IC or OC
0 = OC5 function enabled
1 = IC4 function enabled
RTR[1:0] — RTI Interrupt Rate Selects
These two bits select one of four rates for the real-time interrupt circuit, as shown in Table 32.
Table 32 Real-Time Interrupt Periods
E-Clock
RTR [1:0] = %00
RTR [1:0] = 01
RTR [1:0] = 10
RTR [1:0] = 11
Frequency
1 MHz
2 MHz
3 MHz
4 MHz
5 MHz
6 MHz
Any E
8.192 ms
4.906 ms
2.731 ms
2.048 ms
1.638 ms
16.384 ms
8.192 ms
5.461 ms
4.096 ms
3.277 ms
32.768 ms
16.384 ms
10.923 ms
8.192 ms
6.554 ms
65.536 ms
32.768 ms
21.845 ms
16.384 ms
13.107 ms
1.366 ms
2.731 ms
5.461 ms
10.923 ms
13
14
15
16
2
/E
2
/E
2
/E
2 /E
MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
63
13 Pulse Accumulator
The pulse accumulator can be used either to count events or measure the duration of a particular event.
In event counting mode, the pulse accumulator’s 8-bit counter increments each time a specified edge
is detected on the pulse accumulator input pin, PA7. The maximum clocking rate for this mode is the E-
clock divided by two. In gated time accumulation mode, an internal clock increments the 8-bit counter
at a rate of E-clock ÷ 64 while the input at PA7 remains at a predetermined logic level.
13.1 Pulse Accumulator Block Diagram
1
INTERRUPT
REQUESTS
2
TMSK2
INTERRUPT ENABLES
TFLG2
STATUS FLAGS
PAI EDGE
PAEN
E ÷ 64 CLOCK
(FROM MAIN TIMER)
OVERFLOW
CLOCK
2:1
PACNT
8-BIT COUNTER
MUX
INPUT BUFFER
&
EDGE DETECTION
PA7/
PAI/OC1
ENABLE
OUTPUT
BUFFER
PAEN
FROM
MAIN TIMER
OC1
PACTL
CONTROL
FROM
DDRA
INTERNAL
DATA BUS
Figure 18 Pulse Accumulator Block Diagram
13.2 Pulse Accumulator Registers
TMSK2 — Timer Interrupt Mask 2
$x024
Bit 7
TOI
0
6
RTII
0
5
PAOVI
0
4
PAII
0
3
0
0
2
0
0
1
PR1
0
Bit 0
PR0
0
RESET:
Bits [7:4] in TMSK2 correspond bit for bit with flag bits in TFLG2. Setting any of these bits enables the
corresponding interrupt source.
MOTOROLA
64
MC68HC11F1/FC0
MC68HC11FTS/D
Bits[7:6] — See 12.2 Timer Registers, page 62.
PAOVI — Pulse Accumulator Overflow Interrupt Enable
0 = Pulse accumulator overflow interrupt disabled
1 = Interrupt requested when PAOVF in TFLG2 is set
PAII — Pulse Accumulator Interrupt Enable
0 = Pulse accumulator interrupt disabled
1 = Interrupt requested when PAIF in TFLG2 is set
Bits [3:2] — Not implemented. Reads always return zero and writes have no effect.
Bits [1:0] — See 12.2 Timer Registers, page 62.
TFLG2 — Timer Interrupt Flag 2
$x025
Bit 7
TOF
0
6
RTIF
0
5
PAOVF
0
4
PAIF
0
3
0
0
2
0
0
1
0
0
Bit 0
0
0
RESET:
Bits in TFLG2 are cleared by writing a one to the corresponding bit positions.
Bits [7:6] — See 12.2 Timer Registers, page 62.
PAOVF — Pulse Accumulator Overflow Flag
Set when PACNT rolls over from $FF to $00
PAIF — Pulse Accumulator Input Edge Flag
Set each time a selected active edge is detected on the PAI input line
Bits [3:0] — Not implemented. Reads always return zero and writes have no effect.
PACTL — Pulse Accumulator Control
$x026
Bit 7
6
PAEN
0
5
PAMOD
0
4
PEDGE
0
3
0
0
2
I4/O5
0
1
RTR1
0
Bit 0
RTR0
0
0
0
RESET:
Bit 7 — Not implemented. Reads always return zero and writes have no effect.
PAEN — Pulse Accumulator System Enable
0 = Pulse accumulator disabled
1 = Pulse accumulator enabled
PAMOD — Pulse Accumulator Mode
0 = Event counter
1 = Gated time accumulation
PEDGE — Pulse Accumulator Edge Control
This bit has different meanings depending on the state of the PAMOD bit, as shown in Table 33.
MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
65
Table 33 Pulse Accumulator Edge Control
PAMOD
PEDGE
Action on Clock
PAI falling edge increments the counter.
PAI rising edge increments the counter.
A zero on PAI inhibits counting.
0
0
1
1
0
1
0
1
A one on PAI inhibits counting.
Bit 3 — Not implemented. Reads always return zero and writes have no effect.
Bits [2:0] — See 12.2 Timer Registers, page 63.
PACNT — Pulse Accumulator Count
$x027
Bit 7
Bit 7
U
6
6
5
5
4
4
3
3
2
2
1
1
Bit 0
Bit 0
U
RESET:
U
U
U
U
U
U
U = Unaffected by reset
This eight-bit read/write register contains the count of external input events at the PAI input, or the ac-
cumulated count. The PACNT is readable even if PAI is not active in gated time accumulation mode.
The counter is not affected by reset and can be read or written at any time. Counting is synchronized
to the internal PH2 clock so that incrementing and reading occur during opposite half cycles.
MOTOROLA
66
MC68HC11F1/FC0
MC68HC11FTS/D
MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
67
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Motorola > Semiconductors >
68HC11FC0_ARCHIVED : Microcontroller
Page Contents:
The MC68HC11FC0 is a low cost, high-speed derivative of the MC68HC11F1. It does not have EEPROM
or an analog-to-digital converter. The MC68HC11FC0 can operate at bus speeds as high as six MHz.
Features
Documentation
Tools
Orderable Parts
Related Links
68HC11FC0_ARCHIVED Features
●
●
●
●
●
MC68HC11 CPU
Other Info:
512 Bytes of On-Chip Electrically Erasable Programmable ROM (EEPROM) with Block Protect
(MC68HC11F1 only)
1024 Bytes of On-Chip RAM (All Saved During Standby)
Enhanced 16-Bit Timer System
3rd Party Tool
Vendors
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3 Input Capture (IC) Functions
4 Output Compare (OC) Functions
4th IC or 5th OC (Software Selectable)
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+
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●
On-Board Chip-Selects with Clock Stretching
Real-Time Interrupt Circuit
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68HC11FC0_ARCHIVED Documentation
Documentation
Application Note
Size Rev Date Last
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ID
Name
Vendor ID Format
K
#
Modified Availability
MC68HC11 EEPROM Programming from a Personal
Computer
MOTOROLA
pdf
AN1010/D
AN1050_D
AN1058/D
AN1060/D
AN1060SW
AN1064/D
AN1067/D
AN1220_D
AN1259/D
AN1263/D
291
1
5/20/2002
Designing for Electromagnetic Compatibility (EMC) with
HCMOS Microcontrollers
MOTOROLA
pdf
82
0
0
1
0
0
1
0
0
0
1/01/2000
2/01/2001
1/01/1999
1/01/1995
1/11/2001
5/31/2002
1/01/1996
1/01/1995
1/01/1995
-
-
-
MOTOROLA
pdf
Reducing A/D Errors in Microcontroller Applications
M68HC11 Bootstrap Mode
245
289
176
522
242
317
78
MOTOROLA
pdf
MOTOROLA
zip
Software Files for AN1060 zipped
MOTOROLA
pdf
Use of Stack Simplifies M68HC11 Programming
Pulse Generation and Detection with Microcontroller Units
Optical Character Recognition Using Fuzzy Logic
MOTOROLA
pdf
MOTOROLA
pdf
System Design and Layout Techniques for Noise
Reduction in MCU-Based Systems
MOTOROLA
pdf
Designing for Electromagnetic Compatibility with Single-
Chip Microcontrollers
MOTOROLA
pdf
104
Noise Reduction Techniques for Microcontroller-Based
Systems
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
AN1705/D
AN1706/D
AN1744/D
AN1752/D
AN1771/D
AN1775/D
AN1783/D
AN2103/D
AN2321/D
AN427/D
AN432/D
AN461/D
AN494/D
AN495/D
AN974/D
AN997/D
ANE415/D
pdf
pdf
pdf
pdf
pdf
pdf
pdf
pdf
pdf
pdf
pdf
pdf
pdf
pdf
pdf
pdf
pdf
67
103
80
0
0
0
1
0
1
1
0
0
0
0
0
1
0
0
0
0
1/01/1999
1/01/1997
1/01/1998
5/07/2001
1/01/1998
1/01/1998
Microcontroller Oscillator Circuit Design Considerations
Resetting Microcontrollers During Power Transitions
Data Structures for 8-Bit Microcontrollers
213
250
86
Precision Sine-Wave Tone Synthesis Using 8-Bit MCUs
Expanding Digital Input with an A/D Converter
Determining MCU Oscillator Start-Up Parameters
Local Interconnect Network (LIN) Demonstration
Designing for Board Level Electromagnetic Compatibility
MC68HC11 EEPROM Error Correction Algorithms in C
128K Byte Addressing with the M68HC11
48
1/01/1999
12/01/2000
953
1628
8/15/2002
1/01/2000
1/11/2001
1/01/2000
147
435
An Introduction to the HC16 for HC11 Users
An HC11-Controlled Multiband RDS Radio
667
1052
2/23/2001
3840
299
10/01/1994
RDS decoding for an HC11-controlled
MC68HC11 Floating-Point Package
1/01/2000
1/01/2000
1/01/1988
CONFIG Register Issues Concerning the M68HC11 Family MOTOROLA
53
MC68HC11 Implementation of IEEE-488 Interface for
DSP56000 Monitor
MOTOROLA
1619
Brochure
ID
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#
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FLYREMBEDFLASH/D
Embedded Flash: Changing the Technology World for MOTOROLA
the Better
5/21/2003
pdf
68
2
Data Sheets
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#
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MC68HC11FTS/D
MOTOROLA
pdf
486
MC68HC11F1 8-Bit Microcontroller Technical Summary
0
1/01/1997
Engineering Bulletin
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ID
Name
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K
#
Modified Availability
How the Romon Bit Behaves on the E Series HC11 MCUs MOTOROLA
1/01/1998
EB182/D
EB184/D
EB185/D
EB187/D
EB188/D
EB189/D
EB191/D
EB192/D
EB193/D
EB195/D
EB197/D
EB198/D
EB254/D
EB284/D
EB285/D
EB287/D
EB289/D
EB291/D
EB292/D
EB293/D
EB294/D
EB295/D
EB296/D
EB298/D
EB299/D
EB301/D
pdf
pdf
pdf
pdf
pdf
pdf
pdf
pdf
pdf
pdf
pdf
pdf
pdf
pdf
pdf
pdf
pdf
pdf
pdf
pdf
pdf
pdf
pdf
pdf
pdf
pdf
28
0
Enabling the Security Feature on the MC68HC711E9
Devices with Pcbug11 on the M68HC711E9PGMR
MOTOROLA
MOTOROLA
1/01/1998
1/01/1998
1/01/1998
1/01/1998
1/01/1998
1/01/1999
1/14/2003
1/01/1999
1/01/1999
1/01/1999
1/01/1998
1/01/1998
1/01/1998
1/01/1998
1/01/1999
1/01/1998
1/01/1998
1/01/1998
1/01/1998
1/01/1999
1/01/1998
1/01/1998
1/01/1999
1/01/1998
1/01/1999
30
29
34
29
36
26
101
96
25
15
57
20
23
23
25
26
37
22
30
46
26
28
22
19
24
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Simplify MC68HC711E9PROM Programming with
Pcbug11 and the M68HC711EPGMR Board
Programming MC68HC711E9 Devices with Pcbug11 and MOTOROLA
the M68HC711EVB
Enabling the Security Feature on M68HC811E2 Devices
with PCbug11 on the M68HC711E9PGMR
MOTOROLA
Programming MC68HC811E2 Devices with Pcbug11 and MOTOROLA
the M68HC711E9PGMR
Programming EPROM and EEPROM on the
M68HC11EVM
MOTOROLA
A Quick PWM Tutorial for MC68HC11 K, KA, KW, P and
PH Series Controllers
MOTOROLA
Replacing 68HC11A Series MCUs with 68HC11E Series MOTOROLA
MCUs
MOTOROLA
How to Configure the Reset Pin on the MC68HC11
MOTOROLA
Using Pseudo-Interrupt Vectors on the M68HC11EVBU
Turn Off Your E Clock to Reduce Noise Emission on the
MC68HC11
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
Setting the Programming Voltage on Modular
Microcontrollers with FLASH EEPROM
C Macro Definitions for the MC68HC(7)11D3/D0
C Macro Definitions for the MC68HC(7)11E20
C Macro Definitions for the MC68HC(7)11E9/E8/E1/E0
C Macro Definitions for the MC68HC11F1
Programming MC68HC811E2 Devices with Pcbug11 and MOTOROLA
the M68HC11EVBU
Initialization Considerations When Moving from the
BUFFALO Monitor to a Standalone MC68HC11
MOTOROLA
Simplify MC68HC711E20 EPROM Programming with
Pcbug11
MOTOROLA
How to Write to the 64-Cycle Time-Protected Registers on MOTOROLA
M68HC11 Development Tools
Programming the EEPROM on the MC68HC811E2 with
the M68HC11EVM Board
MOTOROLA
Programming MC68HC711E9 Devices with Pcbug11 and MOTOROLA
the M68HC11EVBU
Programming the BUFFALO Monitor into an
MC68HC711E9
MOTOROLA
Why M68HC711D3PGMR Software Does Not Run on 486 MOTOROLA
33-MHz Computers
Programming EEPROM on the MC68HC811E2 during
Program Execution
MOTOROLA
Handling Considerations for Avoiding Intermittent
Programming and Execution Failures with MC68HC11-
Windowed EPROM Devices
MOTOROLA
1/01/1998
EB303/D
pdf
33
0
Replacing 68HC11KA4/KA2 MCUs with 68HC11KS2/KS8 MOTOROLA
MCUs
1/01/1999
6/22/2000
1/31/2001
3/02/2001
5/10/2001
6/19/2002
1/01/2000
1/01/2000
EB312/D
EB349/D
EB378/D
EB380/D
EB381/D
EB396/D
EB413/D
EB422/D
pdf
pdf
pdf
pdf
pdf
pdf
pdf
pdf
69
45
0
1
0
0
0
0
0
0
RAM Data Retention Considerations for Motorola
Microcontrollers
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
CONFIG Register Programming for EEPROM-Based
M68HC11 Microcontrollers
114
104
137
49
Migrating from the MC68HC811E2 to the MC68HC711E9
Migrating from the MC68HC811E2 to the MC68HC11F1
Use of OSC2/XTAL as a Clock Output on Motorola
Microcontrollers
Resetting MCUs
62
1377
Enhanced M68HC11 Bootstrap Mode
Product Change Notices
Size Rev Date Last
Order
Availability
ID
Name
Vendor ID Format
K
#
Modified
PCN7796
14X14 LQFP ASSY MOVE FROM SHC TO KLM MOTOROLA htm
20
0
8/01/2002
-
Reference Manual
ID
Size Rev Date Last
Order
Name
Vendor ID Format
K
#
Modified Availability
1238
M68HC11ERG
M68HC11E Programming Reference Guide
M68HC11 Reference Manual
MOTOROLA
MOTOROLA
pdf
pdf
pdf
pdf
2
10/31/2003
6400
4697
4765
M68HC11RM/D
6
0
2
4/09/2002
6/01/1990
4/01/1992
MC68HC11D3RG/AD
MC68HC11F1RG/AD
MC68HC11D3 Programming Reference Guide MOTOROLA
MC68HC11F1 Programming Reference Guide MOTOROLA
Selector Guide
Size Rev Date Last
Order
ID
Name
Microcontrollers Selector Guide - Quarter 4, 2003
Vendor ID Format
K
#
Modified Availability
MOTOROLA
pdf
826
10/24/2003
SG1006
SG1011
0
Software and Development Tools Selector Guide - Quarter MOTOROLA
4, 2003
287
10/24/2003
pdf
0
Supporting Information
Size Rev Date Last
Order
Availability
ID
Name
Vendor ID Format
doc
K
#
Modified
ASEMBNEWASM
DOS based freeware assembler documentation MOTOROLA
10
-
-
-
Return to Top
68HC11FC0_ARCHIVED Tools
Software
Application Software
Code Examples
ID
Name
Vendor ID Format Size K Rev # Order Availability
Software Files for AN1010 zipped
Software files for AN1010
AN1010SW
MOTOROLA
zip
113
0
-
B2D04COD
Binary to BCD routine
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
asm
asm
zip
1
0
-
-
-
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
D2B04COD
BCD to Binary routine
DIV48COD
24-Bit Multiply and 48-Bit Divide routines
Examples from HC11 Reference Manual
FFT routine for HC11
4
EXAMPLESCOD
FFTHC11COD
FLOAT11COD
FP11COD
zip
14
12
6
asm
zip
Floating Point routines
Floating Point routines
asm
asm
zip
11
9
GMATHCOD
HC11FP11COD
MUL16C11COD
SOUNDFXCOD
General Math routines
Floating Point routines
19
1
16 x 16 Multiply routine
asm
zip
Sound Effects example
3
Operating Systems
ID
Name
Microcontroller Executive
Vendor ID
MOTOROLA
Format Size K Rev #
arc 92
Order Availability
MCX11V15RTOS
-
-
Software Tools
Assemblers
Size Rev
Order
Availability
ID
Name
Vendor ID Format
K
18
19
57
-
#
68HC11AS11ASM
AS11NEWASM
BASIC11COD
AX6811
DOS based freeware assembler
DOS based freeware assembler
Old source code for BASIC11
MOTOROLA
MOTOROLA
MOTOROLA
COSMIC
exe
exe
zip
-
-
-
-
-
-
-
-
-
AX6811 relocatable and absolute macro assembler for HC11
Compilers
ID
Name
Vendor ID
Format Size K Rev # Order Availability
CWHC11
CX6811
METROWERKS
COSMIC
CodeWarrior Development Tools for HC11
CX6811 C Cross Compiler for HC11
-
-
-
-
-
-
-
Debuggers
ID
Name
Vendor ID
MOTOROLA
MOTOROLA
MOTOROLA
Format Size K Rev # Order Availability
PCBUG11EXEDBG
Bootstrap Mode Programmer & Debugger
Bootstrap Mode Programmer & Debugger
Bootstrap Mode Programmer & Debugger
exe
exe
zip
167
138
107
-
-
-
-
-
-
PCBUG342DBG
PCBUGBDBG
CWHC11
METROWERKS
COSMIC
CodeWarrior Development Tools for HC11
ZAP 6811 Simulator Debugger
-
-
-
-
-
-
ZAP 6811 SIM
-
IDE (Integrated Development Environment)
Order
Availability
ID
Name
Vendor ID
Format Size K Rev #
CWHC11
IDEA11
METROWERKS
CodeWarrior Development Tools for HC11
-
-
-
-
-
-
COSMIC
IDEA11 integrated development environment for HC11
-
Return to Top
Orderable Parts Information
Order
Budgetary
Price
QTY 1000+
($US)
Tape
and
Reel
Life Cycle Description
(code)
PartNumber
Package Info
Additional Info
Availability
REMOVED FROM
ACTIVE
PORTFOLIO(8)
more
more
KMC11FC0CPU4
No
No
-
-
-
-
LQFP 80
14*14*1.4P0.65
PRODUCT LAST
SHIPMENTS(7)
MC68HC11FC0CPU4
NOTE: Are you looking for an obsolete orderable part? Click HERE to check our distributors' inventory.
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Related Links
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Microcontrollers
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