KMC68MH360CAI25L [NXP]

4 CHANNEL(S), 10Mbps, LOCAL AREA NETWORK CONTROLLER, PQFP240, PLASTIC, QFP-240;


型号：	KMC68MH360CAI25L
厂家：	NXP
描述：	4 CHANNEL(S), 10Mbps, LOCAL AREA NETWORK CONTROLLER, PQFP240, PLASTIC, QFP-240 通信时钟局域网数据传输外围集成电路
文件：	总32页 (文件大小：562K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Freescale Semiconductor, Inc.

Order this document by MC68160A/D

The MC68160A Enhanced Ethernet Interface Circuit is a BiCMOS device

which supports both IEEE 802.3 Access Unit Interface (AUI) and 10BASE–T

Twisted Pair (TP) Interface media connections through external isolation

transformers. It encodes NRZ data to Manchester data and supplies the

signals which are required for data communication via 10BASE–T or AUI

interfaces. The MC68160A gluelessly interface to the Ethernet controller

contained in the MC68360 Quad Integrated Communications Controller

(QUICC) device. The MC68160A also interfaces easily to most other

industry–standard IEEE 802.3 LAN controllers. Prior to twisted pair data

reception, Smart Squelch circuitry qualifies input signals for correct

amplitude, pulse width, and sequence requirements.

ENHANCED ETHERNET

INTERFACE TRANSCEIVER

SEMICONDUCTOR

TECHNICAL DATA

• Automatic Twisted Pair Wiring Polarity Fault Detection and Correction

Option

• Automatic Port Selection Option with Status Output

• Driver Pre–emphasis for Twisted Pair Output Data

• Crystal Controlled Clock Oscillator or External Clock Generator Option

• Digital Phase–Locked–Loop (DPLL) Timing Recovery and Data Decoding

• Standby Mode with Reduced Power Consumption

• Twisted Pair Signal Quality Error (Heartbeat) Test Option

• Diagnostic Local Loop Back Option

FB SUFFIX

PLASTIC PACKAGE

CASE 848D

(LQFP–52)

• Transmit, Receive and Collision Detection Status Output

• Full–Duplex Operation Option on Twisted Pair Port

• Twisted Pair Jabber Detection and Status Output

• Link Integrity Testing and Status Output

ORDERING INFORMATION

Operating

Temperature Range

Device

Package

MC68160AFB

= 0° to + 70°C

LQFP

The sale and use of this product is licensed under technology covered by one

or more Digital Equipment Corporation patents.

Rev 1

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MC68160A

Figure 1. 10Base–T Interface Block Diagram

RCLK

Manchester

Decoder

Data

Receiver

Mux

ARX+

ARX–

MFILT

Noise

Reject

Filter

Pulse Conditioner

RXLED

RENA

CLLED

Carrier

Detect

Mux

Noise

Reject

Filter

Collision

Detect

ACX+

ACX–

CLSN

Mux

Pulse

Conditioner

TXLED

ATX–

TENA

Manchester

Encoder

ATX+

Mux

20 MHz

Osc

Receiver

Mux

Twisted

Pair

TCLK

Polarity

Error

Control

Collision

Detector

Control

÷2

CS0

CS1

CS2

TPEN

APORT

TPAPCE

TPSQEL

TPFULDL

Driver

Pre–emphasis

Control

Link

Pulse

Control

Jabber

Control

Receiver

Squelch

Test

Circuit

Mode

Select

LOOP

TPJABB TPTX+ TPTX–

TPLIL

TPSQEL

TPRX–

TPRX+ TPPLR

This device contains 20,000 active transistors.

ANALOG IC DEVICE DATA

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Freescale Semiconductor, Inc.

MC68160A

Enhanced Ethernet Serial Transceiver

Table 1. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Controller Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

AUI Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Twisted Pair Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Oscillator and Frequency Multiplier Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Mode Select Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Status Indicator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Power Supply and Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 2. Controller Interface Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 3. Controller Independent Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Power Supply DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

TTL/CMOS Input and Output DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Twisted Pair Input and Output DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

AUI Input and Output DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

External Clock Input (X1) Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Receive Phase Locked Loop Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Controller Transmit Switching Characteristics (Motorola Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Controller Receive Switching Characteristics (Motorola Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Controller Transmit Switching Characteristics (Intel Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Controller Receive Switching Characteristics (Intel Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Controller Transmit Switching Characteristics (Fujitsu Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Controller Receive Switching Characteristics (Fujitsu Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Controller Transmit Switching Characteristics (National Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Controller Receive Switching Characteristics (National Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

TP Transmit Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

TP Transmit Jabber Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

TP Transmit Signal Quality Error Test Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

TP Receive Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

TP Receive Link Integrity Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

TP Collision Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

TP Full Duplex Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

AUI Transmit Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

AUI Receive Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Data Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Collision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Jabber . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Full Duplex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Auto Port Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Auto Polarity Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Loop Back Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Selection of Crystal and External Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

PLL Filter Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

10BASE–T Filter and Transformer Choice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

AUI Transformer Choice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

ANALOG IC DEVICE DATA

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MC68160A

Table 1. Pin Function Descriptiont

Pin(s)

Symbol

Type

Name/Function

CONTROLLER INTERFACE

RENA

Receive Enable Output: Indication of the presence of network activity, synchronous to

TTL/CMO

RCLK. In the standby mode, RENA is driven to the high impedance state.

Receive Data Output: Recovered data, synchronous to RCLK. Following a reset operation,

TTL/CMOS 100 ms should be allowed before attempting to read data processed by the MC68160A, B

and C. This delay is needed to insure that the receive phase locked loop is properly

synchronized with incoming data. In the standby mode, RX is driven to the high impedance

state.

TCLK

TENA

Transmit Clock Output CMOS/TTL Output: TCLK provides a symmetrical clock signal at

TTL/CMOS 10 MHz for reference timing of data to be encoded. In the standby mode, TCLK is driven to

the high impedance state.

Transmit Enable Input: Input signal synchronous to TCLK which enables data transmission

on the active port. An internal pull–down resistor is provided so that the input is low under no

connect conditions. (This resistor is removed in the standby mode). If TENA is asserted at

the conclusion of a reset operation, it must first be deasserted and then reasserted before

data transmission can occur. In the standby mode, TENA is driven to the high impedance

state.

TTL

RCLK

CLSN

Receive Clock Output: Recovered clock. In the standby mode, RCLK is driven to the high

TTL/CMOS impedance state.

Collision Output: In the AUI mode, indicates the presence of signals at the ACX+ and

TTL/CMOS ACX– terminals which meet threshold and pulse width requirements. In the TP mode,

indicates simultaneous transmit and receive activity, a heartbeat (SQE Test) signal was

generated, or the jabber timer has expired. In the standby mode, CLSN is driven to the high

impedance state.

Transmit Data Input: Input signal synchronous to TCLK which provides NRZ serial data to

TTL

be Manchester encoded. In the standby mode, TX is driven to the high impedance state.

AUI INTERFACE

ACX–

ACX+

AUI Differential Collision Inputs: These inputs are connected to a pair of internally biased

line receivers consisting of a carrier detect receiver with offset threshold and noise filtering to

detect the line activity. Signals at ACX+/– have no effect on data path functions.

ARX–

ARX+

AUI Differential Receiver Inputs: These inputs are connected to a pair of internally biased

line receivers consisting of a carrier detect receiver with offset threshold and noise filtering to

detect the line activity, and a data receiver with no offset for Manchester Data reception.

ATX–

ATX+

AUI Differential Transmit Outputs : This line pair is intended to operate into terminated

transmission lines. For TX signals meeting setup and hold time to TCLK when TENA is

previously asserted, Manchester encoded data is outputted at ATX+/–. When operating into a

78 Ω terminated transmission line, signaling meets the required output levels and skew for

IEEE–802.3 drop cables. When the 10BASE–T port is automatically or manually selected,

the AUI outputs are driven to a low power standby state in which the outputs deliver a

balanced high state voltage.

TWISTED PAIR INTERFACE

TPRX–

TPRX+

Twisted Pair Differential Receiver Inputs: These inputs are connected to a receiver with

Smart Squelch capability which only allows differential receive data to pass as long as the

input amplitude is greater than a minimum signal threshold level and a specific pulse

sequence is received. This assures a good signal to noise ratio while the signal pair is active

by preventing crosstalk and impulse noise conditions from activating the receive function.

TPTX–

TPTX+

Twisted Pair Differential Transmitter Outputs: These lines have pre–distortion drive

capability and are intended to drive terminated twisted pair transmission lines. When the AUI

port is manually selected, the 10BASE–T outputs are driven to a low power standby state in

which the outputs deliver a balanced high state voltage. However, when the AUI port is

automatically selected, the 10BASE–T outputs remain active.

NOTE: The sense of the controller interface pins will change, depending on the controller selected.

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MC68160A

Table 1. Pin Function Description (continued)

Pin(s)

Symbol

Type

Name/Function

OSCILLATOR AND FREQUENCY MULTIPLIER

MFILT

Frequency Multiplier Filter Connection Point: An external resistor capacitor filter must be

attached to this pin.

I/C

CMOS

Oscillator Inverter Input and Crystal Connection Point: When connected for crystal

oscillator operation, the frequency of the clock which appears at TCLK is half that of the

crystal oscillator. As an option, instead of connecting to a crystal, X1 may be driven from an

external 20 MHz CMOS compatible clock generator.

O/C

CMOS

Oscillator Inverter Output and Crystal Connection Point: This pin is used only for the

connection of an external crystal and capacitor. It must be left unconnected if X1 is driven by

an external CMOS Clock generator.

MODE SELECT

CS0

CS1

CS2

Mode Select: The logic states applied to these pins select the appropriate interface for the

desired IEEE–802.3 controller or enable the standby mode. When the standby mode is

selected, the MC68160A power supply current is greatly reduced. Additionally, in the standby

mode, all of the controller inputs and outputs are driven to the high impedance state.

TTL

LOOP

Diagnostic Loopback: Asserting this function causes serial NRZ data at the TX input to be

Manchester encoded and then looped back through the Manchester decoder, appearing at

the RX output. This diagnostic loopback function operates independent of Twisted Pair (TP)

or Access Unit Interface (AUI) port connectivity or activity. Neither the TP port nor the AUI

port transmits data from the controller while diagnostic loopback is selected. Likewise, the

controller interface receives data neither from the TP nor the AUI receivers while in this

mode. The polarity fault detection and link integrity functions are not inhibited by the

diagnostic loopback mode. If otherwise enabled, they continue to function. If the twisted pair

port is selected, and TPSQEL is driven to the low logic state, a collision detect pulse is

delivered following each transmission to simulate the twisted pair SQE test.

TTL

APORT

Automatic Port Selection Enable: When high, MC68160A will automatically select the TP

or AUI port based on the presence or absence of valid link beats or frames at the TP receive

input. If the AUI port is automatically selected, the MC68160A will continue to produce link

pulses for the TP port. Changing ports requires approximately 1.0 ms to allow the circuitry for

the new port to resume normal operation. The power consumption is minimized in the

circuitry associated with the unselected port.

TTL

TPSQEL

Twisted Pair Signal Quality Error Test Enable: Forcing this pin low enables testing of the

internal TP collision detect circuitry after each transmit operation to the TP media. This

function provides a simulated collision to as much of the MC68160A collision detect circuitry

as possible without affecting the attached twisted pair channel. A normal SQE test results in

a high logic state at the CLSN controller interface pin which begins 6 to 16–bit times after the

last transition of a transmitted signal and continues for 5 to 15–bit times. (When the AUI port

is selected, SQE test signals are generated by the coaxial cable transceiver and delivered to

the controller via the MC68160A ACX+/– receive inputs)

TTL

TPFULDL

TPAPCE

Twisted Pair Full Duplex Mode Select: Forcing this pin low allows simultaneous transmit

and receive operation on the twisted pair port without an indicated collision. This pin is not to

be asserted with LOOP as a test mode is enabled that disrupts normal operation.

TTL

Twisted Pair Automatic Polarity Correction Enable: When TPAPCE is high, automatic

polarity correction is enabled, and MC68160A will internally correct for a polarity fault on the

receive circuit. Additionally, when TPAPCE is high, the presence of a polarity fault is

indicated on TPPLR.

TTL

TPEN

I/O

Twisted Pair Port Enable: If APORT is low, TPEN is an input which determines whether the

TTL

AUI port (TPEN low) or TP port (TPEN high) will be manually selected. If the AUI port is

(TTL/CMOS) manually selected, the MC68160A will not produce link pulses for the TP port.

If APORT is high, TPEN is an output which will indicate which port has been automatically

selected by driving TPEN low (for AUI) or high (for TP). In its output mode TPEN can sink

10 mA in the low output state and source 10 mA in the high output state. (See Pin 9

Description.)

Changing ports requires approximately 1.0 ms to allow the circuitry for the new port to

resume normal operation. The power consumption is minimized in the circuitry associated

with the unselected port. In the standby mode, this pin is driven to the high impedance state.

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MC68160A

Table 1. Pin Function Description (continued)

Pin(s)

Symbol

Type

Name/Function

STATUS INDICATOR

TXLED

RXLED

CLLED

Transmit Status LED Driver Output: This pin indicates the transmit status of the currently

TTL/CMOS selected TP or AUI port. When there is no transmit activity detected, an internal pull–up takes

this pin to its normal off (high) state. When transmit activity is detected, the LED driver turns

on. In its on state, TXLED flashes the LED by driving low at approximately 10 Hz at a 50%

duty cycle. In the standby mode, this output is driven to the high impedance state.

Receive Status LED Driver Output: This pin indicates the receive status of the currently

TTL/CMOS selected TP or AUI port. When there is no receive activity detected, an internal pull–up takes

this pin to its normal off (high) state. When receive activity is detected, the LED driver turns

on. In its on state, RXLED flashes the LED by driving low at approximately 10 Hz at a 50%

duty cycle. In the standby mode, this output is driven to the high impedance state.

Collision Status LED Driver Output: This pin indicates the collision status of the currently

TTL/CMOS selected TP or AUI port. When there is no collision activity detected, an internal pull–up takes

this pin to its normal off (high) state. When collision activity is detected, the LED driver turns

on. In its on state, CLLED flashes the LED by driving low at approximately 10 Hz at a 50%

duty cycle. In the standby mode, this output is driven to the high impedance state.

TPLIL

Twisted Pair Link Integrity Output: This output is driven to the low output state to indicate

TTL/CMOS good link integrity on the TP port during TP mode. It is deasserted (high) when link integrity

fails in TP mode. The TPLIL output is driven to the high impedance state when the AUI port

is selected. In the standby mode, this output is also driven to the high impedance state.

TPPLR

Twisted Pair Polarity Error Output: If TPAPCE is high and the wires connected to the

TTL/CMOS Twisted Pair Receiver Inputs (TPRX+, TPRX–) are reversed, TPPLR will be driven to the low

logic state to indicate the fault. TPPLR remains low when the MC68160A, AB and AC has

automatically corrected for the reversed wires. If the twisted pair link integrity tests fail, this

output will be driven to the high logic state. When the AUI mode is selected this output is

driven to the high impedance state. In the standby mode, this output is also driven to the high

impedance state.

TPJABB

Twisted Pair Jabber Output: This pin is driven high to indicate a jabber condition at the

TTL/CMOS TPTX+/– outputs. (Jabber condition also causes CLLED to be driven alternately to the high

and low output levels). TPJABB is driven to the low output state when no jabber condition is

present. When the AUI mode is selected this output is driven to the high impedance state. In

the standby mode, this output is also driven to the high impedance state.

POWER SUPPLY AND GROUND

VDDDIV

Frequency Divider Supply Pin

VDDFM

GNDFM

Frequency Multiplier Supply and Ground Pins

GNDVCO

VDDVCO

Voltage Controlled Oscillator Ground and Supply Pins

GNDSUB

Substrate Ground Pin

VDDDIG

GNDDIG

VDDDIG

GNDDIG

Digital Supply and Ground Pins

VDDANA

GNDANA

Analog Supply and Ground Pins

Power Supply and Ground Pins

GNDPWR

VDDPWR

GNDPWR

GNDCTL

Controller Interface Ground Pin

NOTE: Power and ground pins are not connected internally. Failure to connect externally may cause malfunction or damage to the IC.

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Table 2. Controller Interface Selection

National

Motorola

Transceiver

MC68160A

Motorola

Controller

MC68360

Intel

Fujitsu

Controllers

82586, 82590,

82593, 82596

Controllers

86950 (Etherstar )

86960 (NICE

Controllers

8390, 83C690,

83932B (SONIC )

(EEST

)

(QUICC

)

CS0

CS1

CS2

TCLK

Sense

High

Sense

Low

High

Low

High

Low

TCKN

TXD

Sense

Low

TXC

TXD

TXE

RXC

RXD

CRS

COL

LPBK

Sense

High

TCLK

TXC

TXD

RTS

RXC

RXD

CRS

CDT

LPBK

High

Low

TENA

RCLK

TENA

RCLK

TEN

RCN

RXD

XCD

XCOL

LBC

High

Low

RENA

CLSN

RENA

CLSN

N.A.

LOOP

High

NOTES: 1. Although LOOP input is not ordinarily classifed as a controller pin, it is included in this table because its sense varies according to the controller used.

2. The Motorola controller interface contained in the MC68360 (QUICC ) is compatible with the AMD 7990 (LANCE ) and 79C900 (ILACC ) controllers.

3. The pin sense is shown from the perspective of the identified controller pin.

4. Supported only by MC68160A.

Table 3. Controller Independent Mode Selection

Standby Mode

Reserved

CS0

CS1

CS2

NOTE: In standby mode, the MC68160A consumes less power supply current than in any other

mode. Additionally, in the standby mode, all of the controller inputs and outputs are

driven to the high impedance state. When the standby mode is deasserted, an internal

reset pulse of approximately 6.0 µs duration is generated.

Following a period of operation in the standby mode, the time required to insure stable

data reception is approximately 100 ms.

Figure 2. Applications Block Diagram

ATX+

ATX–

ARX+

ARX–

ACX+

ACX–

ATX+

ATX–

ARX+

ARX–

ACX+

ACX–

TCLK

Pulse

Transformers

DB–15

Connector

TENA

RCLK

LAN

Controller

MC68160A

RENA

CLSN

TPTX+

TPTX–

TPRX+

TPRX–

TPTX+

TPTX–

TPRX+

TPRX–

Filters

and

Pulse

RJ–45

Connector

Transformers

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ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

Characteristic

Symbol

Min

Max

Unit

Storage Temperature Range

stg

–65

150

°C

Power Supply Voltage Range

Analog

Digital

–

7.0

DDA

DDD

Voltage on any TTL compatible input pin with

respect to Ground

Voltage on TPRX, ARX, or ACX input pins with

respect to Ground

–0.5

+ 0.5

6.0

Differential Voltage on TPRX, ARX, or ACX Input

Pins

DIFF

–6.0

NOTE: Stresses in excess of the Absolute Maximum Ratings can cause permanent damage to the

device. Functional operation of the device is not implied at these or any other conditions in

excess of those indicated in the operation sections of this data sheet. Exposure to Absolute

Maximum Ratings conditions for extended periods can adversely affect device reliability.

RECOMMENDED OPERATING CONDITIONS

Characteristic

Symbol

Min

4.75

–

Max

5.25

Unit

Power Supply Voltage Range

Power Supply Ripple (20 kHz to 100 kHz)

Power Supply Impulse Noise (Either Polarity)

Ambient Operating Temperature Range

ARX/ACX Input Differential Rise and Fall Time (see Figure 39)

ARX Pair Idle Time after Transmission (see Figure 39)

–

°C

–

100

2.0

8.0

260

265

–

µs

ESD

Althoughprotection circuitry has been designed into this device, proper precautions should be taken to avoid exposure to electrostatic discharge

(ESD)duringhandlingandmounting. MotorolaemploysaHumanBodyModel(HBM)andaChargedDeviceModel(CDM)forESD–susceptibility

testing and protection design evaluation. ESD has been adopted for the CDM, however, a standard HBM (resistance = 1500 Ω capacitance –

100 pF) is widely used and, therefore, can be used for comparison purposes. The HBM ESD threshold presented here was obtained by using

the circuit parameters contained in this specification. ESD threshold voltage is designed to 700 V Human Body Model.

DC ELECTRICAL CHARACTERISTICS (Unless otherwise noted, minimum and maximum limits apply over the recommended

ambient operating temperature and power supply voltage ranges.)

Characteristic

POWER SUPPLY

Symbol

Test Conditions

Min

Typ

Max

Unit

Undervoltage Shutdown Threshold

Power Supply Current

–

4.4

–

145

–

200

5.0

Standby Mode

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DC ELECTRICAL CHARACTERISTICS (T = 25°C, V

= 5.0 V ± 5%. Unless otherwise noted, minimum and maximum

limits apply over the recommended ambient operating temperature and power supply voltage ranges for each MC68160A except where noted.)

Characteristic

TTL COMPATIBLE INPUTS

Symbol

Test Conditions

Min

Max

Unit

TTL Compatible Input Voltage

Low State

–

(TTL)

–

2.0

0.8

–

High State

Input Current TTL Compatible Input Pins (Note 1)

Input Current TENA TTL Compatible Input Pin:

with Pull–Down Resistor

0 V < V < V

–

±10

µA

–

+200

–20

±10

& I

with Pull–Down Resistor removed in Standby Mode

IH IL

CMOS COMPATIBLE INPUTS

CMOS Compatible Input Voltage

Low State

–

(CMOS)

–

3.0

1.0

–

High State

Input Current (Pin X1)

I & I

IH IL

0 V < V < V

–

±100

µA

TTL/CMOS COMPATIBLE OUTPUTS

TTL/CMOS Compatible Output Voltage

Low State (Note 2)

= 4.0 mA

= 10 mA

–

0.45

Low State (Note 3)

TTL/CMOS Compatible Output Voltage

High State (Note 4)

= –500 µA

= –10 mA

= –4.0 mA

3.9

2.4

–

High State (Note 5)

High State (Note 2)

Three State Output Leakage Current

0 V ≤ V

≤ V

–

±10

µA

Characteristic

Symbol

Test Conditions

Min

Max

Unit

TWISTED PAIR RECEIVER INPUTS

Input Voltage Range (DC + AC)

–

Note 10

Note 9

–

1.5

270

1.8

4.3

390

3.2

–

ITP

Differential Input Squelch Threshold Voltage

Common Mode Bias Generator Voltage

Common Mode Input Resistance

Differential Input Resistance

ITPSQ

BCMTP

1000

2.5

Ω

CMTP

–

kΩ

DIFFTP

TWISTED PAIR TRANSMITTER OUTPUTS

Differential Output Voltage

Pre–Emphasis Level

Signal Level

Note 7

±2.2

±1.56

±2.8

±1.98

ODFTPP

ODFTPS

Common Mode Output Voltage Range

Note 6

4.0

OCMTP

Common Mode Output Voltage in Standby Mode

= –100 µA

– 1.0

OCMTPSB

NOTES: 1. APORT, TPAPCE, CS0, CS1, CS2, TX, LOOP, TPFULDL, TPSQEL and TPEN (In Input Mode).

2. TCLK, RX, RCLK, RENA and CLSN.

3. TPPLR, TPLIL, TPJABB, TXLED, RXLED, CLLED and TPEN (In Output Mode).

4. TPPLR, TPLIL, CLLED, TXLED and RXLED.

5. TPJABB and TPEN (In Output Mode).

6. Measured with Test Load B1 (shown in Figure 3), applied directly to the TPTX+/– pins of the device.

7. Measured differentially with Test Load B2 (shown in Figure 4), applied directly to the TPTX+/– pins of the device.

8. Measured directly on the TPTX+/– pins of the device.

9. Measured with Test Load B3 (shown in Figure 5), applied directly to the TPRX+/– pins of the device.

10. The Common Mode Input Voltage is between 1.8 V and 3.2 V.

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DC ELECTRICAL CHARACTERISTICS (continued) (T = 25°C, V

= 5.0 V ± 5%. Unless otherwise noted, minimum and maximum

limits apply over the recommended ambient operating temperature and power supply voltage ranges for each MC68160A except where noted.)

Characteristic

Symbol

Test Conditions

Min

Max

Unit

TWISTED PAIR TRANSMITTER OUTPUTS

Differential Output Voltage

IDLE Mode

Open Circuit

Note 6

Note 8

–

±50

5.25

ODFTPI

ODFTPO

Differential Output Impedance

TRANSMISSION Mode

IDLE Mode

Note 8

Ω

8.0

ODFTPT

ODFTPI

Common Mode Output Impedance

TRANSMISSION Mode

IDLE Mode

Note 8

3.0

1.0

7.0

Ω

OCMTPT

OCMTPI

NOTES: 1. APORT, TPAPCE, CS0, CS1, CS2, TX, LOOP, TPFULDL, TPSQEL and TPEN (In Input Mode).

2. TCLK, RX, RCLK, RENA and CLSN.

3. TPPLR, TPLIL, TPJABB, TXLED, RXLED, CLLED and TPEN (In Output Mode).

4. TPPLR, TPLIL, CLLED, TXLED and RXLED.

5. TPJABB and TPEN (In Output Mode).

6. Measured with Test Load B1 (shown in Figure 3), applied directly to the TPTX+/– pins of the device.

7. Measured differentially with Test Load B2 (shown in Figure 4), applied directly to the TPTX+/– pins of the device.

8. Measured directly on the TPTX+/– pins of the device.

9. Measured with Test Load B3 (shown in Figure 5), applied directly to the TPRX+/– pins of the device.

10. The Common Mode Input Voltage is between 1.8 V and 3.2 V.

DC ELECTRICAL CHARACTERISTICS (Unless otherwise noted, minimum and maximum limits apply over the recommended

ambient operating temperature and power supply voltage ranges.)

Characteristic

AUI RECEIVER INPUTS

Symbol

Test Conditions

Min

Max

Unit

Input Voltage Range (DC + AC)

–

1.0

±318

–275

1.5

4.2

±1315

–175

–

Differential Mode Input Voltage Range

Differential Input Squelch Threshold Voltage

Common Mode Input Resistance

kΩ

IDFA

IASQ

ICMA

1.0 V < V

< 4.2 V

ICMA

Differential Input Resistance (ARX, ACX Inputs)

1.0 V < V

318 mV < V

< 4.2 V

< 1315 mV

5.0

–

IDFA

ICMA

IDMA

AUI TRANSMITTER OUTPUTS

Common Mode Output Voltage

IDLE Mode

ACTIVE Mode

Figure 6

1.0

4.2

OCMIA

OCMAA

OCMSA

STANDBY Mode

= –100 µA

– 2.0

– 1.2

Differential Output Voltage

IDLE Mode

ACTIVE Mode

Figure 6

–

±600

±40

±1315

ODFIA

ODFAA

Differential Output Load Current

IDLE Mode

Figure 7

ODFIA

–

±4.0

Output Short Circuit Current

Output Short Circuited to

or GND

±150

ODSA

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Figure 3. Test Load B1

Figure 4. Test Load B2

39 Ω

Device

100 Ω

RCM

1.0 k Ω

VCMD

–

39 Ω

Figure 5. Test Load B3

39 Ω

RCM

10 kΩ

Device

VCMD

–

39 Ω

NOTE: A total of 50 Ω per driver output is required for proper series line termination. This is realized with the

39 Ω external resistors shown in Figures 3, 4 and 5, together with the internal driver output resistance.

Figure 6. AUI Common Mode Termination

Figure 7. AUI Differential Output

Short Circuit Current

–

39 Ω

DIFF

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AC ELECTRICAL CHARACTERISTICS (Unless otherwise noted, minimum and maximum limits apply over the recommended

temperature and power supply voltage ranges.)

Characteristic

EXTERNAL CLOCK INPUT (X1)

Symbol

Min

Max

Unit

Cycle Time (Note 1) (See Figure 8)

49.995

–

50.005

5.0

Fall Time

Rise Time

Low Time

High Time

RECEIVE PHASE–LOCKED–LOOP SWITCHING

Stabilization Time

–

100

CONTROLLER TRANSMIT SWITCHING (MOTOROLA MODE)

TCLK Cycle Time

TCLK High Time

TCLK Low Time

–

101

TCLK Rise and Fall Time

8.0

TX Setup Time to TCLK ↑

TX Hold Time to TCLK ↑

–

TENA Setup Time to TCLK ↑

TENA Hold Time to TCLK ↑

–

CONTROLLER RECEIVE SWITCHING

RCLK Cycle Time

RCLK High Time

RCLK Low Time

–

8.0

RCLK Rise and Fall Time

RX Hold Time from RCLK ↑

RX Set–Up Time to RCLK ↑

–

24.1

RCLK Delay from RENA ↑

RX Delay from RENA ↑

–

650

600

RENA Deassertion Delay from RCLK ↑ (See Figure 12)

NOTES: 1. To meet IEEE–802.3 specifications.

2. Load on specified output is 20 pF to ground, unless otherwise noted.

3. ↑ = Rising Edge

Figure 8. X1 Input Voltage Levels for Timing Measurements

4.0V

3.6V

1.5V

3.6V

1.5V

0.4V

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Figure 9. Receive Phase–Locked–Loop Switching

CS0 CS1 CS2

1.5V

TPRX

RENA

1.5V

NOTE: CS0 • CS1 • CS2 is the logical AND operation and refers to the pins not at Logic 1.

Figure 10. Transmit Timing (Motorola Mode)

1.5V

0.8V

1.5V

1.5V 1.5V

1.5V

TCLK

1.5V

TENA

1.5V 1.5V

Figure 11. Receive Timing (Motorola Start of Frame)

1.5V

RENA

1.5V

0.8V

1.5V

RCLK

24.1

1.5V

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Figure 12. Receive Timing (Motorola End of Frame)

RENA

1.5V

RCLK

Last Bit

CONTROLLER TRANSMIT SWITCHING (Intel Mode – Support by MC68160A Only)

Characteristic Symbol

Min

Max

Unit

TXC Cycle Time

TXC High and Low Time

TXC Rise and Fall Time

–

101

–

5.0

TXD Setup Time to TXC ↓

TXD Hold Time to TXC ↓

–

RTS Setup Time to TXC ↓

RTS Hold Time to TXC ↓

–

CONTROLLER RECEIVE SWITCHING

RXC Cycle Time

RXC High Time

RXC Low Time

–

RXC Rise and Fall Time

5.0

RXD Hold Time from RXC ↓

RXD Set–Up Time to RXC ↓

CRS Delay from RXC ↑

–

85.1

NOTE: Load on specified output is 20 pF to ground, unless otherwise noted.

↑ = Rising Edge

↓ = Falling Edge

Figure 13. Transmit Timing (Intel)

TXC

RTS

1.5V

1.5V 1.5V

1.5V

0.8V

1.5V

TXD

Last Bit

1 / 0

1.5V

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Figure 14. Receive Timing (Intel)

CRS

1.5V

.8V

1.5V

RXC

RXD

85.1 85

1.5V

CONTROLLER TRANSMIT SWITCHING (Fujitsu Mode – Supported by MC68160A Only)

Characteristic Symbol

Min

Max

Unit

TCKN Cycle Time

TCKN High and Low Time

TCKN Rise and Fall Time

–

101

8.0

TXD Setup Time to TCKN ↓

TXD Hold Time to TCKN ↓

–

TEN Setup Time to TCKN ↓

TEN Hold Time to TCKN ↓

–

CONTROLLER RECEIVE SWITCHING

RCKN Cycle Time

RCKN High Time

RCKN Low Time

–

8.0

100

101

102

103

RCKN Rise and Fall Time

RXD Hold Time from RCKN ↓

RXD Set–Up Time RCLK ↓

RCKN Delay from XCD ↑

–

600

104

104.1

105

XCD Deassertion Delay from RCKN ↑ (See Figure 17)

–

106

NOTE: Load on specified output is 20 pF to ground, unless otherwise noted.

↑ = Rising Edge

↓ = Falling Edge

Figure 15. Transmit Timing (Fujitsu)

TCKN

1.5V

1.5V 1.5V

1.5V

0.8V

1.5V

TEN

TXD

1.5V

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Figure 16. Receive Timing (Fujitsu Start of Frame)

1.5V

XCD

RCKN

RXD

105

101

100

1.5V

1.5V 1.5V

0.8V

104.1

104

102

103 103

1.5V

Figure 17. Receive Timing (Fujitsu End of Frame)

XCD

1.5V

106

1.5V

RCKN

RXD

CONTROLLER TRANSMIT SWITCHING (National Mode – Supported by MC68160A Only)

Characteristic Symbol

Min

Max

Unit

TXC Cycle Time

TXC High and Low Time

TXC Rise and Fall Time

–

101

8.0

110

111

112

TXD Setup Time to TXC ↑

TXD Hold Time to TXC ↑

–

113

114

TXE Setup Time to TXC ↑

TXE Hold Time to TXC ↑

–

115

116

CONTROLLER RECEIVE SWITCHING

RXC Cycle Time

RXC Low Time

RXC High Time

–

8.0

120

121

122

123

RXC Rise and Fall Time

RXD Hold Time from RXC ↑

RXD Set–Up Time from RXC ↑

RXC Delay from CRS ↑

–

600

124

124.1

125

126

127

CRS Deassertion Delay from RXC ↓

RXC continuing beyond CRS ↓

–

5.0

cycles

NOTE: Load on specified output is 20 pF to ground, unless otherwise noted.

↑ = Rising Edge

↓ = Falling Edge

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Figure 18. Transmit Timing (National)

111

110

1.5V

0.8V

1.5V

TXC

TXE

116

111

112 112

115

1.5V

113 114

1.5V

TXD

Figure 19. Receive Timing (National)

1.5V

CRS

126

122

125

127

120

1.5V

0.8V

1.5V

RXC

RXD

t t

124.1 124

121

123

1.5V

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TP TRANSMIT SWITCHING

Characteristic

Symbol

Min

Typ

Max

Unit

mVrms

TPTX Common Mode AC Output Voltage (Note 3)

–

OCMTP

TX to TPTX Steady State Propagation Delay (Note 2) (See Figure 24)

Bit Duration Center–to–Center

Half–Bit Cell Duration Center–to–Boundary

–

200

102

130

131

132

TENA Assert to RENA Assert Delay (Note 7) (See Figure 24)

Internal Loopback Delay from TX to RX (Note 7) (See Figure 24)

–

400

650

400

133

134

135

TPTX End of Packet Hold Time from last positive TPTX Signal Edge to

+585 mV Differential Output Level (Note 5) (See Figure 25)

250

TPTX Precompensation Pulse Width (Notes 2 and 6) (See Figure 25)

–

45–58

–

136

RENA Deassert Delay from TENA Deassert when Receiver is inactive

Motorola Mode

Fujitsu Mode

National Mode

Intel Mode (Note 4) (See Figure 26)

250

–

450

137

138

TPTX Data–to–Link Test Pulse (Note 2) (See Figure 27)

TPTX Link Test Pulse Width (Note 2)

TPTX Link Test Pulse Decay–to–Idle Condition (Note 1)

TPTX Link Test Pulse to next Link Test Pulse (Note 2)

8.0

–

240

139

140

141

142

8.0

NOTES: 1. Measured differentially across the output of Test Load A which is connected directly to the TPTX+/– pins of the device.

2. Measured differentially across the output of Test Load D shown in Figure 23 which is connected directly to the TPTX+/– pins of the device.

3. Measured across the output of Test Load C which is connected directly to the TPTX+/– pins of the device.

4. Same as t

except the logic states for TENA and RENA are inverted.

137

5. Measured across the output of Test Load B shown in Figure 21.

6. Measured at the +/–90% points of the precompensation voltage feature of the waveform. (The 0% reference is 0 V differential.)

7. Load on specified output is 20 pF to ground.

Figure 20. Test Load A

Figure 21. Test Load B

100µH

1.0µH

39Ω

Device

100Ω

100pF

100Ω

OUT

39Ω

Figure 22. Test Load C

Figure 23. Test Load D

200µH

39Ω

47.5Ω

out

100Ω

OUT

47.5Ω

39Ω

49.9Ω

NOTE: A total of 50 Ω per driver output is required for proper series line termination.

This is realized with the 39 Ω external resistors shown in Figures 20 to 23,

together with the internal driver output resistance.

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Figure 24. TPTX Transmit Timing (Start of Frame) Switching

1.5V

TCLK

TENA

1.5V

RENA

1.5V

133

1.5V

134

1.5V

TPTX +/– Differential

(Logic Levels)

130

132

131

TPTX +/– Differential

(Pre–Emphasis)

Figure 25. TPTX Transmit Timing (End of Frame) Switching

136

135

90%

+585mV

TPTX +/–

Differential

Figure 26. RENA Deassert Delay from TENA

137

TENA

1.5V

RENA

1.5V

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Figure 27. TPTX+/– Link Pulse Timing

142

141

140

139

585mV

±50mV

TP TRANSMIT JABBER SWITCHING

Characteristic

Symbol

Min

Max

Unit

Max Length of Transmission before Assertion

of TPJABB to indicate Jabber Condition

CLSN to indicate Jabber Condition

160

161

Time from End of Jabber Condition to Deassertion:

of TPJABB

of CLSN

500

750

162

163

TP TRANSMIT SIGNAL QUALITY ERROR TEST SWITCHING

CLSN (Signal Quality Error Test) (See Figure 29)

Assertion from last positive TPTX edge

Deassertion from last positive TPTX edge

Pulse Width

µs

0.6

–

0.5

1.6

3.1

1.5

170

171

172

TPSQEL Disable Delay Time (See Figure 29)

–

173

NOTE: The load attached to the specified output is a 20 pF capacitor connected to ground, unless otherwise noted.

Figure 28. TPJABB Switching

TPTX

(Differential)

585mV

–585mV

162

160

1.5V

TPJABB

CLSN

163

161

1.5V

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Figure 29. TPTX SQE (CLSN) Timing (End of Frame)

TPTX+/–

TPSQEL

1.5V

173

171

172

170

1.5V

CLSN

TP RECEIVE SWITCHING

Characteristic

Symbol

Min

Max

Unit

Differential Input Voltage Range Unconditional Squelch (Note 1)

(1.8 V < Input Common Mode Voltage < 3.2 V)

|264|

IDFSTP

Positive or Negative Differential Input Pulse Width for Conditional Receive Unsquelch

(See Figure 31)

180

TPRX to RCLK Bit Loss at start of packet (See Figure 32)

TPRX to RCLK Steady State Propagation Delay (See Figure 32)

TPRX to RX Start Up Delay (See Figure 32)

–

400

1.5

–

Bits

181

182

183

186

187

–

µs

TPRX held high from last valid positive transition (See Figure 33)

230

–

RENA Deassertion Delay from last valid positive transition of TPRX Pair

(See Figure 33)

350

TP RECEIVE LINK INTEGRITY SWITCHING

Required Pulse Width Range to be recognized as a Link Pulse (Note 2)

200

150

200

Last TPRX activity to high state TPLIL Output

(Receive Link Loss Timeout Interval)

100

201

Receive Link Beat Separation

Minimum Range (Note 3)

Maximum Range (Note 4)

3.0

100

7.0

150

202

203

NOTES: 1. Measured with Test Load H attached to the receive pins.

2. Measured at the receive pins.

3. Link beats closer in time to this range of values are considered noise, and are rejected.

4. Link beats further apart in time than this range of values are not considered consecutive, and are rejected.

Figure 30. Test Load H

Figure 31. TPRX Input Switching

1.0µH

200µH

+330mV

180

100pF

1.0µH

100pF

Line

100Ω

0mV

TPRX

–330mV

180

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Figure 32. TPRX Receive Timing (Start of Frame)

Bit n

Bit n+1

Bit n+2

Bit n+3

Bit n+4

–300mV

TPRX+/–

RENA

182

183

181

1.5V

RCLK

Bit n

Bit n+1

Bit n+2

Figure 33. RENA Deassertion Delay from Last Valid Positive Transition of TPRX Pair

186

+300mV

TPRX+/–

RENA

187

1.5V

Figure 34. TP Receive Link Integrity Switching

202 203

200

300mV

201

TPRX

TPLIL

50%

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TP COLLISION SWITCHING

Characteristic

Symbol

Min

Max

Unit

Time from collision (TPRX activity caused assertion of RENA followed by assertion of

TENA) to assertion of CLSN

–

300

210

Time from end of collision (Deassertion of TENA with uninterrupted TPRX pair

activity) to deassertion of CLSN

350

900

211

TP FULL DUPLEX SWITCHING

TPFULDL assert to collision detect disable (See Figure 36)

TPFULDL deassert to collision detect enable

–

220

221

TPFULDL assert to data loop back disable (See Figure 37)

TPFULDL deassert to data loop back enable

–

350

150

222

223

NOTE: Load on specified output is 20 pF to ground, unless otherwise noted.

Figure 35. TPTX Collision Timing

RENA

1.5V

TENA

211

210

1.5V

CLSN

Figure 36. TPTX Full Duplex Timing

TPFULDL

1.5V

221

220

CLSN

1.5V

Figure 37. TPTX Full Duplex Timing

TPFULDL

RENA

1.5V

222

223

1.5V

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AUI TRANSMIT SWITCHING

Characteristic

Symbol

Min

–

Typ

Max

100

5.0

–

Unit

TCLK to ATX Pair Steady State Propagation Delay

–

240

241

242

243

244

Output Differential Rise and Fall Times (Measured directly at device pins)

ATX Bit Cell Duration center–to–center (Measured directly at device pins)

ATX Half–Bit Cell Duration center–to–boundary (Measured directly at device pins)

1.0

–

99.5–100.5

49.5–50.5

–

ATX Pair Held at Positive Differential at start of Idle (Measured through

transformer)

200

–

NOTE: Load on specified output is a shunt 27 µH inductor and 83 Ω resistor.

Figure 38. ATX Transmit Timings

1.5V

TCLK

TENA

240

241

244

90%

10%

90%

70%

ATX+/–

Differential

(Logic Levels)

10%

242

243

AUI RECEIVE SWITCHING

Characteristic

Symbol

Min

Max

Unit

ARX/ACX Differential Input Voltage Range

–

±318

±1315

ARX/ACX Differential Input Pulse Width to:

Initiate Data Reception

–

261

262

Inhibit Data Reception

RENA Assertion Delay

RENA Deassertion Delay

–

100

450

266

267

Squelching Characteristics

The receive data pairs and the collision pairs should have the following squelch characteristics:

1. The squelch circuits are on at idle (with input voltage at approximately 0 V differential).

2. If an input is in squelch, pulse is rejected if the peak differential voltage is more positive than –175 mV, regardless of pulse width.

3. A pulse is considered valid if its peak differential voltage is more negative than –300 mV and its width, measured at –285 mV, is > 25 ns.

4. The squelch circuits are disabled by the first valid negative differential pulse on either the AUI receive data or collision pair.

5. If a positive differential pulse occurs on either the AUI receive data or collision pair > 175 ns, end of frame is assumed and squelch circuitry is turned on.

Figure 39. ARX/ACX Timing

+175mV

ARX+/–

ACX+/–

Differential

–175mV

Input Voltage

261/ 262

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MC68160A

Figure 40. ARX/ACX Timing

Bit Q

Bit U

Bit V

Bit W

Bit X

Bit Y

Bit Z

ARX+/–/

ACX+/–

Differential

Input Voltage

260

261

+300mV

–40mV

90%

–275mV

10%

–300mV

266

267

1.5V

RENA/CLSN

RCLK

Bit Q

Bit U

Bit V

Bit U

Bit X

Bit Y

Bit Z

FUNCTIONAL DESCRIPTION

Introduction

The MC68160A was designed to perform the physical

connection to the Ethernet media. This is done through two

separate media dependent interfaces and a SIA interface.

The media dependent interfaces are the Attachment Unit

Interface(AUI) and the 10BASE–T Twisted Pair(TP) port. The

MC68160A’s SIA interface is compatible with most industry

controllers and selected by three mode control pins. Chip

status is supported indicated by the condition of 6 status

indicator pins. All but one are open collector outputs.

If the EEST isn’t receiving data, the controller may initiate

transmission. NRZ data from the communications controller

SIA interface is encoded by the MC68160A into Manchester

Code in preparation for transmission on the media. The data

is then applied to either the AUI or TP port. If the data was

transmitted using the 10BASE–T port, this data is also

looped back to the receive data interface SIA pins

connected to the controller. This allows detection of a

collision condition in the event that another station on the

media attempted transmission at the same time. After the

entire data frame has been transmitted, the EEST must

force the media idle signal. The idle signal frees the media

for other stations that have deferred transmission. If no

other transmissions are required the link enters an idle

state. During this idle state the 10BASE–T transmitter

issues idle pulses which communicates to the receiver

connected to the other side that the link is valid. If the

transmitter connected at the other end begins transmission,

the EEST will assert a receive enable signal, and forward

the received data to the controller.

Upon reception of data at the 10BASE–T port, the data is

screened for proper sequence and pulse width requirements.

If the preamble of the received frame meets the

requirements, the PLL locks onto the 64–bit preamble and

begins to decode the Manchester Code to NRZ code. This

code is then presented to the communications controller at

the receive data pins at the SIA interface. If data is received

at the AUI port, it is sent directly to the communications

controller via the SIA interface.

Data Transmission

To have properly encoded transmit data, the com–

munications controller must be synchronized to TCLK.

Transmission to the 10BASE–T or AUI media occurs when

TENA is asserted and data is applied to the TX pin. Finally, to

signify transmission, the TXLED in will cycle on and off at a

100 ms period. Data transmission for EEST is accomplished

either over the 10BASE–T port or the AUI port. Both

connections to the media are made with industry standard

media interface components. The 10BASE–T interface

requires a filter and transformer, the AUI interface requires

only a transformer. The filter for the 10BASE–T transmit

circuit will have to be chosen for each application.

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If after approximately 40 ms after a TP or AUI transmission

expire and assert the TPJABB pin to alert the communications

controller of the situation. The TPJABB pin can source or sink

up to 10 mA, and so, is capable of driving a status LED. In the

AUI mode, the pin is driven to high impedance since the

transceiver connected to the AUI port must alert the

communications controller of the jabber condition.

has begun, the EEST is still transmitting, the TPJABB pin will

assert to signify a jabber condition. Also, the CLLED pin will

transition high and low alternately with a 100 ms period. The

transmit circuitry is, however, unaffected by the jabber

condition, so the communications controller has the

responsibility of monitoring and stopping transmission.

When transmission is complete, the transmit circuitry will

begin the end of transmit and decay to idle responses

necessary to meet requirements of the 802.3 standard for the

TP and AUI port.

Full Duplex

A feature unique to the MC68160A is the Full Duplex

mode. In this mode the EEST is capable of transmitting and

receiving simultaneously. Collision conditions are not

announced and internal loop back is disabled. The remainder

of the EEST functionality remains unchanged from the

non–Full Duplex mode. Full Duplex mode is enabled by

asserting the TPFULDL pin.

Data Reception

Other than the case of being in Loop Back mode, data

reception to the RX pin of the EEST is initiated by signaling at

the RX+/– or AUI ARX+/– pins. If at the TP port, the data is

screened for validity by checking for sequence and pulse

width requirements, then passed to the decode and receive

circuitry. The RENA pin asserts and the data and

corresponding clock is passed to the communications

controller. After the frame has been transmitted, the

MC68160A detects the ending transmission and negates

RENA. If at the AUI port, the data is checked for proper pulse

width requirements before being passed to the decode

circuitry. If the data pulses are longer than at least 20 ns,

RENA gets asserted and the frame is decoded to RX with

and accompanying RCLK output.

Auto Port Selection

If the APORT pin is asserted, the MC68160A will

automatically select the TP or AUI port depending on the

presence of valid link beats or frames at the TP RX+/– pins. If

the AUI port is automatically selected by another transmitting

station or by setting TPEN low, the TP transmit port of the

EEST continues to transmit link beats to keep the link active.

Auto Polarity Selection

If the RX+ and the RX– wires happen to get reversed, the

MC68160A has the ability to automatically reverse the pins

internally so that the received data is valid. In addition, an open

collector status pin (TPPLR) is driven low to indicate the fault.

In the AUI or reset mode this pin presents a high impedance.

Collision

Collision is the occurrence of simultaneous transmit

activity by two or more stations on the network. In the event of

collision, the data transfer paths are unaffected. If the

MC68160A is in the twisted pair mode, collision is detect by

simultaneous receive and transmit activity. If in the AUI

mode, collision is detected by activity on the ACX+/– pins. In

either case, if collision is detected, the CLSN pin will assert to

notify the communications controller.

Loop Back Mode

To test the transmit and receive circuitry without disturbing

the connected network, the EEST has a Loop Back mode.

Loop Back mode routes transmit data and clock to the

receive data and clock pins using as much of the transmit and

receive circuitry as possible. This gives a test of the

MC68160A Manchester encode and decode function. LOOP

must not be asserted when TPFULDL pin is asserted. This

causes the MC68160A to enter a test mode. This test mode

is used during final test and is not intended to be entered

under normal operation (see Application Notes section).

Jabber

The EEST has a jabber timer to detect the jabber condition.

In the event that the transmitting station continues to transmit

beyond the allowable transmit time, a jabber timer (40 ms) will

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APPLICATIONS INFORMATION

Selection of Crystal and External Components

Accuracy of frequency and stability over temperature are

the main determinants of crystal choice. Specifications for a

suitable crystal are tabulated below.

Vendor

Part #

FEE Fil–Mag

78Z1120B–01, 78Z1122B/D–01,

78Z1122 F–01

Valor Electronics

PT3877, FL1012, FL1066

Frequency

20.000 MHz

Fundamental

± 100 ppm

± 5 ppm/yr

7.0 pF

Pulse Engineering PE–65434, PE65424, PE65433

TOKO PM01–00, PM02–00, PM05–00

Mode

Tolerance

AUI Transformer Choice

Stability

Like the 10BASE–T outputs, the AUI differential outputs

are low impedance sources and capable of meeting the IEEE

802.3 waveform requirements when a coupling transformer

is used. Some AUI transformer vendors and their products

are provided below.

Aging

Shunt Capacitance

Load Capacitance

Series Fundamental Resistance (ESR)

Drive Level

18–20 pF

25 Ω

500 µW

Vendor

Part #

Coilcraft

LAX–ET304

FEE Fil–Mag

Valor Electronics

23Z90, 23Z91/ 23Z92

LT6032, LT6033

A suitable crystal is the MTRON

HC49 MP–1, 20.000 MHz crystal.

20 pF for C4 and C5 have been

shown to work reliably.

Pulse Engineering PE64502, PE6103

TOKO

Q30ALQ8–1AA3, Q30ALQ9–1AA3

Application Notes:

PLL Filter Components

Resetting the MC68160A after power up.

The filter components at Pin 12 were chosen to assure

adequate pull–range but with a emphasis on stability. It is not

foreseeable that a design would need to change the

components, but for the sake of completeness, relevant

values are provided here.

In some applications, after initial power up, the MC68160A

may not be able to transmit or receive data. This is usually

caused by the LOOP and TPFULDL control lines being active

at the same time. This is an illegal condition during normal

operation, it places the MC68160A into the production test

mode.

To exit the test mode and return to normal: Set LOOP low,

TPFULDL high and TPSQEL low. Then, while keeping

TPSQEL low, raise LOOP after 300 ms lower TPFULDL. This

will put the MC68160A into test mode but also resets the

MC68160A. After 500 ms lower LOOP to get out of the test

mode. TPFULDL may then be de–asserted if desired.

The MC68160A is now ready for operation.

MHz

Volt • sec

VCO Gain

and,

rad

100

Phase Detector Gain

and the

filter impedance function is;

1 C6)

1 C5)

Z(j )

(for C6

C5)

• C5 • (j

A hardware implementation of this fix would be to place a

pull down resistor on the TPSQEL pin. Even if test mode is

entered by accident, this ensures that zero’s will be written to

the test register. The hardware implementation will solve the

problem if the test mode is entered because of noise on the

TPSQEL pin. If the controller is toggling the MC68160A lines

while it is booting up, the reset procedure must be followed.

10BASE–T Filter and Transformer Choice

The MC68160A differential outputs are low impedance

voltage sources. Therefore, external series resistors must be

used in order to match the characteristic impedance of

twisted pair. Since the output resistance of each leg of the

transmitter is about 10 Ω, a 39 Ω resistor is used in series as

shown in the applications schematic. So the impedance

presented from the source to the isolation transformer is then

very nearly 100 Ω. The following is a list of some 10BASE–T

filter module vendors and their products.

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MC68160A

Figure 41.

AUI

( E x a m p l e o f P E - 6 5 4 2 4 )

A U I X F M R

Ω

T X L E D

R X L E D

T A X +

T A X –

C L L E D

T P L I L

A R X +

A R X –

A C X +

T P P L R

T P J A B B

T P E N

G N D C T L

T C L K

A C X –

G N D S U B

G N D D I G

V D D D I G

T E N A

R C L K

C L S N

X 2

X 1

V D D V C O

G N D V C O

T X

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OUTLINE DIMENSIONS

FB SUFFIX

PLASTIC PACKAGE

CASE 848D-03

(LQFP–52)

ISSUE C

4X TIPS

–X–

X=L, M, N

0.20 (0.008) H L–M N

0.20 (0.008) T L–M N

3X VIEW Y

–L–

–M–

VIEW Y

BASE METAL

PLATING

0.13 (0.005)

T L–M

–N–

SECTION AB–AB

ROTATED 90 CLOCKWISE

NOTES:

DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

CONTROLLING DIMENSION: MILLIMETER.

DATUM PLANE –H– IS LOCATED AT BOTTOM OF LEAD AND

IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS

THE PLASTIC BODY AT THE BOTTOM OF THE PARTING

LINE.

4X θ2

4X θ3

DATUMS –L–, –M– AND –N– TO BE DETERMINED AT DATUM

PLANE –H–.

DIMENSIONS S AND V TO BE DETERMINED AT SEATING

PLANE –T–.

DIMENSIONS A AND B DO NOT INCLUDE MOLD

PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010)

PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD

MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-.

DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION.

DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD

WIDTH TO EXCEED 0.46 (0.018). MINIMUM SPACE BETWEEN

PROTRUSION AND ADJACENT LEAD OR PROTRUSION 0.07

(0.003).

0.10 (0.004) T

–H–

–T–

SEATING

PLANE

VIEW AA

MILLIMETERS

DIM MIN MAX

10.00 BSC

INCHES

MIN MAX

0.394 BSC

0.197 BSC

0.394 BSC

0.197 BSC

5.00 BSC

10.00 BSC

5.00 BSC

0.05 (0.002)

2 X R R1

–––

0.05

1.30

0.20

0.45

0.22

1.70

–––

0.20 0.002

1.50 0.051

0.40 0.008

0.75 0.018

0.35 0.009

0.067

θ1

0.008

0.059

0.016

0.030

0.014

0.25 (0.010)

GAGE PLANE

0.65 BSC

0.07

0.026 BSC

0.20 0.003

0.008

0.50 REF

0.020 REF

0.08

0.20 0.003

0.008

12.00 BSC

0.472 BSC

0.236 BSC

0.16 0.004 0.006

6.00 BSC

0.09

12.00 BSC

6.00 BSC

0.20 REF

1.00 REF

0.472 BSC

0.236 BSC

0.008 REF

0.039 REF

VIEW AA

–––

REF

–––

REF

θ1

θ2

θ3

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NOTES

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NOTES

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