KMC9S12A256BCFU [NXP]
16-BIT, FLASH, 8MHz, MICROCONTROLLER, PQFP80, QFP-80;
| 型号： | KMC9S12A256BCFU |
| 厂家： | 
NXP |
| 描述： | 16-BIT, FLASH, 8MHz, MICROCONTROLLER, PQFP80, QFP-80 时钟 外围集成电路 |
| 文件： | 总96页 (文件大小：720K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
9S12A256DGV1/D
4/2002
MC9S12A256
Device Guide
V01.01
Original Release Date: 8 March 2002
Revised: 12 April 2002
Motorola, Inc
Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or
design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein;
neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to
support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where
personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized
application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was
negligent regarding the design or manufacture of the part.
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MC9S12A256 Device Guide — V01.01
Revision History
Version Revision Effective
Author
Description of Changes
Number
Date
Date
8 MAR
2002
8 MAR
2002
V01.00
Initial release
Replaced document order number with version except for cover
sheet
Table A-4 Operating Conditions — Changed minimum values for
V
and V
to 2.35 V
DD
DDPLL
12 APRIL 12 APRIL
2002 2002
Table A-6 5V I/O Characteristics — Changed input capacitance
for standard I/O pin to 6 pF
V01.01
Table A-9 ATD Electrical Characteristics — Changed maximum
value for C
to 22 pF
INS
Table A-15 Oscillator Characteristics — Removed oscillator
start-up time from POR or STOP
For additional information, refer to the MC9S12A256 8-Bit Microcontroller Unit Mask Set Errata
(Motorola document order number, 9S12A256MSE1). The errata can be found on the World Wide Web at:
http://www.motorola.com/semiconductors/
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MC9S12A256 Device Guide — V01.01
Table of Contents
Section 1 Introduction
1.1
1.2
1.3
1.4
1.5
1.6
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Device Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Part ID Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Section 2 Signal Description
2.1
Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Signal Properties Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Detailed Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
EXTAL, XTAL — Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
RESET — External Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
TEST — Test Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
VREGEN — Voltage Regulator Enable Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
XFC — PLL Loop Filter Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
BKGD / TAGHI / MODC — Background Debug, Tag High, and Mode Pin . . . . . . . .29
PAD15 / AN15 / ETRIG1 — Port AD Input Pin of ATD1 . . . . . . . . . . . . . . . . . . . . . .29
PAD[14:08] / AN[14:08] — Port AD Input Pins of ATD1 . . . . . . . . . . . . . . . . . . . . . .29
PAD7 / AN07 / ETRIG0 — Port AD Input Pin of ATD0 . . . . . . . . . . . . . . . . . . . . . . .29
2.2
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
2.3.7
2.3.8
2.3.9
2.3.10 PAD[06:00] / AN[06:00] — Port AD Input Pins of ATD0 . . . . . . . . . . . . . . . . . . . . . .29
2.3.11 PA[7:0] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins . . . . . . . . . . . . . . . . . . . . . . .29
2.3.12 PB[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . .29
2.3.13 PE7 / NOACC / XCLKS — Port E I/O Pin 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
2.3.14 PE6 / MODB / IPIPE1 — Port E I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
2.3.15 PE5 / MODA / IPIPE0 — Port E I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
2.3.16 PE4 / ECLK — Port E I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
2.3.17 PE3 / LSTRB / TAGLO — Port E I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
2.3.18 PE2 / R/W — Port E I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
2.3.19 PE1 / IRQ — Port E Input Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
2.3.20 PE0 / XIRQ — Port E Input Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
2.3.21 PH7 / KWH7 / SS2 — Port H I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
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MC9S12A256 Device Guide — V01.01
2.3.22 PH6 / KWH6 / SCK2 — Port H I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
2.3.23 PH5 / KWH5 / MOSI2 — Port H I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
2.3.24 PH4 / KWH4 / MISO2 — Port H I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
2.3.25 PH3 / KWH3 / SS1 — Port H I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
2.3.26 PH2 / KWH2 / SCK1 — Port H I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
2.3.27 PH1 / KWH1 / MOSI1 — Port H I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
2.3.28 PH0 / KWH0 / MISO1 — Port H I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
2.3.29 PJ7 / KWJ7 / SCL — PORT J I/O Pin 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
2.3.30 PJ6 / KWJ6 / SDA — PORT J I/O Pin 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
2.3.31 PJ[1:0] / KWJ[1:0] — Port J I/O Pins [1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
2.3.32 PK7 / ECS / ROMONE — Port K I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
2.3.33 PK[5:0] / XADDR[19:14] — Port K I/O Pins [5:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
2.3.34 PM7 — Port M I/O Pin 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
2.3.35 PM6 — Port M I/O Pin 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
2.3.36 PM5 / SCK0 — Port M I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
2.3.37 PM4 / MOSI0 — Port M I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
2.3.38 PM3 / SS0 — Port M I/O Pin 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
2.3.39 PM2 / MISO0 — Port M I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
2.3.40 PM1 — Port M I/O Pin 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
2.3.41 PM0 — Port M I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
2.3.42 PP7 / KWP7 / PWM7 / SCK2 — Port P I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . .33
2.3.43 PP6 / KWP6 / PWM6 / SS2 — Port P I/O Pin 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
2.3.44 PP5 / KWP5 / PWM5 / MOSI2 — Port P I/O Pin 5. . . . . . . . . . . . . . . . . . . . . . . . . . .33
2.3.45 PP4 / KWP4 / PWM4 / MISO2 — Port P I/O Pin 4. . . . . . . . . . . . . . . . . . . . . . . . . . .34
2.3.46 PP3 / KWP3 / PWM3 / SS1 — Port P I/O Pin 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
2.3.47 PP2 / KWP2 / PWM2 / SCK1 — Port P I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .34
2.3.48 PP1 / KWP1 / PWM1 / MOSI1 — Port P I/O Pin 1. . . . . . . . . . . . . . . . . . . . . . . . . . .34
2.3.49 PP0 / KWP0 / PWM0 / MISO1 — Port P I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . .34
2.3.50 PS7 / SS0 — Port S I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
2.3.51 PS6 / SCK0 — Port S I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
2.3.52 PS5 / MOSI0 — Port S I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
2.3.53 PS4 / MISO0 — Port S I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
2.3.54 PS3 / TXD1 — Port S I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
2.3.55 PS2 / RXD1 — Port S I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
2.3.56 PS1 / TXD0 — Port S I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
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MC9S12A256 Device Guide — V01.01
2.3.57 PS0 / RXD0 — Port S I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
2.3.58 PT[7:0] / IOC[7:0] — Port T I/O Pins [7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
2.4
Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
2.4.1
2.4.2
VDDX, VSSX — Power & Ground Pins for I/O Drivers. . . . . . . . . . . . . . . . . . . . . . . . .36
VDDR, VSSR — Power & Ground Pins for I/O Drivers &
for Internal Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
2.4.3
2.4.4
2.4.5
2.4.6
2.4.7
VDD1, VDD2, VSS1, VSS2 — Core Power Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
VDDA, VSSA — Power Supply Pins for ATD and VREG. . . . . . . . . . . . . . . . . . . . . . . .36
VRH, VRL — ATD Reference Voltage Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
VDDPLL, VSSPLL — Power Supply Pins for PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
VREGEN — On Chip Voltage Regulator Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Section 3 System Clock Description
3.1
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Section 4 Modes of Operation
4.1
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Normal Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Special Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Test Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Securing the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Operation of the Secured Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Unsecuring the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
4.2
4.2.1
4.2.2
4.2.3
4.3
4.3.1
4.3.2
4.3.3
4.4
Section 5 Resets and Interrupts
5.1
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Vector Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
5.2
5.2.1
5.3
5.3.1
5.3.2
Section 6 HCS12 Core Block Description
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MC9S12A256 Device Guide — V01.01
Section 7 Clock and Reset Generator (CRG) Block Description
7.1
Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
XCLKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
7.1.1
Section 8 Enhanced Capture Timer (ECT) Block Description
Section 9 Analog to Digital Converter (ATD) Block Description
Section 10 Inter-IC Bus (IIC) Block Description
Section 11 Serial Communications Interface (SCI) Block Description
Section 12 Serial Peripheral Interface (SPI) Block Description
Section 13 Pulse Width Modulator (PWM) Block Description
Section 14 Flash EEPROM 256K Block Description
Section 15 EEPROM 4K Block Description
Section 16 RAM Block Description
Section 17 Port Integration Module (PIM) Block Description
Section 18 Voltage Regulator (VREG) Block Description
Appendix A Electrical Characteristics
A.1
General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Power Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Current Injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
ESD Protection and Latch-up Immunity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Power Dissipation and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
A.1.1
A.1.2
A.1.3
A.1.4
A.1.5
A.1.6
A.1.7
A.1.8
A.1.9
A.1.10 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
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MC9S12A256 Device Guide — V01.01
A.2
ATD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Factors Influencing Accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
ATD Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
NVM, Flash, and EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
NVM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
NVM Reliability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Voltage Regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Reset, Oscillator and PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
General Muxed Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
A.2.1
A.2.2
A.2.3
A.3
A.3.1
A.3.2
A.4
A.5
A.5.1
A.5.2
A.5.3
A.6
A.6.1
A.6.2
A.7
A.7.1
Appendix B Package Information
B.1
B.2
B.3
General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
112-Pin LQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
80-Pin QFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
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MC9S12A256 Device Guide — V01.01
8
MC9S12A256 Device Guide — V01.01
List of Figures
Figure 1-1 MC9S12A256 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Figure 1-2 MC9S12A256 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Figure 2-1 Pin Assignments in 112-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Figure 2-2 Pin Assignments in 80-Pin QFP for MC9S12A256 . . . . . . . . . . . . . . . . . . . . . . .25
Figure 2-3 PLL Loop Filter Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Figure 3-1 Clock Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Figure 18-1 Recommended PCB Layout 112 LQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Figure 18-2 Recommended PCB Layout for 80 QFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Figure A-1 ATD Accuracy Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure A-2 Basic PLL Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure A-3 Jitter Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure A-4 Maximum Bus Clock Jitter Approximation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure A-5 SPI Master Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure A-6 SPI Master Timing (CPHA =1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure A-7 SPI Slave Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure A-8 SPI Slave Timing (CPHA =1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure A-9 General External Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure B-1 112-Pin LQFP Mechanical Dimensions (Case no. 987) . . . . . . . . . . . . . . . . . . 92
Figure B-2 80-Pin QFP Mechanical Dimensions (Case no. 841B) . . . . . . . . . . . . . . . . . . . 93
9
MC9S12A256 Device Guide — V01.01
10
MC9S12A256 Device Guide — V01.01
List of Tables
Table 0-1 Document References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Table 1-1 Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Table 1-2 Assigned Part ID Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Table 1-3 Memory Size Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Table 2-1 Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Table 2-2 MC9S12A256 Power and Ground Connection Summary . . . . . . . . . . . . . . . . . . .37
Table 4-1 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Table 5-1 Interrupt Vector Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Table A-1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Table A-2 ESD and Latch-up Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Table A-3 ESD and Latch-Up Protection Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Table A-4 Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Table A-5 Thermal Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Table A-6 5V I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Table A-7 Supply Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Table A-8 ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Table A-9 ATD Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Table A-10 ATD Conversion Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Table A-11 NVM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Table A-12 NVM Reliability Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Table A-13 Voltage Regulator Recommended Load Capacitances . . . . . . . . . . . . . . . . . . . .75
Table A-14 Startup Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Table A-15 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Table A-16 PLL Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Table A-17 SPI Master Mode Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Table A-18 SPI Slave Mode Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Table A-19 Expanded Bus Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
11
MC9S12A256 Device Guide — V01.01
12
MC9S12A256 Device Guide — V01.01
Preface
The Device User Guide provides information about the MC9S12A256 device made up of standard HCS12
blocks and the HCS12 processor core.
This document is part of the customer documentation. A complete set of device manuals also includes the
CPU12 Reference Manual (Motorola order number, CPU12RM/AD) and all the individual Block User
Guides of the implemented modules. In a effort to reduce redundancy all module specific information is
located only in the respective Block User Guide. If applicable, special implementation details of the
module are given in the block description sections of this document.
See Table 0-1 for names and versions of the referenced documents throughout the Device User Guide.
Table 0-1 Document References
User Guide
Version
V01
V02
V01
V02
V02
V02
V02
V01
V02
V02
V01
V01
Document Order Number
HCS12COREUG/D
S12CRGV3/D
HCS12 Core User Guide
CRG Block Guide
ECT_16B8C Block Guide
ATD_10B8C Block Guide
IIC Block Guide
S12ECT16B8CV1/D
S12ATD10B8CV2/D
S12IICV2/D
SCI Block Guide
S12SCIV2/D
SPI Block Guide
S12SPIV2/D
PWM_8B8C Block Guide
FTS256K Block Guide
EETS4K Block Guide
VREG Block Guide
PIM_9A256 Block Guide
S12PWM8B8CV1/D
S12FTS256KV2/D
S12EETS4KV2/D
S12VREGV1/D
S12A256PIMV1/D
13
MC9S12A256 Device Guide — V01.01
14
MC9S12A256 Device Guide — V01.01
Section 1 Introduction
1.1 Overview
The MC9S12A256 microcontroller unit (MCU) is a 16-bit device composed of standard on-chip
peripherals including a 16-bit central processing unit (HCS12 CPU), 256K bytes of Flash EEPROM, 12K
bytes of RAM, 4K bytes of EEPROM, two asynchronous serial communications interfaces (SCI), three
serial peripheral interfaces (SPI), an 8-channel IC/OC enhanced capture timer, two 8-channel, 10-bit
analog-to-digital converters (ADC), an 8-channel pulse-width modulator (PWM), 29 discrete digital I/O
channels (Port A, Port B, Port K and Port E), 20 discrete digital I/O lines with interrupt and wakeup
capability and an Inter-IC Bus. System resource mapping, clock generation, interrupt control and bus
interfacing are managed by the System Integration Module (SIM). The MC9S12A256 has full 16-bit data
paths throughout. However, the external bus can operate in an 8-bit narrow mode so single 8-bit wide
memory can be interfaced for lower cost systems. The inclusion of a PLL circuit allows power
consumption and performance to be adjusted to suit operational requirements.
1.2 Features
•
HCS12 Core
– 16-bit HCS12 CPU
i. Upward compatible with M68HC11 instruction set
ii. Interrupt stacking and programmer’s model identical to M68HC11
iii.Instruction queue
iv. Enhanced indexed addressing
– MEBI (Multiplexed External Bus Interface)
– MMC (Module Mapping Control)
– INT (Interrupt control)
– BKP (Breakpoints)
– BDM (Background Debug Mode)
CRG (low current oscillator, PLL, reset, clocks, COP watchdog, real time interrupt, clock monitor)
8-bit and 4-bit ports with interrupt functionality
– Digital filtering
•
•
– Programmable rising or falling edge trigger
Memory
•
– 256K Flash EEPROM
– 4K byte EEPROM
– 12K byte RAM
15
MC9S12A256 Device Guide — V01.01
•
Two 8-channel Analog-to-Digital Converters
– 10-bit resolution
– External conversion trigger capability
Enhanced Capture Timer
•
– 16-bit main counter with 7-bit prescaler
– 8 programmable input capture or output compare channels
– Two 8-bit or one 16-bit pulse accumulators
8 PWM channels
•
– Programmable period and duty cycle
– 8-bit 8-channel or 16-bit 4-channel
– Separate control for each pulse width and duty cycle
– Center-aligned or left-aligned outputs
– Programmable clock select logic with a wide range of frequencies
– Fast emergency shutdown input
– Usable as interrupt inputs
•
•
Serial interfaces
– Two asynchronous Serial Communications Interfaces (SCI)
– Three Synchronous Serial Peripheral Interface (SPI)
Inter-IC Bus (IIC)
– Compatible with I2C Bus standard
– Multi-master operation
– Software programmable for one of 256 different serial clock frequencies
112-Pin LQFP and 80-pin QFP packages
– I/O lines with 5V input and drive capability
– 5V A/D converter inputs
•
– Operation at 50MHz equivalent to 25MHz Bus Speed
– Development support
– Single-wire background debug™ mode (BDM)
– On-chip hardware breakpoints
16
MC9S12A256 Device Guide — V01.01
1.3 Modes of Operation
User modes
•
Normal and Emulation Operating Modes
– Normal Single-Chip Mode
– Normal Expanded Wide Mode
– Normal Expanded Narrow Mode
– Emulation Expanded Wide Mode
– Emulation Expanded Narrow Mode
Special Operating Modes
•
– Special Single-Chip Mode with active Background Debug Mode
– Special Test Mode (Motorola use only)
– Special Peripheral Mode (Motorola use only)
Low power modes
•
•
•
Stop Mode
Pseudo Stop Mode
Wait Mode
17
MC9S12A256 Device Guide — V01.01
1.4 Block Diagram
Figure 1-1 shows a block diagram of the MC9S12A256 device.
18
MC9S12A256 Device Guide — V01.01
Figure 1-1 MC9S12A256 Block Diagram
VRH
VRL
VDDA
VSSA
VRH
VRL
VDDA
VSSA
VRH
VRL
VDDA
VSSA
256K Byte Flash EEPROM
12K Byte RAM
ATD0
ATD1
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
PAD00
PAD01
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
PAD08
PAD09
4K Byte EEPROM
PAD02
PAD03
PAD04
PAD05
PAD06
PAD10
PAD11
PAD12
PAD13
PAD14
VDDR
VSSR
VREGEN
VDD1,2
VSS1,2
Voltage Regulator
PAD07
PAD15
PIX0
PK0 XADDR14
PK1 XADDR15
Single-wire Background
BKGD
PIX1
PIX2
PIX3
PIX4
PIX5
ECS
CPU12
Debug Module
PPAGE
PK2
XADDR16
XFC
VDDPLL
VSSPLL
EXTAL
XTAL
PK3 XADDR17
PK4 XADDR18
PK5 XADDR19
Clock and
Reset
Generation
Module
PLL
Periodic Interrupt
COP Watchdog
Clock Monitor
Breakpoints
PK7
ECS
IOC0
IOC1
IOC2
IOC3
IOC4
IOC5
IOC6
IOC7
PT0
PT1
PT2
PT3
PT4
PT5
RESET
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
XIRQ
IRQ
R/W
LSTRB
ECLK
MODA
MODB
Enhanced Capture
Timer
System
Integration
Module
(SIM)
PT6
PT7
NOACC/XCLKS
RXD
TXD
RXD
TXD
PS0
PS1
SCI0
TEST
PS2
PS3
PS4
PS5
PS6
PS7
SCI1
SPI0
MISO
MOSI
SCK
SS
Multiplexed Address/Data Bus
DDRA
PTA
DDRB
PTB
PM0
PM1
PM2
PM3
PM4
PM5
PM6
PM7
Multiplexed
Wide Bus
KWJ0
KWJ1
KWJ6
KWJ7
PJ0
PJ1
PJ6
PJ7
Multiplexed
Narrow Bus
SDA
SCL
IIC
Internal Logic 2.5V
VDD1,2
VSS1,2
I/O Driver 5V
PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7
KWP0
KWP1
KWP2
KWP3
KWP4
KWP5
KWP6
KWP7
PP0
PP1
PP2
PP3
PP4
PP5
VDDX
VSSX
PWM
A/D Converter 5V &
Voltage Regulator Reference
PLL 2.5V
VDDPLL
VSSPLL
VDDA
VSSA
PP6
PP7
MISO
MOSI
SCK
SS
MISO
MOSI
SCK
SS
KWH0
KWH1
KWH2
KWH3
KWH4
KWH5
KWH6
KWH7
PH0
PH1
PH2
PH3
PH4
PH5
Voltage Regulator 5V & I/O
SPI1
SPI2
VDDR
VSSR
PH6
PH7
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MC9S12A256 Device Guide — V01.01
1.5 Device Memory Map
Table 1-1 and Figure 1-2 show the device memory map of the MC9S12A256 after reset. Note that after
reset the bottom 1K of the EEPROM ($0000 - $03FF) are hidden by the register space.
Table 1-1 Device Memory Map
Size
(Bytes)
Address
Module
$0000 - $0017 CORE (Ports A, B, E, Modes, Inits, Test)
$0018 - $0019 Reserved
24
2
$001A - $001B Device ID register (PARTID)
$001C - $001F CORE (MEMSIZ, IRQ, HPRIO)
$0020 - $0027 Reserved
2
4
8
$0028 - $002F CORE (Background Debug Mode)
$0030 - $0033 CORE (PPAGE, Port K)
8
4
$0034 - $003F Clock and Reset Generator (PLL, RTI, COP)
$0040 - $007F Enhanced Capture Timer 16-bit 8 channels
$0080 - $009F Analog to Digital Converter 10-bit 8 channels (ATD0)
$00A0 - $00C7 Pulse Width Modulator 8-bit 8 channels (PWM)
$00C8 - $00CF Serial Communications Interface 0 (SCI0)
$00D0 - $00D7 Serial Communications Interface 0 (SCI1)
$00D8 - $00DF Serial Peripheral Interface (SPI0)
$00E0 - $00E7 Inter IC Bus
12
64
32
40
8
8
8
8
$00E8 - $00EF Reserved
8
$00F0 - $00F7 Serial Peripheral Interface (SPI1)
$00F8 - $00FF Serial Peripheral Interface (SPI2)
$0100- $010F Flash Control Register
8
8
16
12
4
$0110 - $011B EEPROM Control Register
$011C - $011F Reserved
$0120 - $013F Analog to Digital Converter 10-bit 8 channels (ATD1)
$0140 - $023F Reserved
32
256
64
384
4096
12288
$0240 - $027F Port Integration Module (PIM)
$0280 - $03FF Reserved
$0000 - $0FFF EEPROM array
$1000 - $3FFF RAM array
Fixed Flash EEPROM array
$4000 - $7FFF
16384
16384
incl. 0.5K, 1K, 2K or 4K Protected Sector at start
$8000 - $BFFF Flash EEPROM Page Window
Fixed Flash EEPROM array
$C000 - $FFFF incl. 0.5K, 1K, 2K or 4K Protected Sector at end
and 256 bytes of Vector Space at $FF80 - $FFFF
16384
20
MC9S12A256 Device Guide — V01.01
Figure 1-2 MC9S12A256 Memory Map
$0000
$0000
$0400
REGISTERS
(Mappable to any 2k Block
within the first 32K)
$03FF
$0000
4K Bytes EEPROM
$1000
$4000
(Mappable to any 4K Block)
$0FFF
$1000
12K Bytes RAM
(Mappable to any 16K
and alignable to top or
bottom)
$3FFF
$4000
16K Fixed Flash
Page $3E = 62
(This is dependant on the
state of the ROMHM bit)
$7FFF
$8000
$8000
16K Page Window
16 x 16K Flash EEPROM
pages
EXTERN
$BFFF
$C000
$C000
16K Fixed Flash
Page $3F = 63
$FFFF
$FF00
BDM
$FF00
$FFFF
(if active)
$FFFF
VECTORS
VECTORS
VECTORS
SPECIAL
SINGLE CHIP
EXPANDED*
NORMAL
SINGLE CHIP
* Assuming that a ‘0’ was driven onto port K bit 7 during MCU reset is reset into
normal expanded wide or narrow mode.
21
MC9S12A256 Device Guide — V01.01
1.6 Part ID Assignments
The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses $001A and $001B after
reset). The read-only value is a unique part ID for each revision of the chip. Table 1-2 shows the assigned
part ID number.
Table 1-2 Assigned Part ID Numbers
1
Device
Mask Set Number
Part ID
$0010
$0011
MC9S12A256
MC9S12A256
NOTES:
1. The coding is as follows:
Bit 15-12: Major family identifier
Bit 11-8: Minor family identifier
Bit 7-4: Major mask set revision number including FAB transfers
Bit 3-0: Minor - non full - mask set revision
The device memory sizes are located in two 8-bit registers MEMSIZ0 and MEMSIZ1 (addresses $001C
and $001D after reset). Table 1-3 shows the read-only values of these registers. Refer to the HCS12 Core
User Guide (Motorola order number, HCS12COREUG/D) for further details.
Table 1-3 Memory Size Registers
Register name
MEMSIZ0
Value
$25
MEMSIZ1
$81
22
MC9S12A256 Device Guide — V01.01
Section 2 Signal Description
This section describes signals that connect off-chip. It includes a pinout diagram, a table of signal
properties, and detailed discussion of signals. It is built from the signal description sections of the Block
User Guides of the individual IP blocks on the device.
2.1 Device Pinout
The MC9S12A256 is available in a 112-pin low profile quad flat pack (LQFP) and is also available in a
80-pin quad flat pack (QFP). Most pins perform two or more functions, as described in the Signal
Descriptions. Figure 2-1 and Figure 2-2 show the pin assignments.
23
MC9S12A256 Device Guide — V01.01
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
SS1/PWM3/KWP3/PP3
SCK1/PWM2/KWP2/PP2
MOSI1/PWM1/KWP1/PP1
MISO1/PWM0/KWP0/PP0
XADDR17/PK3
XADDR16/PK2
XADDR15/PK1
XADDR14/PK0
IOC0/PT0
1
2
3
4
5
6
7
8
VRH
VDDA
PAD15/AN15/ETRIG1
PAD07/AN07/ETRIG0
PAD14/AN14
PAD06/AN06
PAD13/AN13
PAD05/AN05
PAD12/AN12
PAD04/AN04
PAD11/AN11
PAD03/AN03
PAD10/AN10
PAD02/AN02
PAD09/AN09
PAD01/AN01
PAD08/AN08
9
IOC1/PT1
IOC2/PT2
IOC3/PT3
VDD1
VSS1
IOC4/PT4
IOC5/PT5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
MC9S12A256
IOC6/PT6
IOC7/PT7
PAD00/AN00
VSS2
VDD2
XADDR19/PK5
XADDR18/PK4
KWJ1/PJ1
PA7/ADDR15/DATA15
PA6/ADDR14/DATA14
PA5/ADDR13/DATA13
PA4/ADDR12/DATA12
PA3/ADDR11/DATA11
PA2/ADDR10/DATA10
PA1/ADDR9/DATA9
PA0/ADDR8/DATA8
KWJ0/PJ0
MODC/TAGHI/BKGD
ADDR0/DATA0/PB0
ADDR1/DATA1/PB1
ADDR2/DATA2/PB2
ADDR3/DATA3/PB3
ADDR4/DATA4/PB4
Signals shown in Bold are not available on the 80 Pin Package
Figure 2-1 Pin Assignments in 112-Pin LQFP
24
MC9S12A256 Device Guide — V01.01
60
59
58
57
SS1/PWM3/KWP3/PP3
SCK1/PWM2/KWP2/PP2
MOSI1/PWM1/KWP1/PP1
MISO1/PWM0/KWP0/PP0
IOC0/PT0
1
2
3
4
VRH
VDDA
PAD07/AN07/ETRIG0
PAD06/AN06
56
5
PAD05/AN05
55
IOC1/PT1
6
PAD04/AN04
54
IOC2/PT2
7
PAD03/AN03
53
IOC3/PT3
8
PAD02/AN02
52
VDD1
9
PAD01/AN01
51
50
49
48
47
46
45
44
VSS1
IOC4/PT4
IOC5/PT5
IOC6/PT6
10
11
12
13
14
15
16
17
18
19
20
PAD00/AN00
VSS2
VDD2
PA7/ADDR15/DATA15
PA6/ADDR14/DATA14
PA5/ADDR13/DATA13
PA4/ADDR12/DATA12
PA3/ADDR11/DATA11
MC9S12A256
IOC7/PT7
MODC/TAGHI/BKGD
ADDR0/DATA0/PB0
ADDR1/DATA1/PB1
ADDR2/DATA2/PB2
ADDR3/DATA3/PB3
ADDR4/DATA4/PB4
43
42
41
PA2/ADDR10/DATA10
PA1/ADDR9/DATA9
PA0/ADDR8/DATA8
Figure 2-2 Pin Assignments in 80-Pin QFP for MC9S12A256
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MC9S12A256 Device Guide — V01.01
2.2 Signal Properties Summary
Table 2-1 summarizes the pin functionality. Signals shown in bold are not available in the 80 pin
package.
Table 2-1 Signal Properties
Pin Name
Pin Name
Pin Name
Function 3
Pin Name
Function 4
Powered by
Description
Function 1 Function 2
EXTAL
XTAL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
V
Oscillator Pins
DDPLL
V
RESET
TEST
External Reset
Test Input
DDR
N.A.
V
V
Voltage Regulator Enable Input
PLL Loop Filter
REGEN
DDX
V
XFC
—
—
—
—
DDPLL
V
BKGD
TAGHI
MODC
Background Debug, Tag High, Mode Input
DDR
Port AD Input, Analog Input AN7 of
ATD1, External Trigger Input of ATD1
PAD15
PAD[14:8]
PAD07
AN15
AN[14:08]
AN07
ETRIG1
—
—
—
—
—
—
Port AD Inputs, Analog Inputs AN[6:0]
of ATD1
—
ETRIG0
—
V
DDA
Port AD Input, Analog Input AN7 of ATD0,
External Trigger Input of ATD0
Port AD Inputs, Analog Inputs AN[6:0] of
ATD0
PAD[06:00]
PA[7:0]
AN[06:00]
ADDR[15:8]/
DATA[15:8]
—
Port A I/O, Multiplexed Address/Data
Port B I/O, Multiplexed Address/Data
ADDR[7:0]/
DATA[7:0]
PB[7:0]
—
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
PH7
PH6
PH5
PH4
PH3
PH2
PH1
PH0
NOACC
IPIPE1
IPIPE0
ECLK
LSTRB
R/W
XCLKS
MODB
MODA
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Port E I/O, Access, Clock Select
Port E I/O, Pipe Status, Mode Input
Port E I/O, Pipe Status, Mode Input
Port E I/O, Bus Clock Output
TAGLO
—
Port E I/O, Byte Strobe, Tag Low
Port E I/O, R/W in expanded modes
Port E Input, Maskable Interrupt
Port E Input, Non Maskable Interrupt
Port H I/O, Interrupt, SS of SPI2
Port H I/O, Interrupt, SCK of SPI2
Port H I/O, Interrupt, MOSI of SPI2
Port H I/O, Interrupt, MISO of SPI2
Port H I/O, Interrupt, SS of SPI1
Port H I/O, Interrupt, SCK of SPI1
Port H I/O, Interrupt, MOSI of SPI1
Port H I/O, Interrupt, MISO of SPI1
V
DDR
IRQ
—
XIRQ
—
KWH7
KWH6
KWH5
KWH4
KWH3
KWH2
KWH1
KWH0
SS2
SCK2
MOSI2
MISO2
SS1
SCK1
MOSI1
MISO1
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MC9S12A256 Device Guide — V01.01
Pin Name
Pin Name
Pin Name
Function 3
Pin Name
Function 4
Powered by
Description
Function 1 Function 2
PJ7
PJ6
KWJ7
KWJ6
SCL
SDA
—
Port J I/O, Interrupt, SCL of IIC
Port J I/O, Interrupt, SDA of IIC
Port J I/O, Interrupts
PJ[1:0]
KWJ[1:0]
—
—
Port K I/O, Emulation Chip Select, ROM
On Enable
PK7
ECS
ROMONE
PK[5:0]
PM7
PM6
PM5
PM4
PM3
PM2
PM1
PM0
XADDR[19:14]
—
—
—
—
—
—
—
—
—
Port K I/O, Extended Addresses
Port M I/O
—
—
—
—
—
—
—
—
—
—
Port M I/O
SCK0
MOSI0
SS0
MISO0
—
Port M I/O, SCK of SPI0
Port M I/O, MOSI of SPI0
Port M I/O, SS of SPI0
Port M I/O, MISO of SPI0
Port M I/O
—
Port M I/O
Port P I/O, Interrupt, Channel 7 of PWM,
SCK of SPI2
PP7
PP6
PP5
PP4
PP3
PP2
PP1
PP0
KWP7
KWP6
KWP5
KWP4
KWP3
KWP2
KWP1
KWP0
PWM7
PWM6
PWM5
PWM4
PWM3
PWM2
PWM1
PWM0
SCK2
SS2
Port P I/O, Interrupt, Channel 6 of PWM,
SS of SPI2
Port P I/O, Interrupt, Channel 5 of PWM,
MOSI of SPI2
MOSI2
MISO2
SS1
VDDX
Port P I/O, Interrupt, Channel 4 of PWM,
MISO2 of SPI2
Port P I/O, Interrupt, Channel 3 of PWM,
SS of SPI1
Port P I/O, Interrupt, Channel 2 of PWM,
SCK of SPI1
SCK1
MOSI1
MISO1
Port P I/O, Interrupt, Channel 1 of PWM,
MOSI of SPI1
Port P I/O, Interrupt, Channel 0 of PWM,
MISO2 of SPI1
PS7
PS6
SS0
SCK0
MOSI0
MISO0
TXD1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Port S I/O, SS of SPI0
Port S I/O, SCK of SPI0
Port S I/O, MOSI of SPI0
Port S I/O, MISO of SPI0
Port S I/O, TXD of SCI1
Port S I/O, RXD of SCI1
Port S I/O, TXD of SCI0
Port S I/O, RXD of SCI0
Port T I/O, Timer channels
PS5
PS4
PS3
PS2
RXD1
TXD0
PS1
PS0
RXD0
IOC[7:0]
PT[7:0]
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MC9S12A256 Device Guide — V01.01
2.3 Detailed Signal Descriptions
2.3.1 EXTAL, XTAL — Oscillator Pins
EXTAL and XTAL are the crystal driver and external clock pins. On reset all the device clocks are derived
from the EXTAL input frequency. XTAL is the crystal output.
2.3.2 RESET — External Reset Pin
An active low bidirectional control signal, it acts as an input to initialize the MCU to a known start-up state,
and an output when an internal MCU function causes a reset.
2.3.3 TEST — Test Pin
This input only pin is reserved for test.
NOTE: The TEST pin must be tied to VSS in all applications.
2.3.4 VREGEN — Voltage Regulator Enable Pin
This input only pin enables or disables the on-chip voltage regulator.
2.3.5 XFC — PLL Loop Filter Pin
PLL loop filter, see A.5.3 Phase Locked Loop. If needed, contact your Motorola representative for the
interactive application note to compute PLL loop filter elements. Any current leakage on this pin must be
avoided.
XFC
R
0
C
P
MCU
C
S
V
V
DDPLL
DDPLL
Figure 2-3 PLL Loop Filter Connections
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MC9S12A256 Device Guide — V01.01
2.3.6 BKGD / TAGHI / MODC — Background Debug, Tag High, and Mode Pin
The BKGD/TAGHI/MODC pin is used as a pseudo-open-drain pin for the background debug
communication. In MCU expanded modes of operation when instruction tagging is on, an input low on
this pin during the falling edge of E-clock tags the high half of the instruction word being read into the
instruction queue. It is used as a MCU operating mode select pin during reset. The state of this pin is
latched to the MODC bit at the rising edge of RESET.
2.3.7 PAD15 / AN15 / ETRIG1 — Port AD Input Pin of ATD1
PAD15 is a general purpose input pin and analog input AN7 of the analog to digital converter ATD1. It
can act as an external trigger input for the ATD1.
2.3.8 PAD[14:08] / AN[14:08] — Port AD Input Pins of ATD1
PAD14 - PAD08 are general purpose input pins and analog inputs AN[6:0] of the analog to digital
converter ATD1.
2.3.9 PAD7 / AN07 / ETRIG0 — Port AD Input Pin of ATD0
PAD7 is a general purpose input pin and analog input AN7 of the analog to digital converter ATD0. It can
act as an external trigger input for the ATD0.
2.3.10 PAD[06:00] / AN[06:00] — Port AD Input Pins of ATD0
PAD06 - PAD00 are general purpose input pins and analog inputs AN[6:0] of the analog to digital
converter ATD0.
2.3.11 PA[7:0] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins
PA7-PA0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are
used for the multiplexed external address and data bus.
2.3.12 PB[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins
PB7-PB0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are
used for the multiplexed external address and data bus.
2.3.13 PE7 / NOACC / XCLKS — Port E I/O Pin 7
PE7 is a general purpose input or output pin. During MCU expanded modes of operation, the NOACC
signal, when enabled, is used to indicate that the current bus cycle is an unused or “free” cycle. This signal
will assert when the CPU is not using the bus.
The XCLKS input selects between an external clock or oscillator configuration. The state of this pin is
latched at the rising edge of RESET. If the input is a logic low the EXTAL pin is configured for an external
29
MC9S12A256 Device Guide — V01.01
clock drive. If input is a logic high an oscillator circuit is configured on EXTAL and XTAL. Since this pin
is an input with a pull-up device, if the pin is left floating, the default configuration is an oscillator circuit
on EXTAL and XTAL.
2.3.14 PE6 / MODB / IPIPE1 — Port E I/O Pin 6
PE6 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset.
The state of this pin is latched to the MODB bit at the rising edge of RESET. This pin is shared with the
instruction queue tracking signal IPIPE1. This pin is an input with a pull-down device which is only active
when RESET is low.
2.3.15 PE5 / MODA / IPIPE0 — Port E I/O Pin 5
PE5 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset.
The state of this pin is latched to the MODA bit at the rising edge of RESET. This pin is shared with the
instruction queue tracking signal IPIPE0. This pin is an input with a pull-down device which is only active
when RESET is low.
2.3.16 PE4 / ECLK — Port E I/O Pin 4
PE4 is a general purpose input or output pin. It can be configured to drive the internal bus clock ECLK.
ECLK can be used as a timing reference.
2.3.17 PE3 / LSTRB / TAGLO — Port E I/O Pin 3
PE3 is a general purpose input or output pin. In MCU expanded modes of operation, LSTRB can be used
for the low-byte strobe function to indicate the type of bus access and when instruction tagging is on,
TAGLO is used to tag the low half of the instruction word being read into the instruction queue.
2.3.18 PE2 / R/W — Port E I/O Pin 2
PE2 is a general purpose input or output pin. In MCU expanded modes of operations, this pin drives the
read/write output signal for the external bus. It indicates the direction of data on the external bus.
2.3.19 PE1 / IRQ — Port E Input Pin 1
PE1 is a general purpose input pin and the maskable interrupt request input that provides a means of
applying asynchronous interrupt requests. This will wake up the MCU from STOP or WAIT mode.
2.3.20 PE0 / XIRQ — Port E Input Pin 0
PE0 is a general purpose input pin and the non-maskable interrupt request input that provides a means of
applying asynchronous interrupt requests. This will wake up the MCU from STOP or WAIT mode.
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MC9S12A256 Device Guide — V01.01
2.3.21 PH7 / KWH7 / SS2 — Port H I/O Pin 7
PH7 is a general purpose input or output pin. It can be configured to generate an interrupt causing the
MCU to exit STOP or WAIT mode. It can be configured as slave select pin SS of the Serial Peripheral
Interface 2 (SPI2).
2.3.22 PH6 / KWH6 / SCK2 — Port H I/O Pin 6
PH6 is a general purpose input or output pin. It can be configured to generate an interrupt causing the
MCU to exit STOP or WAIT mode. It can be configured as serial clock pin SCK of the Serial Peripheral
Interface 2 (SPI2).
2.3.23 PH5 / KWH5 / MOSI2 — Port H I/O Pin 5
PH5 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as master output (during master mode) or slave input
pin (during slave mode) MOSI of the Serial Peripheral Interface 2 (SPI2).
2.3.24 PH4 / KWH4 / MISO2 — Port H I/O Pin 4
PH4 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as master input (during master mode) or slave output
(during slave mode) pin MISO of the Serial Peripheral Interface 2 (SPI2).
2.3.25 PH3 / KWH3 / SS1 — Port H I/O Pin 3
PH3 is a general purpose input or output pin. It can be configured to generate an interrupt causing the
MCU to exit STOP or WAIT mode. It can be configured as slave select pin SS of the Serial Peripheral
Interface 1 (SPI1).
2.3.26 PH2 / KWH2 / SCK1 — Port H I/O Pin 2
PH2 is a general purpose input or output pin. It can be configured to generate an interrupt causing the
MCU to exit STOP or WAIT mode. It can be configured as serial clock pin SCK of the Serial Peripheral
Interface 1 (SPI1).
2.3.27 PH1 / KWH1 / MOSI1 — Port H I/O Pin 1
PH1 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as master output (during master mode) or slave input
pin (during slave mode) MOSI of the Serial Peripheral Interface 1 (SPI1).
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MC9S12A256 Device Guide — V01.01
2.3.28 PH0 / KWH0 / MISO1 — Port H I/O Pin 0
PH0 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as master input (during master mode) or slave output
(during slave mode) pin MISO of the Serial Peripheral Interface 1 (SPI1).
2.3.29 PJ7 / KWJ7 / SCL — PORT J I/O Pin 7
PJ7 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as the serial clock pin SCL of the IIC module.
2.3.30 PJ6 / KWJ6 / SDA — PORT J I/O Pin 6
PJ6 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as the serial data pin SDA of the IIC module.
2.3.31 PJ[1:0] / KWJ[1:0] — Port J I/O Pins [1:0]
PJ1 and PJ0 are general purpose input or output pins. They can be configured to generate an interrupt
causing the MCU to exit STOP or WAIT mode.
2.3.32 PK7 / ECS / ROMONE — Port K I/O Pin 7
PK7 is a general purpose input or output pin. During MCU expanded modes of operation, this pin is used
as the emulation chip select output (ECS). During MCU normal expanded modes of operation, this pin is
used to enable the Flash EEPROM memory in the memory map (ROMONE). At the rising edge of RESET,
the state of this pin is latched to the ROMON bit.
2.3.33 PK[5:0] / XADDR[19:14] — Port K I/O Pins [5:0]
PK5-PK0 are general purpose input or output pins. In MCU expanded modes of operation, these pins
provide the expanded address XADDR[19:14] for the external bus.
2.3.34 PM7 — Port M I/O Pin 7
PM7 is a general purpose input or output pin.
2.3.35 PM6 — Port M I/O Pin 6
PM6 is a general purpose input or output pin.
2.3.36 PM5 / SCK0 — Port M I/O Pin 5
PM5 is a general purpose input or output pin. It can be configured as the serial clock pin SCK of the Serial
Peripheral Interface 0 (SPI0).
32
MC9S12A256 Device Guide — V01.01
2.3.37 PM4 / MOSI0 — Port M I/O Pin 4
PM4 is a general purpose input or output pin. It can be configured as the master output (during master
mode) or slave input pin (during slave mode) MOSI for the Serial Peripheral Interface 0 (SPI0).
2.3.38 PM3 / SS0 — Port M I/O Pin 3
PM3 is a general purpose input or output pin. It can be configured as the slave select pin SS of the Serial
Peripheral Interface 0 (SPI0).
2.3.39 PM2 / MISO0 — Port M I/O Pin 2
PM2 is a general purpose input or output pin. It can be configured as the master input (during master mode)
or slave output pin (during slave mode) MISO for the Serial Peripheral Interface 0 (SPI0).
2.3.40 PM1 — Port M I/O Pin 1
PM1 is a general purpose input or output pin.
2.3.41 PM0 — Port M I/O Pin 0
PM0 is a general purpose input or output pin.
2.3.42 PP7 / KWP7 / PWM7 / SCK2 — Port P I/O Pin 7
PP7 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 7 output. It
can be configured as serial clock pin SCK of the Serial Peripheral Interface 2 (SPI2).
2.3.43 PP6 / KWP6 / PWM6 / SS2 — Port P I/O Pin 6
PP6 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 6 output. It
can be configured as slave select pin SS of the Serial Peripheral Interface 2 (SPI2).
2.3.44 PP5 / KWP5 / PWM5 / MOSI2 — Port P I/O Pin 5
PP5 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 5 output. It
can be configured as master output (during master mode) or slave input pin (during slave mode) MOSI of
the Serial Peripheral Interface 2 (SPI2).
33
MC9S12A256 Device Guide — V01.01
2.3.45 PP4 / KWP4 / PWM4 / MISO2 — Port P I/O Pin 4
PP4 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 4 output. It
can be configured as master input (during master mode) or slave output (during slave mode) pin MISO of
the Serial Peripheral Interface 2 (SPI2).
2.3.46 PP3 / KWP3 / PWM3 / SS1 — Port P I/O Pin 3
PP3 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 3 output. It
can be configured as slave select pin SS of the Serial Peripheral Interface 1 (SPI1).
2.3.47 PP2 / KWP2 / PWM2 / SCK1 — Port P I/O Pin 2
PP2 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 2 output. It
can be configured as serial clock pin SCK of the Serial Peripheral Interface 1 (SPI1).
2.3.48 PP1 / KWP1 / PWM1 / MOSI1 — Port P I/O Pin 1
PP1 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 1 output. It
can be configured as master output (during master mode) or slave input pin (during slave mode) MOSI of
the Serial Peripheral Interface 1 (SPI1).
2.3.49 PP0 / KWP0 / PWM0 / MISO1 — Port P I/O Pin 0
PP0 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU
to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 0 output. It
can be configured as master input (during master mode) or slave output (during slave mode) pin MISO of
the Serial Peripheral Interface 1 (SPI1).
2.3.50 PS7 / SS0 — Port S I/O Pin 7
PS6 is a general purpose input or output pin. It can be configured as the slave select pin SS of the Serial
Peripheral Interface 0 (SPI0).
2.3.51 PS6 / SCK0 — Port S I/O Pin 6
PS6 is a general purpose input or output pin. It can be configured as the serial clock pin SCK of the Serial
Peripheral Interface 0 (SPI0).
34
MC9S12A256 Device Guide — V01.01
2.3.52 PS5 / MOSI0 — Port S I/O Pin 5
PS5 is a general purpose input or output pin. It can be configured as master output (during master mode)
or slave input pin (during slave mode) MOSI of the Serial Peripheral Interface 0 (SPI0).
2.3.53 PS4 / MISO0 — Port S I/O Pin 4
PS4 is a general purpose input or output pin. It can be configured as master input (during master mode) or
slave output pin (during slave mode) MOSI of the Serial Peripheral Interface 0 (SPI0).
2.3.54 PS3 / TXD1 — Port S I/O Pin 3
PS3 is a general purpose input or output pin. It can be configured as the transmit pin TXD of Serial
Communication Interface 1 (SCI1).
2.3.55 PS2 / RXD1 — Port S I/O Pin 2
PS2 is a general purpose input or output pin. It can be configured as the receive pin RXD of Serial
Communication Interface 1 (SCI1).
2.3.56 PS1 / TXD0 — Port S I/O Pin 1
PS1 is a general purpose input or output pin. It can be configured as the transmit pin TXD of Serial
Communication Interface 0 (SCI0).
2.3.57 PS0 / RXD0 — Port S I/O Pin 0
PS0 is a general purpose input or output pin. It can be configured as the receive pin RXD of Serial
Communication Interface 0 (SCI0).
2.3.58 PT[7:0] / IOC[7:0] — Port T I/O Pins [7:0]
PT7-PT0 are general purpose input or output pins. They can be configured as input capture or output
compare pins IOC7-IOC0 of the Enhanced Capture Timer (ECT).
2.4 Power Supply Pins
MC9S12A256 power and ground pins are described below.
NOTE: All VSS pins must be connected together in the application.
35
MC9S12A256 Device Guide — V01.01
2.4.1 VDDX, VSSX — Power & Ground Pins for I/O Drivers
External power and ground for I/O drivers. Because fast signal transitions place high, short-duration
current demands on the power supply, use bypass capacitors with high-frequency characteristics and place
them as close to the MCU as possible. Bypass requirements depend on how heavily the MCU pins are
loaded.
2.4.2 VDDR, VSSR — Power & Ground Pins for I/O Drivers & for Internal
Voltage Regulator
External power and ground for I/O drivers and input to the internal voltage regulator. Because fast signal
transitions place high, short-duration current demands on the power supply, use bypass capacitors with
high-frequency characteristics and place them as close to the MCU as possible. Bypass requirements
depend on how heavily the MCU pins are loaded.
2.4.3 VDD1, VDD2, VSS1, VSS2 — Core Power Pins
Power is supplied to the MCU through VDD and VSS. Because fast signal transitions place high,
short-duration current demands on the power supply, use bypass capacitors with high-frequency
characteristics and place them as close to the MCU as possible. This 2.5V supply is derived from the
internal voltage regulator. There is no static load on those pins allowed. The internal voltage regulator is
turned off, if VREGEN is tied to ground.
NOTE: No load allowed except for bypass capacitors.
2.4.4 VDDA, VSSA — Power Supply Pins for ATD and VREG
VDDA, VSSA are the power supply and ground input pins for the voltage regulator and the analog to digital
converter. It also provides the reference for the internal voltage regulator. This allows the supply voltage
to the ATD and the reference voltage to be bypassed independently.
2.4.5 VRH, VRL — ATD Reference Voltage Input Pins
VRH and VRL are the reference voltage input pins for the analog to digital converter.
2.4.6 VDDPLL, VSSPLL — Power Supply Pins for PLL
Provides operating voltage and ground for the Oscillator and the Phased-Locked Loop. This allows the
supply voltage to the Oscillator and PLL to be bypassed independently.This 2.5V voltage is generated by
the internal voltage regulator.
NOTE: No load allowed except for bypass capacitors.
36
MC9S12A256 Device Guide — V01.01
2.4.7 VREGEN — On Chip Voltage Regulator Enable
Enables the internal 5V to 2.5V voltage regulator. If this pin is tied low, VDD1,2 and VDDPLL must be
supplied externally.
Table 2-2 MC9S12A256 Power and Ground Connection Summary
Pin Number
Nominal
Voltage
Mnemonic
Description
112-pin QFP
V
V
13, 65
14, 66
41
2.5 V
0V
DD1, 2
Internal power and ground generated by internal regulator
SS1, 2
V
5.0 V
0 V
External power and ground, supply to pin drivers and internal
voltage regulator.
DDR
SSR
DDX
V
40
V
107
106
83
5.0 V
0 V
External power and ground, supply to pin drivers.
V
V
SSX
5.0 V
Operating voltage and ground for the analog-to-digital
converters and the reference for the internal voltage regulator,
allows the supply voltage to the A/D to be bypassed
independently.
DDA
V
86
0 V
SSA
V
85
84
43
0 V
RL
Reference voltages for the analog-to-digital converter.
V
5.0 V
2.5 V
RH
V
V
Provides operating voltage and ground for the Phased-Locked
Loop. This allows the supply voltage to the PLL to be
bypassed independently. Internal power and ground
generated by internal regulator.
DDPLL
SSPLL
REGEN
45
97
0 V
5V
V
Internal Voltage Regulator enable/disable
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MC9S12A256 Device Guide — V01.01
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MC9S12A256 Device Guide — V01.01
Section 3 System Clock Description
3.1 Overview
The Clock and Reset Generator provides the internal clock signals for the core and all peripheral modules.
Figure 3-1 shows the clock connections from the CRG to all modules.
Consult the HCS12 Clock and Reset Generator (CRG) Block Guide (Motorola document order number,
S12CRGV3/D) for details on clock generation.
1/2
BDM
S12_CORE
core clock
Flash
RAM
EEPROM
ECT
ATD0, 1
PWM
EXTAL
XTAL
bus clock
CRG
SCI0, SCI1
SPI0, 1, 2
IIC
oscillator clock
PIM
Figure 3-1 Clock Connections
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MC9S12A256 Device Guide — V01.01
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Section 4 Modes of Operation
4.1 Overview
Eight possible modes determine the operating configuration of the MC9S12A256. Each mode has an
associated default memory map and external bus configuration.
Three low power modes exist for the device.
4.2 Modes of Operation
The operating mode out of reset is determined by the states of the MODC, MODB, and MODA pins during
reset (Table 4-1). The MODC, MODB, and MODA bits in the MODE register show the current operating
mode and provide limited mode switching during operation. The states of the MODC, MODB, and MODA
pins are latched into these bits on the rising edge of the reset signal.
Table 4-1 Mode Selection
MODC
MODB
MODA
Mode Description
Special Single Chip, BDM allowed and ACTIVE. BDM is allowed in all
other modes but a serial command is required to make BDM active.
0
0
0
0
0
0
1
1
0
1
1
0
0
1
0
1
0
1
Emulation Expanded Narrow, BDM allowed
Special Test (Expanded Wide), BDM allowed
Emulation Expanded Wide, BDM allowed
Normal Single Chip, BDM allowed
Normal Expanded Narrow, BDM allowed
Peripheral; BDM allowed but bus operations would cause bus conflicts
(must not be used)
1
1
1
1
0
1
Normal Expanded Wide, BDM allowed
There are two basic types of operating modes:
1. Normal modes: Some registers and bits are protected against accidental changes.
2. Special modes: Allow greater access to protected control registers and bits for special purposes such
as testing.
A system development and debug feature, background debug mode (BDM), is available in all modes. In
special single-chip mode, BDM is active immediately after reset.
Some aspects of Port E are not mode dependent. Bit 1 of Port E is a general purpose input or the IRQ
interrupt input. IRQ can be enabled by bits in the CPU’s condition codes register but it is inhibited at reset
so this pin is initially configured as a simple input with a pull-up. Bit 0 of Port E is a general purpose input
or the XIRQ interrupt input. XIRQ can be enabled by bits in the CPU’s condition codes register but it is
inhibited at reset so this pin is initially configured as a simple input with a pull-up. The ESTR bit in the
EBICTL register is set to one by reset in any user mode.This assures that the reset vector can be fetched
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MC9S12A256 Device Guide — V01.01
even if it is located in an external slow memory device. The PE6/MODB/IPIPE1 and PE5/MODA/IPIPE0
pins act as high-impedance mode select inputs during reset.
The following paragraphs discuss the default bus setup and describe which aspects of the bus can be
changed after reset on a per mode basis.
4.2.1 Normal Operating Modes
These modes provide three operating configurations. Background debug is available in all three modes,
but must first be enabled for some operations by means of a BDM background command, then activated.
4.2.1.1 Normal Single-Chip Mode
There is no external expansion bus in this mode. All pins of Ports A, B and E are configured as general
purpose I/O pins Port E bits 1 and 0 are available as general purpose input only pins with internal pull-ups
enabled. All other pins of Port E are bidirectional I/O pins that are initially configured as high-impedance
inputs with internal pull-ups enabled. Ports A and B are configured as high-impedance inputs with their
internal pull-ups disabled.
The pins associated with Port E bits 6, 5, 3, and 2 cannot be configured for their alternate functions IPIPE1,
IPIPE0, LSTRB, and R/W while the MCU is in single chip modes. In single chip modes, the associated
control bits PIPOE, LSTRE, and RDWE are reset to zero. Writing the opposite state into them in single
chip mode does not change the operation of the associated Port E pins.
In normal single chip mode, the MODE register is writable one time. This allows a user program to change
the bus mode to narrow or wide expanded mode and/or turn on visibility of internal accesses.
Port E, bit 4 can be configured for a free-running E clock output by clearing NECLK=0. Typically the only
use for an E clock output while the MCU is in single chip modes would be to get a constant speed clock
for use in the external application system.
4.2.1.2 Normal Expanded Wide Mode
In expanded wide modes, Ports A and B are configured as a 16-bit multiplexed address and data bus and
Port E bit 4 is configured as the E clock output signal. These signals allow external memory and peripheral
devices to be interfaced to the MCU.
Port E pins other than PE4/ECLK are configured as general purpose I/O pins (initially high-impedance
inputs with internal pull-up resistors enabled). Control bits PIPOE, NECLK, LSTRE, and RDWE in the
PEAR register can be used to configure Port E pins to act as bus control outputs instead of general purpose
I/O pins.
It is possible to enable the pipe status signals on Port E bits 6 and 5 by setting the PIPOE bit in PEAR, but
it would be unusual to do so in this mode. Development systems where pipe status signals are monitored
would typically use the special variation of this mode.
The Port E bit 2 pin can be reconfigured as the R/W bus control signal by writing “1” to the RDWE bit in
PEAR. If the expanded system includes external devices that can be written, such as RAM, the RDWE bit
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MC9S12A256 Device Guide — V01.01
would need to be set before any attempt to write to an external location. If there are no writable resources
in the external system, PE2 can be left as a general purpose I/O pin.
The Port E bit 3 pin can be reconfigured as the LSTRB bus control signal by writing “1” to the LSTRE bit
in PEAR. The default condition of this pin is a general purpose input because the LSTRB function is not
needed in all expanded wide applications.
The Port E bit 4 pin is initially configured as ECLK output with stretch. The E clock output function
depends upon the settings of the NECLK bit in the PEAR register, the IVIS bit in the MODE register and
the ESTR bit in the EBICTL register. The E clock is available for use in external select decode logic or as
a constant speed clock for use in the external application system.
4.2.1.3 Normal Expanded Narrow Mode
This mode is used for lower cost production systems that use 8-bit wide external EPROMs or RAMs. Such
systems take extra bus cycles to access 16-bit locations but this may be preferred over the extra cost of
additional external memory devices.
Ports A and B are configured as a 16-bit address bus and Port A is multiplexed with data. Internal visibility
is not available in this mode because the internal cycles would need to be split into two 8-bit cycles.
Since the PEAR register can only be written one time in this mode, use care to set all bits to the desired
states during the single allowed write.
The PE3/LSTRB pin is always a general purpose I/O pin in normal expanded narrow mode. Although it
is possible to write the LSTRE bit in PEAR to “1” in this mode, the state of LSTRE is overridden and Port
E bit 3 cannot be reconfigured as the LSTRB output.
It is possible to enable the pipe status signals on Port E bits 6 and 5 by setting the PIPOE bit in PEAR, but
it would be unusual to do so in this mode. LSTRB would also be needed to fully understand system
activity. Development systems where pipe status signals are monitored would typically use special
expanded wide mode or occasionally special expanded narrow mode.
The PE4/ECLK pin is initially configured as ECLK output with stretch. The E clock output function
depends upon the settings of the NECLK bit in the PEAR register, the IVIS bit in the MODE register and
the ESTR bit in the EBICTL register. In normal expanded narrow mode, the E clock is available for use
in external select decode logic or as a constant speed clock for use in the external application system.
The PE2/R/W pin is initially configured as a general purpose input with a pull-up but this pin can be
reconfigured as the R/W bus control signal by writing “1” to the RDWE bit in PEAR. If the expanded
narrow system includes external devices that can be written such as RAM, the RDWE bit would need to
be set before any attempt to write to an external location. If there are no writable resources in the external
system, PE2 can be left as a general purpose I/O pin.
4.2.1.4 Internal Visibility
Internal visibility is available when the MCU is operating in expanded wide modes or emulation narrow
mode. It is not available in single-chip, peripheral or normal expanded narrow modes. Internal visibility is
enabled by setting the IVIS bit in the MODE register.
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MC9S12A256 Device Guide — V01.01
If an internal access is made while E, R/W, and LSTRB are configured as bus control outputs and internal
visibility is off (IVIS=0), E will remain low for the cycle, R/W will remain high, and address, data and the
LSTRB pins will remain at their previous state.
When internal visibility is enabled (IVIS=1), certain internal cycles will be blocked from going external.
During cycles when the BDM is selected, R/W will remain high, data will maintain its previous state, and
address and LSTRB pins will be updated with the internal value. During CPU no access cycles when the
BDM is not driving, R/W will remain high, and address, data and the LSTRB pins will remain at their
previous state.
4.2.1.5 Emulation Expanded Wide Mode
In expanded wide modes, Ports A and B are configured as a 16-bit multiplexed address and data bus and
Port E provides bus control and status signals. These signals allow external memory and peripheral devices
to be interfaced to the MCU. These signals can also be used by a logic analyzer to monitor the progress of
application programs.
The bus control related pins in Port E (PE7/NOACC, PE6/MODB/IPIPE1, PE5/MODA/IPIPE0,
PE4/ECLK, PE3/LSTRB/TAGLO, and PE2/R/W) are all configured to serve their bus control output
functions rather than general purpose I/O. Notice that writes to the bus control enable bits in the PEAR
register in emulation mode are restricted.
4.2.1.6 Emulation Expanded Narrow Mode
Expanded narrow modes are intended to allow connection of single 8-bit external memory devices for
lower cost systems that do not need the performance of a full 16-bit external data bus. Accesses to internal
resources that have been mapped external (i.e., PORTA, PORTB, DDRA, DDRB, PORTE, DDRE, PEAR,
PUCR, RDRIV) will be accessed with a 16-bit data bus on Ports A and B. Accesses of 16-bit external
words to addresses which are normally mapped external will be broken into two separate 8-bit accesses
using Port A as an 8-bit data bus. Internal operations continue to use full 16-bit data paths. They are only
visible externally as 16-bit information if IVIS=1.
Ports A and B are configured as multiplexed address and data output ports. During external accesses,
address A15, data D15 and D7 are associated with PA7, address A0 is associated with PB0 and data D8
and D0 are associated with PA0. During internal visible accesses and accesses to internal resources that
have been mapped external, address A15 and data D15 is associated with PA7 and address A0 and data
D0 is associated with PB0.
The bus control related pins in Port E (PE7/NOACC, PE6/MODB/IPIPE1, PE5/MODA/IPIPE0,
PE4/ECLK, PE3/LSTRB/TAGLO, and PE2/R/W) are all configured to serve their bus control output
functions rather than general purpose I/O. Notice that writes to the bus control enable bits in the PEAR
register in emulation mode are restricted.
The main difference between special modes and normal modes is that some of the bus control and system
control signals cannot be written in emulation modes.
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MC9S12A256 Device Guide — V01.01
4.2.2 Special Operating Modes
There are two special operating modes that correspond to normal operating modes. These operating modes
are commonly used in factory testing and system development.
4.2.2.1 Special Single-Chip Mode
When the MCU is reset in this mode, the background debug mode is enabled and active. The MCU does
not fetch the reset vector and execute application code as it would in other modes. Instead the active
background mode is in control of CPU execution and BDM firmware is waiting for additional serial
commands through the BKGD pin. When a serial command instructs the MCU to return to normal
execution, the system will be configured as described below unless the reset states of internal control
registers have been changed through background commands after the MCU was reset.
There is no external expansion bus after reset in this mode. Ports A and B are initially simple bidirectional
I/O pins that are configured as high-impedance inputs with internal pull-ups disabled; however, writing to
the mode select bits in the MODE register (which is allowed in special modes) can change this after reset.
All of the Port E pins (except PE4/ECLK) are initially configured as general purpose high-impedance
inputs with pull-ups enabled. PE4/ECLK is configured as the E clock output in this mode.
The pins associated with Port E bits 6, 5, 3, and 2 cannot be configured for their alternate functions IPIPE1,
IPIPE0, LSTRB, and R/W while the MCU is in single chip modes. In single chip modes, the associated
control bits PIPOE, LSTRE and RDWE are reset to zero. Writing the opposite value into these bits in
single chip mode does not change the operation of the associated Port E pins.
Port E, bit 4 can be configured for a free-running E clock output by clearing NECLK=0. Typically the only
use for an E clock output while the MCU is in single chip modes would be to get a constant speed clock
for use in the external application system.
4.2.2.2 Special Test Mode
In expanded wide modes, Ports A and B are configured as a 16-bit multiplexed address and data bus and
Port E provides bus control and status signals. In special test mode, the write protection of many control
bits is lifted so that they can be thoroughly tested without needing to go through reset.
4.2.3 Test Operating Mode
There is a test operating mode in which an external master, such as an I.C. tester, can control the on-chip
peripherals.
4.2.3.1 Peripheral Mode
This mode is intended for Motorola factory testing of the MCU. In this mode, the CPU is inactive and an
external (tester) bus master drives address, data and bus control signals in through Ports A, B and E. In
effect, the whole MCU acts as if it was a peripheral under control of an external CPU. This allows faster
testing of on-chip memory and peripherals than previous testing methods. Since the mode control register
is not accessible in peripheral mode, the only way to change to another mode is to reset the MCU into a
different mode. Background debugging should not be used while the MCU is in special peripheral mode
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MC9S12A256 Device Guide — V01.01
as internal bus conflicts between BDM and the external master can cause improper operation of both
functions.
4.3 Security
The device will make available a security feature preventing the unauthorized read and write of the
memory contents. This feature allows:
•
•
•
•
Protection of the contents of FLASH,
Protection of the contents of EEPROM,
Operation in single-chip mode,
Operation from external memory with internal FLASH and EEPROM disabled.
The user must be reminded that part of the security must lie with the user’s code. An extreme example
would be user’s code that dumps the contents of the internal program. This code would defeat the purpose
of security. At the same time the user may also wish to put a back door in the user’s program. An example
of this is the user downloads a key through the SCI which allows access to a programming routine that
updates parameters stored in EEPROM.
4.3.1 Securing the Microcontroller
Once the user has programmed the FLASH and EEPROM (if desired), the part can be secured by
programming the security bits located in the FLASH module. These non-volatile bits will keep the part
secured through resetting the part and through powering down the part.
The security byte resides in a portion of the Flash array.
Check the HCS12 256K FLASH Block Guide (Motorola document order number, S12FTS256KV2/D) for
more details on the security configuration.
4.3.2 Operation of the Secured Microcontroller
4.3.2.1 Normal Single Chip Mode
This will be the most common usage of the secured part. Everything will appear the same as if the part was
not secured with the exception of BDM operation. The BDM operation will be blocked.
4.3.2.2 Executing from External Memory
The user may wish to execute from external space with a secured microcontroller. This is accomplished
by resetting directly into expanded mode. The internal FLASH and EEPROM will be disabled. BDM
operations will be blocked.
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MC9S12A256 Device Guide — V01.01
4.3.3 Unsecuring the Microcontroller
In order to unsecure the microcontroller, the internal FLASH and EEPROM must be erased. This can be
done through an external program in expanded mode.
Once the user has erased the FLASH and EEPROM, the part can be reset into special single chip mode.
This invokes a program that verifies the erasure of the internal FLASH and EEPROM. Once this program
completes, the user can erase and program the FLASH security bits to the unsecured state. This is generally
done through the BDM, but the user could also change to expanded mode (by writing the mode bits
through the BDM) and jumping to an external program (again through BDM commands). Note that if the
part goes through a reset before the security bits are reprogrammed to the unsecure state, the part will be
secured again.
4.4 Low Power Modes
Consult the respective Block User Guide for information on the module behavior in Stop, Pseudo Stop,
and Wait Mode.
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Section 5 Resets and Interrupts
5.1 Overview
Consult the Exception Processing section of the HCS12 Core User Guide (Motorola order number,
HCS12COREUG/D) for information on resets and interrupts.
5.2 Vectors
5.2.1 Vector Table
Table 5-1 lists interrupt sources and vectors in default order of priority.
Table 5-1 Interrupt Vector Locations
CCR
Mask
HPRIO Value
to Elevate
Vector Address
Interrupt Source
Local Enable
$FFFE, $FFFF
$FFFC, $FFFD
$FFFA, $FFFB
$FFF8, $FFF9
$FFF6, $FFF7
$FFF4, $FFF5
$FFF2, $FFF3
$FFF0, $FFF1
$FFEE, $FFEF
$FFEC, $FFED
$FFEA, $FFEB
$FFE8, $FFE9
$FFE6, $FFE7
$FFE4, $FFE5
$FFE2, $FFE3
$FFE0, $FFE1
$FFDE, $FFDF
$FFDC, $FFDD
$FFDA, $FFDB
$FFD8, $FFD9
Reset
None
None
None
None
None
X-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
None
PLLCTL (CME, SCME)
COP rate select
None
–
Clock Monitor fail reset
–
COP failure reset
–
Unimplemented instruction trap
SWI
–
None
–
XIRQ
None
–
IRQ
IRQCR (IRQEN)
CRGINT (RTIE)
TIE (C0I)
$F2
$F0
$EE
$EC
$EA
$E8
$E6
$E4
$E2
$E0
$DE
$DC
$DA
$D8
Real Time Interrupt
Enhanced Capture Timer channel 0
Enhanced Capture Timer channel 1
Enhanced Capture Timer channel 2
Enhanced Capture Timer channel 3
Enhanced Capture Timer channel 4
Enhanced Capture Timer channel 5
Enhanced Capture Timer channel 6
Enhanced Capture Timer channel 7
Enhanced Capture Timer overflow
Pulse accumulator A overflow
Pulse accumulator input edge
SPI0
TIE (C1I)
TIE (C2I)
TIE (C3I)
TIE (C4I)
TIE (C5I)
TIE (C6I)
TIE (C7I)
TSRC2 (TOF)
PACTL (PAOVI)
PACTL (PAI)
SP0CR1 (SPIE, SPTIE)
SC0CR2
(TIE, TCIE, RIE, ILIE)
$FFD6, $FFD7
$FFD4, $FFD5
SCI0
SCI1
I-Bit
I-Bit
$D6
$D4
SC1CR2
(TIE, TCIE, RIE, ILIE)
$FFD2, $FFD3
$FFD0, $FFD1
$FFCE, $FFCF
$FFCC, $FFCD
$FFCA, $FFCB
ATD0
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
ATD0CTL2 (ASCIE)
ATD1CTL2 (ASCIE)
PTJIF (PTJIE)
$D2
$D0
$CE
$CC
$CA
ATD1
Port J
Port H
PTHIF(PTHIE)
Modulus Down Counter underflow
MCCTL(MCZI)
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MC9S12A256 Device Guide — V01.01
$FFC8, $FFC9
$FFC6, $FFC7
$FFC4, $FFC5
$FFC2, $FFC3
$FFC0, $FFC1
$FFBE, $FFBF
$FFBC, $FFBD
$FFBA, $FFBB
$FFB8, $FFB9
Pulse Accumulator B Overflow
I-Bit
I-Bit
I-Bit
PBCTL(PBOVI)
CRGINT(LOCKIE)
CRGINT (SCMIE)
$C8
$C6
$C4
CRG PLL lock
CRG Self Clock Mode
Reserved
IIC Bus
SPI1
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
IBCR (IBIE)
$C0
$BE
$BC
$BA
$B8
SP1CR1 (SPIE, SPTIE)
SP2CR1 (SPIE, SPTIE)
EECTL(CCIE, CBEIE)
FCTL(CCIE, CBEIE)
SPI2
EEPROM
FLASH
$FF90 to
$FFB7
Reserved
$FF8E, $FF8F
$FF8C, $FF8D
Port P Interrupt
I-Bit
I-Bit
PTPIF (PTPIE)
$8E
$8C
PWM Emergency Shutdown
PWMSDN (PWMIE)
$FF80 to
$FF8B
Reserved
5.3 Effects of Reset
When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to the
respective module Block User Guides for register reset states.
5.3.1 I/O Pins
Refer to the HCS12 Core User Guide (Motorola order number, HCS12COREUG/D) for mode dependent
pin configuration of port A, B, E and K out of reset.
Refer to the MC9S12A256 Port Integration Module (PIM) Block Guide (Motorola document order
number, S12A256PIMV1/D) for reset configurations of all peripheral module ports.
NOTE: For devices assembled in 80-pin QFP packages all non-bonded out pins should be
configured as outputs after reset in order to avoid current drawn from floating
inputs. Refer to Table 2-1 for affected pins.
5.3.2 Memory
Refer to Table 1-1 for locations of the memories depending on the operating mode after reset.
The RAM array is not automatically initialized out of reset.
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MC9S12A256 Device Guide — V01.01
Section 6 HCS12 Core Block Description
Consult the HCS12 Core User Guide (Motorola order number, HCS12COREUG/D) for information about
the HCS12 core modules, i.e., central processing unit (CPU), interrupt module (INT), module mapping
control module (MMC), multiplexed external bus interface (MEBI), breakpoint module (BKP) and
background debug mode module (BDM).
Section 7 Clock and Reset Generator (CRG) Block
Description
Consult the HCS12 Clock and Reset Generator (CRG) Block Guide (Motorola document order number,
S12CRGV3/D) for information about the Clock and Reset Generator module.
7.1 Device-Specific Information
7.1.1 XCLKS
The XCLKS input signal is active low (see 2.3.13 PE7 / NOACC / XCLKS — Port E I/O Pin 7).
Refer to Figure 2-3. Pierce Oscillator Connections (XCLKS=1) of the HCS12 Clock and Reset Generator
(CRG) Block Guide (Motorola document order number, S12CRGV3/D).
Section 8 Enhanced Capture Timer (ECT) Block Description
Consult the HCS12 16-Bit, 8-Channel Enhanced Capture Timer (ECT) Block Guide (Motorola document
order number, S12ECT16B8CV1/D) for information about the Enhanced Capture Timer module.
Section 9 Analog to Digital Converter (ATD) Block
Description
There are two Analog to Digital Converters (ATD1 and ATD0) implemented on the MC9S12A256.
Consult the HCS12 10-Bit, 8-Channel Analog-to-Digital Converter (ATD) Block Guide (Motorola
document order number, S12ATD10B8CV2/D) for information about each Analog to Digital Converter
module.
Section 10 Inter-IC Bus (IIC) Block Description
Consult the HCS12 Inter-Integrated Circuit (IIC) Block Guide (Motorola document order number,
S12IICV2/D) for information about the Inter-IC Bus module.
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Section 11 Serial Communications Interface (SCI) Block
Description
There are two Serial Communications Interfaces (SCI1 and SCI0) implemented on the MC9S12A256
device. Consult the HCS12 Serial Communications Interface (SCI) Block Guide (Motorola document
order number, S12SCIV2/D) for information about each Serial Communications Interface module.
Section 12 Serial Peripheral Interface (SPI) Block
Description
There are three Serial Peripheral Interfaces(SPI2, SPI1 and SPI0) implemented on MC9S12A256. Consult
the HCS12 Serial Peripheral Interface (SPI) Block Guide (Motorola document order number,
S12SPIV2/D) for information about each Serial Peripheral Interface module.
Section 13 Pulse Width Modulator (PWM) Block Description
Consult the HCS12 8-Bit, 8-Channel Pulse Width Modulator (PWM) Block Guide (Motorola document
order number, S12PWM8B8CV1/D) for information about the Pulse Width Modulator module.
Section 14 Flash EEPROM 256K Block Description
Consult the HCS12 256K FLASH Block Guide (Motorola document order number, S12FTS256KV1/D) for
information about the flash module.
Section 15 EEPROM 4K Block Description
Consult the HCS12 4K EEPROM Block Guide (Motorola document order number, S12EETS4KV1/D) for
information about the EEPROM module.
Section 16 RAM Block Description
This module supports single-cycle misaligned word accesses.
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MC9S12A256 Device Guide — V01.01
Section 17 Port Integration Module (PIM) Block Description
Consult the MC9S12A128 Port Integration Module (PIM) Block Guide (Motorola document order
number, S12A128PIMV1/D) for information about the Port Integration Module.
Section 18 Voltage Regulator (VREG) Block Description
Consult the HCS12 Voltage Regulator Block Guide (Motorola document order number, S12VREGV1/D)
for information about the dual output linear voltage regulator.
Component
Purpose
Type
Value
100 .. 220nF
100 .. 220nF
100nF
V
V
V
V
filter cap
C1
C2
C3
C4
C5
ceramic X7R
ceramic X7R
ceramic X7R
X7R/tantalum
ceramic X7R
X7R/tantalum
DD1
DD2
DDA
filter cap
filter cap
filter cap
filter cap
>=100nF
100nF
DDR
V
DDPLL
V
filter cap
C6
C7
>=100nF
DDX
OSC load cap
OSC load cap
PLL loop filter cap
PLL loop filter cap
DC cutoff cap
PLL loop filter res
Quartz
C8
C9
C10
C11
R1
See A.5.3 Phase Locked Loop
Q1
53
MC9S12A256 Device Guide — V01.01
The PCB must be carefully laid out to ensure proper operation of the voltage regulator as well as
of the MCU itself. The following rules must be observed:
•
Every supply pair must be decoupled by a ceramic capacitor connected as near as
possible to the corresponding pins(C1 - C6).
•
•
•
•
Central point of the ground star should be the VSSR pin.
Use low ohmic low inductance connections between VSS1, VSS2, and VSSR
.
VSSPLL must be directly connected to VSSR
.
Keep traces of VSSPLL, EXTAL and XTAL as short as possible and occupied board area
for C7, C8, C11 and Q1 as small as possible.
•
•
Do not place other signals or supplies underneath area occupied by C7, C8, C10 and Q1
and the connection area to the MCU.
Central power input should be fed in at the VDDA/VSSA pins.
54
MC9S12A256 Device Guide — V01.01
Figure 18-1 Recommended PCB Layout 112 LQFP
VSSA
C3
VSSX
VDDA
VDD1
VSS1
C1
VSS2
C2
VDD2
VSSR
VDDR
Q1
VSSPLL
VDDPLL
R1
55
MC9S12A256 Device Guide — V01.01
Figure 18-2 Recommended PCB Layout for 80 QFP
C3
VSSA
VSSX
VDDA
VDD1
C1
VSS2
C2
VSS1
VDD2
VSSR
VDDR
Q1
VSSPLL
VDDPLL
R1
56
MC9S12A256 Device Guide — V01.01
Appendix A Electrical Characteristics
A.1 General
NOTE: The electrical characteristics given in this section are preliminary and should be
used as a guide only. Values cannot be guaranteed by Motorola and are subject to
change without notice.
This supplement contains the most accurate electrical information for the MC9S12A256 microcontroller
available at the time of publication. The information should be considered PRELIMINARY and is subject
to change.
This introduction is intended to give an overview on several common topics like power supply, current
injection etc.
A.1.1 Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the
customer a better understanding the following classification is used and the parameters are tagged
accordingly in the tables where appropriate.
NOTE: This classification is shown in the column labeled “C” in the parameter tables
where appropriate.
P:
Those parameters are guaranteed during production testing on each individual device.
C:
Those parameters are achieved by the design characterization by measuring a statistically relevant
sample size across process variations.
T:
Those parameters are achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted. All values shown in the typical column are within
this category.
D:
Those parameters are derived mainly from simulations.
57
MC9S12A256 Device Guide — V01.01
A.1.2 Power Supply
The MC9S12A256 utilizes several pins to supply power to the I/O ports, A/D converter, oscillator and PLL
as well as the digital core.
The VDDA, VSSA pair supplies the A/D converter and the resistor ladder of the internal voltage regulator.
The VDDX, VSSX, VDDR, and VSSR pairs supply the I/O pins, VDDR supplies also the internal voltage
regulator.
VDD1, VSS1, VDD2, and VSS2 are the supply pins for the digital logic, VDDPLL, VSSPLL supply the
oscillator and the PLL.
VSS1 and VSS2 are internally connected by metal.
VDDA, VDDX, VDDR as well as VSSA, VSSX, VSSR are connected by anti-parallel diodes for ESD
protection.
NOTE: In the following context VDD5 is used for either VDDA, VDDR, and VDDX; VSS5 is
used for either VSSA, VSSR, and VSSX unless otherwise noted.
IDD5 denotes the sum of the currents flowing into the VDDA, VDDX and VDDR pins.
V
DD is used for VDD1, VDD2, and VDDPLL, VSS is used for VSS1, VSS2, and VSSPLL
.
IDD is used for the sum of the currents flowing into VDD1 and VDD2
.
A.1.3 Pins
There are four groups of functional pins.
A.1.3.1 5V I/O pins
Those I/O pins have a nominal level of 5V. This class of pins is comprised of all port I/O pins, the analog
inputs, BKGD and the RESET pins.The internal structure of all those pins is identical, however some of
the functionality may be disabled. E.g. for the analog inputs the output drivers, pull-up and pull-down
resistors are disabled permanently.
A.1.3.2 Analog Reference
This group is made up by the VRH and VRL pins.
A.1.3.3 Oscillator
The pins XFC, EXTAL, XTAL dedicated to the oscillator have a nominal 2.5V level. They are supplied
by VDDPLL
.
A.1.3.4 TEST
This pin is used for production testing only.
58
MC9S12A256 Device Guide — V01.01
A.1.3.5 VREGEN
This pin is used to enable the on chip voltage regulator.
A.1.4 Current Injection
Power supply must maintain regulation within operating VDD5 or VDD range during instantaneous and
operating maximum current conditions. If positive injection current (Vin > VDD5) is greater than IDD5, the
injection current may flow out of VDD5 and could result in external power supply going out of regulation.
Ensure external VDD5 load will shunt current greater than maximum injection current. This will be the
greatest risk when the MCU is not consuming power; e.g., if no system clock is present, or if clock rate is
very low which would reduce overall power consumption.
A.1.5 Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima
is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the
device.
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (e.g., either VSS5 or VDD5).
59
MC9S12A256 Device Guide — V01.01
Table A-1 Absolute Maximum Ratings1
Num
Rating
Symbol
Min
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
Max
6.0
3.0
3.0
0.3
0.3
6.0
6.0
3.0
10.0
Unit
V
V
1
2
3
4
5
6
7
8
9
I/O, Regulator and Analog Supply Voltage
DD5
2
V
V
Digital Logic Supply Voltage
DD
2
V
V
PLL Supply Voltage
DDPLL
Voltage difference V
Voltage difference V
to V
to V
and V
and V
∆
V
DDX
SSX
DDR
DDA
VDDX
∆
V
SSR
SSA
VSSX
V
Digital I/O Input Voltage
Analog Reference
V
IN
V
V
V
RH, RL
V
XFC, EXTAL, XTAL inputs
TEST input
V
ILV
V
V
TEST
Instantaneous Maximum Current
Single pin limit for all digital I/O pins
I
10
11
12
-25
-25
+25
+25
mA
mA
D
3
Instantaneous Maximum Current
I
DL
4
Single pin limit for XFC, EXTAL, XTAL
Instantaneous Maximum Current
I
-0.25
0
mA
DT
5
Single pin limit for TEST
T
13
Storage Temperature Range
– 65
155
°C
stg
NOTES:
1. Beyond absolute maximum ratings device might be damaged.
2. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply.
The absolute maximum ratings apply when the device is powered from an external source.
3. All digital I/O pins are internally clamped to V
and V
, V
and V
or V
and V
.
SSX
DDX
SSR
DDR
SSA
DDA
4. Those pins are internally clamped to V
and V
.
SSPLL
DDPLL
5. This pin is clamped low to V
, but not clamped high. This pin must be tied low in applications.
SSPLL
60
MC9S12A256 Device Guide — V01.01
A.1.6 ESD Protection and Latch-up Immunity
All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for Automotive Grade
Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body
Model (HBM), the Machine Model (MM) and the Charge Device Model.
A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
Table A-2 ESD and Latch-up Test Conditions
Model
Description
Symbol
Value
1500
100
Unit
Ohm
pF
Series Resistance
R1
C
Storage Capacitance
Human Body
Number of Pulse per pin
positive
negative
-
3
3
-
Series Resistance
R1
C
0
Ohm
pF
Storage Capacitance
200
Machine
Latch-up
Number of Pulse per pin
positive
negative
-
3
3
-
Minimum input voltage limit
Maximum input voltage limit
-2.5
7.5
V
V
Table A-3 ESD and Latch-Up Protection Characteristics
Num C
Rating
Symbol
Min
2000
200
Max
Unit
V
1
2
3
C Human Body Model (HBM)
-
-
-
V
V
V
HBM
V
C Machine Model (MM)
MM
V
C Charge Device Model (CDM)
500
CDM
Latch-up Current at T = 125°C
A
I
4
5
C
C
+100
-100
-
-
mA
mA
positive
negative
LAT
Latch-up Current at T = 27°C
A
I
+200
-200
positive
negative
LAT
61
MC9S12A256 Device Guide — V01.01
A.1.7 Operating Conditions
This chapter describes the operating conditions of the device. Unless otherwise noted those conditions
apply to all the following data.
NOTE: Please refer to the temperature rating of the device (C) with regards to the ambient
temperature TA and the junction temperature TJ. For power dissipation
calculations refer to A.1.8 Power Dissipation and Thermal
Characteristics.
Table A-4 Operating Conditions
Rating
Symbol
Min
4.5
Typ
Max
5.25
2.75
2.75
0.1
Unit
V
V
I/O, Regulator and Analog Supply Voltage
5
2.5
2.5
0
DD5
1
V
2.35
2.35
-0.1
-0.1
0.5
V
Digital Logic Supply Voltage
DD
2
V
V
PLL Supply Voltage
DDPLL
Voltage Difference V
to V
to V
and V
and V
∆
V
DDX
SSX
DDR
DDA
VDDX
Voltage Difference V
∆
0
0.1
V
SSR
SSA
VSSX
f
Oscillator
-
16
MHz
MHz
osc
f
Bus Frequency
MC9S12A256C
0.5
-
25
bus
T
Operating Junction Temperature Range
-40
-40
-
100
85
°C
°C
J
2
T
27
Operating Ambient Temperature Range
A
NOTES:
1. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. The
absolute maximum ratings apply when this regulator is disabled and the device is powered from an external
source.
2. Please refer to A.1.8 Power Dissipation and Thermal Characteristics for more details about the relation be-
tween ambient temperature T and device junction temperature T .
A
J
62
MC9S12A256 Device Guide — V01.01
A.1.8 Power Dissipation and Thermal Characteristics
Power dissipation and thermal characteristics are closely related. The user must assure that the maximum
operating junction temperature is not exceeded. The average chip-junction temperature (TJ) in °C can be
obtained from:
T
= T + (P • Θ
)
J
A
D
JA
T = Junction Temperature, [°C]
J
T
P
= Ambient Temperature, [°C]
A
= Total Chip Power Dissipation, [W]
D
Θ
= Package Thermal Resistance, [°C/W]
JA
The total power dissipation can be calculated from:
P
= P
+ P
D
INT
IO
P
= Chip Internal Power Dissipation, [W]
INT
Two cases with internal voltage regulator enabled and disabled must be considered:
1. Internal Voltage Regulator disabled
P
= I
V
+ I
V
+ I
V
INT
DD DD DDPLL DDPLL DDA DDA
2
P
=
R
I
∑
IO
DSON IO
i
i
PIO is the sum of all output currents on I/O ports associated with VDDX and VDDR
For RDSON is valid:
.
V
OL
R
= ------------ ;fo r ou tp uts drive n lo w
DSON
I
OL
respectively
V
– V
DD5
OH
R
= ----------------------------------- ;fo r outp uts d rive n hig h
DSON
I
OH
2. Internal voltage regulator enabled
P
= I
V
+ I
V
INT
DDR
DDR DDA DDA
63
MC9S12A256 Device Guide — V01.01
IDDR is the current shown in Table A-7 and not the overall current flowing into VDDR, which
additionally contains the current flowing into the external loads with output high.
2
P
=
R
I
IO
∑
DSON IO
i
i
PIO is the sum of all output currents on I/O ports associated with VDDX and VDDR
.
Table A-5 Thermal Package Characteristics1
Num C
Rating
Symbol
Min
Typ
Max
Unit
2
o
θ
1
2
3
4
T
T
T
T
-
-
54
Thermal Resistance LQFP112, single sided PCB
C/W
JA
Thermal Resistance LQFP112, double sided PCB
o
θ
-
-
-
-
-
-
41
51
41
C/W
JA
3
with 2 internal planes
o
θ
Thermal Resistance LQFP 80, single sided PCB
C/W
JA
Thermal Resistance LQFP 80, double sided PCB
with 2 internal planes
o
θ
C/W
JA
NOTES:
1. The values for thermal resistance are achieved by package simulations
2. PC Board according to EIA/JEDEC Standard 51-2
3. PC Board according to EIA/JEDEC Standard 51-7
A.1.9 I/O Characteristics
This section describes the characteristics of all 5V I/O pins. All parameters are not always applicable, e.g.,
not all pins feature pull up/down resistances.
64
MC9S12A256 Device Guide — V01.01
Table A-6 5V I/O Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C Rating
Symbol
Min
Typ
Max
Unit
V
V
0.65*V
1
P Input High Voltage
-
-
DD5
IH
V
V
+ 0.3
DD5
T Input High Voltage
P Input Low Voltage
T Input Low Voltage
C Input Hysteresis
-
-
-
V
IH
V
0.35*V
2
-
-
V
DD5
IL
V
V
- 0.3
SS5
-
V
IL
V
3
4
250
mV
HYS
Input Leakage Current (pins in high impedance input
1
I
mode)
P
P
P
–2.5
-
-
-
2.5
-
µA
V
in
V
= V
or V
DD5 SS5
in
Output High Voltage (pins in output mode)
Partial Drive I = +2mA
V
V
– 0.8
5
6
OH
= +10mA
DD5
OH
Full Drive I
OH
Output Low Voltage (pins in output mode)
Partial Drive I = +2mA
V
OL
= +10mA
-
0.8
V
OL
Full Drive I
OL
Internal Pull Up Device Current,
I
7
8
9
P
P
P
P
-
-10
-
-
-
-
-130
-
µA
µA
µA
PUL
tested at V Max.
IL
Internal Pull Up Device Current,
I
PUH
tested at V Min.
IH
Internal Pull Down Device Current,
I
130
PDH
tested at V Min.
IH
Internal Pull Down Device Current,
I
10
11
10
-
-
-
µA
PDL
tested at V Max.
IL
C
D Input Capacitance
6
pF
in
2
Injection current
I
12
T
-2.5
-25
-
2.5
25
mA
ICS
Single Pin limit
Total Device Limit. Sum of all injected currents
I
ICP
3
t
13
14
P
P
3
µs
µs
Port H, J, P Interrupt Input Pulse filtered
PULSE
3
t
10
Port H, J, P Interrupt Input Pulse passed
PULSE
NOTES:
1. Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for
each 8°C to 12°C in the temperature range from 50°C to 125°C.
2. Refer to A.1.4 Current Injection, for more details
3. Parameter only applies in STOP or Pseudo STOP mode.
65
MC9S12A256 Device Guide — V01.01
A.1.10 Supply Currents
This section describes the current consumption characteristics of the device as well as the conditions for
the measurements.
A.1.10.1 Measurement Conditions
All measurements are without output loads. Unless otherwise noted the currents are measured in single
chip mode, internal voltage regulator enabled and at 25MHz bus frequency using a 4MHz oscillator in
Colpitts mode. Production testing is performed using a square wave signal at the EXTAL input.
A.1.10.2 Additional Remarks
In expanded modes the currents flowing in the system are highly dependent on the load at the address, data
and control signals as well as on the duty cycle of those signals. No generally applicable numbers can be
given. A very good estimate is to take the single chip currents and add the currents due to the external
loads.
Table A-7 Supply Current Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
Min
Typ
Max
Unit
Run supply currents
1
P
mA
I
Single Chip, Internal regulator enabled
65
DD5
Wait Supply current
All modules enabled, PLL on
I
2
P
P
40
5
mA
DDW
1
only RTI enabled
1, 2
Pseudo Stop Current (RTI and COP disabled)
-40°C
27°C
70°C
85°C
C
P
C
C
P
C
370
400
450
550
600
650
500
I
3
4
5
µA
DDPS
“C” Temp Option 100°C
105°C
1600
1, 2
Pseudo Stop Current (RTI and COP enabled)
C
C
C
C
C
570
600
650
750
850
-40°C
27°C
70°C
85°C
105°C
I
µA
µA
DDPS
2
Stop Current
C
P
C
C
P
C
12
25
100
130
160
200
-40°C
27°C
70°C
85°C
100
I
DDS
1200
“C” Temp Option 100°C
105°C
NOTES:
1. PLL off
2. At those low power dissipation levels T = T can be assumed
J
A
66
MC9S12A256 Device Guide — V01.01
A.2 ATD Characteristics
This section describes the characteristics of the analog to digital converter.
A.2.1 ATD Operating Characteristics
The Table A-8 shows conditions under which the ATD operates.
The following constraints exist to obtain full-scale, full range results:
VSSA ≤ VRL ≤ VIN ≤ VRH ≤ VDDA. This constraint exists since the sample buffer amplifier can not drive
beyond the power supply levels that it ties to. If the input level goes outside of this range it will effectively
be clipped.
Table A-8 ATD Operating Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
Min
Typ
Max
Unit
Reference Potential
1
D
Low
High
V
V
V /2
DDA
V
V
RL
SSA
V
V
/2
V
RH
DDA
DDA
1
2
3
C
V
-V
4.50
5.00
5.25
2.0
V
Differential Reference Voltage
RH RL
ATDCLK
D ATD Clock Frequency
f
0.5
MHz
ATD 10-Bit Conversion Period
D
2
4
5
Clock Cycles
N
T
14
7
28
14
Cycles
µs
CONV10
Conv, Time at 2.0MHz ATD Clock f
ATDCLK
CONV10
ATD 8-Bit Conversion Period
D
2
N
T
12
6
26
13
Cycles
µs
Clock Cycles
CONV8
CONV8
Conv, Time at 2.0MHz ATD Clock f
ATDCLK
Recovery Time (V
D
=5.0 Volts)
6
7
8
t
20
µs
DDA
REC
P Reference Supply current 2 ATD blocks on
P Reference Supply current 1 ATD block on
I
I
0.750
0.375
mA
mA
REF
REF
NOTES:
1. Full accuracy is not guaranteed when differential voltage is less than 4.50V
2. The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample
period of 16 ATD clocks.
67
MC9S12A256 Device Guide — V01.01
A.2.2 Factors Influencing Accuracy
Three factors - source resistance, source capacitance and current injection - have an influence on the
accuracy of the ATD.
A.2.2.1 Source Resistance
Due to the input pin leakage current as specified in Table A-6 in conjunction with the source resistance
there will be a voltage drop from the signal source to the ATD input. The maximum source resistance RS
specifies results in an error of less than 1/2 LSB (2.5mV) at the maximum leakage current. If device or
operating conditions are less than worst case or leakage-induced error is acceptable, larger values of source
resistance is allowed.
A.2.2.2 Source Capacitance
When sampling an additional internal capacitor is switched to the input. This can cause a voltage drop due
to charge sharing with the external and the pin capacitance. For a maximum sampling error of the input
voltage ≤ 1LSB, then the external filter capacitor, Cf ≥ 1024 * (CINS- CINN).
A.2.2.3 Current Injection
There are two cases to consider.
1. A current is injected into the channel being converted. The channel being stressed has conversion
values of $3FF ($FF in 8-bit mode) for analog inputs greater than VRH and $000 for values less than
VRL unless the current is higher than specified as disruptive condition.
2. Current is injected into pins in the neighborhood of the channel being converted. A portion of this
current is picked up by the channel (coupling ratio K), This additional current impacts the accuracy
of the conversion depending on the source resistance.
The additional input voltage error on the converted channel can be calculated as VERR = K * RS *
IINJ, with IINJ being the sum of the currents injected into the two pins adjacent to the converted
channel.
Table A-9 ATD Electrical Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
Min
Typ
Max
Unit
R
1
C Max input Source Resistance
-
-
1
KΩ
S
Total Input Capacitance
Non Sampling
Sampling
C
2
T
10
22
pF
INN
C
INS
I
3
4
5
C Disruptive Analog Input Current
-2.5
2.5
mA
A/A
A/A
NA
-4
K
C Coupling Ratio positive current injection
C Coupling Ratio negative current injection
10
p
-2
K
10
n
68
MC9S12A256 Device Guide — V01.01
A.2.3 ATD Accuracy
Table A-10 specifies the ATD conversion performance excluding any errors due to current injection,
input capacitance and source resistance.
Table A-10 ATD Conversion Performance
Conditions are shown in Table A-4 unless otherwise noted
V
= V - V = 5.12V. Resulting to one 8 bit count = 20mV and one 10 bit count = 5mV
REF
RH RL
f
= 2.0MHz
ATDCLK
Num C
Rating
Symbol
LSB
DNL
INL
Min
Typ
Max
Unit
mV
1
2
3
4
5
6
7
8
P 10-Bit Resolution
5
P 10-Bit Differential Nonlinearity
–1
–2.5
-3
1
2.5
3
Counts
Counts
Counts
mV
P 10-Bit Integral Nonlinearity
±1.5
±2.0
20
1
P
AE
10-Bit Absolute Error
P 8-Bit Resolution
P 8-Bit Differential Nonlinearity
P 8-Bit Integral Nonlinearity
1
LSB
DNL
INL
–0.5
–1.0
-1.5
0.5
1.0
1.5
Counts
Counts
Counts
±0.5
±1.0
P
AE
8-Bit Absolute Error
NOTES:
1. These values include the quantization error which is inherently 1/2 count for any A/D converter.
For the following definitions see also Figure A-1.
Differential Non-Linearity (DNL) is defined as the difference between two adjacent switching steps.
V – V
i
i – 1
DNL(i) =
– 1
-------------------------
1LSB
The Integral Non-Linearity (INL) is defined as the sum of all DNLs:
n
V – V
n
0
INL(n) =
DNL(i) =
– n
--------------------
∑
1LSB
i = 1
69
MC9S12A256 Device Guide — V01.01
DNL
10-Bit Absolute Error Boundary
LSB
Vi-1
Vi
$3FF
$3FE
$3FD
$3FC
$3FB
$3FA
$3F9
$3F8
$3F7
$3F6
$3F5
$3F4
$3F3
8-Bit Absolute Error Boundary
$FF
$FE
$FD
2
9
8
7
6
5
4
3
2
1
0
Ideal Transfer Curve
10-Bit Transfer Curve
1
8-Bit Transfer Curve
5
10
15
20
25
30
35
40
45
5055 5060 5065 5070 5075 5080 5085 5090 5095 5100 5105 5110 5115 5120
Vin
mV
Figure A-1 ATD Accuracy Definitions
NOTE: Figure A-1 shows only definitions, for specification values refer to Table A-10.
70
MC9S12A256 Device Guide — V01.01
A.3 NVM, Flash, and EEPROM
NOTE: Unless otherwise noted the abbreviation NVM (Non Volatile Memory) is used for
both Flash and EEPROM.
A.3.1 NVM Timing
The time base for all NVM program or erase operations is derived from the oscillator. A minimum
oscillator frequency fNVMOSC is required for performing program or erase operations. The NVM modules
do not have any means to monitor the frequency and will not prevent program or erase operation at
frequencies above or below the specified minimum. Attempting to program or erase the NVM modules at
a lower frequency a full program or erase transition is not assured.
The Flash and EEPROM program and erase operations are timed using a clock derived from the oscillator
using the FCLKDIV and ECLKDIV registers respectively. The frequency of this clock must be set within
the limits specified as fNVMOP
.
The minimum program and erase times shown in Table A-11 are calculated for maximum fNVMOP and
maximum fbus. The maximum times are calculated for minimum fNVMOP and a fbus of 2MHz.
A.3.1.1 Single Word Programming
The programming time for single word programming is dependant on the bus frequency as a well as on
the frequency fNVMOP and can be calculated according to the following formula.
1
1
t
= 9 ------------------------ + 25 -----------
swpgm
f
f
NVMOP
bus
A.3.1.2 Burst Programming
This applies only to the Flash where up to 32 words in a row can be programmed consecutively using burst
programming by keeping the command pipeline filled. The time to program a consecutive word can be
calculated as:
1
1
t
= 4 ------------------------ + 9 -----------
bwpgm
f
f
NVMOP
bus
The time to program a whole row is:
t
= t
+ 31 t
brpgm
swpgm
bwpgm
Burst programming is more than 2 times faster than single word programming.
71
MC9S12A256 Device Guide — V01.01
A.3.1.3 Sector Erase
Erasing a 512 byte Flash sector or a 4 byte EEPROM sector takes:
1
------------------------
t
≈ 4000
era
f
NVMOP
The setup time can be ignored for this operation.
A.3.1.4 Mass Erase
Erasing a NVM block takes:
1
------------------------
t
≈ 20000
mass
f
NVMOP
The setup time can be ignored for this operation.
A.3.1.5 Blank Check
The time it takes to perform a blank check on the Flash or EEPROM is dependant on the location of the
first non-blank word starting at relative address zero. It takes one bus cycle per word to verify plus a setup
of the command.
t
≈ location t
+ 10 t
check
cyc
cyc
72
MC9S12A256 Device Guide — V01.01
Table A-11 NVM Timing Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
Min
0.5
1
Typ
Max
Unit
MHz
MHz
kHz
µs
1
f
1
2
D External Oscillator Clock
50
NVMOSC
f
D Bus frequency for Programming or Erase Operations
D Operating Frequency
NVMBUS
f
3
150
200
NVMOP
2
3
t
4
P Single Word Programming Time
46
74.5
swpgm
4
2
3
t
5
D
D
µs
Flash Burst Programming consecutive word
20.4
31
bwpgm
4
2
3
t
6
µs
Flash Burst Programming Time for 32 Words
brpgm
678.4
1035.5
5
3
t
7
P Sector Erase Time
ms
20
26.7
133
era
5
3
t
8
P Mass Erase Time
ms
100
mass
6
7
t
t
9
D Blank Check Time Flash per block
D Blank Check Time EEPROM per block
11
11
32778
check
cyc
6
7
t
t
10
2058
check
cyc
NOTES:
1. Restrictions for oscillator in crystal mode apply!
2. Minimum Programming times are achieved under maximum NVM operating frequency f
and maximum bus frequency
NVMOP
f
.
bus
3. Maximum Erase and Programming times are achieved under particular combinations of f
and bus frequency f
.
bus
NVMOP
Refer to formulae in A.3.1.1 Single Word Programming- A.3.1.4 Mass Erase for guidance.
4. urst Programming operations are not applicable to EEPROM
5. Minimum Erase times are achieved under maximum NVM operating frequency f
6. Minimum time, if first word in the array is not blank
.
NVMOP
7. Maximum time to complete check on an erased block
73
MC9S12A256 Device Guide — V01.01
A.3.2 NVM Reliability
The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process
monitors and burn-in to screen early life failures.
The failure rates for data retention and program/erase cycling are specified at the operating conditions
noted.
The program/erase cycle count on the sector is incremented every time a sector or mass erase event is
executed.
NOTE: All values shown in Table A-12 are target values and subject to further extensive
characterization.
Table A-12 NVM Reliability Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Data Retention
Num
C
NVM Array
Cycles
Lifetime
10 years
10 years
1
2
C
C
Flash/EEPROM (–40 to +85°C)
EEPROM (–40 to +85°C)
1000
10,000
NOTE: Flash cycling performance is 1000 cycles at –40 to + 85°C. Data Retention is
specified for 10 years.
NOTE: EEPROM cycling performance is 10,000 cycles at –40 to +85°C. Data retention is
specified for 10 years.
NOTE: These figures are provided for commercial quality levels not automotive.
74
MC9S12A256 Device Guide — V01.01
A.4 Voltage Regulator
The on-chip voltage regulator is intended to supply the internal logic and oscillator circuits. No external
DC load is allowed.
Table A-13 Voltage Regulator Recommended Load Capacitances
Rating
Symbol
Min
Typ
220
220
Max
Unit
nF
Load Capacitance on V
C
DD1, 2
DDPLL
LVDD
Load Capacitance on V
C
nF
LVDDPLL
75
MC9S12A256 Device Guide — V01.01
A.5 Reset, Oscillator, and PLL
This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and
Phase-Locked-Loop (PLL).
A.5.1 Startup
Table A-14 summarizes several startup characteristics explained in this section. Detailed description of
the startup behavior can be found in the HCS12 Clock and Reset Generator (CRG) Block Guide (Motorola
document order number, S12CRGV3/D).
Table A-14 Startup Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
Min
Typ
Max
Unit
V
V
1
2
3
4
5
6
T
T
POR release level
POR assert level
2.07
PORR
V
0.97
2
V
PORA
PW
t
D Reset input pulse width, minimum input time
D Startup from Reset
RSTL
osc
n
n
192
20
196
14
RST
osc
PW
D Interrupt pulse width, IRQ edge-sensitive mode
D Wait recovery startup time
ns
IRQ
t
t
WRS
cyc
A.5.1.1 POR
The release level VPORR and the assert level VPORA are derived from the VDD supply. They are also valid
if the device is powered externally. After releasing the POR reset the oscillator and the clock quality check
are started. If after a time tCQOUT no valid oscillation is detected, the MCU will start using the internal self
clock. The fastest startup time possible is given by nuposc
.
A.5.1.2 SRAM Data Retention
Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing
code when VDD5 is out of specification limits, the SRAM contents integrity is guaranteed if after the reset
the PORF bit in the CRG Flags Register has not been set.
A.5.1.3 External Reset
When external reset is asserted for a time greater than PWRSTL the CRG module generates an internal
reset, and the CPU starts fetching the reset vector without doing a clock quality check, if there was an
oscillation before reset.
76
MC9S12A256 Device Guide — V01.01
A.5.1.4 Stop Recovery
Out of STOP the controller can be woken up by an external interrupt. A clock quality check as after POR
is performed before releasing the clocks to the system.
A.5.1.5 Pseudo Stop and Wait Recovery
The recovery from Pseudo STOP and Wait are essentially the same since the oscillator was not stopped in
both modes. The controller can be woken up by internal or external interrupts. After twrs the CPU starts
fetching the interrupt vector.
A.5.2 Oscillator
The device features an internal Colpitts oscillator. By asserting the XCLKS input during reset this
oscillator can be bypassed allowing the input of a square wave. Before asserting the oscillator to the
internal system clocks the quality of the oscillation is checked for each start from either power-on, STOP
or oscillator fail. tCQOUT specifies the maximum time before switching to the internal self clock mode after
POR or STOP if a proper oscillation is not detected. The quality check also determines the minimum
oscillator start-up time tUPOSC. The device also features a clock monitor. A Clock Monitor Failure is
asserted if the frequency of the incoming clock signal is below the Assert Frequency fCMFA.
Table A-15 Oscillator Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
Min
0.5
Typ
Max
Unit
MHz
µA
f
1
2
3
4
5
6
7
8
9
C Crystal oscillator range
16
OSC
i
P Startup Current
100
OSC
1
2
t
C Oscillator start-up time
ms
s
8
100
UPOSC
t
D Clock Quality check time-out
0.45
50
2.5
200
50
CQOUT
f
P Clock Monitor Failure Assert Frequency
100
KHz
MHz
ns
CMFA
3
f
P
0.5
9.5
9.5
External square wave input frequency
EXT
t
D External square wave pulse width low
D External square wave pulse width high
D External square wave rise time
EXTL
t
ns
EXTH
t
1
1
ns
EXTR
t
10 D External square wave fall time
ns
EXTF
C
11
12
D Input Capacitance (EXTAL, XTAL pins)
9
pF
IN
DC Operating Bias in Colpitts Configuration on
V
C
1.1
V
DCBIAS
EXTAL Pin
NOTES:
1. f = 4MHz, C = 22pF.
osc
2. Maximum value is for extreme cases using high Q, low frequency crystals
3. XCLKS =0 during reset
77
MC9S12A256 Device Guide — V01.01
A.5.3 Phase Locked Loop
The oscillator provides the reference clock for the PLL. The PLL´s Voltage Controlled Oscillator (VCO)
is also the system clock source in self clock mode.
A.5.3.1 XFC Component Selection
This section describes the selection of the XFC components to achieve a good filter characteristics.
VDDPLL
Cs
Cp
R
Phase
VCO
KV
fref
fvco
fosc
1
∆
KΦ
refdv+1
Detector
fcmp
Loop Divider
1
1
2
synr+1
Figure A-2 Basic PLL Functional Diagram
The following procedure can be used to calculate the resistance and capacitance values using typical
values for K1, f1 and ich from Table A-16.
The VCO Gain at the desired VCO output frequency is approximated by:
(f – f
)
1
vco
---------------------------
1V
K
1
K
= K
e
V
1
The phase detector relationship is given by:
K
= – i
K
Φ
ch
V
ich is the current in tracking mode.
78
MC9S12A256 Device Guide — V01.01
The loop bandwidth fC should be chosen to fulfill the Gardner’s stability criteria by at least a factor of 10,
typical values are 50. ζ = 0.9 ensures a good transient response.
2 ζ f
f
ref
1
50
ref
4 50
f < ------------------------------------------ ------ → f < ------------- ;(ζ = 0.9)
C
C
2
π
ζ + 1 + ζ
And finally the frequency relationship is defined as
f
VCO
n = --------------- = 2 (s y n r + 1 )
f
ref
With the above inputs the resistance can be calculated as:
2 π n f
C
R = -----------------------------
K
Φ
The capacitance Cs can now be calculated as:
2
2 ζ
0.516
C
= ---------------------- ≈ --------------;(ζ = 0.9)
s
π f
R
f
R
C
C
The capacitance Cp should be chosen in the range of:
C ⁄ 20 ≤ C ≤ C ⁄ 10
s
p
s
The stabilization delays shown in Table A-16 are dependant on PLL operational settings and external
component selection (e.g. crystal, XFC filter).
A.5.3.2 Jitter Information
The basic functionality of the PLL is shown in Figure A-2. With each transition of the clock fcmp, the
deviation from the reference clock fref is measured and input voltage to the VCO is adjusted
accordingly.The adjustment is done continuously with no abrupt changes in the clock output frequency.
Noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock
jitter. This jitter affects the real minimum and maximum clock periods as illustrated in Figure A-3.
79
MC9S12A256 Device Guide — V01.01
1
2
3
N-1
N
0
tmin1
tnom
tmax1
tminN
tmaxN
Figure A-3 Jitter Definitions
The relative deviation of tnom is at its maximum for one clock period, and decreases towards zero for larger
number of clock periods (N).
Defining the jitter as:
t
(N)
t
(N)
max
min
J(N) = max 1 –
, 1 –
----------------------
----------------------
N t
N t
nom
nom
For N < 100, the following equation is a good fit for the maximum jitter:
j
1
J(N) =
+ j
-------
2
N
J(N)
1
5
10
20
N
Figure A-4 Maximum Bus Clock Jitter Approximation
This is very important to notice with respect to timers, serial modules where a pre-scaler will eliminate the
effect of the jitter to a large extent.
80
MC9S12A256 Device Guide — V01.01
Table A-16 PLL Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C Rating
P Self Clock Mode frequency
D VCO locking range
Symbol
Min
1
Typ
Max
5.5
Unit
MHz
MHz
f
1
2
SCM
f
8
50
VCO
Lock Detector transition from Acquisition to Tracking
mode
1
|∆
|
3
D
3
4
%
trk
1
|∆
|
4
5
D Lock Detection
0
1.5
2.5
%
Lock
1
|∆
|
D Un-Lock Detection
0.5
unl
%
Lock Detector transition from Tracking to Acquisition
mode
1
|∆
|
6
D
6
8
%
unt
2
t
7
8
9
C
D
D
0.5
0.3
ms
ms
PLLON Total Stabilization delay (Auto Mode)
stab
2
t
PLLON Acquisition mode stabilization delay
acq
2
t
0.2
ms
PLLON Tracking mode stabilization delay
al
K
10 D Fitting parameter VCO loop gain
11 D Fitting parameter VCO loop frequency
-120
75
MHz/V
MHz
µA
1
f
1
| i
| i
|
|
12 D Charge pump current acquisition mode
38.5
3.5
ch
ch
13 D Charge pump current tracking mode
µA
2
j
14
15
C
C
1.1
%
Jitter fit parameter 1
Jitter fit parameter 2
1
2
j
0.13
%
2
NOTES:
1. % deviation from target frequency
2. f = 4MHz, f = 25MHz equivalent f = 50MHz: REFDV = #$03, SYNR = #$018, Cs = 4.7nF, Cp = 470pF, Rs =
VCO
REF
BUS
10KΩ.
81
MC9S12A256 Device Guide — V01.01
A.6 SPI
A.6.1 Master Mode
Figure A-5 and Figure A-6 illustrate the master mode timing. Timing values are shown in Table A-17.
1
SS
(OUTPUT)
2
1
3
11
12
SCK
(CPOL = 0)
(OUTPUT)
4
4
SCK
(CPOL = 1)
(OUTPUT)
5
6
MISO
(INPUT)
2
BIT 6 . . . 1
MSB IN
LSB IN
9
9
10
MOSI
(OUTPUT)
2
BIT 6 . . . 1
LSB OUT
MSB OUT
1. If configured as output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure A-5 SPI Master Timing (CPHA = 0)
82
MC9S12A256 Device Guide — V01.01
1
SS
(OUTPUT)
1
12
11
11
12
3
2
SCK
(CPOL = 0)
(OUTPUT)
4
4
SCK
(CPOL = 1)
(OUTPUT)
5
6
MISO
(INPUT)
2
MSB IN
BIT 6 . . . 1
LSB IN
10
BIT 6 . . . 1
9
MOSI
(OUTPUT)
2
PORT DATA
MASTER LSB OUT
PORT DATA
MASTER MSB OUT
1. If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure A-6 SPI Master Timing (CPHA =1)
Table A-17 SPI Master Mode Timing Characteristics1
Conditions are shown in Table A-4 unless otherwise noted, C
= 200pF on all outputs
LOAD
Num C
Rating
Symbol
Min
DC
4
Typ
Max
1/4
Unit
f
f
1
1
2
3
4
5
6
9
P Operating Frequency
SCK Period t = 1./f
op
bus
t
t
P
2048
—
sck
op
sck
bus
t
t
D Enable Lead Time
D Enable Lag Time
1/2
1/2
lead
sck
t
t
lag
sck
t
t
− 30
1024 t
bus
D Clock (SCK) High or Low Time
D Data Setup Time (Inputs)
D Data Hold Time (Inputs)
ns
ns
ns
ns
ns
ns
ns
wsck
bus
t
25
0
su
t
hi
t
D Data Valid (after Enable Edge)
25
v
t
10 D Data Hold Time (Outputs)
11 D Rise Time Inputs and Outputs
0
ho
t
25
25
r
t
12 D Fall Time Inputs and Outputs
f
NOTES:
1. The numbers 7, 8 in the column labeled “Num” are missing. This has been done on purpose to be consistent between the
Master and the Slave timing shown in Table A-18.
83
MC9S12A256 Device Guide — V01.01
A.6.2 Slave Mode
Figure A-7 and Figure A-8 illustrate the slave mode timing. Timing values are shown in Table A-18.
SS
(INPUT)
1
12
11
11
12
3
SCK
(CPOL = 0)
(INPUT)
4
4
2
SCK
(CPOL = 1)
(INPUT)
8
7
9
10
10
MISO
(OUTPUT)
BIT 6 . . . 1
SLAVE LSB OUT
MSB OUT
6
SLAVE
5
MOSI
(INPUT)
BIT 6 . . . 1
MSB IN
LSB IN
Figure A-7 SPI Slave Timing (CPHA = 0)
SS
(INPUT)
3
1
12
11
12
2
SCK
(CPOL = 0)
(INPUT)
4
4
11
10
SCK
(CPOL = 1)
(INPUT)
8
9
MISO
BIT 6 . . . 1
SLAVE LSB OUT
LSB IN
SLAVE MSB OUT
(OUTPUT)
7
5
6
MOSI
(INPUT)
MSB IN
BIT 6 . . . 1
Figure A-8 SPI Slave Timing (CPHA =1)
84
MC9S12A256 Device Guide — V01.01
Table A-18 SPI Slave Mode Timing Characteristics
Conditions are shown in Table A-4 unless otherwise noted, C
= 200pF on all outputs
LOAD
Num C
Rating
Symbol
Min
DC
4
Typ
Max
1/4
Unit
f
f
1
1
2
3
4
5
6
7
8
9
P Operating Frequency
SCK Period t = 1./f
op
bus
t
t
P
2048
sck
op
sck
bus
t
t
D Enable Lead Time
D Enable Lag Time
1
lead
cyc
t
t
1
lag
cyc
t
t
− 30
D Clock (SCK) High or Low Time
D Data Setup Time (Inputs)
D Data Hold Time (Inputs)
D Slave Access Time
ns
ns
ns
wsck
cyc
t
25
25
su
t
hi
t
t
1
1
a
cyc
t
t
D Slave MISO Disable Time
D Data Valid (after SCK Edge)
dis
cyc
t
25
ns
ns
ns
ns
v
t
10 D Data Hold Time (Outputs)
11 D Rise Time Inputs and Outputs
12 D Fall Time Inputs and Outputs
0
ho
t
25
25
r
t
f
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MC9S12A256 Device Guide — V01.01
A.7 External Bus Timing
A timing diagram of the external multiplexed-bus is illustrated in Figure A-9 with the actual timing
values shown on table Table A-19. All major bus signals are included in the diagram. While both a data
write and data read cycle are shown, only one or the other would occur on a particular bus cycle.
A.7.1 General Muxed Bus Timing
The expanded bus timings are highly dependent on the load conditions. The timing parameters shown
assume a balanced load across all outputs.
86
MC9S12A256 Device Guide — V01.01
1, 2
3
4
ECLK
PE4
5
6
16
10
9
15
11
Addr/Data
(read)
PA, PB
data
data
data
addr
7
8
12
14
data
13
Addr/Data
(write)
PA, PB
addr
17
19
23
26
18
Non-Multiplexed
Addresses
PK5:0
20
21
22
ECS
PK7
24
27
25
28
R/W
PE2
29
32
LSTRB
PE3
31
34
30
33
NOACC
PE7
35
36
IPIPO0
IPIPO1, PE6,5
Figure A-9 General External Bus Timing
87
MC9S12A256 Device Guide — V01.01
Table A-19 Expanded Bus Timing Characteristics
Conditions are shown in Table A-4 unless otherwise noted, C
= 50pF
LOAD
Num C
Rating
Symbol
Min
0
Typ
Max
Unit
MHz
ns
f
1
2
3
4
5
6
7
8
9
P Frequency of operation (E-clock)
P Cycle time
25.0
o
t
40
19
19
cyc
PW
D Pulse width, E low
ns
EL
1
PW
D
ns
Pulse width, E high
D Address delay time
Address valid time to E rise (PW –t
EH
t
8
ns
AD
)
t
D
11
2
ns
EL AD
AV
t
D Muxed address hold time
D Address hold to data valid
D Data hold to address
ns
MAH
t
7
ns
AHDS
t
2
ns
DHA
t
10 D Read data setup time
11 D Read data hold time
13
0
ns
DSR
t
ns
DHR
t
12 D Write data delay time
13 D Write data hold time
7
ns
DDW
t
2
ns
DHW
1
t
14
15
16
D
D
D
12
ns
ns
Write data setup time (PW –t
)
DSW
EH DDW
1
t
19
6
Address access time (t –t –t
)
ACCA
cyc AD DSR
1
t
ns
ns
ns
ns
ns
ns
E high access time (PW –t
)
ACCE
EH DSR
t
17 D Non-multiplexed address delay time
Non-muxed address valid to E rise (PW –t
6
NAD
)
t
18
D
15
2
EL NAD
NAV
t
19 D Non-multiplexed address hold time
NAH
t
20 D Chip select delay time
16
CSD
1
t
21
D
11
2
Chip select access time (t –t
–t
)
ACCS
cyc CSD DSR
t
22 D Chip select hold time
23 D Chip select negated time
24 D Read/write delay time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CSH
t
8
CSN
t
7
7
7
RWD
Read/write valid time to E rise (PW –t
)
t
25
D
14
2
EL RWD
RWV
t
26 D Read/write hold time
27 D Low strobe delay time
RWH
t
LSD
Low strobe valid time to E rise (PW –t
)
t
28
D
14
2
EL LSD
LSV
t
29 D Low strobe hold time
LSH
t
30 D NOACC strobe delay time
NOD
NOACC valid time to E rise (PW –t
)
t
31
D
14
EL NOD
NOV
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MC9S12A256 Device Guide — V01.01
Table A-19 Expanded Bus Timing Characteristics (Continued)
Conditions are shown in Table A-4 unless otherwise noted, C
= 50pF
LOAD
Num C
Rating
Symbol
Min
2
Typ
Max
Unit
ns
t
32 D NOACC hold time
33 D IPIPO[1:0] delay time
NOH
t
2
7
ns
P0D
IPIPO[1:0] valid time to E rise (PW –t
)
t
34
35
D
D
11
ns
EL P0D
P0V
1
t
2
25
ns
ns
IPIPO[1:0] delay time (PW -t
)
P1D
EH P1V
t
36 D IPIPO[1:0] valid time to E fall
11
P1V
NOTES:
1. Affected by clock stretch: add N x t
where N=0,1, 2 or 3, depending on the number of clock stretches.
cyc
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MC9S12A256 Device Guide — V01.01
Appendix B Package Information
B.1 General
This section provides the physical dimensions of the MC9S12A256 packages.
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MC9S12A256 Device Guide — V01.01
B.2 112-Pin LQFP Package
4X
0.20 T L-M N
4X 28 TIPS
0.20 T L-M N
4X
P
J1
J1
PIN 1
IDENT
112
85
C
L
1
84
VIEW Y
X
108X
G
X=L, M OR N
VIEW Y
V
B
L
M
AA
J
B1
V1
28
57
BASE
METAL
F
D
29
56
M
0.13
T L-M N
N
SECTION J1-J1
A1
S1
ROTATED 90 COUNTERCLOCKWISE
°
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
A
2. DIMENSIONS IN MILLIMETERS.
3. DATUMS L, M AND N TO BE DETERMINED AT
SEATING PLANE, DATUM T.
S
4. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE, DATUM T.
5. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.25 PER SIDE. DIMENSIONS
A AND B INCLUDE MOLD MISMATCH.
6. DIMENSION D DOES NOT INCLUDE DAMBAR
C2
VIEW AB
θ2
C
0.050
112X
0.10
T
SEATING
PLANE
MILLIMETERS
DIM MIN
MAX
20.000 BSC
10.000 BSC
θ3
A
A1
B
B1
C
T
20.000 BSC
10.000 BSC
---
1.600
0.150
1.450
0.370
0.750
0.330
C1 0.050
C2 1.350
θ
D
E
F
0.270
0.450
0.270
G
J
K
P
0.650 BSC
0.090
0.170
R R2
0.500 REF
0.325 BSC
R1 0.100
R2 0.100
0.200
0.200
0.25
R R1
S
S1
V
V1
Y
22.000 BSC
11.000 BSC
22.000 BSC
11.000 BSC
0.250 REF
1.000 REF
GAGE PLANE
(K)
Z
C1
θ1
AA 0.090
0.160
E
8 °
0 °
3 °
11 °
11 °
θ
7 °
13 °
13 °
θ 1
θ 2
θ 3
(Y)
(Z)
VIEW AB
Figure B-1 112-Pin LQFP Mechanical Dimensions (Case no. 987)
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MC9S12A256 Device Guide — V01.01
B.3 80-Pin QFP Package
L
60
61
41
40
B
P
B
-A-
L
-B-
V
B
-A-,-B-,-D-
DETAIL A
DETAIL A
21
80
F
1
20
-D-
A
S
M
S
S
S
0.20
H
A-B
A-B
D
D
0.05 A-B
J
N
M
S
0.20
C
D
M
E
DETAIL C
M
S
S
0.20
C
A-B
D
SECTION B-B
C
DATUM
PLANE
VIEW ROTATED 90
-H-
°
-C-
0.10
H
SEATING
PLANE
M
G
NOTES:
MILLIMETERS
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
DIM MIN
MAX
14.10
14.10
2.45
0.38
2.40
A
B
C
D
E
13.90
13.90
2.15
0.22
2.00
0.22
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE
LEAD WHERE THE LEAD EXITS THE PLASTIC
BODY AT THE BOTTOM OF THE PARTING LINE.
4. DATUMS -A-, -B- AND -D- TO BE
DETERMINED AT DATUM PLANE -H-.
5. DIMENSIONS S AND V TO BE DETERMINED
AT SEATING PLANE -C-.
U
T
F
0.33
G
H
J
K
L
0.65 BSC
DATUM
PLANE
---
0.13
0.65
0.25
0.23
0.95
-H-
R
6. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
12.35 REF
M
N
P
5
10
0.17
°
°
PROTRUSION IS 0.25 PER SIDE. DIMENSIONS
A AND B DO INCLUDE MOLD MISMATCH
AND ARE DETERMINED AT DATUM PLANE -H-.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION. DAMBAR CANNOT
BE LOCATED ON THE LOWER RADIUS OR
THE FOOT.
0.13
0.325 BSC
K
Q
R
S
0
7
0.30
Q
°
°
W
0.13
16.95
0.13
17.45
---
---
17.45
0.45
X
T
DETAIL C
U
V
W
X
0
°
16.95
0.35
1.6 REF
Figure B-2 80-Pin QFP Mechanical Dimensions (Case no. 841B)
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MC9S12A256 Device Guide — V01.01
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MC9S12A256 Device Guide — V01.01
User Guide End Sheet
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MC9S12A256 Device Guide — V01.01
FINAL PAGE OF
96
PAGES
96
相关型号：
KMC9S12DG256BCPV
Microcontroller, 16-Bit, FLASH, 25MHz, CMOS, PQFP112, 20 X 20 MM, 1.40 MM HEIGHT, 0.65 MM PITCH, PLASTIC, LQFP-112
MOTOROLA
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