LH7A400N0B000B3A [NXP]
32-Bit System-on-Chip;
| 型号： | LH7A400N0B000B3A |
| 厂家： | 
NXP |
| 描述： | 32-Bit System-on-Chip |
| 文件： | 总65页 (文件大小：814K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LH7A400
32-Bit System-on-Chip
Preliminary data sheet
• Three Programmable Timers
FEATURES
• 32-bit ARM9TDMI™ RISC Core
• Three UARTs
– Classic IrDA (115 kbit/s)
• Smart Card Interface (ISO7816)
– 16 kB Cache: 8 kB Instruction and 8 kB Data
– MMU (Windows CE™ Enabled)
– Up to 250 MHz; see Table 1 for options
• Two DC-to-DC Converters
• MultiMediaCard™ Interface
• AC97 Codec Interface
• 80 kB On-Chip Static RAM
• Programmable Interrupt Controller
• External Bus Interface
– Up to 125 MHz; see Table 1 for options
– Asynchronous SRAM/ROM/Flash
– Synchronous DRAM/Flash
– PCMCIA
• Smart Battery Monitor Interface
• Real Time Clock (RTC)
• Up to 60 General Purpose I/Os
• Watchdog Timer
• JTAG Debug Interface and Boundary Scan
• Operating Voltage
– CompactFlash
• Clock and Power Management
– 32.768 kHz and 14.7456 MHz Oscillators
– Programmable PLL
– 1.8 V Core
– 3.3 V Input/Output
• 5 V Tolerant Digital Inputs (except oscillator pins)
– Oscillator pins P15, P16, R13, and T13 are
1.8 V 10 %.
• Programmable LCD Controller
– Up to 1,024 × 768 Resolution
– Supports STN, Color STN, AD-TFT, HR-TFT, TFT
– Up to 64 k-Colors and 15 Gray Shades
• Operating Temperature: −40°C to +85°C
• 256-ball BGA or 256-ball LFBGA Package
• DMA (10 Channels)
– AC97
DESCRIPTION
– MMC
The LH7A400, powered by an ARM922T, is a com-
plete System-on-Chip with a high level of integration to
satisfy a wide range of requirements and expectations.
– USB
• USB Device Interface (USB 2.0, Full Speed)
• Synchronous Serial Port (SSP)
– Motorola SPI™
This high degree of integration lowers overall
system costs, reduces development cycle time and
accelerates product introduction.
– Texas Instruments SSI
– National MICROWIRE™
Table 1. LH7A400 versions
BUS
CORE
PART NUMBER
LH7A400N0F076B5
LH7A400N0F000B3A
LH7A400N0F000B5
LH7A400N0G000B5
LOW POWER CURRENT BY MODE (TYP.)
TEMP. RANGE
CLOCK
CLOCK
0°C to +70°C/
−40°C to +85°C
250 MHz/
245 MHz
125 MHz Run = 250 mA; Halt = 50 mA; Standby = 129 µA
100 MHz Run = 125 mA; Halt: 25 mA; Standby = 42 µA
100 MHz Run = 125 mA; Halt: 25 mA; Standby = 42 µA
100 MHz Run = 125 mA; Halt: 25 mA; Standby = 42 µA
200 MHz/
195 MHz
0°C to +70°C/
−40°C to +85°C
200 MHz/
195 MHz
0°C to +70°C/
−40°C to +85°C
200 MHz/
195 MHz
0°C to +70°C/
−40°C to +85°C
Preliminary data sheet
1
LH7A400
NXP Semiconductors
32-Bit System-on-Chip
Table 2. Ordering information
Package
Type number
Version
Name
BGA256
Description
plastic ball grid array package; 256 balls
LH7A400N0G000B5
LH7A400N0F000B3A
SOT1018-1
plastic low profile fine-pitch ball grid array
package; 256 balls
LFBGA256
LFBGA256
LFBGA256
SOT1020-1
SOT1020-1
SOT1020-1
plastic low profile fine-pitch ball grid array
package; 256 balls
LH7A400N0F000B5
LH7A400N0F076B5
plastic low profile fine-pitch ball grid array
package; 256 balls
2
Rev. 01 — 16 July 2007
Preliminary data sheet
32-Bit System-on-Chip
NXP Semiconductors
LH7A400
LH7A400
14.7456 MHz 32.768 kHz
REAL TIME
CLOCK
OSCILLATOR,
PLL1 and PLL2, POWER
MANAGEMENT, and
RESET CONTROL
WATCHDOG
TIMER
TIMER (3)
ARM922T
INTERRUPT
CONTROLLER
GENERAL
PURPOSE I/O
(60)
STATIC
(ASYNCHRONOUS)
MEMORY
CONTROLLER
(SMC)
SYNCHRONOUS
SERIAL PORT
ADVANCED
PERIPHERAL
BUS BRIDGE
BATTERY
MONITOR
INTERFACE
PCMCIA/CF
CONTROLLER
EXTERNAL
BUS
INTERFACE
SYNCHRONOUS
DYNAMIC RAM
CONTROLLER
(SDMC)
UART (3)
IrDA
INTERFACE
LCD AHB
BUS
USB DEVICE
INTERFACE
80KB
SRAM
MULTIMEDIACARD
INTERFACE
COLOR LCD
CONTROLLER
DMA
CONTROLLER
ADVANCED AUDIO
CODEC (AC97)
ADVANCED LCD
INTERFACE
AUDIO CODEC
INTERFACE
SMART CARD
INTERFACE
(ISO7816)
ADVANCED
HIGH-PERFORMANCE
BUS (AHB)
ADVANCED
PERPHERAL
BUS (APB)
DC to DC
INTERFACE
(2)
LH7A400-1
Figure 1. LH7A400 block diagram
Preliminary data sheet
Rev. 01 — 16 July 2007
3
LH7A400
NXP Semiconductors
32-Bit System-on-Chip
LH7A400
ball A1
index area
2
4
6
8
10 12 14 16
9 11 13 15
1
3
5
7
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
002aad223
Transparent top view
Figure 2. Pin configuration (BGA256)
LH7A400
ball A1
index area
2
4
6
8
10 12 14 16
9 11 13 15
1
3
5
7
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
002aad224
Transparent top view
Figure 3. Pin configuration (LFBGA256)
4
Rev. 01 — 16 July 2007
Preliminary data sheet
32-Bit System-on-Chip
NXP Semiconductors
LH7A400
Table 3. Functional Pin List
BGA LFBGA
SIGNAL
RESET
STATE
STANDBY
STATE
OUTPUT
DRIVE
DESCRIPTION
I/O NOTES
PIN
PIN
G7
F1
C10
F9
K7
F11
F14
G8
H13
J9
M1
M5
T6
R14
M14
J11
J12
F13
B14
E10
B8
VDD
I/O Ring Power
K15
L7
N6
N8
N12
N13
P11
B8
H7
G3
C6
K4
D5
N5
D13
E8
P6
T14
R16
N16
K13
H9
F7
G13
H9
VSS
I/O Ring Ground
J14
K7
C15
A11
E8
L8
L10
L12
M11
M14
C4
A5
F7
E1
J4
D7
P3
D10
F4
T8
K9
F10
J4
VDDC
Core Power
L13
E15
D12
A7
J8
K8
L6
H5
G7
H4
M3
L9
H8
T10
N15
H12
B15
C9
L4
L9
VSSC
Core Ground
N3
N7
N10
R5
G6
Preliminary data sheet
Rev. 01 — 16 July 2007
5
LH7A400
NXP Semiconductors
32-Bit System-on-Chip
Table 3. Functional Pin List (Cont’d)
BGA LFBGA
RESET
STATE
STANDBY
STATE
OUTPUT
DRIVE
SIGNAL
DESCRIPTION
I/O NOTES
PIN
PIN
R11
N12
P12
T11
D3
P12
M10
R13
N11
E4
VDDA
Analog Power for PLL
VSSA
Analog Ground for PLL
Power On Reset
nPOR
Input
Input
No Change
No Change
I
I
3
3
User Reset; should be pulled HIGH for normal or
JTAG operation.
H6
D1
nURESET
D4
E4
C2
E2
F2
D2
WAKEUP
nPWRFL
nEXTPWR
Wake Up
Input
Input
Input
No Change
No Change
No Change
I
I
I
3
3
3
Power Fail Signal
External Power
14.7456 MHz Crystal Oscillator pins. An external
clock source can be connected to XTALIN leaving
XTALOUT open.
R13
T13
P16
P15
R14
R15
N14
M13
XTALIN
Input
HIGH
Input
No Change
HIGH
I
XTALOUT
XTAL32IN
XTAL32OUT
O
I
32.768 kHz Real Time Clock Crystal Oscillator
pins. An external clock source can be connected to
XTAL32IN leaving XTAL32OUT open.
No Change
No Change
Output
O
P14
J6
M12
J5
CLKEN
PGMCLK
nCS0
External Osc Clock Enable Output
Programmable Clock (14.7456 MHz MAX.)
Async Memory Chip Select 0
LOW
LOW
HIGH
HIGH
HIGH
LOW
8 mA
8 mA
O
O
O
O
O
LOW or HIGH
No Change
No Change
No Change
K11
K10
P13
P14
P16
N15
12 mA
12 mA
12 mA
nCS1
Async Memory Chip Select 1
nCS2
Async Memory Chip Select 2
nCS3/
nMMSPICS
• Async Memory Chip Select 3
• MultiMediaCard SPI Mode Chip Select
HIGH:
nCS3
M12
N16
No Change
12 mA
O
L12
M15
N13
L16
L15
L14
H11
K12
J15
L11
L13
L14
K11
L16
K14
J15
J12
J10
H16
H14
H11
G16
G9
D0
D1
D2
D3
D4
D5
D6
D7
D8
J13
D9
J10
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
H15
H13
G15
G11
G12
F15
F12
E14
D16
H10
D14
F10
A16
A14
B13
Data Bus
LOW
LOW
12 mA I/O
G14
G12
F15
E15
D16
F12
E13
D14
E12
B16
D12
A16
6
Rev. 01 — 16 July 2007
Preliminary data sheet
32-Bit System-on-Chip
NXP Semiconductors
LH7A400
Table 3. Functional Pin List (Cont’d)
BGA LFBGA
SIGNAL
RESET
STATE
STANDBY
STATE
OUTPUT
DRIVE
DESCRIPTION
I/O NOTES
PIN
PIN
C13
E12
G10
B12
B11
D11
B13
B14
C12
A14
B12
A12
D26
D27
D28
D29
D30
D31
Data Bus
LOW
LOW
12 mA I/O
• Asynchronous Address Bus
• Asynchronous Memory Write Byte Enable 1
HIGH:
nWE1
M16
N14
M15
M16
A0/nWE1
A1/nWE2
HIGH
HIGH
12 mA
12 mA
O
O
• Asynchronous Address Bus
• Asynchronous Memory Write Byte Enable 2
HIGH:
nWE2
M13
K16
K15
K14
J8
L15
K12
K13
K16
J13
A2/SA0
A3/SA1
A4/SA2
A5/SA3
A6/SA4
J16
J14
J9
J11
A7/SA5
J16
A8/SA6
• Asynchronous Address Bus
• Synchronous Address Bus
LOW
LOW
12 mA
O
H15
H10
H12
G15
G10
G11
F16
A9/SA7
H16
H14
G16
G14
G13
F16
A10/SA8
A11/SA9
A12/SA10
A13/SA11
A14/SA12
A15/SA13
• Async Address Bus
• Sync Device Bank Address 0
F14
E16
E16
F13
A16/SB0
A17/SB1
LOW
LOW
LOW
LOW
12 mA
12 mA
O
O
• Async Address Bus
• Sync Device Bank Address 1
E13
F11
D15
C16
B16
A15
A13
E14
D15
C16
C15
C14
B15
E11
A18
A19
A20
A21
A22
A23
A24
Asynchronous Address Bus
LOW
LOW
12 mA
O
• Async Memory Address Bus
• Smart Card Interface I/O (Data)
G8
F8
A8
D8
B7
A7
A25/SCIO
LOW: A25
LOW: A26
LOW: A27
LOW
LOW
LOW
12 mA I/O
12 mA I/O
• Async Memory Address Bus
• Smart Card Interface Clock
A26/SCCLK
A27/SCRST
• Async Memory Address Bus
• Smart Card Interface Reset
12 mA
O
D8
C8
C8
F8
D9
nOE
Async Memory Output Enable
HIGH
HIGH
HIGH
No Change
No Change
No Change
12 mA
12 mA
8 mA
O
O
O
nWE0
nWE3
Async Memory Write Byte Enable 0
Async Memory Write Byte Enable 3
D10
• Async Memory Chip Select 6
• Sync Memory Clock Enable 1 or 2
B10
C10
E9
CS6/SCKE1_2
CS7/SCKE0
LOW: CS6
LOW: CS7
No Change
No Change
12 mA
O
O
• Async Memory Chip Select 7
• Sync Memory Clock Enable 0
A10
12 mA
12 mA
G9
A10
C14
A11
B10
C13
SCKE3
SCLK
Sync Memory Clock Enable 3
Sync Memory Clock
LOW
LOW
HIGH
LOW
O
I/O
O
No Change
No Change
2
nSCS0
Sync Memory Chip Select 0
12 mA
Preliminary data sheet
Rev. 01 — 16 July 2007
7
LH7A400
NXP Semiconductors
32-Bit System-on-Chip
Table 3. Functional Pin List (Cont’d)
BGA LFBGA
RESET
STANDBY
OUTPUT
DRIVE
SIGNAL
nSCS1
DESCRIPTION
I/O NOTES
PIN
PIN
STATE
STATE
D13
E11
A12
C12
C11
F9
A15
D11
E10
A13
B11
C11
C9
Sync Memory Chip Select 1
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
12 mA
12 mA
12 mA
12 mA
12 mA
12 mA
12 mA
12 mA
12 mA
12 mA
O
O
O
O
O
O
O
O
O
O
nSCS2
nSCS3
nSWE
nCAS
Sync Memory Chip Select 2
Sync Memory Chip Select 3
Sync Memory Write Enable
Sync Memory Column Address Strobe Signal
Sync Memory Row Address Strobe Signal
Sync Memory Data Mask 0
Sync Memory Data Mask 1
Sync Memory Data Mask 2
Sync Memory Data Mask 3
• GPIO Port A
nRAS
A9
DQM0
DQM1
DQM2
DQM3
B9
A9
D9
B9
E9
A8
J5
K1
K2
PA0/LCDVD16 • LCD Data bit 16. This CLCDC output signal is
always LOW.
Input: PA0
Input: PA1
No Change
No Change
8 mA
8 mA
I/O
I/O
• GPIO Port A
K1
PA1/LCDVD17 • LCD Data bit 17. This CLCDC output signal is
always LOW.
K2
K3
K5
L1
L2
L3
K3
K4
K6
K5
L1
L2
PA2
PA3
I/O
I/O
I/O
I/O
I/O
I/O
PA4
GPIO Port A
PA5
Input
No Change
No Change
8 mA
PA6
PA7
PB0/
UARTRX1
• GPIO Port B
• UART1 Receive Data Input
L4
L3
Input: PB0
Input: PB1
8 mA
8 mA
I/O
LOW if
PINMUX:
UART3CON
= 1 (bit 3);
otherwise
No Change
• GPIO Port B
• UART3 Transmit Data Out
L5
M1
PB1/UARTTX3
I/O
PB2/
UARTRX3
• GPIO Port B
• UART3 Receive Data In
L7
M2
M4
N1
M2
M3
L5
Input: PB2
Input: PB3
Input: PB4
Input: PB5
No Change
No Change
No Change
No Change
8 mA
8 mA
8 mA
8 mA
I/O
I/O
I/O
I/O
PB3/
UARTCTS3
• GPIO Port B
• UART3 Clear to Send
PB4/
UARTDCD3
• GPIO Port B
• UART3 Data Carrier Detect
PB5/
UARTDSR3
• GPIO Port B
• UART3 Data Set Ready
N1
• GPIO Port B
• Single Wire Data
• Smart Battery Data
PB6/SWID/
SMBD
N2
N2
Input: PB6
No Change
8 mA
8 mA
I/O
PB7/
SMBCLK
• GPIO Port B
• Smart Battery Clock
N3
P1
P2
R1
K6
L8
M4
P1
P2
R1
M5
P3
Input: PB7
LOW: PC0
LOW: PC1
LOW: PC2
LOW: PC3
LOW: PC4
No Change
No Change
No Change
No Change
No Change
No Change
I/O
7
PC0/
UARTTX1
• GPIO Port C
• UART1 Transmit Data Output
12 mA I/O
12 mA I/O
12 mA I/O
12 mA I/O
12 mA I/O
• GPIO Port C
• HR-TFT Power Save
PC1/LCDPS
PC2/
LCDVDDEN
• GPIO Port C
• HR-TFT Power Sequence Control
• GPIO Port C
• HR-TFT Gray Scale Voltage Reverse
PC3/LCDREV
PC4/
LCDSPS
• GPIO Port C
• HR-TFT Reset Row Driver Counter
8
Rev. 01 — 16 July 2007
Preliminary data sheet
32-Bit System-on-Chip
NXP Semiconductors
LH7A400
Table 3. Functional Pin List (Cont’d)
BGA LFBGA
SIGNAL
RESET
STATE
STANDBY
STATE
OUTPUT
DRIVE
DESCRIPTION
I/O NOTES
PIN
PIN
PC5/
LCDCLS
• GPIO Port C
• HR-TFT Row Driver Clock
T1
N4
LOW: PC5
No Change
No Change
No Change
12 mA I/O
12 mA I/O
12 mA I/O
PC6/LCDHR- • GPIO Port C
LP
T2
R2
R2
N5
LOW: PC6
LOW: PC7
• LCD Latch Pulse
PC7/
LCDSPL
• GPIO Port C
• LCD Start Pulse Left
M11
L11
K8
M9
K10
P10
T11
T12
R11
R12
T13
T9
PD0/LCDVD8
PD1/LCDVD9
PD2/LCDVD10
PD3/LCDVD11
PD4/LCDVD12
PD5/LCDVD13
PD6/LCDVD14
PD7/LCDVD15
PE0/LCDVD4
PE1/LCDVD5
PE2/LCDVD6
LOW: PD0
LOW: PD1
LOW: PD2
LOW: PD3
LOW: PD4
LOW: PD5
LOW: PD6
LOW: PD7
Input: PE0
Input: PE1
Input: PE2
I/O
I/O
I/O
LOW if
PINMUX:
PDOCON = 1
(bit 1);
otherwise,
No Change
N11
R9
I/O
12 mA
• GPIO Port D
• LCD Video Data Bus
I/O
T9
I/O
I/O
I/O
I/O
I/O
P10
R10
L10
N10
M9
LOW if
PINMUX:
PDOCON or
PEOCON = 1
(bits [1:0]);
otherwise
K9
• GPIO Port E
• LCD Video Data Bus
T10
I/O
12 mA
M10
A6
R10
A5
PE3/LCDVD7
PF0/INT0
Input: PE3
I/O
No Change
• GPIO Port F
• External FIQ Interrupt. Interrupts can be level or Input: PF0
edge triggered and are internally debounced.
No Change
8 mA
I/O
3
• GPIO Port F
• External IRQ Interrupts. Interrupts can be level or
edge triggered and are internally debounced.
B6
C6
B4
E7
PF1/INT1
PF2/INT2
Input: PF1
Input: PF2
No Change
No Change
8 mA
8 mA
I/O
I/O
3
3
• GPIO Port F
H8
B5
B3
C5
PF3/INT3
• External IRQ Interrupt. Interrupts can be level or Input: PF3
edge triggered and are internally debounced.
No Change
8 mA
8 mA
I/O
I/O
3
3
• GPIO Port F
LOW if SCI is
Enabled;
otherwise
PF4/INT4/
SCVCCEN
• External IRQ Interrupt. Interrupts can be level or
edge triggered and are internally debounced.
Input: PF4
• Smart Card Supply Voltage Enable
No Change
• GPIO Port F
PF5/INT5/
SCDETECT
• External IRQ Interrupt. Interrupts can be level or
Input: PF5
D6
E6
D6
A4
No Change
No Change
8 mA
8 mA
I/O
I/O
3
3
edge triggered and are internally debounced.
• Smart Card Detection
• GPIO Port F
• External IRQ Interrupt. Interrupts can be level or
PF6/INT6/
PCRDY1
edge triggered and are internally debounced.
• Ready for Card 1 for PC Card (PCMCIA or CF) in
single or dual card mode
Input: PF6
Input: PF7
• GPIO Port F
• External IRQ Interrupt. Interrupts can be level or
edge triggered and are internally debounced.
• Ready for Card 2 for PC Card (PCMCIA or CF) in
single or dual card mode
PF7/INT7/
PCRDY2
C5
A3
No Change
8 mA
I/O
3
• GPIO Port G
R3
T3
M6
T1
PG0/nPCOE
PG1/nPCWE
• Output Enable for PC Card (PCMCIA or CF) in
single or dual card mode
LOW: PG0 No Change
8 mA
8 mA
I/O
I/O
• GPIO Port G
• Write Enable for PC Card (PCMCIA or CF) in sin- LOW: PG1 No Change
gle or dual card mode
Preliminary data sheet
Rev. 01 — 16 July 2007
9
LH7A400
NXP Semiconductors
32-Bit System-on-Chip
Table 3. Functional Pin List (Cont’d)
BGA LFBGA
RESET
STATE
STANDBY
STATE
OUTPUT
DRIVE
SIGNAL
PG2/
DESCRIPTION
I/O NOTES
PIN
PIN
• GPIO Port G
L6
P4
• I/O Read Strobe for PC Card (PCMCIA or CF) in LOW: PG2 No Change
single or dual card mode
8 mA
8 mA
8 mA
I/O
nPCIOR
• GPIO Port G
PG3/
nPCIOW
M6
N6
R3
T2
• I/O Write Strobe for PC Card (PCMCIA or CF) in LOW: PG3 No Change
single or dual card mode
I/O
I/O
• GPIO Port G
PG4/nPCREG • Register Memory Access for PC Card (PCMCIA LOW: PG4 No Change
or CF) in single or dual card mode
• GPIO Port G
• Card Enable 1 for PC Card (PCMCIA or CF) in
M7
M8
P5
R4
PG5/nPCCE1
single or dual card mode. This signal and
nPCCE2 are used by the PC Card for decoding
low and high byte accesses.
LOW: PG5 No Change
LOW: PG6 No Change
8 mA
8 mA
I/O
I/O
• GPIO Port G
• Card Enable 2 for PC Card (PCMCIA or CF) in
single or dual card mode. This signal and
nPCCE1 are used by the PC Card for decoding
low and high byte accesses.
PG6/nPCCE2
PG7/PCDIR
• GPIO Port G
N4
P4
T3
P6
• Direction for PC Card (PCMCIA or CF) in single LOW: PG7 No Change
or dual card mode
8 mA
8 mA
I/O
I/O
• GPIO Port H
PH0/
PCRESET1
• Reset Card 1 for PC Card (PCMCIA or CF) in sin- Input: PH0
gle or dual card mode
No Change
• GPIO Port H
PH1/CFA8/
PCRESET2
• Address Bit 8 for PC Card (CF) in single card mode
• Reset Card 2 for PC Card (PCMCIA or CF) in
dual card mode
R4
T4
T4
Input: PH1
No Change
8 mA
8 mA
I/O
I/O
• GPIO Port H
PH2/
nPCSLOTE1
• Enable Card 1 for PC Card (PCMCIA or CF) in sin-
Input: PH2
M7
No Change
gle or dual card mode. This signal is used for gating
other control signals to the appropriate PC Card.
• GPIO Port H
• Address Bit 9 for PC Card (CF) in single card mode
• Address Bit 25 for PC Card (PCMCIA) in single
PH3/CFA9/
N7
P8
P5
T5
R6
R7
PCMCIAA25/
nPCSLOTE2
card mode
Input: PH3
No Change
No Change
No Change
8 mA
8 mA
8 mA
I/O
I/O
I/O
• Enable Card 2 for PC Card (PCMCIA or CF) in
dual card mode. This signal is used for gating
other control signals to the appropriate PC Card.
• GPIO Port H
PH4/
nPCWAIT1
• WAIT Signal for Card 1 for PC Card (PCMCIA or Input: PH4
CF) in single or dual card mode
• GPIO Port H
• Address Bit 10 for PC Card (CF) in single
card mode
• Address Bit 24 for PC Card (PCMCIA) in single
card mode
PH5/CFA10/
PCMCIAA24/
nPCWAIT2
Input: PH5
• WAIT Signal for Card 2 for PC Card (PCMCIA or
F) in dual card mode
PH6/
• GPIO Port H
R5
T5
P7
T6
Input: PH6
No Change
No Change
8 mA
8 mA
I/O
I/O
nAC97RESET • Audio Codec (AC97) Reset
• GPIO Port H
PH7/
nPCSTATRE
• Status Read Enable for PC Card (PCMCIA or F) Input: PH7
in single or dual card mode
R6
R8
T7
LCDFP
LCDLP
LCD Frame Synchronization pulse
LCD Line Synchronization pulse
LOW
LOW
LOW
LOW
12 mA
12 mA
O
O
R9
10
Rev. 01 — 16 July 2007
Preliminary data sheet
32-Bit System-on-Chip
NXP Semiconductors
LH7A400
Table 3. Functional Pin List (Cont’d)
BGA LFBGA
SIGNAL
RESET
STATE
STANDBY
STATE
OUTPUT
DRIVE
DESCRIPTION
I/O NOTES
PIN
PIN
LCDENAB/
LCDM
LCD TFT Data Enable
LCD STN AC Bias
LCD Data Clock
LOW:
LCDENAB
P9
P9
LOW
LOW
12 mA
12 mA
O
N9
P7
N9
M8
P8
LCDDCLK
LCDVD0
LCDVD1
LCDVD2
LCDVD3
USBDP
LOW
O
O
O
O
O
R7
LCD Video Data Bus
LOW
LOW
12 mA
T7
R8
N8
T8
T15
T16
T16
R16
USB Data Positive (Differential Pair)
USB Data Negative (Differential Pair)
Input
Input
No Change
No Change
I/O
I/O
10
10
USBDN
• DC-DC Converter Pulse Width
• Modulator 0 Enable
E7
D7
C7
A6
nPWME0
nPWME1
Input
Input
No Change
No Change
I
I
• DC-DC Converter Pulse Width
• Modulator 1 Enable
• DC-DC Converter Pulse Width
C7
B7
B6
B5
PWM0
PWM1
• Modulator 0 Output during normal operation and
Polarity Selection input at reset
Input
Input
No Change
No Change
8 mA
8 mA
I/O
I/O
• DC-DC Converter Pulse Width
• Modulator 1 Output during normal operation and
Polarity Selection input at reset
• Audio Codec (AC97) Clock
• Audio Codec (ACI) Clock
C4
D5
A2
A1
ACBITCLK
ACOUT
Input
LOW
No Change
No Change
8 mA
8 mA
I/O
O
• Audio Codec (AC97) Output
• Audio Codec (ACI) Output
• Audio Codec (AC97)
B4
B2
ACSYNC
ACIN
Synchronization
• Audio Codec (ACI) Synchronization
LOW
Input
No Change
8 mA
O
• Audio Codec (AC97) Input
• Audio Codec (ACI) Input
A4
A3
B3
A2
E2
E3
E6
C3
B1
D4
E1
F3
No Change
LOW
I
O
I/O
I/O
I
MMCCLK/
MMSPICLK
• MultiMediaCard Clock (20 MHz MAX.)
• MultiMediaCard SPI Mode Clock
LOW:
MMCCLK
8 mA
8 mA
8 mA
MMCCMD/
MMSPIDIN
• MultiMediaCard Command
• MultiMediaCard SPI Mode Data Input
Input:
MMCCMD
Input
MMCDATA/
• MultiMediaCard Data
Input:
MMCDATA
Input
MMSPIDOUT • MultiMediaCard SPI Mode Data Output
• UART2 Clear to Send Signal. This pin is an
UARTCTS2
Input
Input
No Change
No Change
output for JTAG boundary scan only.
• UART2 Data Carrier Detect Signal. This pin is
UARTDCD2
I
output for JTAG boundary scan only.
E5
F2
G4
G5
UARTDSR2
UARTIRTX1
UART2 Data Set Ready Signal
IrDA Transmit
Input
LOW
No Change
No Change
I
8 mA
8 mA
8 mA
O
IrDA Receive. This pin is an output for JTAG
boundary scan only.
F3
F4
J7
G6
F1
G3
UARTIRRX1
UARTTX2
UARTRX2
Input
HIGH
Input
No Change
No Change
No Change
I
O
I
UART2 Transmit Data Output
UART2 Receive Data Input. This pin is an output
for JTAG boundary scan only.
H4
J1
J2
J3
J6
J7
SSPCLK
SSPRX
SSPTX
Synchronous Serial Port Clock
Synchronous Serial Port Receive
Synchronous Serial Port Transmit
LOW
Input
LOW
No Change
No Change
LOW
O
I
8 mA
8 mA
I/O
SSPFRM/
nSSPFRM
J3
J2
Synchronous Serial Port Frame Sync
Input
Input
I/O
Preliminary data sheet
Rev. 01 — 16 July 2007
11
LH7A400
NXP Semiconductors
32-Bit System-on-Chip
Table 3. Functional Pin List (Cont’d)
BGA LFBGA
RESET
STANDBY
OUTPUT
DRIVE
SIGNAL
COL0
DESCRIPTION
I/O NOTES
PIN
PIN
G2
G1
H3
H5
H6
H7
H2
H1
J1
STATE
STATE
F6
F5
COL1
COL2
COL3
COL4
COL5
COL6
COL7
TBUZ
G1
G2
G4
G5
H1
H2
H3
Keyboard Interface
HIGH
HIGH
8 mA
8 mA
O
O
Timer Buzzer (254 kHz MAX.)
LOW
Input
LOW
Boot Device Media Change. Used with WIDTH0
and WIDTH1 to specify boot memory device.
C3
F5
MEDCHG
No Change
I
3
3
External Memory Width Pins. Also, used with
MEDCHG to specify the boot memory device size.
The pins must be pulled HIGH with a 33 kΩ resistor.
P11
R12
T14
T15
WIDTH0
WIDTH1
Input
No Change
I
D1
D2
E3
F6
BATOK
Battery OK
Input
Input
No Change
No Change
I
I
3
3
nBATCHG
Battery Change
JTAG Data In. This signal is internally pulled-up t
o VDD.
A1
B1
B2
C1
E5
C2
D3
C1
TDI
Input
Input
No Change
No Change
No Change
No Change
I
I
4
3
JTAG Clock. This signal should be externally
pulled-up to VDD with a 33 kΩ resistor.
TCK
TDO
TMS
JTAG Data Out. This signal should be externally
pulled up to VDD with a 33 kΩ resistor.
High-Z
Input
4 mA
O
I
JTAG Test Mode select. This signal is internally
pulled-up to VDD.
4
4
Test Pin 0. Internally pulled up to VDD. For Normal
mode, leave open. For JTAG mode, tie to GND.
See Table 4.
T12
R15
P15
P13
nTEST0
nTEST1
Input
No Change
I
Test Pin 1. internally pulled up to VDD. For Normal
and JTAG mode, leave open. See Table 4.
1. Signals beginning with ‘n’ are Active LOW.
2. The SCLK pin can source up to 12 mA and sink up to 20 mA. See ‘DC Characteristics’.
3. Schmitt trigger input; see ’DC Specifications’, page 31 for triggers points and hysteresis.
4. Input only for JTAG boundary scan mode.
5. Output only for JTAG boundary scan mode.
6. The internal pullup and pull-down resistance on all digital I/O pins is 50 kΩ
7. When used as SMBCLK, this pin must have a resistor.
8. The RESET STATE is defined as the state during power-on reset.
9. The STANDBY STATE is defined as the state when the device is in standby. During this state,
I/O cells are forced to input (Input), output driving low (LOW), output driving high (HIGH), or their
current state is preserved (No Change). In some case, function selection has an overall effect on the standby state.
10.All unused USB Device pins with a differential pair must be pulled
to ground with a 15 kΩ resistor.
Table 4. nTest Pin Function
MODE
JTAG
nTEST0
nTEST1
nURESET
0
1
1
1
1
x
Normal
12
Rev. 01 — 16 July 2007
Preliminary data sheet
32-Bit System-on-Chip
NXP Semiconductors
LH7A400
Table 5. LCD Data Multiplexing
STN
LCD
BGA
PIN
LFBGA
PIN
MONO 4-BIT
MONO 8-BIT
COLOR
AD-TFT/
HR-TFT
DATA
TFT
SIGNAL
SINGLE
PANEL
DUAL
PANEL
SINGLE
DUAL
PANEL
SINGLE
DUAL
PANEL
PANEL
PANEL
K1
J5
K2
K1
LCDVD17
LCDVD16
LCDVD15
LCDVD14
LCDVD13
LCDVD12
LCDVD11
LCDVD10
LCDVD9
LCDVD8
LCDVD7
LCDVD6
LCDVD5
LCDVD4
LCDVD3
LCDVD2
LCDVD1
LCDVD0
LOW
LOW
R10
P10
T9
T13
R12
R11
T12
T11
P10
K10
M9
MLSTN7
MLSTN6
MLSTN5
MLSTN4
MLSTN3
MLSTN2
MLSTN1
MLSTN0
MUSTN7
MUSTN6
MUSTN5
MUSTN4
MUSTN3
MUSTN2
MUSTN1
MUSTN0
CLSTN7
CLSTN6
CLSTN5
CLSTN4
CLSTN3
CLSTN2
CLSTN1
CLSTN0
CUSTN7
CUSTN6
CUSTN5
CUSTN4
CUSTN3
CUSTN2
CUSTN1
CUSTN0
Intensity
BLUE4
BLUE3
BLUE2
BLUE1
BLUE0
GREEN4
GREEN3
GREEN2
GREEN1
GREEN0
RED4
Intensity
BLUE4
BLUE3
BLUE2
BLUE1
BLUE0
GREEN4
GREEN3
GREEN2
GREEN1
GREEN0
RED4
R9
N11
K8
L11
M11
M10
M9
N10
L10
N8
R10
T10
K9
MLSTN3
MLSTN2
MLSTN1
MLSTN0
MUSTN3
MUSTN2
MUSTN1
MUSTN0
MUSTN7
MUSTN6
MUSTN5
MUSTN4
MUSTN3
MUSTN2
MUSTN1
MUSTN0
CUSTN7
CUSTN6
CUSTN5
CUSTN4
CUSTN3
CUSTN2
CUSTN1
CUSTN0
T9
T8
MUSTN3
MUSTN2
MUSTN1
MUSTN0
RED3
RED3
T7
R8
RED2
RED2
R7
P8
RED1
RED1
P7
M8
RED0
RED0
Notes:
1. The Intensity bit is identically generated for all three colors.
2. MU = Monochrome Upper
3. CU = Color Upper
4. CL = Color Lower
Preliminary data sheet
Rev. 01 — 16 July 2007
13
LH7A400
BGA PIN
NXP Semiconductors
32-Bit System-on-Chip
Table 6. 256-Ball BGA Package
Numerical Pin List
Table 6. 256-Ball BGA Package
Numerical Pin List (Cont’d)
SIGNAL
BGA PIN SIGNAL
A1
A2
TDI
C14
C15
C16
D1
nSCS0
VSS
MMCDATA/MMSPIDOUT
A3
MMCCLK/MMSPICLK
ACIN
A21
A4
BATOK
nBATCHG
nPOR
A5
VSS
D2
A6
PF0/INT0
VDDC
D3
A7
D4
WAKEUP
ACOUT
PF5/INT5/SCDETECT
nPWME1
nOE
A8
A27/SCRST
DQM0
D5
A9
D6
A10
A11
A12
A13
A14
A15
A16
B1
SCLK
D7
VSS
D8
nSCS3
D9
DQM2
A24
D10
D11
D12
D13
D14
D15
D16
E1
nWE3
D24
D31
A23
VDDC
D23
nSCS1
D21
TCK
B2
TDO
A20
B3
MMCCMD/MMSPIDIN
ACSYNC
PF4/INT4/SCVCCEN
PF1/INT1
PWM1
D19
B4
VDDC
B5
E2
UARTCTS2
UARTDCD2
nPWRFL
UARTDSR2
PF6/INT6/PCRDY1
nPWME0
VSS
B6
E3
B7
E4
B8
VDD
E5
B9
DQM1
E6
B10
B11
B12
B13
B14
B15
B16
C1
CS6/SCKE1_2
D30
E7
E8
D29
E9
DQM3
D25
E10
E11
E12
E13
E14
E15
E16
F1
VDD
VDD
nSCS2
D27
VSSC
A22
A18
TMS
D18
C2
nEXTPWR
MEDCHG
ACBITCLK
PF7/INT7/PCRDY2
PF2/INT2
PWM0
VDDC
C3
A17/SB1
VDD
C4
C5
F2
UARTIRTX1
UARTIRRX1
UARTTX2
COL1
C6
F3
C7
F4
C8
nWE0
F5
C9
VSSC
F6
COL0
C10
C11
C12
C13
CS7/SCKE0
nCAS
F7
VSS
F8
A26/SCCLK
nRAS
nSWE
F9
D26
F10
D22
14
Rev. 01 — 16 July 2007
Preliminary data sheet
32-Bit System-on-Chip
NXP Semiconductors
LH7A400
Table 6. 256-Ball BGA Package
Numerical Pin List (Cont’d)
Table 6. 256-Ball BGA Package
Numerical Pin List (Cont’d)
BGA PIN
SIGNAL
BGA PIN
SIGNAL
F11
F12
F13
F14
F15
F16
G1
A19
J8
J9
A6/SA4
A9/SA7
D10
D17
VDD
J10
J11
J12
J13
J14
J15
J16
K1
A16/SB0
D16
VDD
VDD
A15/SA13
COL2
D9
A8/SA6
D8
G2
COL3
G3
VSS
A7/SA5
PA1/LCDVD17
PA2
G4
COL4
G5
COL5
K2
G6
VSSC
K3
PA3
G7
VDD
K4
VSS
G8
A25/SCIO
SCKE3
D28
K5
PA4
G9
K6
PC3/LCDREV
VDD
G10
G11
G12
G13
G14
G15
G16
H1
K7
D14
K8
PD2/LCDVD10
VDDC
D15
K9
A14/SA12
A13/SA11
D13
K10
K11
K12
K13
K14
K15
K16
L1
nCS1
nCS0
D7
A12/SA10
COL6
VSS
A5/SA3
A4/SA2
A3/SA1
PA5
H2
COL7
H3
TBUZ
H4
SSPCLK
VSSC
H5
L2
PA6
H6
nURESET
VSS
L3
PA7
H7
L4
PB0/UARTRX1
PB1/UARTTX3
PG2/nPCIOR
PB2/UARTRX3
PC4/LCDSPS
VSSC
H8
PF3/INT3
VSS
L5
H9
L6
H10
H11
H12
H13
H14
H15
H16
J1
D20
L7
D6
L8
VSSC
L9
D12
L10
L11
L12
L13
L14
L15
L16
M1
M2
M3
PE0/LCDVD4
PD1/LCDVD9
D0
A11/SA9
D11
A10/SA8
SSPRX
SSPTX
SSPFRM/nSSPFRM
VDDC
VDDC
D5
J2
D4
J3
D3
J4
VDD
J5
PA0/LCDVD16
PGMCLK
UARTRX2
PB3/UARTCTS3
VSSC
J6
J7
Preliminary data sheet
Rev. 01 — 16 July 2007
15
LH7A400
BGA PIN
NXP Semiconductors
32-Bit System-on-Chip
Table 6. 256-Ball BGA Package
Numerical Pin List (Cont’d)
Table 6. 256-Ball BGA Package
Numerical Pin List (Cont’d)
SIGNAL
BGA PIN SIGNAL
M4
M5
PB4/UARTDCD3
VDD
P16
R1
XTAL32IN
PC2/LCDVDDEN
PC7/LCDSPL
PG0/nPCOE
PH1/CFA8/PCRESET2
PH6/nAC97RESET
LCDFP
M6
PG3/nPCIOW
PG5/nPCCE1
PG6/nPCCE2
PE2/LCDVD6
PE3/LCDVD7
PD0/LCDVD8
nCS3/nMMSPICS
A2/SA0
R2
M7
R3
M8
R4
M9
R5
M10
M11
M12
M13
M14
M15
M16
N1
R6
R7
LCDVD1
R8
LCDLP
R9
PD4/LCDVD12
PD7/LCDVD15
VDDA
VDD
R10
R11
R12
R13
R14
R15
R16
T1
D1
A0/nWE1
WIDTH1
PB5/UARTDSR3
PB6/SWID/SMBD
PB7/SMBCLK
PG7/PCDIR
VSS
XTALIN
N2
VDD
N3
nTEST1
N4
VSS
N5
PC5/LCDCLS
PC6/LCDHRLP
PG1/nPCWE
PH2/nPCSLOTE1
PH7/nPCSTATRE
VDD
N6
PG4/nPCREG
PH3/CFA9/PCMCIAA25/nPCSLOTE2
LCDVD3
T2
N7
T3
N8
T4
N9
LCDDCLK
T5
N10
N11
N12
N13
N14
N15
N16
P1
PE1/LCDVD5
PD3/LCDVD11
VDDA
T6
T7
LCDVD2
T8
VDDC
D2
T9
PD5/LCDVD13
VSSC
A1/nWE2
T10
T11
T12
T13
T14
T15
T16
VSSC
VSSA
VSS
nTEST0
PC0/UARTTX1
PC1/LCDPS
VDDC
XTALOUT
VSS
P2
P3
USBDP
P4
PH0/PCRESET1
PH5/CFA10/PCMCIAA24/nPCWAIT2
VSS
USBDN
P5
P6
P7
LCDVD0
P8
PH4/nPCWAIT1
LCDENAB/LCDM
PD6/LCDVD14
WIDTH0
P9
P10
P11
P12
P13
P14
P15
VSSA
nCS2
CLKEN
XTAL32OUT
16
Rev. 01 — 16 July 2007
Preliminary data sheet
32-Bit System-on-Chip
NXP Semiconductors
LH7A400
Table 7. 256-Ball LFBGA Package
Table 7. 256-Ball LFBGA Package
Numerical Pin List
Numerical Pin List
LFBGA PIN
SIGNAL
LFBGA PIN
SIGNAL
A1
A2
ACOUT
ACBITCLK
PF7/INT7/PCRDY2
PF6/INT6/PCRDY1
PF0/INT0
nPWME1
A27/SCRST
DQM3
C14
C15
C16
D1
A22
A21
A3
A20
A4
nURESET
nEXTPWR
TDO
A5
D2
A6
D3
A7
D4
MMCDATA/MMSPIDOUT
VSS
A8
D5
A9
DQM1
D6
PF5/INT5/SCDETECT
VDDC
A10
A11
A12
A13
A14
A15
A16
B1
CS7/SCKE0
SCKE3
D7
D8
A25/SCIO
nWE3
D31
D9
nSWE
D10
D11
D12
D13
D14
D15
D16
E1
VDDC
D29
nSCS2
D24
nSCS1
D25
VSS
MMCCMD/MMSPIDIN
ACSYNC
PF3/INT3
PF1/INT1
PWM1
D21
B2
A19
B3
D18
B4
UARTCTS2
WAKEUP
BATOK
nPOR
B5
E2
B6
PWM0
E3
B7
A26/SCCLK
VSS
E4
B8
E5
TDI
B9
DQM2
E6
ACIN
B10
B11
B12
B13
B14
B15
B16
C1
SCLK
E7
PF2/INT2
VSS
nCAS
E8
D30
E9
CS6/SCKE1_2
nSCS3
A24
D26
E10
E11
E12
E13
E14
E15
E16
F1
D27
A23
D22
D23
D20
TMS
A18
C2
TCK
D17
C3
MMCCLK/MMSPICLK
VDDC
A16/SB0
UARTTX2
nPWRFL
UARTDCD2
VDDC
C4
C5
PF4/INT4/SCVCCEN
VSS
F2
C6
F3
C7
nPWME0
nOE
F4
C8
F5
MEDCHG
nBATCHG
C9
DQM0
F6
C10
C11
C12
C13
VDD
F7
F8
F9
VSS
nRAS
nWE0
VDD
D28
nSCS0
Preliminary data sheet
Rev. 01 — 16 July 2007
17
LH7A400
NXP Semiconductors
32-Bit System-on-Chip
Table 7. 256-Ball LFBGA Package
Table 7. 256-Ball LFBGA Package
Numerical Pin List
Numerical Pin List
LFBGA PIN
SIGNAL
LFBGA PIN
SIGNAL
F10
F11
F12
F13
F14
F15
F16
G1
VDDC
J6
J7
SSPRX
SSPTX
VDDC
VDD
VDD
D19
J8
A17/SB1
VDD
J9
J10
J11
J12
J13
J14
J15
J16
K1
D8
D16
A7/SA5
D7
A15/SA13
COL1
A6/SA4
VSS
G2
COL0
G3
UARTRX2
UARTDSR2
UARTIRTX1
UARTIRRX1
VSSC
VDD
D6
G4
A8/SA6
PA0/LCDVD16
PA1/LCDVD17
PA2
G5
G6
K2
G7
K3
G8
K4
PA3
G9
D13
K5
PA5
G10
G11
G12
G13
G14
G15
G16
H1
A13/SA11
A14/SA12
D15
K6
PA4
K7
VSS
K8
VDDC
PE1/LCDVD5
PD1/LCDVD9
D3
VSS
K9
D14
K10
K11
K12
K13
K14
K15
K16
L1
A12/SA10
D12
A3/SA1
A4/SA2
D5
COL7
H2
COL6
H3
COL2
VDD
H4
VSSC
COL3
A5/SA3
PA6
H5
H6
COL4
L2
PA7
H7
COL5
L3
PB0/UARTRX1
VSSC
PB4/UARTDCD3
VDDC
VDD
H8
VSSC
VSS
L4
H9
L5
H10
H11
H12
H13
H14
H15
H16
J1
A10/SA8
D11
L6
L7
A11/SA9
VDD
L8
VSS
L9
VSSC
VSS
D10
L10
L11
L12
A9/SA7
D9
D0
VSS
TBUZ
L13
L14
L15
L16
M1
D1
J2
J3
J4
J5
SSPFRM/nSSPFRM
SSPCLK
D2
A2/SA0
VDDC
D4
PGMCLK
PB1/UARTTX3
18
Rev. 01 — 16 July 2007
Preliminary data sheet
32-Bit System-on-Chip
NXP Semiconductors
LH7A400
Table 7. 256-Ball LFBGA Package
Table 7. 256-Ball LFBGA Package
Numerical Pin List
Numerical Pin List
LFBGA PIN
SIGNAL
LFBGA PIN
SIGNAL
M2
M3
PB2/UARTRX3
PB3/UARTCTS3
PB7/SMBCLK
PC3/LCDREV
PG0/nPCOE
PH2/nPCSLOTE1
LCDVD0
P14
P15
P16
R1
nCS0
nTEST0
M4
nCS1
M5
PC2/LCDVDDEN
PC6/LCDHRLP
PG3/nPCIOW
PG6/nPCCE2
VSSC
M6
R2
M7
R3
M8
R4
M9
PD0/LCDVD8
VDDA
R5
M10
M11
M12
M13
M14
M15
M16
N1
R6
PH4/nPCWAIT1
PH5/CFA10/PCMCIAA24/nPCWAIT2
LCDVD2
VSS
R7
CLKEN
R8
XTAL32OUT
VSS
R9
LCDLP
R10
R11
R12
R13
R14
R15
R16
T1
PE3/LCDVD7
PD5/LCDVD13
PD6/LCDVD14
VSSA
A0/nWE1
A1/nWE2
PB5/UARTDSR3
PB6/SWID/SMBD
VSSC
N2
XTALIN
N3
XTALOUT
N4
PC5/LCDCLS
PC7/LCDSPL
VDD
USBDN
N5
PG1/nPCWE
PG4/nPCREG
PG7/PCDIR
N6
T2
N7
VSSC
T3
N8
VDD
T4
PH1/CFA8/PCRESET2
PH3/CFA9/PCMCIAA25/nPCSLOTE2
PH7/nPCSTATRE
LCDFP
N9
LCDDCLK
VSSC
T5
N10
N11
N12
N13
N14
N15
N16
P1
T6
VSSA
T7
VDD
T8
LCDVD3
VDD
T9
PE0/LCDVD4
PE2/LCDVD6
PD3/LCDVD11
PD4/LCDVD12
PD7/LCDVD15
WIDTH0
XTAL32IN
nCS2
T10
T11
T12
T13
T14
T15
T16
nCS3/nMMSPICS
PC0/UARTTX1
PC1/LCDPS
PC4/LCDSPS
PG2/nPCIOR
PG5/nPCCE1
PH0/PCRESET1
P2
P3
WIDTH1
P4
USBDP
P5
P6
P7
P8
PH6/AC97RESET
LCDVD1
P9
LCDENAB/LCDM
PD2/LCDVD10
VDD
P10
P11
P12
P13
VDDA
nTEST1
Preliminary data sheet
Rev. 01 — 16 July 2007
19
LH7A400
NXP Semiconductors
32-Bit System-on-Chip
TOUCH
SCREEN
CONTR.
ROM
FLASH
1
4
7
2
5
8
0
3
6
9
#
SMART
CARD
*
SSP
UART
SRAM
STN/TFT/
AD-TFT
GPIO
SCI
MULTIMEDIA
CARD
MMC
SDRAM
LH7A400
DMA
COMPACT
FLASH
CODEC
AC97
PC
CARD
PCMCIA
UART
USB
IR
BMI
DC to DC
VOLTAGE
GENERATION
CIRCUITRY
BATTERY
LH7A400-3
Figure 4. Application Diagram
The 32.768 kHz clock provides the source for the
Real Time Clock tree and power-down logic.This clock
is used for the power state control in the design and is
the only clock in the LH7A400 that runs permanently.
The 32.768 kHz clock is divided down to 1 Hz using a
ripple divider to save power. This generated 1 Hz clock
is used in the Real Time Clock counter.
SYSTEM DESCRIPTIONS
ARM922T Processor
The LH7A400 microcontroller features the
ARM922T cached core with an Advanced High Perfor-
mance Bus (AHB) interface. The processor is a mem-
ber of the ARM9T family of processors. For more
information, see the ARM document, ‘ARM922T Tech-
nical Reference Manual’, available on ARM’s website
at www.arm.com.
The 14.7456 MHz source is used to generate the
main system clocks for the LH7A400. It is the source
for PLL1 and PLL2, it acts as the primary clock to the
peripherals and is the source clock to the Programma-
ble clock (PGM) divider.
Clock and State Controller
The clocking scheme in the LH7A400 is based
around two primary oscillator inputs. These are the
14.7456 MHz input crystal and the 32.768 kHz real time
clock oscillator. See Figure 5. The 14.7456 MHz oscil-
lator is used to generate the main system clock
domains for the LH7A400, where as the 32.768 kHz is
used for controlling the power down operations and
real time clock peripheral. The clock and state control-
ler provides the clock gating and frequency division
necessary, and then supplies the clocks to the proces-
sor and to the rest of the system. The amount of clock
gating that actually takes place is dependent on the
current power saving mode selected.
PLL1 provides the main clock tree for the chip, it
generates the following clocks: FCLK, HCLK and
PCLK. FCLK is the clock that drives the ARM922T
core. HCLK is the main bus (AHB) clock, as such it
clocks all memory interfaces, bus arbitrators and the
AHB peripherals. HCLK is generated by dividing FCLK
by 1, 2, 3, or 4. HCLK can be gated by the system to
enable low power operation. PCLK is the peripheral
bus (APB) clock. It is generated by dividing HCLK by
either 2, 4, or 8.
PLL2 is used to generate a fixed frequency of
48 MHz for the USB peripheral.
20
Rev. 01 — 16 July 2007
Preliminary data sheet
32-Bit System-on-Chip
NXP Semiconductors
LH7A400
14.7456 MHz
MAIN OSC.
FCLK
32.768 kHz
RTC OSC.
STATE CONTROLLER
HCLK
(TO PROCESSOR CORE)
DIVIDE REGISTER
HCLK
/2, /4, /8
PCLKs
LH7A400-4
Figure 5. Clock and State Controller Block Diagram
Power Modes
Data Paths
The LH7A400 has three operational states: Run,
Halt, and Standby. In Run mode, all clocks are hard-
ware-enabled and the processor is clocked. Halt mode
stops the processor clock while waiting for an event
such as a key press, but the device continues to func-
tion. Finally, Standby equates to the computer being
switched ‘off’, i.e. no display (LCD disabled) and the
main oscillator is shut down. The 32.768 kHz oscillator
operates in all three modes.
The data paths in the LH7A400 are:
• The AMBA AHB bus
• The AMBA APB bus
• The External Bus Interface
• The LCD AHB bus
• The DMA busses.
AMBA AHB BUS
The Advanced Microprocessor Bus Architecture
Advanced High-performance Bus (AMBA AHB) bus is a
high speed 32-bit-wide data bus. The AMBA AHB is for
high-performance, high clock frequency system modules.
Reset Modes
There are three external signals that can generate
resets to the LH7A400; these are nPOR (power on
reset), nPWRFL (power failure) and nURESET (user
reset). If any of these are active, a system reset is gen-
erated internally. A nPOR reset performs a full system
reset. The nPWRFL and nURESET resets will perform
a full system reset except for the SDRAM refresh con-
trol, SDRAM Global Configuration, SDRAM Device
Configuration and the RTC peripheral registers. The
SDRAM controller will issue a self-refresh command to
external SDRAM before the system enters this reset
(the nPWRFL and nURESET resets only, not so for the
nPOR reset). This allows the system to maintain its
Real Time Clock and SDRAM contents. On coming out
of reset, the chip enters Standby mode. Once in Run
mode the PWRSR register can be interrogated to deter-
mine the nature of the reset, and the trigger source,
after which software can then take appropriate actions.
Peripherals that have high bandwidth requirements
are connected to the LH7A400 core processor using
the AHB bus. These include the external and internal
memory interfaces, the LCD registers, palette RAM
and the bridge to the Advanced Peripheral Bus (APB)
interface. The APB Bridge transparently converts the
AHB access into the slower speed APB accesses. All
of the control registers for the APB peripherals are pro-
grammed using the AHB - APB bridge interface. The
main AHB data and address lines are configured using
a multiplexed bus. This removes the need for tri-state
buffers and bus holders, and simplifies bus arbitration.
Preliminary data sheet
Rev. 01 — 16 July 2007
21
LH7A400
NXP Semiconductors
32-Bit System-on-Chip
AMBA APB BUS
The LH7A400 can boot from either synchronous or
asynchronous ROM/Flash. The selection is determined
by the value of the MEDCHG pin at Power On Reset as
shown in Table 8. When booting from synchronous
memory, then synchronous bank 4 (nSCS3) is mapped
into memory location zero. When booting from asyn-
chronous memory, asynchronous memory bank 0
(nSCS0) is mapped into memory location zero.
The AMBA APB bus is a lower-speed 32-bit-wide
peripheral data bus. The speed of this bus is selectable
to be a divide-by-2, divide-by-4 or divide-by-8 of the
speed of the AHB bus.
EXTERNAL BUS INTERFACE
The External Bus Interface (EBI) provides a 32-bit
wide, high speed gateway to external memory devices.
The memory devices supported include:
Figure 6 shows the memory map of the LH7A400
system for the two boot modes.
• Asynchronous RAM/ROM/Flash
• Synchronous DRAM/Flash
• PCMCIA interfaces
Once the LH7A400 has booted, the boot code can
configure the ARM922T MMU to remap the low mem-
ory space to a location in RAM. This allows the user to
set the interrupt vector table.
• CompactFlash interfaces.
The EBI can be controlled by either the Asynchro-
nous memory controller or Synchronous memory con-
troller. There is an arbiter on the EBI input, with priority
given to the Synchronous Memory Controller interface.
Table 8. Boot Modes
LATCHED LATCHED
LATCHED
BOOT MODE
BOOT-
WIDTH1
BOOT-
WIDTH0
MEDCHG
8-bit ROM
0
0
1
1
0
1
0
1
0
0
0
0
LCD AHB BUS
16-bit ROM
32-bit ROM
32-bit ROM
The LCD controller has its own local memory bus
that connects it to the system’s embedded memory and
external SDRAM. The function of this local data bus is
to allow the LCD controller to perform its video refresh
function without congesting the AHB bus. This leads to
better system performance and lower power consump-
tion. There is an arbiter on both the embedded memory
and the synchronous memory controller. In both cases
the LCD bus is given priority.
16-bit SFlash
(Initializes Mode Register)
0
0
1
1
0
1
0
1
1
1
1
1
16-bit SROM
(Initializes Mode Register)
32-bit SFlash
(Initializes Mode Register)
32-bit SROM
(Initializes Mode Register)
DMA BUSES
The LH7A400 has a DMA system that connects the
higher speed/higher data volume APB peripherals
(MMC, USB and AC97) to the AHB bus. This enables
the efficient transfer of data between these peripherals
and external memory without the intervention of the
ARM922T core. The DMA engine does not support
memory to memory transfers.
Interrupt Controller
The LH7A400 interrupt controller is designed to con-
trol the interrupts from 28 different sources. Four inter-
rupt sources are mapped to the FIQ input of the
ARM922T and 24 are mapped to the IRQ input. FIQs
have a higher priority than the IRQs. If two interrupts
with the same priority become active at the same time,
the priority must be resolved in software.
Memory Map
When an interrupt becomes active, the interrupt con-
troller generates an FIQ or IRQ if the corresponding
mask bit is set. No latching of interrupts takes place in
the controller. After a Power On Reset all mask register
bits are cleared, therefore masking all interrupts.
Hence, enabling of the mask register must be done by
software after a power-on-reset.
The LH7A400 system has a 32-bit-wide address bus.
This allows it to address up to 4GB of memory. This
memory space is subdivided into a number of memory
banks; see Figure 6. Four of these banks (each of
256MB) are allocated to the Synchronous memory con-
troller. Eight of the banks (again, each 256MB) are allo-
cated to the Asynchronous memory controller. Two of
these eight banks are designed for PCMCIA systems.
Part of the remaining memory space is allocated to the
embedded SRAM, and to the control registers of the
AHB and APB. The rest is unused.
22
Rev. 01 — 16 July 2007
Preliminary data sheet
32-Bit System-on-Chip
NXP Semiconductors
LH7A400
256MB
256MB
F000.0000
E000.0000
ASYNCHRONOUS MEMORY (nCS0)
SYNCHRONOUS MEMORY (nSCS3)
SYNCHRONOUS MEMORY (nSCS2)
SYNCHRONOUS MEMORY (nSCS1)
SYNCHRONOUS MEMORY (nSCS0)
RESERVED
SYNCHRONOUS MEMORY (nSCS2)
SYNCHRONOUS MEMORY (nSCS1)
SYNCHRONOUS MEMORY (nSCS0)
256MB
256MB
D000.0000
C000.0000
B001.4000
B000.0000
RESERVED
80KB
EMBEDDED SRAM
EMBEDDED SRAM
RESERVED
RESERVED
8000.3800
8000.2000
AHB INTERNAL REGISTERS
APB INTERNAL REGISTERS
ASYNCHRONOUS MEMORY (CS7)
ASYNCHRONOUS MEMORY (CS6)
PCMCIA/CompactFlash (nPCSLOTE2)
PCMCIA/CompactFlash (nPCSLOTE1)
ASYNCHRONOUS MEMORY (nCS3)
ASYNCHRONOUS MEMORY (nCS2)
ASYNCHRONOUS MEMORY (nCS1)
SYNCHRONOUS ROM (nSCS3)
AHB INTERNAL REGISTERS
APB INTERNAL REGISTERS
ASYNCHRONOUS MEMORY (CS7)
ASYNCHRONOUS MEMORY (CS6)
PCMCIA/CompactFlash (nPCSLOTE2)
PCMCIA/CompactFlash (nPCSLOTE1)
ASYNCHRONOUS MEMORY (nCS3)
ASYNCHRONOUS MEMORY (nCS2)
ASYNCHRONOUS MEMORY (nCS1)
ASYNCHRONOUS ROM (nCS0)
8000.0000
7000.0000
256MB
256MB
256MB
6000.0000
5000.0000
256MB
256MB
256MB
256MB
256MB
4000.0000
3000.0000
2000.0000
1000.0000
0000.0000
SYNCHRONOUS MEMORY BOOT
ASYNCHRONOUS MEMORY BOOT
LH7A400-6
Figure 6. Memory Mapping for Each Boot Mode
4 kB page boundary in SDRAM, allowing software to
set the MMU (in the LCD controller) page tables such
that the two memory areas appear contiguous. Byte,
Half-Word and Word accesses are permissible.
External Bus Interface
The external bus interface allows the ARM922T,
LCD controller and DMA engine access to an external
memory system. The LCD controller has access to an
internal frame buffer in embedded SRAM and an exten-
sion buffer in Synchronous Memory for large displays.
The processor and DMA engine share the main system
bus, providing access to all external memory devices
and the embedded SRAM frame buffer.
Asynchronous Memory Controller
The Asynchronous memory controller is incorpo-
rated as part of the memory controller to provide an
interface between the AMBA AHB system bus and
external (off-chip) memory devices.
An arbitration unit ensures that control over the
External Bus Interface (EBI) is only granted when an
existing access has been completed. See Figure 7.
The Asynchronous Memory Controller provides sup-
port for up to eight independently configurable memory
banks simultaneously. Each memory bank is capable
of supporting:
Embedded SRAM
• SRAM
The amount of Embedded SRAM contained in the
LH7A400 is 80 kB. This Embedded memory is
designed to be used for storing code, data, or LCD
frame data and to be contiguous with external SDRAM.
The 80 kB is large enough to store a QVGA panel (320
× 240) at 8 bits per pixel, equivalent to 70 kB of informa-
tion.
• ROM
• Flash EPROM
• Burst ROM memory.
Each memory bank may use devices using either 8-,
16-, or 32-bit external memory data paths. The memory
controller supports only little-endian operation.
Containing the frame buffer on chip reduces the
overall power consumed in any application that uses
the LH7A400. Normally, the system has to perform
external accesses to acquire this data. The LCD con-
troller is designed to automatically use an overflow
frame buffer in SDRAM if a larger screen size is
required. This overflow buffer can be located on any
The memory banks can be configured to support:
• Non-burst read and write accesses only to high-
speed CMOS static RAM.
• Non-burst write accesses, nonburst read accesses
and asynchronous page mode read accesses to
fast-boot block flash memory.
Preliminary data sheet
Rev. 01 — 16 July 2007
23
LH7A400
NXP Semiconductors
32-Bit System-on-Chip
EXTERNAL TO
THE LH7A400
INTERNAL TO
THE LH7A400
ARM922T
ASYNCHRONOUS
STATIC
MEMORY
CONTROLLER
(SMC)
SDRAM
SDRAM
SRAM
ROM
EXTERNAL
BUS
INTERFACE
(EBI)
DATA
PCMCIA/CF
SUPPORT
ADDRESS
and
CONTROL
SYNCHRONOUS
DYNAMIC
MEMORY
CONTROLLER
(SDMC)
80KB
EMBEDDED
SRAM
LCD
AHB
LCD MEMORY
MANAGEMENT
UNIT (MMU)
COLOR LCD
CONTROLLER
(CLCDC)
DMA
CONTROLLER
AD-TFT
LCD TIMING
CONTROLLER
ADVANCED
HIGH-PERFORMANCE
BUS (AHB)
LH7A400-8
Figure 7. External Bus Interface Block Diagram
24
Rev. 01 — 16 July 2007
Preliminary data sheet
32-Bit System-on-Chip
NXP Semiconductors
LH7A400
The Asynchronous Memory Controller has six main
functions:
MMC bus lines can be divided into three groups:
• Power supply: VDD and VSS
• Data Transfer: MMCCMD, MMCDATA
• Clock: MMCLK.
• Memory bank select
• Access sequencing
• Wait states generation
• Byte lane write control
• External bus interface
• CompactFlash or PCMCIA interfacing.
MULTIMEDIACARD ADAPTER
The MultiMediaCard Adapter implements MultiMedia-
Card specific functions, serves as the bus master for the
MultiMediacard Bus and implements the standard inter-
face to the MultiMediaCard Cards (card initialization,
CRC generation and validation, command/response
transactions, etc.).
Synchronous Memory Controller
The Synchronous memory controller provides a high
speed memory interface to a wide variety of Synchro-
nous memory devices, including SDRAM, Synchro-
nous Flash and Synchronous ROMs.
Smart Card Interface (SCI)
The SCI (ISO7816) interfaces to an external Smart
Card reader. The SCI can autonomously control data
transfer to and from the smart card. Transmit and
receive data FIFOs are provided to reduce the required
interaction between the CPU core and the peripheral.
The key features of the controller are:
• LCD DMA port for high bandwidth
• Up to four Synchronous Memory banks that can be
independently set up
• Special configuration bits for Synchronous ROM
operation
SCI FEATURES
• Supports asynchronous T0 and T1 transmission
protocols
• Ability to program Synchronous Flash devices using
write and erase commands
• Supports clock rate conversion factor F = 372, with
bit rate adjustment factors D = 1, 2, or 4 supported
• On booting from Synchronous ROM, (and optionally
with Synchronous Flash), a configuration sequence is
performed before releasing the processor from reset
• Eight-character-deep buffered Tx and Rx paths
• Direct interrupts for Tx and Rx FIFO level monitoring
• Interrupt status register
• Data is transferred between the controller and the
SDRAM in quad-word bursts. Longer transfers within
the same page are concatenated, forming a seam-
less burst
• Hardware-initiated card deactivation sequence on
detection of card removal
• Programmable for 16- or 32-bit data bus size
• Software-initiated card deactivation sequence on
transaction complete
• Two reset domains are provided to enable SDRAM
contents to be preserved over a ‘soft’ reset
• Limited support for synchronous Smart Cards via
registered input/output.
• Power saving Synchronous Memory SCKE and
external clock modes provided.
PROGRAMMABLE PARAMETERS
• Smart Card clock frequency
MultiMediaCard (MMC)
• Communication baud rate
• Protocol convention
The MMC adapter combines all of the requirements
and functions of an MMC host. The adapter supports
the full MMC bus protocol, defined by the MMC Defini-
tion Group’s specification v.2.11. The controller can
also implement the SPI interface to the cards.
• Card activation/deactivation time
• Check for maximum time for first character of
Answer to Reset - ATR reception
• Check for maximum duration of ATR character
stream
INTERFACE DESCRIPTION AND MMC OVERVIEW
The MMC controller uses the three-wire serial data
bus (clock, command, and data) to transfer data to and
from the MMC card, and to configure and acquire status
information from the card’s registers.
• Check for maximum time of receipt of first character
of data stream
• Check for maximum time allowed between characters
• Character guard time
• Block guard time
• Transmit/receive character retry.
Preliminary data sheet
Rev. 01 — 16 July 2007
25
LH7A400
NXP Semiconductors
32-Bit System-on-Chip
Direct Memory Access Controller (DMA)
Color LCD Controller
The DMA Controller interfaces streams from the fol-
lowing three peripherals to the system memory:
The LH7A400’s LCD Controller is programmable to
support up to 1,024 × 768, 16-bit color LCD panels. It
interfaces directly to STN, color STN, TFT, AD-TFT,
and HR-TFT panels. Unlike other LCD controllers, the
LH7A400’s LCD Controller incorporates the timing con-
version logic from TFT to HR- and AD-TFT, allowing a
direct interface to these panels and minimizing external
chip count.
• USB (1 Tx and 1 Rx DMA Channel)
• MMC (1 Tx and 1 Rx DMA Channel)
• AC97 (3 Tx and 3 Rx DMA Channels).
Each has its own bi-directional peripheral DMA bus
capable of transferring data in both directions simulta-
neously. All memory transfers take place via the main
system AHB bus.
The Color LCD Controller features support for:
• Up to 1,024 × 768 Resolution
• 16-bit Video Bus
DMA Specific features are:
• Independent DMA channels for Tx and Rx
• STN, Color STN, AD-TFT, HR-TFT, TFT panels
• Single and Dual Scan STN panels
• Up to 15 Gray Shades
• Two Buffer Descriptors per channel to avoid poten-
tial data under/over-flows due to software introduced
latency
• No Buffer wrapping
• Up to 64,000 Colors
• Buffer size may be equal to, greater than, or less
than the packet size. Transfers can automatically
switch between buffers.
AC97 Advanced Audio Codec Interface
The AC97 Advanced Audio Codec controller
includes a 5-pin serial interface to an external audio
codec. The AC97 LINK is a bi-directional, fixed rate,
serial Pulse Code Modulation (PCM) digital stream,
dividing each audio frame into 12 outgoing and 12
incoming data streams (slots), each with 20-bit sample
resolution.
• Maskable interrupt generation
• Internal arbitration between DMA Channels and
external bus arbiter.
• For DMA Data transfer sizes, byte, word and quad-
word data transfers are supported.
A set of control and status registers are available to
the system processor for setting up DMA operations
and monitoring their status. A system interrupt is gen-
erated when any or all of the DMA channels wish to
inform the processor that a new buffer needs to be allo-
cated. The DMA controller services three peripherals
using ten DMA channels, each with its own peripheral
DMA bus capable of transferring data in both directions
simultaneously.
The AC97 controller contains logic that controls the
AC97 link to the Audio Codec and an interface to the
AMBA APB.
Its main features include:
• Serial-to-parallel conversion for data received from
the external codec
• Parallel-to-serial conversion for data transmitted to
the external codec
The MMC and USB peripherals each use two DMA
channels, one for transmit and one for receive. The
AC97 peripheral uses six DMA channels (three trans-
mit and three receive) to allow different sample fre-
quency data queues to be handled with low software
overheads. The DMA Controller does not support
memory to memory transfers.
• Reception/Transmission of control and status infor-
mation via the AMBA APB interface
• Supports up to 4 different codec sampling rates at a
time with its 4 transmit and 4 receive channels. The
transmit and receive paths are buffered with internal
FIFO memories, allowing data to be stored indepen-
dently in both transmit and receive modes. The out-
going data for the FIFOs can be written via either the
APB interface or with DMA channels 1 - 3.
USB Device
The features of the USB are:
• Fully compliant to USB 1.1 specification
• Provides a high level interface that shields the firm-
ware from USB protocol details
• Compatible with both OpenHCI and Intel’s UHCI
standards
• Supports full-speed (12 Mbps) functions
• Supports Suspend and Resume signalling.
26
Rev. 01 — 16 July 2007
Preliminary data sheet
32-Bit System-on-Chip
NXP Semiconductors
LH7A400
The transmit and receive paths are buffered with inter-
nal FIFO memories allowing up to 16 bytes to be stored
independently in both transmit and receive modes.
Audio Codec Interface (ACI)
The ACI provides:
• A digital serial interface to an off-chip 8-bit CODEC
The UART can generate:
• All the necessary clocks and timing pulses to per-
form serialization or de-serialization of the data
stream to or from the CODEC device.
• Four individually maskable interrupts from the
receive, transmit and modem status logic blocks
• A single combined interrupt so that the output is
asserted if any of the individual interrupts are
asserted and unmasked.
The interface supports full duplex operation and the
transmit and receive paths are buffered with internal
FIFO memories allowing up to 16 bytes to be stored
independently in both transmit and receive modes.
If a framing, parity, or break error occurs during
reception, the appropriate error bit is set, and is stored
in the FIFO. If an overrun condition occurs, the overrun
register bit is set immediately and the FIFO data is pre-
vented from being overwritten. UART1 also supports
IrDA 1.0 (15.2 kbit/s).
The ACI includes a programmable frequency divider
that generates a common transmit and receive bit clock
output from the on-chip ACI clock input (ACICLK).
Transmit data values are output synchronous with the
rising edge of the bit clock output. Receive data values
are sampled on the falling edge of the bit clock output.
The start of a data frame is indicated by a synchroniza-
tion output signal that is synchronous with the bit clock.
The modem status input signals Clear to Send
(CTS), Data Carrier Detect (DCD) and Data Set Ready
(DSR) are supported on UART2 and UART3.
Synchronous Serial Port (SSP)
Timers
The LH7A400 SSP is a master-only interface for
synchronous serial communication with device periph-
eral devices that has either Motorola SPI, National
Semiconductor MICROWIRE or Texas Instruments
Synchronous Serial Interfaces.
Two identical timers are integrated in the LH7A400.
Each of these timers has an associated 16-bit read/write
data register and a control register. Each timer is loaded
with the value written to the data register immediately,
this value will then be decremented on the next active
clock edge to arrive after the write. When the timer
underflows, it will immediately assert its appropriate
interrupt. The timers can be read at any time. The clock
source and mode is selectable by writing to various bits
in the system control register. Clock sources are
508 kHz and 2 kHz.
The LH7A400 SSP performs serial-to-parallel con-
version on data received from a peripheral device. The
transmit and receive paths are buffered with internal
FIFO memories allowing up to eight 16-bit values to be
stored independently in both transmit and receive
modes. Serial data is transmitted on SSPTXD and
received on SSPRXD.
Timer 3 (TC3) has the same basic operation, but is
clocked from a single 7.3728 MHz source. It has the
same register arrangement as Timer 1 and Timer 2, pro-
viding a load, value, control and clear register. Once the
timer has been enabled and is written to, unlike the
Timer 1 and Timer 2, will decrement the timer on the
next rising edge of the 7.3728 MHz clock after the data
register has been updated. All the timers can operate in
two modes, free running mode or pre-scale mode.
The LH7A400 SSP includes a programmable bit rate
clock divider and prescaler to generate the serial output
clock SCLK from the input clock SSPCLK. Bit rates are
supported to 2 MHz and beyond, subject to choice of
frequency for SSPCLK; the maximum bit rate will usu-
ally be determined by peripheral devices.
UART/IrDA
The LH7A400 contains three UARTs, UART1,
UART2, and UART3.
FREE-RUNNING MODE
In free-running mode, the timer will wrap around to
0xFFFF when it underflows and continue counting down.
The UART performs:
• Serial-to-Parallel conversion on data received from
the peripheral device
PRE-SCALE MODE
In pre-scale (periodic) mode, the value written to
each timer is automatically re-loaded when the timer
underflows. This mode can be used to produce a pro-
grammable frequency to drive an external buzzer or
generate a periodic interrupt.
• Parallel-to-Serial conversion on data transmitted to
the peripheral device.
Preliminary data sheet
Rev. 01 — 16 July 2007
27
LH7A400
NXP Semiconductors
32-Bit System-on-Chip
Real Time Clock (RTC)
DC-to-DC Converter
The RTC can be used to provide a basic alarm func-
tion or long time-base counter. This is achieved by gen-
erating an interrupt signal after counting for a
programmed number of cycles of a real-time clock
input. Counting in one second intervals is achieved by
use of a 1 Hz clock input to the RTC.
The features of the DC-DC Converter interface are:
• Dual drive PWM outputs, with independent closed
loop feedback
• Software programmable configuration of one of 8
output frequencies (each being a fixed divide of the
input clock).
• Software programmable configuration of duty cycle
from 0 to 15/16, in intervals of 1/16.
Battery Monitor Interface (BMI)
The LH7A400 BMI is a serial communication inter-
face specified for two types of Battery Monitors/Gas
Gauges. The first type employs a single wire interface.
The second interface employs a two-wire multi-master
bus, the Smart Battery System Specification. If both
interfaces are enabled at the same time, the Single
Wire Interface will have priority. A brief overview of
these two interface types are given here.
• Output polarity (for positive or negative voltage gen-
eration) is hardware-configured during power-on
reset via the polarity select inputs
• Each PWM output can be dynamically switched to
one of a pair of preprogrammed frequency/duty
cycle combinations via external pins.
Watchdog Timer (WDT)
SINGLE WIRE INTERFACE
The Watchdog Timer provides hardware protection
against malfunctions. It is a programmable timer that is
reset by software at regular intervals. Failure to reset
the timer will cause a FIQ interrupt. Failure to service
the FIQ interrupt will then generate a System Reset.
The WDT features are:
The Single Wire Interface performs:
• Serial-to-parallel conversion on data received from
the peripheral device
• Parallel-to-serial conversion on data transmitted to
the peripheral device
• Driven by the system clock
• Data packet coding/decoding on data transfers
(incorporating Start/Data/Stop data packets)
16
31
• 16 programmable time-out periods: 2 through 2
clock cycles
The Single Wire interface uses a command-based
protocol, in which the host initiates a data transfer by
sending a WriteData/Command word to the Battery
Monitor. This word will always contain the Command
section, which tells the Single Wire Interface device the
location for the current transaction. The most signifi-
cant bit of the Command determines if the transaction
is Read or Write. In the case of a Write transaction,
then the word will also contain a WriteData section with
the data to be written to the peripheral.
• Generates a system reset (resets LH7A400) or a
FIQ Interrupt whenever a time-out period is reached
• Software enable, lockout, and counter-reset mecha-
nisms add security against inadvertent writes
• Protection mechanism guards against
interrupt-service-failure:
– The first WDT time-out triggers FIQ and asserts
nWDFIQ status flag
– If FIQ service routine fails to clear nWDFIQ, then
the next WDT time-out triggers a System Reset.
SMART BATTERY INTERFACE
The SMBus Interface performs:
General Purpose I/O (GPIO)
• Serial-to-Parallel conversion on data received from
the peripheral device
The LH7A400 GPIO has eight ports, each with a
data register and a data direction register. It also has
added registers including Keyboard Scan, PINMUX,
GPIO Interrupt Enable, INTYPE1/2, GPIOFEOI, and
PGHCON.
• Parallel-to-Serial conversion of data transmitted to
the peripheral device.
The Smart Battery Interface uses a two-wire multi-
master bus (the SMBus), meaning that more than one
device capable of controlling the bus can be connected
to it. A master device initiates a bus transfer and provides
the clock signals. A slave device can receive data pro-
vided by the master or it can provide data to the master.
Since more than one device may attempt to take control
of the bus as a master, SMBus provides an arbitration
mechanism, by relying on the wired-AND connection of
all SMBus interfaces to the SMBus.
The data direction register determines whether a
port is configured as an input or an output while the
data register is used to read the value of the GPIO pins.
The GPIO Interrupt Enable, INTYPE1/2, and GPI-
OFEOI registers are used to control edge-triggered
Interrupts on Port F. The PINMUX register controls
what signals are output of Port D and Port E when they
are set as outputs, while the PGHCON controls the
operations of Port G and H.
28
Rev. 01 — 16 July 2007
Preliminary data sheet
32-Bit System-on-Chip
NXP Semiconductors
LH7A400
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
PARAMETER
MINIMUM MAXIMUM
DC Core Supply Voltage (VDDC)
DC I/O Supply Voltage (VDD)
−0.3 V
−0.3 V
−0.3 V
−0.5 V
2.4 V
4.6 V
2.4 V
5.5 V
2 kV
DC Analog Supply Voltage (VDDA)
5 V Tolerant Digital Input Pin Voltage
ESD, Human Body Model (Analog pins AN0 - AN9 rated at 500 V)
ESD, Charged Device Model
1 kV
Storage Temperature
−55°C
125°C
NOTE: Except for Storage Temperature, these ratings are only for
transient conditions. Operation at or beyond absolute maxi-
mum rating conditions may affect reliability and cause per-
manent damage to the device.
Recommended Operating Conditions
PARAMETER
MINIMUM
TYPICAL
MAXIMUM
NOTES
DC Core Supply Voltage (VDDC)
DC Core Supply Voltage (VDDC)
DC I/O Supply Voltage (VDD)
1.71 V
2.0 V
1.8 V
2.1 V
3.3 V
3.3 V
1.8 V
1.89 V
2.2 V
1, 4
1, 5
2, 6
2, 7
3.0 V
3.6 V
DC I/O Supply Voltage (VDD)
3.14 V
1.71 V
10 MHz
10 MHz
3.6 V
DC Analog Supply Voltage for PLLs (VDDA)
Clock Frequency (0°C to +70°C)
Clock Frequency (−40°C to +85°C)
Bus Clock Frequency (−40°C to +85°C)
Clock Frequency (0°C to +70°C)
Clock Frequency (−40°C to +85°C)
Bus Clock Frequency (−40°C to +85°C)
External Clock Input (XTALIN)
External Clock Input (XTALIN) Voltage
Operating Temperature
1.89 V
200 MHz
195 MHz
100 MHz
250 MHz
245 MHz
125 MHz
20 MHz
1.89 V
3, 4, 6
3, 4, 6
3, 4, 6
3, 5, 7
3, 5, 7
3, 5, 7
8
10 MHz
10 MHz
14 MHz
1.71 V
14.7456 MHz
1.8 V
−40°C
25°C
+85°C
NOTES:
1. Core Voltage should never exceed I/O Voltage after initial power up. See “Power Supply Sequencing” on page 33
2. USB is not functional below 3.0 V
3. Using 14.7456 MHz Main Oscillator Crystal and 32.768 kHz RTC Oscillator Crystal
4. VDDC = 1.71 V to 1.89 V (LH7A400N0G000xx)
5. VDDC = 2.1 V ± 5 % (LH7A400N0G076xx only)
6. VDD = 3.0 V to 3.6 V (LH7A400N0G000xx)
7. VDD = 3.14V to 3.60 V (LH7A400N0G076xx only)
8. IMPORTANT: Most peripherals will NOT function with crystals other than 14.7456 MHz.
Preliminary data sheet
Rev. 01 — 16 July 2007
29
LH7A400
NXP Semiconductors
32-Bit System-on-Chip
245
240
235
230
225
220
215
1.89 V (+5%)
1.80 V
210
205
200
195
1.71 V (-5%)
85
25
35
45
55
65
75
TEMP (°C)
LH7A400-206
Figure 8. Temperature/Voltage/Speed Chart
(For LH7A400N0G000xx)
Table 9. Clock Frequency vs. Voltages (VDDC) vs. Temperature
PARAMETER
1.71 V
211 MHz 225 MHz 240 MHz
4.74 ns 4.44 ns 4.17 ns
200 MHz 212 MHz 227 MHz
5.00 ns 4.72 ns 4.41 ns
195 MHz 208 MHz 222 MHz
5.13 ns 4.81 ns 4.50 ns
1.8 V
1.89 V
Clock Frequency (FCLK)
Clock Period (FCLK)
25°C
70°C
Clock Frequency (FCLK)
Clock Period (FCLK)
Clock Frequency (FCLK)
Clock Period (FCLK)
85°C
NOTES:
1. Table 9 is representative of a typical wafer process. Guaranteed
values are in the Recommended
Operating Conditions table.
2. LH7A400N0G000xx
30
Rev. 01 — 16 July 2007
Preliminary data sheet
32-Bit System-on-Chip
NXP Semiconductors
LH7A400
DC/AC SPECIFICATIONS
Unless otherwise noted, all data provided in these
specifications are based on −40°C to +85°C, VDDC =
1.71 V to 1.89 V, VDD = 3.0 V to 3.6 V, VDDA = 1.71 V
to 1.89 V.
DC Specifications
SYMBOL
PARAMETER
MIN. TYP. MAX. UNIT
CONDITIONS
NOTES
CMOS and Schmitt Trigger Input HIGH Volt-
age
VIH
2.0
5.5
0.8
V
V
CMOS and Schmitt Trigger Input LOW Volt-
age
VIL
−0.2
VHST
Schmitt Trigger Hysteresis
Output Drive 2
0.25
2.6
V
V
VIL to VIH
IOH = −4 mA
IOH = −8 mA
IOH = −12 mA
IOL = 4 mA
VOH
VOL
Output Drive 3
2.6
V
Output Drive 4 and 5
Output Drive 2
2.6
V
1
1
0.4
0.4
0.4
0.4
10
V
Output Drive 3
V
IOL = 8 mA
Output Drive 4
V
IOL = 12 mA
IOL = 20 mA
VIN = VDD or GND
Output Drive 5
V
Input Leakage Current
−10
−200
−10
µA
IIN
Input Leakage Current
(with pull-up resistors installed)
−20
µA
VIN = VDD or GND
IOZ
Output Tri-state Leakage Current
10
50
µA
µA
mA
mA
µA
pF
VOUT = VDD or GND
ISTARTUP Startup Current
2
IACTIVE
IHALT
Active Current
Halt Current
125
25
180
41
ISTANDBY Standby Current
42
CIN
Input Capacitance
Output Capacitance
4
4
COUT
pF
NOTES:
1. Output Drive 5 can sink 20 mA of current, but sources 12 mA of current.
2. Current consumption until oscillators are stabilized.
AC Test Conditions
PARAMETER
RATING
UNIT
DC I/O Supply Voltage (VDD)
3.0 to 3.6
V
DC Core Supply Voltage (VDDC)
Input Pulse Levels
1.71 to 1.89
VSS to 3
2
V
V
Input Rise and Fall Times
ns
V
Input and Output Timing Reference Levels
VDD/2
Preliminary data sheet
Rev. 01 — 16 July 2007
31
LH7A400
NXP Semiconductors
32-Bit System-on-Chip
CURRENT CONSUMPTION BY OPERATING MODE
Table 10. Current Consumption by Mode
Current consumption can depend on a number of
parameters. To make this data more usable, the values
presented in Table 10 were derived under the condi-
tions presented here.
SYMBOL PARAMETER
Maximum Specified Value
The values specified in the MAXIMUM column were
determined using these operating characteristics:
TYP. MAX. TYP. UNITS
ACTIVE MODE
• All IP blocks either operating or enabled at maximum
frequency and size configuration
ICORE
IIO
Core Current
I/ O Current
110
15
135
45
250
mA
mA
• Core operating at maximum power configuration
• All voltages at maximum specified values
HALT MODE (ALL PERIPHERALS DISABLED)
• Maximum specified ambient temperature (tAMB).
ICORE
IIO
Core Current
I/ O Current
24
1
39
2
50
mA
mA
Typical
STANDBY MODE (TYPICAL CONDITIONS ONLY)
The values in the TYPICAL column were determined
using a ‘typical’ application under ‘typical’ environmental
conditions and the following operating characteristics:
ICORE
IIO
Core Current
I/ O Current
40
2
125
4
µA
µA
• LINUX operating system running from SDRAM
PERIPHERAL CURRENT CONSUMPTION
• UART and AC97 peripherals operating; all other
peripherals as needed by the OS
In addition to the modal current consumption, Table
11 shows the typical current consumption for each of
the on-board peripheral blocks. The values were deter-
mined with the CPU clock running at 200 MHz, typical
conditions, and no I/O loads. This current is supplied by
the 1.8 VDDC power supply.
• LCD enabled with 320 × 240 × 16-bit color, 60 Hz
refresh rate, data in SDRAM
• I/O loads at nominal
• Cache enabled
• FCLK = 200 MHz or 250 MHz; HCLK = 100 MHz or
125 MHz; PCLK = 50 MHz or 62.5 MHz
Table 11. Peripheral Current Consumption
• All voltages at typical values
PERIPHERAL
AC97
TYPICAL
UNITS
• Nominal case temperature (tAMB).
1.3
1.0
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
UART (Each)
RTC
0.005
0.1
Timers (Each)
LCD (+I/O)
MMC
5.4 (1.0)
0.6
SCI
23
PWM (each)
BMI-SWI
BMI-SBus
SDRAM (+I/O)
USB (+PLL)
ACI
< 0.1
1.0
1.0
1.5 (14.8)
5.6 (3.3)
0.8
32
Rev. 01 — 16 July 2007
Preliminary data sheet
32-Bit System-on-Chip
NXP Semiconductors
LH7A400
• ACBITCLK, AC97 clock
Power Supply Sequencing
NXP recommends that the 1.8 V power supply be
energized before the 3.3 V supply. If this is not possi-
ble, the 1.8 V supply may not lag the 3.3 V supply by
more than 100 µs. If longer delay time is needed, it is
recommended that the voltage difference between the
two power supplies be within 1.5 V during power supply
ramp up.
• SCLK, Synchronous Memory clock.
All signal transitions are measured at the 50 % point.
For outputs from the LH7A400, tOVXXX (e.g. tOVA)
represents the amount of time for the output to become
valid from a valid address bus, or rising edge of the
peripheral clock. Maximum requirements for tOVXXX
are shown in Table 12.
To avoid a potential latchup condition, voltage
should be applied to input pins only after the device is
powered-on as described above.
The signal tOHXXX (e.g. tOHA) represents the
amount of time the output will be held valid from the valid
address bus, or rising edge of the peripheral clock. Min-
imum requirements for tOHXXX are listed in Table 12.
AC Specifications
For Inputs, tISXXX (e.g. tISD) represents the amount
of time the input signal must be valid before a valid
address bus, or rising edge of the peripheral clock
(except SSP and ACI). Maximum requirements for
tISXXX are shown in Table 12.
All signals described in Table 12 relate to transi-
tions after a reference clock signal. The illustration in
Figure 9 represents all cases of these sets of mea-
surement parameters.
The reference clock signals in this design are:
• HCLK, internal System Bus clock (‘C’ in timing data)
• PCLK, Peripheral Bus clock
The signal tIHXXX (e.g. tIHD) represents the
amount of time the output must be held valid from the
valid address bus, or rising edge of the peripheral clock
(except SSP and ACI). Minimum requirements are
shown in Table 12.
• SSPCLK, Synchronous Serial Port clock
• UARTCLK, UART Interface clock
• LCDDCLK, LCD Data clock from the
LCD Controller
REFERENCE
CLOCK
tOHXXX
tOVXXX
OUTPUT
SIGNAL (O)
tISXXX tIHXXX
INPUT
SIGNAL (I)
7A400-28
Figure 9. LH7A400 Signal Timing
Preliminary data sheet
Rev. 01 — 16 July 2007
33
LH7A400
NXP Semiconductors
32-Bit System-on-Chip
Table 12. AC Signal Characteristics
SIGNAL
TYPE
LOAD
SYMBOL
MIN.
MAX.
DESCRIPTION
1
ASYNCHRONOUS MEMORY INTERFACE SIGNALS (+ [wait states × HCLK period])
Output 50 pF
Output 50 pF
tRC
4 × tHCLK – 7.0 ns 4 × tHCLK + 7.5 ns Read Cycle Time
4 × tHCLK – 7.0 ns 4 × tHCLK + 7.5 ns Write Cycle Time
A[27:0]
tWC
—
—
tWS
tHCLK ns
tHCLK – 6.0 ns
tHCLK – 7.0 ns
tHCLK – 5.0 ns
tHCLK – 7.0 ns
15 ns
tHCLK ns
Wait State Width
tDVWE
tDHWE
tDVBE
tDHBE
tDSCS
tDHCS
tDSOE
tDHOE
tDSBE
tDHBE
tCS
tHCLK – 2.0 ns
Data Valid to Write Edge (nWE invalid)
Data Hold after Write Edge (nWE invalid)
Data Valid to nBLE Invalid
Data Hold after nBLE Invalid
Data Setup to nCSx Invalid
Data Hold to nCSx Invalid
Data Setup to nOE Invalid
Data Hold to nOE Invalid
tHCLK + 2.0 ns
Output 50 pF
tHCLK – 1.0 ns
tHCLK + 3.0 ns
—
—
—
—
—
—
D[31:0]
0 ns
15 ns
Input
—
0 ns
15 ns
Data Setup to nBLE Invalid
Data Hold to nBLE Invalid
0 ns
2 × tHCLK – 3.0 ns 2 × tHCLK + 3.0 ns nCSx Width
nCS[7:0]
SA[13:0]
Output 30 pF
Output 50 pF
tAVCS
tAHCS
tHCLK – 4.0 ns
tHCLK
tHCLK
Address Valid to nCSx Valid
tHCLK + 4.5 ns
Address Hold after nCSx Invalid
SYNCHRONOUS MEMORY INTERFACE SIGNALS
tOVA
tOHA
5.53/7.54 ns
5.53/7.54 ns
5.53/7.54 ns
Address Valid
1.53/1.54 ns
Address Hold
SA[17:16]/SB[1:0] Output 50 pF
tOVB
Bank Select Valid
Data Hold
tOHD
1.5ns
2 ns
1.53/2.54 ns
1.03/1.54 ns
2 ns
Output 50 pF
tOVD
Data Valid
D[31:0]
tISD
Data Setup
Input
tIHD
Data Hold
tOVCA
tOHCA
tOVRA
tOHRA
tOVSDW
tOHSDW
tOVC
5.53/7.54 ns
5.53/7.54 ns
5.53/7.54 ns
CAS Valid
nCAS
nRAS
nSWE
Output 30 pF
Output 30 pF
Output 30 pF
1.53/24 ns
CAS Hold
2 ns
RAS Valid
1.53/24 ns
2 ns
1.53/24 ns
RAS Hold
Write Enable Valid
Write Enable Hold
Clock Enable Valid
Data Mask Valid
Synchronous Chip Select Valid
Synchronous Chip Select Hold
SCKE[1:0]
DQM[3:0]
Output 30 pF
Output 30 pF
2 ns
5.53/7.54 ns
5.53/7.54 ns
5.53/7.54 ns
tOVDQ
tOVSC
tOHSC
2 ns
2 ns
1.53/24 ns
nSCS[3:0]
Output 30 pF
PCMCIA INTERFACE SIGNALS (+ wait states × HCLK period)
tOVDREG
tOHDREG
tOVD
tHCLK
nREG Valid
nPCREG
D[31:0]
Output 30 pF
Output 50 pF
Input
4 × tHCLK – 5 ns
4 × tHCLK – 5 ns
4 × tHCLK – 5 ns
4 × tHCLK – 5 ns
4 × tHCLK – 5 ns
3 × tHCLK – 5 ns
3 × tHCLK – 5 ns
4 × tHCLK – 5 ns
nREG Hold
tHCLK
Data Valid
tOHD
Data Hold
tISD
tHCLK - 10 ns
tHCLK
Data Setup Time
Data Hold Time
Chip Enable 1 Valid
Chip Enable 1 Hold
Chip Enable 2 Valid
Chip Enable 2 Hold
Output Enable Valid
Output Enable Hold
Write Enable Valid
Write Enable Hold
Card Direction Valid
Card Direction Hold
tIHD
tOVCE1
tOHCE1
tOVCE2
tOHCE2
tOVOE
tOHOE
tOVWE
tOHWE
tOVPCD
tOHPCD
nPCCE1
nPCCE2
nPCOE
nPCWE
PCDIR
Output 30 pF
Output 30 pF
Output 30 pF
Output 30 pF
Output 30 pF
tHCLK
tHCLK + 1 ns
tHCLK + 1 ns
tHCLK
34
Rev. 01 — 16 July 2007
Preliminary data sheet
32-Bit System-on-Chip
NXP Semiconductors
LH7A400
Table 12. AC Signal Characteristics (Cont’d)
SIGNAL
TYPE
LOAD
SYMBOL
MIN.
MAX.
DESCRIPTION
MMC INTERFACE SIGNALS
tOS
tOH
tOS
tOH
5 ns
MMC Command Setup
MMCCMD
Output 100 pF
Output 100 pF
5 ns
MMC Command Hold
MMC Data Setup
MMC Data Hold
5 ns
MMCDATA
5 ns
3 ns
tIS
tIH
tIS
tIH
MMC Data Setup
MMCDATA
MMCCMD
Input
Input
3 ns
MMC Data Hold
3 ns
MMC Command Setup
MMC Command Hold
3 ns
AC97 INTERFACE SIGNALS
tOVAC97
tOHAC97
tISAC97
15 ns
AC97 Output Valid/Sync Valid
AC97 Output Hold/Sync Hold
AC97 Input Setup
ACOUT/ACSYNC Output 30 pF
10 ns
10 ns
2.5 ns
72 ns
ACIN
Input
Input
tIHAC97
AC97 Input Hold
ACBITCLK
tACBITCLK
90 ns
AC97 Clock Period
SYNCHRONOUS SERIAL PORT (SSP)
tOVSSPFRM
10 ns
SSPFRM Valid
SSPFRM
SSPTX
Output
tOHSSPFRM
tOVSSPOUT
tOHSSPOUT
tISSSPIN
5 ns
SSPFRM Hold
10 ns
SSP Transmit Valid
SSP Transmit Hold
SSP Receive Setup
SSP Clock Period
Output 50 pF
5 ns
14 ns
SSPRX
Input
SSPCLK
Output
tSSPCLK
8.819 ms
271 ns
AUDIO CODEC INTERFACE (ACI)
15 ns
tOVD
tOHD
tIS
ACOUT delay from rising clock edge
ACOUT Hold
ACOUT
ACIN
Output 30 pF
Input
10 ns
10 ns
ACIN Setup
tIH
2.5 ns
ACIN Hold
COLOR LCD CONTROLLER
LCDVD [17:0]
Output 30 pF
tOV
—
3 ns
LCD Data Clock to Data Valid
NOTES:
1. Register BCRx:WST1 = 0b000
2. For Output Drive strength specifications, refer to Table 3
3. LH7A400N0G076xx only
4. LH7A400N0G000xx only
Preliminary data sheet
Rev. 01 — 16 July 2007
35
LH7A400
NXP Semiconductors
32-Bit System-on-Chip
deassertion of nCS by a maximum of one HCLK, or at
minimum, can coincide (see Table 12). Figure 12 and
Figure 13 show the waveform and timing for an Exter-
nal Asynchronous Memory Read.
SMC Waveforms
Figure 10 and Figure 11 show the waveform and
timing for an External Asynchronous Memory Write.
Note that the deassertion of nWE can precede the
0
1
2
3
4
HCLK
tWC
A[27:0]
VALID ADDRESS
tDVWE,
tDVBE
tDHWE,
tDHBE
D[31:0]
VALID DATA
tAVCS
tAVWE
tCS
tAHCS
nCSx
nWE
nCS Valid
tWE
tCSHWE
nWE Valid
WRITE EDGE
tCSHBE
tAVBE
tBEW
nBLE Valid
nBLE
LH7A400-201
Figure 10. External Asynchronous Memory Write with 0 Wait States (BCRx:WST1 = 0b000)
36
Rev. 01 — 16 July 2007
Preliminary data sheet
32-Bit System-on-Chip
NXP Semiconductors
LH7A400
0
1
2
3
4
5
6
7
8
HCLK
VALID ADDRESS
VALID DATA
A[27:0]
D[31:0]
nCSx
nCSx Valid
WRITE EDGE
nWE
nWE Valid
nBLE Valid
nBLE
WAIT
WAIT
WAIT
WAIT
STATE 1 STATE 2 STATE 3 STATE 4
0 WAIT STATE
tWS
tWS
tWS
tWS
LH7A400-203
Figure 11. External Asynchronous Memory Write with 4 Wait States (BCRx:WST1 = 0b100)
Preliminary data sheet
Rev. 01 — 16 July 2007
37
LH7A400
NXP Semiconductors
32-Bit System-on-Chip
0
1
2
3
4
HCLK
tRC
tAHCS,
tAHOE, tAHBE
A[27:0]
D[31:0]
VALID ADDRESS
VALID
DATA
tDSCS
DATA
LATCHED
HERE
tAVCS
tCS
tDHCS
nCSx
nCS Valid
tOE
tDSOE
tAVOE
tDHOE
nOE
nOE Valid
tBER
tDSBE
tAVBE
tDHBE
nBLE
nBLE Valid
LH7A400-200
Figure 12. External Asynchronous Memory Read with 0 Wait States (BCRx:WST1 = 0b000)
38
Rev. 01 — 16 July 2007
Preliminary data sheet
32-Bit System-on-Chip
NXP Semiconductors
LH7A400
0
1
2
3
4
5
6
7
8
9
10
HCLK
A[27:0]
VALID ADDRESS
nCSx Valid
nCS[3:0,
CS[7:6]
nOE
nBLE
nOE Valid
nBLE Valid
D[31:0]
VALID DATA
WAIT
WAIT
WAIT
WAIT
STATE 1 STATE 2 STATE 3 STATE 4
0 WAIT STATE,
DATA WOULD BE
LATCHED HERE
4 WAIT STATES,
DATA LATCHED
HERE
tWS tWS tWS tWS
LH7A400-202
Figure 13. External Asynchronous Memory Read with 4 Wait States (BCRx:WST1 = 0b100)
Figure 16 and Figure 17 show Texas Instruments
synchronous serial frame format, Figure 18 through
Synchronous Memory Controller Waveforms
Figure 14 shows the timing for a Synchronous Burst
Figure 25 show the Motorola SPI format, and Figure 26
Read (page already open). Figure 15 shows the timing
and Figure 27 show National Semiconductor’s MICRO-
for Activate a Bank and Write.
WIRE data frame format.
For Texas Instruments SSI format, the SSPFRM pin
is pulsed prior to each frame’s transmission for one
SSP Waveforms
The Synchronous Serial Port (SSP) supports three
serial clock period beginning at its rising edge. For this
data frame formats:
frame format, both the SSP and the external slave
• Texas Instruments SSI
device drive their output data on the rising edge of the
• Motorola SPI
clock and latch data from the other device on the falling
edge. See Figure 16 and Figure 17.
• National Semiconductor MICROWIRE
Each frame format is between 4 and 16 bits in
length, depending upon the programmed data size.
Each data frame is transmitted beginning with the
Most Significant Bit (MSB) i.e. ‘big endian’. For all
three formats, the SSP serial clock is held LOW (inac-
tive) while the SSP is idle. The SSP serial clock tran-
sitions only during active transmission of data. The
SSPFRM signal marks the beginning and end of a
frame. The SSPEN signal controls an off-chip line
driver’s output enable pin.
Preliminary data sheet
Rev. 01 — 16 July 2007
39
LH7A400
NXP Semiconductors
32-Bit System-on-Chip
tSCLK
SCLK
tOHXXX
READ
tOHA, tOHB
SDRAMcmd
tOVXXX
nDQM
SA[13:0],
SB[1:0]
BANK,
COLUMN
tISD tIHD
DATA n
tOVA, tOVB
D[31:0]
NOTES:
DATA n + 2
DATA n + 1
1. SDRAMcmd is the combination of nRAS, nCAS, nSWE, and nSCSx.
2. tOVXXX represents tOVRA, tOVCA, tOVSVW, or tOVSC.
3. tOHXXX represents tOHRA, tOHCA, tOHSVW, or tOHSC.
4. DQM[3:0] is static LOW.
DATA n + 3
5. SCKE is static HIGH.
LH7A400-23
Figure 14. Synchronous Burst Read
SCLK
SCKE
tOVC
tOVXXX tOHXXX
ACTIVE
tOHA
WRITE
SDRAMcmd
SA[13:0],
SB[1:0]
BANK,
ROW
BANK,
COLUMN
tOVA
DATA
D[31:0]
tOVD
tOHD
NOTES:
1. SDRAMcmd is the combination of nRAS, nCAS, nSWE, and nSCSx.
2. tOVXXX represents tOVRA, tOVCA, tOVSVW, or tOVSC. Refer to the AC timing table.
3. tOHXXX represents tOHRA, tOHCA, tOHSVW, or tOHSC.
LH7A400-24
Figure 15. Synchronous Bank Activate and Write
40
Rev. 01 — 16 July 2007
Preliminary data sheet
32-Bit System-on-Chip
NXP Semiconductors
LH7A400
SSPCLK
SSPFRM
SSPTXD/
SSPRXD
MSB
LSB
4 to 16 BITS
LH7A400-97
Figure 16. Texas Instruments Synchronous Serial Frame Format (Single Transfer)
SSPCLK
SSPFRM
SSPTXD/
MSB
LSB
SSPRXD
4 to 16 BITS
LH7A400-98
Figure 17. Texas Instruments Synchronous Serial Frame Format (Continuous Transfer)
SSPCLK
nSSPFRM
LSB
LSB
Q
SSPRXD
MSB
4 to 16 BITS
MSB
SSPTXD
NOTE: Q is undefined.
LH7A400-99
Figure 18. Motorola SPI Frame Format (Single Transfer) with SPO = 0 and SPH = 0
Preliminary data sheet
Rev. 01 — 16 July 2007
41
LH7A400
NXP Semiconductors
32-Bit System-on-Chip
SSPCLK
nSSPFRM
SSPTXD/
SSSRXD
LSB
LSB
MSB
MSB
4 to 16 BITS
LH7A400-100
Figure 19. Motorola SPI Frame Format (Continuous Transfer) with SPO = 0 and SPH = 0
SSPCLK
nSSPFRM
Q
LSB
LSB
Q
SSPRXD
SSPTXD
MSB
MSB
4 to 16 BITS
NOTE: Q is undefined.
LH7A400-101
Figure 20. Motorola SPI Frame Format (Single Transfer) with SPO = 0 and SPH = 1
SSPCLK
nSSPFRM
SSPTXD/
LSB
MSB
LSB
MSB
SSSRXD
4 to 16 BITS
LH7A400-102
Figure 21. Motorola SPI Frame Format (Continuous Transfer) with SPO = 0 and SPH = 1
SSPCLK
nSSPFRM
SSPTXD/
LSB
MSB
LSB
MSB
SSSRXD
4 to 16 BITS
LH7A400-103
Figure 22. Motorola SPI Frame Format (Continuous Transfer) with SPO = 1 and SPH = 1
42
Rev. 01 — 16 July 2007
Preliminary data sheet
32-Bit System-on-Chip
NXP Semiconductors
LH7A400
SSPCLK
nSSPFRM
SSPRXD
Q
LSB
LSB
MSB
4 to 16 BITS
SSPTXD
MSB
NOTE: Q is undefined.
LH7A400-104
Figure 23. Motorola SPI Frame Format (Single Transfer) with SPO = 1 and SPH = 0
SSPCLK
nSSPFRM
SSPTXD/
LSB
MSB
LSB
MSB
SSPRXD
4 to 16 BITS
LH7A400-105
Figure 24. Motorola SPI Frame Format (Continuous Transfer) with SPO = 1 and SPH = 0
SSPCLK
nSSPFRM
SSPRXD
Q
Q
MSB
MSB
LSB
LSB
4 to 16 BITS
SSPTXD
NOTE: Q is undefined.
LH7A400-106
Figure 25. Motorola SPI Frame Format (Single Transfer) with SPO = 1 and SPH = 1
Preliminary data sheet
Rev. 01 — 16 July 2007
43
LH7A400
NXP Semiconductors
32-Bit System-on-Chip
For National Semiconductor MICROWIRE format,
an 8-bit control message is transmitted to the off-chip
slave. During this transmission no incoming data is
received by the SSP. After the message has been sent,
the external slave device decodes the message. After
waiting one serial clock period after the last bit of the 8-
bit control message was received it responds by return-
ing the requested data. The returned data can be 4 to
16 bits in length, making the total frame length between
13 to 25 bits. See Figure 26 and Figure 27.
the serial frame pin (SSPFRM) is active LOW. Both the
SSP and external slave device drive their output data
on the falling edge of the clock, and latch data from the
other device on the rising edge of the clock. Unlike the
full-duplex transmission of the other two frame formats,
the National Semiconductor MICROWIRE format uti-
lizes a master-slave messaging technique that oper-
ates in half-duplex. When a frame begins in this mode,
SSPCLK
nSSPFRM
MSB
LSB
SSPTXD
SSPRXD
8-BIT CONTROL
0
MSB
LSB
4 to 16 BITS
OUTPUT DATA
LH7A400-107
Figure 26. MICROWIRE Frame Format (Single Transfer)
SSPCLK
nSSPFRM
SSPTXD
LSB
MSB
LSB
8-BIT CONTROL
0
MSB
LSB
MSB
SSPRXD
4 to 16 BITS
OUTPUT DATA
LH7A400-108
Figure 27. MICROWIRE Frame Format (Continuous Transfers)
44
Rev. 01 — 16 July 2007
Preliminary data sheet
32-Bit System-on-Chip
NXP Semiconductors
LH7A400
PC Card (PCMCIA) Waveforms
Figure 28 shows the waveforms and timing for a
PCMCIA Read Transfer, Figure 29 shows the wave-
forms and timing for a PCMCIA Write Transfer.
PRECHARGE ACCESS
TIME TIME
HOLD
TIME
(See Note 1) (See Note 1) (See Note 1)
HCLK
A[25:0]
ADDRESS
nPCREG
tOVDREG
tOVCEx
tOHDREG
tOHCEx
nPCCEx
(See Note 2)
PCDIR
tOVPCD
tOHPCD
DATA
D[15:0]
nPCOE
tISD
tIHD
tOVOE
tOHOE
NOTES:
1. Precharge time, access time, and hold
time are programmable wait-state times.
2.
nPCCE1 nPCCE2 TRANSFER TYPE
0
0
1
1
0
1
0
1
Common Memory
Attribute Memory
I/O
None
LH7A400-11
Figure 28. PCMCIA Read Transfer
Preliminary data sheet
Rev. 01 — 16 July 2007
45
LH7A400
NXP Semiconductors
32-Bit System-on-Chip
PRECHARGE ACCESS
HOLD
TIME
TIME
TIME
(See Note 1) (See Note 1) (See Note 1)
HCLK
A[25:0]
ADDRESS
nPCREG
tOVDREG
tOVCEx
tOHDREG
tOHCEx
nPCCEx
(See Note 2)
PCDIR
D[15:0]
tOVPCD
tOVD
DATA
tOHD
nPCWE
tOVWE
tOHWE
NOTES:
1. Precharge time, access time, and hold
time are programmable wait-state times.
2.
nPCCE1 nPCCE2 TRANSFER TYPE
0
0
1
1
0
1
0
1
Common Memory
Attribute Memory
I/O
None
LH7A400-12
Figure 29. PCMCIA Write Transfer
ACCESS
nPCWE,
nPCOE
PRECHARGE
HOLD
nCSx
LH7A400-209
Figure 30. PCMCIA Precharge, Access, and Hold Waveform
46
Rev. 01 — 16 July 2007
Preliminary data sheet
32-Bit System-on-Chip
NXP Semiconductors
LH7A400
MMC Interface Waveform
AC97 Interface Waveform
Figure 31 shows the waveforms and timing for an
MMC command or data Read and Write.
Figure 32 shows the waveforms and timing for the
AC97 interface Data Setup and Hold.
MMC CLOCK
tIS tIH
SOC INPUT
DATA/CMD
DATA
tOS
tOH
SOC OUTPUT
INVALID
DATA
INVALID
DATA/CMD
LH7A400-14
Figure 31. MMC Command/Data Read and Write Timing
tACBITCLK
ACBITCLK
tOVAC97
tOHAC97
ACOUT/ACSYNC
ACIN
tISAC97 tIHAC97
LH7A400-16
Figure 32. AC97 Data Setup and Hold
Preliminary data sheet
Rev. 01 — 16 July 2007
47
LH7A400
NXP Semiconductors
32-Bit System-on-Chip
Audio Codec Interface Waveforms
Color LCD Controller Waveforms
Figure 33 and Figure 34 show the timing for the ACI.
Transmit data is clocked on the rising edge of ACBIT-
CLK (whether transmitted by the LH7A400 ACI or by the
external codec chip); receive data is clocked on the fall-
ing edge. This allows full-speed, full duplex operation.
Figure 35 shows the Valid Output Setup Time for
LCD data. Timing diagrams for each CLCDC mode
appear in Figure 36 through Figure 41.
ACBITCLK
ACSYNC/ACOUT
tOS
tOH
ACIN
tIS tIH
LH7A400-169
Figure 33. ACI Signal Timing
ACBITCLK
ACSYNC
BIT
7
6
5
4
3
2
1
0
7
6
ACIN/ACOUT
ACIN/ACOUT
SAMPLED ON
FALLING EDGE
LH7A400-181
Figure 34. ACI Data stream
LCDDCLK
tOV
DATA VALID
LCDVD
(SoC Output)
LH7A400-211
Figure 35. CLCDC Valid Output Data Time
48
Rev. 01 — 16 July 2007
Preliminary data sheet
32-Bit System-on-Chip
NXP Semiconductors
LH7A400
Figure 36. STN Horizontal Timing Diagram
Preliminary data sheet
Rev. 01 — 16 July 2007
49
LH7A400
NXP Semiconductors
32-Bit System-on-Chip
Figure 37. STN Vertical Timing Diagram
50
Rev. 01 — 16 July 2007
Preliminary data sheet
32-Bit System-on-Chip
NXP Semiconductors
LH7A400
Figure 38. TFT Horizontal Timing Diagram
Preliminary data sheet
Rev. 01 — 16 July 2007
51
LH7A400
NXP Semiconductors
32-Bit System-on-Chip
Figure 39. TFT Vertical Timing Diagram
52
Rev. 01 — 16 July 2007
Preliminary data sheet
32-Bit System-on-Chip
NXP Semiconductors
LH7A400
1 AD-TFT or HR-TFT HORIZONTAL LINE
CLCDC CLOCK
(INTERNAL)
TIMING0:HSW
R8 LCDLP
(HORIZONTAL SYNC PULSE)
LCDDCLK
(PANEL DATA CLOCK)
TIMING2:PCD
TIMING2:BCD
TIMING2:IPC
TIMING2:CPL
LCDVD[17:0]
16 × (TIMING0:PPL+1)
001 002 003 004 005 006 007 008
PIXEL DATA
320
TIMING0:HSW +
TIMING0:HBP
LCDENAB
(INTERNAL DATA ENABLE)
N9 LCDDCLK
(DELAYED FOR HR-TFT)
LCDVD[17:0]
(DELAYED FOR HR-TFT)
001 002 003 004 005 006
317 318 319 320
1 LCDDCLK
ALITIMING2:SPLDEL
LCDSPL
(LINE START PULSE LEFT)
R2
R8
1 LCDDCLK
ALITIMING1:LPDEL
LCDLP
(HORIZONTAL SYNC PULSE)
ALITIMING1:PSCLS
ALITIMING2:PS2CLS2
LCDCLS
T1
LCDPS
P2
ALITIMING1:REVDEL
K6 LCDREV
NOTE:
Circled numbers are LHA400 pin numbers.
LH7A400-111
Figure 40. AD-TFT and HR-TFT Horizontal Timing Diagram
Preliminary data sheet
Rev. 01 — 16 July 2007
53
LH7A400
NXP Semiconductors
32-Bit System-on-Chip
TIMING1:VSW
1.5 µs - 4 µs
LCDSPS
(Vertical Sync)
L8
LCDHRLP
(Horizontal Sync)
T2
LCDVD
(LCD Data)
2x H-LINE
R2 LCDSPL
LH7A400-66
Figure 41. AD-TFT and HR-TFT Vertical Timing Diagram
CLOCK AND STATE CONTROLLER (CSC)
WAVEFORMS
Figure 42 shows the behavior of the LH7A400 when
coming out of Reset or Power On. Figure 43 shows exter-
nal reset timing, and Table 13 gives the timing parame-
ters. Figure 44 depicts signal timing following a Reset.
‘battery good’ indication caused by alkaline battery
recovery that can immediately follow a battery-low
switch off. The battery sampling takes place on the ris-
ing edge of the 1 Hz clock. This clock is derived from
the 32.768 kHz oscillator. The WAKEUP pin can be
pulsed, but at least one edge must follow the 2 second
delay to be recognized. For more information, see the
application note “Implementing Auto-Wakeup on the
LH7A4xx Series Devices” at www.nxp.com.
At Power-On, nPOR must be held LOW at least until
the 32.768 kHz oscillator is stable, and must be deas-
serted at least two 32.768 kHz clock periods before the
WAKEUP signal is asserted. Once the 14.7456 MHz
oscillator is stable, the PLLs require 250 µs to lock.
Figure 45 shows the recommended components for
the NXP LH7A400 32.768 kHz external oscillator cir-
cuit. Figure 46 shows the same for the 14.7456 MHz
external oscillator circuit. In both figures, the NAND
gate represents the internal logic of the chip.
On transition from Standby to Run (including a Cold
Boot), the Wakeup pin must not be asserted for 2 sec-
onds after assertion of nPOR to allow time for sampling
BATOK and nEXTPWR. The delay prevents a false
Table 13. Reset AC Timing
DESCRIPTION
PARAMETER
tOSC32
tOSC14
MIN. MAX.
UNIT
32.768 kHz Oscillator Stabilization Time after Power On*
14.7456 MHz Oscillator Stabilization Time after Wake UP
550
ms
ms
4
tURESET/tPWRFL nURESET/nPWRFL Pulse Width
4
32.768 kHz clock periods
NOTE: *VDDC = VDDCmin
54
Rev. 01 — 16 July 2007
Preliminary data sheet
32-Bit System-on-Chip
NXP Semiconductors
LH7A400
VDDCmin
VDDC
XTAL32
tOSC32
WAKEUP
tOSC14
XTAL14
nPOR
LH7A400-25
Figure 42. Oscillator Start-up
tURESET
tPWRFL
nURESET
nPWRFL
LH7A400-26
Figure 43. External Reset
nPOR
2 sec.
WAKEUP
(asynchronous)
≤ 7.8125 ms
CLKEN
7.8125 ms
START UP
HCLK
STABLE CLOCK
LH7A400-175
Figure 44. Signal Timing After Reset
Preliminary data sheet
Rev. 01 — 16 July 2007
55
LH7A400
NXP Semiconductors
32-Bit System-on-Chip
ENABLE
INTERNAL TO
THE LH7A400
EXTERNAL TO
THE LH7A400
XTALIN
Y1
XTALOUT
32.768 kHz
R1
18 MΩ
C1
15 pF
C2
18 pF
GND
GND
NOTES:
RECOMMENDED CRYSTAL SPECIFICATIONS
1. Y1 is a parallel-resonant type crystal. (See table)
2. The nominal values for C1 and C2 shown are for
a crystal specified at 12.5 pF load capacitance (CL).
3. The values for C1 and C2 are dependent upon
the cystal's specified load capacitance and PCB
stray capacitance.
PARAMETER
DESCRIPTION
32.768 kHz Crystal
Tolerance
Aging
Parallel Mode
30 ppm
3 ppm
4. R1 must be in the circuit.
Load Capacitance
ESR (MAX.)
Drive Level
12.5 pF
50 kΩ
1.0 µW (MAX.)
MTRON SX1555 or equivalent
5. Ground connections should be short and return
to the ground plane which is connected to the
processor's core ground pins.
Recommended Part
6. Tolerance for R1, C1, C2 is ≤ 5%.
LH7A400-187
Figure 45. 32.768 kHz External Oscillator Components and Schematic
56
Rev. 01 — 16 July 2007
Preliminary data sheet
32-Bit System-on-Chip
NXP Semiconductors
LH7A400
ENABLE
INTERNAL TO
THE LH7A400
EXTERNAL TO
THE LH7A400
XTALIN
XTALOUT
Y1
14.7456 MHz
R1
1 MΩ
C1
18 pF
C2
22 pF
GND
GND
RECOMMENDED CRYSTAL SPECIFICATIONS
PARAMETER DESCRIPTION
14.7456 MHz Crystal (AT-Cut) Parallel Mode
NOTES:
1. Y1 is a parallel-resonant type crystal. (See table)
2. The nominal values for C1 and C2 shown are for
a crystal specified at 18 pF load capacitance (CL).
3. The values for C1 and C2 are dependent upon
the cystal's specified load capacitance and PCB
stray capacitance.
Tolerance
50 ppm
Stability
100 ppm
Aging
5 ppm
4. R1 must be in the circuit.
Load Capacitance
ESR (MAX.)
Drive Level
Recommended Part
18 pF
40 Ω
5. Ground connections should be short and return
to the ground plane which is connected to the
processor's core ground pins.
100 µW (MAX.)
MTRON SX2050 or equivalent
6. Tolerance for R1, C1, C2 is ≤ 5%.
LH7A400-188
Figure 46. 14.7456 MHz External Oscillator Components and Schematic
Preliminary data sheet
Rev. 01 — 16 July 2007
57
LH7A400
NXP Semiconductors
32-Bit System-on-Chip
Operating Temperature and Noise Immunity
The junction temperature, Tj, is the operating tem-
perature of the transistors in the integrated circuit. The
switching speed of the CMOS circuitry within the SoC
depends partly on Tj, and the lower the operating tem-
perature, the faster the CMOS circuits will switch.
Increased switching noise generated by faster switch-
ing circuits could affect the overall system stability. The
amount of switching noise is directly affected by the
application executed on the SoC.
VDDC
(SOURCE)
VDDC
LH7A400
10 µH
VDDA
+
22 µF
0.1 µF
VSSA
NXP recommends that users implementing a system
to meet industrial temperature standards should use an
external oscillator rather than a crystal to drive the sys-
tem clock input of the System-on-Chip. This change
from crystal to oscillator will increase the robustness
(i.e., noise immunity of the clock input to the SoC).
LH7A400-189
Figure 47. VDDA, VSSA Filter Circuit
UNUSED INPUT SIGNAL CONDITIONING
Floating input signals can cause excessive power
consumption. Unused inputs without internal pull-up or
pull-down resistors should be pulled up or down exter-
nally (NXP recommends tying HIGH), to tie the signal
to its inactive state. 33 KΩ or less is recommended.
Printed Circuit Board Layout Practices
LH7A400 POWER SUPPLY DECOUPLING
The LH7A400 has separate power and ground pins
for different internal circuitry sections. The VDD and
VSS pins supply power to I/O buffers, while VDDC and
VSSC supply power to the core logic, and VDDA/VSSA
supply analog power to the PLLs.
Some GPIO signals default to inputs. If the pins that
carry these signals are unused, software can program
these signals as outputs, eliminating the need for pull-
ups or pull-downs. Power consumption may be higher
than expected until software completes programming
the GPIO. Some LH7A400 inputs have internal pull-
ups or pull-downs. If unused, these inputs do not
require external conditioning.
Each of the VDD and VDDC pins must be provided
with a low impedance path to the corresponding board
power supply. Likewise, the VSS, VSSA, and VSSC
pins must be provided with a low impedance path to the
board ground.
OTHER CIRCUIT BOARD LAYOUT PRACTICES
Each power supply must be decoupled to ground
using at least one 0.1 µF high frequency capacitor
located as close as possible to a VDDx, VSSx pin pair
on each of the four sides of the chip. If room on the cir-
cuit board allows, add one 0.01 µF high frequency
capacitor near each VDDx, VSSx pair on the chip.
All outputs have fast rise and fall times. Printed cir-
cuit trace interconnection length must therefore be
reduced to minimize overshoot, undershoot and reflec-
tions caused by transmission line effects of these fast
output switching times. This recommendation particu-
larly applies to the address and data buses.
To be effective, the capacitor leads and associated
circuit board traces connecting to the chip VDDx, VSSx
pins must be kept to less than half an inch (12.7 mm)
per capacitor lead. There must be one bulk 10 µF
capacitor for each power supply placed near one side
of the chip.
When considering capacitance, calculations must
consider all device loads and capacitances due to the
circuit board traces. Capacitance due to the traces will
depend upon a number of factors, including the trace
width, dielectric material the circuit board is made from
and proximity to ground and power planes.
RECOMMENDED PLL, VDDA, VSSA FILTER
Attention to power supply decoupling and printed cir-
cuit board layout becomes more critical in systems with
higher capacitive loads. As these capacitive loads
increase, transient currents in the power supply and
ground return paths also increase.
The VDDA pins supply power to the chip PLL cir-
cuitry. VSSA is the ground return path for the PLL cir-
cuit. NXP recommends a low-pass filter attached as
shown in Figure 47. The values of the inductor and
capacitors are not critical. The low-pass filter prevents
high frequency noise from adversely affecting the PLL
circuits. The distance from the IC pin to the high fre-
quency capacitor should be as short as possible.
58
Rev. 01 — 16 July 2007
Preliminary data sheet
32-Bit System-on-Chip
NXP Semiconductors
LH7A400
PACKAGE SPECIFICATIONS
BGA256: plastic ball grid array package; 256 balls
SOT1018-1
D
B
D
A
1
ball A1
index area
A
2
A
1
E
1
E
A
detail X
e
1
C
M
M
∅ v
∅ w
C A
C
B
b
e
1/2 e
y
1
y
C
T
R
P
M
K
H
F
N
L
e
J
e
2
G
E
C
A
1/2 e
D
B
ball A1
index area
1
3
5
7
9
11
13
15
2
4
6
8
10
12
14
16
X
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
UNIT
A
1
A
2
b
D
D
1
E
E
1
e
e
1
e
2
v
w
y
y
1
max
0.5
0.3
1.45 0.55 17.2 15.75 17.2 15.75
1.25 16.8 14.75 16.8 14.75
mm
1.95
1
15
15
0.25
0.1
0.15 0.35
0.45
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
07-07-07
07-07-07
SOT1018-1
Figure 48. Package outline SOT1018-1 (BGA256)
Preliminary data sheet
Rev. 01 — 16 July 2007
59
LH7A400
NXP Semiconductors
32-Bit System-on-Chip
LFBGA256: plastic low profile fine-pitch ball grid array package; 256 balls
SOT1020-1
D
B
A
ball A1
index area
A
2
A
1
E
A
detail X
e
1
C
y
M
∅ v
∅ w
C A
C
B
b
e
1/2 e
y
1
M
C
T
R
P
N
M
K
H
e
L
J
e
2
G
1/2 e
F
E
D
B
C
A
ball A1
index area
1
3
5
7
9
11
13
15
X
2
4
6
8
10
12
14
16
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
UNIT
A
1
A
2
b
D
E
e
e
1
e
2
v
w
y
y
1
max
0.4
0.3
1.35
1.15
0.5
0.4
14.1 14.1
13.9 13.9
mm
1.7
0.8
12
12
0.15 0.08 0.12
0.1
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
07-07-07
07-07-07
SOT1020-1
Figure 49. Package outline SOT1020-1 (LFBGA256)
60
Rev. 01 — 16 July 2007
Preliminary data sheet
32-Bit System-on-Chip
NXP Semiconductors
LH7A400
REVISION HISTORY
Table 14. Revision history
Document ID
Release date Data sheet status
Change notice Supersedes
FAST LH7A400 v1-5 5-9-07
LH7A400_N_1 20070716
Preliminary data
sheet
-
Modifications:
• First NXP version based on the LH7A400 data sheet of 20070509
Preliminary data sheet
Rev. 01 — 16 July 2007
61
LH7A400
NXP Semiconductors
32-Bit System-on-Chip
1. Legal information
1.1
Data sheet status
[1][2]
[3]
Document status
Product status
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of a NXP Semiconductors product can reasonably be expected to
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
1.2
Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the full
data sheet shall prevail.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
1.3
Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without limitation
specifications and product descriptions, at any time and without notice. This
document supersedes and replaces all information supplied prior to the
publication hereof.
1.4
Trademarks
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
2. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: salesaddresses@nxp.com
© NXP B.V. 2007. All rights reserved.
IMPORTANT NOTICE
Dear customer,
As from June 1st, 2007 NXP Semiconductors has acquired the LH7xxx ARM Microcontrollers from
Sharp Microelectronics. The following changes are applicable to the attached data sheet. In data
sheets where the previous Sharp or Sharp Corporation references remain, please use the new
links as shown below.
For www.sharpsma.com use www.nxp.com/microcontrollers
for indicated sales addresses use salesaddresses@nxp.com (email)
The copyright notice at the bottom of each page (or elsewhere in the document, depending on the
version)
- Copyright © (year) by SHARP Corporation.
is replaced with:
- © NXP B.V. (year). All rights reserved.
If you have any questions related to the data sheet, please contact our nearest sales office via
e-mail or phone (details via salesaddresses@nxp.com). Thank you for your cooperation and
understanding, In addition to that the Annex A (attached hereto) is added to the document.
NXP Semiconductors
ANNEX A: Disclaimers (11)
1. t001dis100.fm: General (DS, AN, UM)
General — Information in this document is believed to be accurate and reliable. However, NXP
Semiconductors does not give any representations or warranties, expressed or implied, as to the
accuracy or completeness of such information and shall have no liability for the consequences of
use of such information.
2. t001dis101.fm: Right to make changes (DS, AN, UM)
Right to make changes — NXP Semiconductors reserves the right to make changes to
information published in this document, including without limitation specifications and product
descriptions, at any time and without notice. This document supersedes and replaces all
information supplied prior to the publication hereof.
3. t001dis102.fm: Suitability for use (DS, AN, UM)
Suitability for use — NXP Semiconductors products are not designed, authorized or warranted
to be suitable for use in medical, military, aircraft, space or life support equipment, nor in
applications where failure or malfunction of a NXP Semiconductors product can reasonably be
expected to result in personal injury, death or severe property or environmental damage. NXP
Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in
such equipment or applications and therefore such inclusion and/or use is at the customer’s own
risk.
4. t001dis103.fm: Applications (DS, AN, UM)
Applications — Applications that are described herein for any of these products are for
illustrative purposes only. NXP Semiconductors makes no representation or warranty that such
applications will be suitable for the specified use without further testing or modification.
5. t001dis104.fm: Limiting values (DS)
Limiting values — Stress above one or more limiting values (as defined in the Absolute
Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting
values are stress ratings only and operation of the device at these or any other conditions above
those given in the Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
6. t001dis105.fm: Terms and conditions of sale (DS)
Terms and conditions of sale — NXP Semiconductors products are sold subject to the general
terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms,
including those pertaining to warranty, intellectual property rights infringement and limitation of
liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any
inconsistency or conflict between information in this document and such terms and conditions, the
latter will prevail.
7. t001dis106.fm: No offer to sell or license (DS)
No offer to sell or license — Nothing in this document may be interpreted or construed as an
offer to sell products that is open for acceptance or the grant, conveyance or implication of any
license under any copyrights, patents or other industrial or intellectual property rights.
8. t001dis107.fm: Hazardous voltage (DS, AN, UM; if applicable)
Hazardous voltage — Although basic supply voltages of the product may be much lower, circuit
voltages up to 60 V may appear when operating this product, depending on settings and
application. Customers incorporating or otherwise using these products in applications where
such high voltages may appear during operation, assembly, test etc. of such application, do so at
their own risk. Customers agree to fully indemnify NXP Semiconductors for any damages
resulting from or in connection with such high voltages. Furthermore, customers are drawn to
safety standards (IEC 950, EN 60 950, CENELEC, ISO, etc.) and other (legal) requirements
applying to such high voltages.
9. t001dis108.2.fm: Bare die (DS; if applicable)
Bare die (if applicable) — Products indicated as Bare Die are subject to separate specifications
and are not tested in accordance with standard testing procedures. Product warranties and
guarantees as stated in this document are not applicable to Bare Die Products unless such
warranties and guarantees are explicitly stated in a valid separate agreement entered into by
NXP Semiconductors and customer.
10. t001dis109.fm: AEC unqualified products (DS, AN, UM; if applicable)
AEC unqualified products — This product has not been qualified to the appropriate Automotive
Electronics Council (AEC) standard Q100 or Q101 and should not be used in automotive critical
applications, including but not limited to applications where failure or malfunction of an NXP
Semiconductors product can reasonably be expected to result in personal injury, death or severe
property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or
use of NXP Semiconductors products in such equipment or applications and therefore such
inclusion and/or use is for the customer’s own risk.
11. t001dis110.fm: Suitability for use in automotive applications only (DS, AN, UM; if
applicable)
Suitability for use in automotive applications only — This NXP Semiconductors product has
been developed for use in automotive applications only. The product is not designed, authorized
or warranted to be suitable for any other use, including medical, military, aircraft, space or life
support equipment, nor in applications where failure or malfunction of an NXP Semiconductors
product can reasonably be expected to result in personal injury, death or severe property or
environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore such inclusion and/or
use is at the customer’s own risk.
相关型号：
LH7A400N0F000XX
RISC Microcontroller, 32-Bit, FLASH, 195MHz, CMOS, PBGA256, LEAD FREE, PLASTIC, BGA-256
SHARP
©2020 ICPDF网 联系我们和版权申明