LPC1124JBD48/303_技术文档

LPC112x

32-bit ARM Cortex-M0 microcontroller; 64 kB flash and 8 kB

SRAM; 12-bit ADC

Rev. 1 — 24 February 2015

Product data sheet

1. General description

The LPC112x are a ARM Cortex-M0 based, low-cost 32-bit MCU family, designed for

8/16-bit microcontroller applications, offering performance, low power, simple instruction

set and memory addressing together with reduced code size compared to existing 8/16-bit

architectures.

The LPC112x operate at CPU frequencies of up to 50 MHz.

The peripheral complement of the LPC112x includes 64 kB of flash memory, 8 kB of data

memory, one Fast-mode Plus I²C-bus interface, three RS-485/EIA-485 UARTs, two SSP

interfaces, four general purpose counter/timers, a 12-bit ADC, and up to 38 general

purpose I/O pins.

2. Features and benefits

 System:

 ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.

 ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).

 Non-Maskable Interrupt (NMI) input selectable from several input sources.

 Serial Wire Debug.

 System tick timer.

 Memory:

 64 kB on-chip flash programming memory.

 256 byte page erase function.

 8 kB SRAM.

 In-System Programming (ISP) and In-Application Programming (IAP) via on-chip

bootloader software.

 Digital peripherals:

 Up to 38 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down

resistors. A configurable open-drain mode is supported.

 GPIO pins can be used as edge and level sensitive interrupt sources.

 High-current output driver (20 mA) on one pin.

 High-current sink drivers (20 mA) on two I²C-bus pins in Fast-mode Plus.

 Four general purpose counter/timers with up to six capture inputs and up to 13

match outputs.

 Programmable windowed WDT.

 Analog peripherals:

 12-bit ADC with 2 Msamples/s and eight channels.

LPC112x

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

 Serial interfaces:

 Three UARTs with fractional baud rate generation, internal FIFO, and RS-485

support. One UART with modem control.

 Two SSP controllers with FIFO and multi-protocol capabilities.

 I²C-bus interface supporting full I²C-bus specification and Fast-mode Plus with a

data rate of 1 Mbit/s with multiple address recognition and monitor mode.

 Clock generation:

 12 MHz internal RC oscillator trimmed to 1 % accuracy for 25 C  T_amb +85 C

that can optionally be used as a system clock.

 Crystal oscillator with an operating range of 1 MHz to 25 MHz.

 Programmable watchdog oscillator with a frequency range of 9.4 kHz to 2.3 MHz.

 PLL allows CPU operation up to the maximum CPU rate without the need for a

high-frequency crystal. May be run from the system oscillator or the internal RC

oscillator.

 Clock output function with divider that can reflect the system oscillator clock, IRC

clock, CPU clock, and the Watchdog clock.

 Power control:

 Integrated PMU (Power Management Unit) to minimize power consumption during

Sleep, Deep-sleep, and Deep power-down modes.

 Power profiles residing in boot ROM allowing to optimize performance and

minimize power consumption for any given application through one simple function

call.

 Three reduced power modes: Sleep, Deep-sleep, and Deep power-down.

 Processor wake-up from Deep-sleep mode via a dedicated start logic using up to

13 of the functional pins.

 Power-On Reset (POR).

 Brownout detect with up to four separate thresholds for interrupt and forced reset.

 Unique device serial number for identification.

 Single power supply (1.8 V to 3.6 V).

 Available as LQFP48 package.

3. Applications

 eMetering

 Lighting

 Alarm systems

 White goods

4. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

Version

LPC1125JBD48/303

LPC1124JBD48/303

LQFP48

LQFP48: plastic low profile quad flat package; 48 leads; body 7  7  SOT313-2

1.4 mm

LQFP48

LQFP48: plastic low profile quad flat package; 48 leads; body 7  7  SOT313-2

1.4 mm

LPC112x

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Product data sheet

Rev. 1. — 24 February 2015

2 of 63

LPC112x

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

4.1 Ordering options

Table 2.

Ordering options

Type number

Flash

Total

SRAM

UART

RS-485

I²C/

Fast+

SSP ADC

channels

GPIO

Package

LPC1125JBD48/303

LPC1124JBD48/303

64 kB

32 kB

8 kB

3

1

2

8

38

LQFP48

8

LPC112x

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Product data sheet

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LPC112x

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

5. Block diagram

XTALIN

SWD

XTALOUT

RESET

CLOCK

IRC

GENERATION

POWER CONTROL,

SYSTEM

LPC112x

CLKOUT

TEST/DEBUG

INTERFACE

POR

FUNCTIONS

clocks and controls

ARM

CORTEX-M0

FLASH

64 kB

SRAM

8 kB

ROM

slave

system

bus

slave

GPIO ports

PIO0/1/2/3

HIGH-SPEED

GPIO

AHB-LITE BUS

slave

AHB TO APB

BRIDGE

U0_RXD

U0_TXD

U0_DTR,

U0_DSR,

U0_CTS,

UART0

12-bit ADC

SSP0

ADC_[8:1]

SSP0_SCK,

SSP0_SSEL,

SSP0_MISO,

SSP0_MOSI

SSP1_SCK,

SSP1_SSEL,

SSP1_MISO,

SSP1_MOSI

U0_DCD,

U0_RI, U0_RTS

U1_TXD

U1_RXD

UART1

UART2

SSP1

U2_TXD

U2_RXD

I2C0_SCL

I2C0_SDA

2

I C

CT32B0_MAT[3:0]

CT32B0_CAP0

32-bit COUNTER/TIMER 0

32-bit COUNTER/TIMER 1

16-bit COUNTER/TIMER 0

16-bit COUNTER/TIMER 1

WWDT

IOCON

CT32B1_MAT[3:0]

CT32B1_CAP0

CT16B0_MAT[2:0]

CT16B0_CAP[1:0]

SYSTEM CONTROL

PMU

CT16B1_MAT[1:0]

CT16B1_CAP[1:0]

aaa-016082

Fig 1. LPC112x block diagram

6. Pinning information

6.1 Pinning

LPC112x

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Product data sheet

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4 of 63

LPC112x

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

PIO2_3 37

24 PIO2_9

23 PIO0_7

22 PIO0_6

21 PIO3_5

20 PIO2_5

19 PIO2_4

18 PIO3_4

17 PIO1_9

16 PIO0_5

15 PIO0_4

14 PIO0_3

13 PIO2_1

SWDIO/PIO1_3 38

PIO1_4/WAKEUP 39

VSSA 40

VSS 41

PIO1_11 42

VDDA 43

LPC112x

VDD 44

PIO1_5 45

PIO1_6 46

PIO1_7 47

PIO3_3 48

aaa-016083

Fig 2. LQFP48 package

LPC112x

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Product data sheet

Rev. 1. — 24 February 2015

5 of 63

LPC112x

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

6.2 Pin description

Table 3.

Symbol

Pin description

Reset Start

Type Description

state logic

[1]

wake-up

[8]

[6]

RESET/PIO0_0

PIO0_1

3

4

I; PU

yes

I

RESET — External reset input: A LOW-going pulse as

short as 50 ns on this pin resets the device, causing

I/O ports and peripherals to take on their default

states, and processor execution to begin at address 0.

I/O

PIO0_0 — General purpose port 0 input/output 0.

yes

PIO0_1 — General purpose port 0 input/output 1. A

LOW level on this pin during reset starts the ISP

command handler.

O

I/O

I

CLKOUT — Clock output.

CT32B0_MAT2 — Match output 2 for 32-bit timer 0.

PIO0_2 — General purpose port 0 input/output 2.

SSP0_SSEL — Slave select for SSP0.

CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.

ADC_PIN_TRIG0 — ADC pin trigger input 0.

PIO0_3 — General purpose port 0 input/output 3.

R — Reserved.

[6]

PIO0_2

PIO0_3

10

14

I; PU

yes

I

I/O

-

R — Reserved.

I

U2_RXD — Receiver input for UART2.

PIO0_4

PIO0_5

PIO0_6

15

16

22

I; IA

I; PU

yes

I/O

PIO0_4 — General purpose port 0 input/output 4.

I2C0_SCL — I²C-bus, open-drain clock input/output.

High-current sink only if I²C Fast-mode Plus is

selected in the I/O configuration register.

[7]

[6]

I/O

PIO0_5 — General purpose port 0 input/output 5.

I2C0_SDA — I²C-bus, open-drain data input/output.

High-current sink only if I²C Fast-mode Plus is

selected in the I/O configuration register.

I/O

-

PIO0_6 — General purpose port 0 input/output 6.

R — Reserved.

I/O

O

SSP0_SCK — Serial clock for SSP0.

U1_TXD — Transmitter output for UART1.

[5]

PIO0_7

PIO0_8

23

26

I; PU

yes

I/O

PIO0_7 — General purpose port 0 input/output 7.

High-current output driver.

I

U0_CTS — Clear To Send input for UART0.

ADC_PIN_TRIG1 — ADC pin trigger input 1.

U1_RXD — Receiver input for UART1.

PIO0_8 — General purpose port 0 input/output 8.

SSP0_MISO — Master In Slave Out for SSP0.

CT16B0_MAT0 — Match output 0 for 16-bit timer 0.

R — Reserved.

I

[6]

I/O

O

-

I

ADC_PIN_TRIG2 — ADC pin trigger input 2.

LPC112x

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Product data sheet

Rev. 1. — 24 February 2015

6 of 63

LPC112x

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

Table 3.

Symbol

Pin description

Reset Start

Type Description

state logic

[1]

wake-up

[6]

PIO0_9

27

I; PU

yes

I/O

O

PIO0_9 — General purpose port 0 input/output 9.

SSP0_MOSI — Master Out Slave In for SSP0.

CT16B0_MAT1 — Match output 1 for 16-bit timer 0.

R — Reserved.

-

I

ADC_PIN_TRIG3 — ADC pin trigger input 3.

SWCLK — Serial wire clock.

[6]

[3]

SWCLK/PIO0_10

R/PIO0_11

28

30

I; PU

yes

I/O

O

PIO0_10 — General purpose port 0 input/output 10.

SSP0_SCK — Serial clock for SSP0.

CT16B0_MAT2 — Match output 2 for 16-bit timer 0.

I

R — Reserved. Configure for an alternate function in

the IOCON block.

I/O

AI

O

I

PIO0_11 — General purpose port 0 input/output 11.

ADC_7 — A/D converter, input 7.

CT32B0_MAT3 — Match output 3 for 32-bit timer 0.

[3]

R/PIO1_0

31

32

35

38

I; PU

yes

R — Reserved. Configure for an alternate function in

the IOCON block.

I/O

AI

I

PIO1_0 — General purpose port 1 input/output 0.

ADC_6 — A/D converter, input 6.

CT32B1_CAP0 — Capture input 0 for 32-bit timer 1.

R/PIO1_1

O; PU no

O

R — Reserved. Configure for an alternate function in

the IOCON block.

I/O

AI

O

I

PIO1_1 — General purpose port 1 input/output 1.

ADC_5 — A/D converter, input 5.

CT32B1_MAT0 — Match output 0 for 32-bit timer 1.

R/PIO1_2

I; PU

no

R — Reserved. Configure for an alternate function in

the IOCON block.

I/O

AI

PIO1_2 — General purpose port 1 input/output 2.

ADC_4 — A/D converter, input 4.

O

CT32B1_MAT1 — Match output 1 for 32-bit timer 1.

SWDIO/PIO1_3

I/O

SWDIO — Serial Wire Debug I/O. SWDIO is enabled

by default on this pin.

I/O

AI

O

PIO1_3 — General purpose port 1 input/output 3.

ADC_3 — A/D converter, input 3.

CT32B1_MAT2 — Match output 2 for 32-bit timer 1.

LPC112x

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Product data sheet

Rev. 1. — 24 February 2015

7 of 63

LPC112x

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

Table 3.

Symbol

Pin description

Reset Start

Type Description

state logic

[1]

wake-up

[4]

PIO1_4/

39

I; PU

no

IO

PIO1_4 — General purpose port 1 input/output 4.

WAKEUP

General-purpose digital input/output pin. This pin also

serves as the Deep power-down mode wake-up pin

with 20 ns glitch filter. Pull this pin HIGH externally

before entering Deep power-down mode. Pull this pin

LOW to exit Deep power-down mode. A LOW-going

pulse as short as 50 ns wakes up the part.

AI

O

I/O

O

I

ADC_2 — A/D converter, input 2.

CT32B1_MAT3 — Match output 3 for 32-bit timer 1.

PIO1_5 — General purpose port 1 input/output 5.

U0_RTS — Request To Send output for UART0.

CT32B0_CAP0 — Capture input 0 for 32-bit timer 0.

PIO1_6 — General purpose port 1 input/output 6.

[6]

PIO1_5

PIO1_6

45

46

I; PU

no

I/O

I

U0_RXD — Receiver input for UART0. In ISP mode,

connect to UART.

O

CT32B0_MAT0 — Match output 0 for 32-bit timer 0.

PIO1_7 — General purpose port 1 input/output 7.

[6]

PIO1_7

PIO1_8

47

9

I; PU

no

I/O

O

U0_TXD — Transmitter output for UART0. In ISP

mode, connect to UART.

O

CT32B0_MAT1 — Match output 1 for 32-bit timer 0.

PIO1_8 — General purpose port 1 input/output 8.

CT16B1_CAP0 — Capture input 0 for 16-bit timer 1.

R — Reserved.

I/O

I

-

O

U2_TXD — Transmitter output for U2.

[6]

[3]

PIO1_9

17

29

I; PU

no

I/O

O

PIO1_9 — General purpose port 1 input/output 9.

CT16B1_MAT0 — Match output 0 for 16-bit timer 1.

SSP1_MOSI — Master Out Slave In for SSP1.I

PIO1_10 — General purpose port 1 input/output 10.

ADC_8 — A/D converter, input 8.

I/O

AI

O

PIO1_10

CT16B1_MAT1 — Match output 1 for 16-bit timer 1.

SSP1_MISO — Master In Slave Out for SSP1.

PIO1_11 — General purpose port 1 input/output 11.

ADC_1 — A/D converter, input 1.

I/O

AI

I

[3]

[6]

PIO1_11

PIO2_0

42

2

I; PU

no

CT32B1_CAP1 — Capture input 1 for 32-bit timer 1.

PIO2_0 — General purpose port 2 input/output 0.

U0_DTR — Data Terminal Ready output for UART0.

SSP1_SSEL — Slave Select for SSP1.

IO

O

I/O

I

ADC_PIN_TRIG4 — ADC pin trigger input 4.

PIO2_1 — General purpose port 2 input/output 1.

U0_DSR — Data Set Ready input for UART0.

SSP1_SCK — Serial clock for SSP1.

[6]

PIO2_1

13

I; PU

no

I/O

I

I/O

LPC112x

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Product data sheet

Rev. 1. — 24 February 2015

8 of 63

LPC112x

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

Table 3.

Symbol

Pin description

Reset Start

Type Description

state logic

[1]

wake-up

[6]

PIO2_2

PIO2_3

PIO2_4

25

I; PU

no

I/O

I

PIO2_2 — General purpose port 2 input/output 2.

U0_DCD — Data Carrier Detect input for UART0.

I/O

I

SSP1_MISO — Master In Slave Out for SSP1.

PIO2_3 — General purpose port 2 input/output 3.

U0_RI — Ring Indicator input for UART0.

37

19

no

I/O

O

SSP1_MOSI — Master Out Slave In for SSP1.

PIO2_4 — General purpose port 2 input/output 4.

CT16B1_MAT1 — Match output 1 for 16-bit timer 1.

SSP1_SSEL — Slave Select for SSP1.

I/O

O

[6]

PIO2_5

PIO2_6

PIO2_7

20

1

I; PU

no

PIO2_5 — General purpose port 2 input/output 5.

CT32B0_MAT0 — Match output 0 for 32-bit timer 0.

PIO2_6 — General purpose port 2 input/output 6.

CT32B0_MAT1 — Match output 1 for 32-bit timer 0.

PIO2_7 — General purpose port 2 input/output 7.

CT32B0_MAT2 — Match output 2 for 32-bit timer 0.

U0_RXD — Receiver input for UART0.

I/O

O

11

I/O

O

I

[6]

PIO2_8

PIO2_9

12

24

I; PU

no

I/O

I

PIO2_8 — General purpose port 2 input/output 8.

CT32B0_MAT3 — Match output 3 for 32-bit timer 0.

U0_TXD — Transmitter output for UART0.

O

I/O

I

PIO2_9 — General purpose port 2 input/output 9.

CT32B0_CAP0 — Capture input 0 for 32-bit timer 0.

PIO2_10 — General purpose port 2 input/output 10.

PIO3_0 — General purpose port 3 input/output 0.

U0_DTR — Data Terminal Ready output for UART0.

CT16B0_MAT0 — Match output 0 for 16-bit timer 0.

U0_TXD — Transmitter Output for UART0.

[6]

PIO2_10

PIO3_0

-

I: PU

I; PU

no

I/O

O

36

O

[6]

PIO3_2

-

I; PU

no

I/O

I

PIO3_2 — General purpose port 3 input/output 2.

U0_DCD — Data Carrier Detect input for UART0.

CT16B0_MAT2 — Match output 2 for 16-bit timer 0.

SSP1_SCK — Serial clock for SSP1.

O

I/O

I

[6]

PIO3_3

PIO3_4

PIO3_5

48

18

21

I; PU

no

PIO3_3 — General purpose port 3 input/output 3.

U0_RI — Ring Indicator input for UART0.

I

CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.

PIO3_4 — General purpose port 3 input/output 4.

CT16B0_CAP1 — Capture input 1 for 16-bit timer 0.

U0_RXD — Receiver input for UART0.

I/O

I

I/O

I

PIO3_5 — General purpose port 3 input/output 5.

CT16B1_CAP1 — Capture input 1 for 16-bit timer 1.

U0_TXD — Transmitter output for UART0.

O

LPC112x

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Product data sheet

Rev. 1. — 24 February 2015

9 of 63

LPC112x

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

Table 3.

Symbol

Pin description

Reset Start

Type Description

state logic

[1]

wake-up

[2]

XTALIN

6

7

-

Input to the oscillator circuit and internal clock

generator circuits. Input voltage must not exceed

1.8 V.

XTALOUT

VREFP

VREFN

V_DD

-

Output from the oscillator amplifier.

Positive reference voltage for the ADC.

Negative reference voltage for the ADC.

33

34

8;

44

3.3 V supply voltage to the internal regulator and the

external rail.

V_DDA

V_SSA

V_SS

43

40

-

Analog supply voltage.

Analog ground.

Ground.

5;

41

[1] Pin state at reset for default function: I = Input; AI = Analog Input; O = Output; PU = internal pull-up enabled (pins pulled up to full V_DD

level (V_DD= 3.3 V)); IA = inactive, no pull-up/down enabled.

[2] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded

(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.

[3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.

When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see Figure 27).

[4] Pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input. When

configured as a ADC input, digital section of the pad is disabled (see Figure 27). In deep power-down mode, this pin serves as the

wake-up pin.

[5] High-current output driver. Pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis

(see Figure 27).

[6] Standard digital I/O pin. Pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see

Figure 27).

[7] I²C-bus pins compliant with the I²C-bus specification for I²C standard mode, I²C Fast-mode, and I²C Fast-mode Plus. The pin requires

an external pull-up to provide output functionality. When power is switched off, this pin is floating and does not disturb the I²C lines.

Open-drain configuration applies to all functions on this pin.

[8] 5 V tolerant pad. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up

from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode. See Figure 28 for the

reset pad configuration.

LPC112x

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Product data sheet

Rev. 1. — 24 February 2015

10 of 63

LPC112x

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

7. Functional description

7.1 ARM Cortex-M0 processor

The ARM Cortex-M0 is a general purpose, 32-bit microprocessor, which offers high

performance and very low power consumption.

7.2 On-chip flash program memory

The LPC112x contain up to 64 kB of on-chip flash memory.

7.3 On-chip SRAM

The LPC112x contain a total of 8 kB on-chip static RAM memory.

7.4 Memory map

The LPC112x incorporate several distinct memory regions, shown in the following figures.

Figure 3 shows the overall map of the entire address space from the user program

viewpoint following reset. The interrupt vector area supports address remapping.

The AHB peripheral area is 2 MB in size, and is divided to allow for up to 128 peripherals.

The APB peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals.

Each peripheral of either type is allocated 16 kB of space. This allows simplifying the

address decoding for each peripheral.

LPC112x

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Product data sheet

Rev. 1. — 24 February 2015

11 of 63

LPC112x

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

AHB peripherals

0x5020 0000

LPC112x

4 GB

0xFFFF FFFF

reserved

0xE010 0000

0xE000 0000

127-16 reserved

0x5004 0000

private peripheral bus

12-15

8-11

4-7

GPIO PIO3

GPIO PIO2

GPIO PIO1

GPIO PIO0

reserved

0x5003 0000

0x5002 0000

0x5020 0000

0x5000 0000

AHB peripherals

0x5001 0000

0x5000 0000

0-3

reserved

APB peripherals

0x4008 0000

31-23 reserved

SSP1

0x4005 C000

0x4005 8000

0x4008 0000

0x4000 0000

22

APB peripherals

reserved

1 GB

21-19 reserved

0x4004 C000

0x4004 8000

0x4004 4000

0x4004 0000

system control

IOCON

18

17

16

15

14

SSP0

0x2000 0000

0.5 GB

flash controller

PMU

0x4003 C000

0x4003 8000

reserved

0x1FFF 4000

0x1FFF 0000

13-10 reserved

16 kB boot ROM

reserved

0x4002 8000

0x4002 4000

0x4002 0000

9

8

7

6

5

4

3

2

1

0

UART2

UART1

0x1000 2000

8 kB SRAM

reserved

12-bit ADC

0x4001 C000

0x4001 8000

32-bit counter/timer 1

32-bit counter/timer 0

16-bit counter/timer 1

16-bit counter/timer 0

UART0

0x4001 4000

0x4001 0000

0x4000 C000

0x4000 8000

0x1000 0000

0x0001 0000

WWDT

0x4000 4000

0x4000 0000

64 kB on-chip flash

(LPC1125)

2

I C-bus

0x0000 E000

0x0000 0000

32 kB on-chip flash

(LPC1124)

0x0000 00C0

active interrupt vectors

0x0000 0000

0 GB

aaa-016174

Fig 3. LPC112x memory map

7.5 Nested Vectored Interrupt Controller (NVIC)

The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M0. The

tight coupling to the CPU allows for low interrupt latency and efficient processing of late

arriving interrupts.

7.5.1 Features

• Controls system exceptions and peripheral interrupts.

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• On the LPC112x, the NVIC supports 32 vectored interrupts including up to 13 inputs

to the start logic from individual GPIO pins.

• Four programmable interrupt priority levels with hardware priority level masking.

• Software interrupt generation.

7.5.2 Interrupt sources

Each peripheral device has one interrupt line connected to the NVIC but may have several

interrupt flags. Individual interrupt flags may also represent more than one interrupt

source.

Any GPIO pin (total of up to 40 pins) regardless of the selected function, can be

programmed to generate an interrupt on a level, or rising edge or falling edge, or both.

7.6 IOCON block

The IOCON block allows selected pins of the microcontroller to have more than one

function. Configuration registers control the multiplexers to allow connection between the

pin and the on-chip peripherals.

Peripherals should be connected to the appropriate pins prior to being activated and prior

to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is

not mapped to a related pin should be considered undefined.

7.7 Fast general purpose parallel I/O

Device pins that are not connected to a specific peripheral function are controlled by the

GPIO registers. Pins may be dynamically configured as inputs or outputs. Multiple outputs

can be set or cleared in one write operation.

LPC112x use accelerated GPIO functions:

• GPIO registers are a dedicated AHB peripheral so that the fastest possible I/O timing

can be achieved.

• Entire port value can be written in one instruction.

Additionally, any GPIO pin (total of 38 pins) providing a digital function can be

programmed to generate an interrupt on a level, a rising or falling edge, or both.

7.7.1 Features

• Bit level port registers allow a single instruction to set or clear any number of bits in

one write operation.

• Direction control of individual bits.

• All I/O default to inputs with pull-ups enabled after reset with the exception of the

I²C-bus pins PIO0_4 and PIO0_5.

• Pull-up/pull-down resistor configuration can be programmed through the IOCON block

for each GPIO pin (except for pins PIO0_4 and PIO0_5).

• All GPIO pins (except PIO0_4 and PIO0_5) are pulled up to 3.3 V (V_DD= 3.3 V) if their

pull-up resistor is enabled in the IOCON block.

• Programmable open-drain mode.

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7.8 UART

32-bit ARM Cortex-M0 microcontroller

The LPC112x contain three UARTs.

Support for RS-485/9-bit mode allows both software address detection and automatic

address detection using 9-bit mode.

The UART includes a fractional baud rate generator. Standard baud rates such as

115200 Bd can be achieved with any crystal frequency above 2 MHz.

7.8.1 Features

• Maximum UART data bit rate of 3.125 MBit/s.

• 16 Byte Receive and Transmit FIFOs.

• Register locations conform to 16C550 industry standard.

• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.

• Built-in fractional baud rate generator covering wide range of baud rates without a

need for external crystals of particular values.

• FIFO control mechanism that enables software flow control implementation.

• Support for RS-485/9-bit mode.

• Support for modem control.

7.9 SSP controller

The LPC112x contains two SSP controllers.

The SSP controller is capable of operation on a SSP, 4-wire SSI, or Microwire bus. It can

interact with multiple masters and slaves on the bus. Only a single master and a single

slave can communicate on the bus during a given data transfer. The SSP supports full

duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the

slave and from the slave to the master. In practice, often only one of these data flows

carries meaningful data.

7.9.1 Features

• Maximum SSP speed of 25 Mbit/s (master) or 4.17 Mbit/s (slave) (in SSP mode).

• Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National

Semiconductor Microwire buses.

• Synchronous serial communication.

• Master or slave operation.

• 8-frame FIFOs for both transmit and receive.

• 4-bit to 16-bit frame.

7.10 I²C-bus serial I/O controller

The LPC112x contains one I²C-bus controller.

The I²C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock Line

(SCL) and a Serial DAta line (SDA). Each device is recognized by a unique address and

can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the

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capability to both receive and send information (such as memory). Transmitters and/or

receivers can operate in either master or slave mode, depending on whether the chip has

to initiate a data transfer or is only addressed. The I²C is a multi-master bus and can be

controlled by more than one bus master connected to it.

7.10.1 Features

• The I²C-interface is a standard I²C-bus compliant interface with open-drain pins. The

I²C-bus interface also supports Fast-mode Plus with bit rates up to 1 Mbit/s.

• Easy to configure as master, slave, or master/slave.

• Programmable clocks allow versatile rate control.

• Bidirectional data transfer between masters and slaves.

• Multi-master bus (no central master).

• Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus.

• Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus.

• Serial clock synchronization can be used as a handshake mechanism to suspend and

resume serial transfer.

• The I²C-bus can be used for test and diagnostic purposes.

• The I²C-bus controller supports multiple address recognition and a bus monitor mode.

7.11 Analog-to-Digital Converter (ADC)

The ADC supports a resolution of 12 bit and fast conversion rates of up to 2 Msamples/s.

Sequences of analog-to-digital conversions can be triggered by multiple sources. Possible

trigger sources are internal connections to the 16-bit timer match outputs, five external

pins, and the ARM TXEV interrupt.

The ADC includes a hardware threshold compare function with zero-crossing detection.

7.11.1 Features

• 12-bit successive approximation analog to digital converter.

• 12-bit conversion rate of 2 Msamples/s.

• Input multiplexing among 8 pins.

• Two configurable conversion sequences with independent triggers.

• Optional automatic high/low threshold comparison and zero-crossing detection.

• Power-down mode and low-power operating mode.

• Measurement range VREFN to VREFP (typically 3 V; not to exceed VDDA voltage

level).

• Burst conversion mode for single or multiple inputs.

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7.12 General purpose external event counter/timers

The LPC112x include two 32-bit counter/timers and two 16-bit counter/timers. The

counter/timer is designed to count cycles of the system derived clock. It can optionally

generate interrupts or perform other actions at specified timer values, based on four

match registers. Each counter/timer also includes up to two capture inputs to trap the

timer value when an input signal transitions, optionally generating an interrupt.

7.12.1 Features

• A 32-bit/16-bit timer/counter with a programmable 32-bit/16-bit prescaler.

• Counter or timer operation.

• Up to two capture channels per timer, that can take a snapshot of the timer value

when an input signal transitions. A capture event may also generate an interrupt.

• The timer and prescaler may be configured to be cleared on a designated capture

event. This feature permits easy pulse width measurement by clearing the timer on

the leading edge of an input pulse and capturing the timer value on the trailing edge.

• Four match registers per timer that allow:

– Continuous operation with optional interrupt generation on match.

– Stop timer on match with optional interrupt generation.

– Reset timer on match with optional interrupt generation.

• Up to four external outputs corresponding to match registers, with the following

capabilities:

– Set LOW on match.

– Set HIGH on match.

– Toggle on match.

– Do nothing on match.

7.13 System tick timer

The ARM Cortex-M0 includes a system tick timer (SYSTICK) that is intended to generate

a dedicated SYSTICK exception at a fixed time interval (typically 10 ms).

7.14 Windowed WatchDog Timer

The purpose of the watchdog is to reset the controller if software fails to periodically

service it within a programmable time window.

7.14.1 Features

• Internally resets chip if not periodically reloaded during the programmable time-out

period.

• Optional windowed operation requires reload to occur between a minimum and

maximum time period, both programmable.

• Optional warning interrupt can be generated at a programmable time prior to

watchdog time-out.

• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be

disabled.

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• Incorrect feed sequence causes reset or interrupt if enabled.

• Flag to indicate watchdog reset.

• Programmable 24-bit timer with internal prescaler.

• Selectable time period from (T_cy(WDCLK) 256  4) to (T_cy(WDCLK) 2²⁴ 4) in

multiples of T_cy(WDCLK) 4.

• The Watchdog Clock (WDCLK) source can be selected from the IRC or the dedicated

watchdog oscillator (WDO). This gives a wide range of potential timing choices of

watchdog operation under different power conditions.

7.15 Clocking and power control

7.15.1 Crystal oscillators

The LPC112x include three independent oscillators. These are the system oscillator, the

Internal RC oscillator (IRC), and the Watchdog oscillator. Each oscillator can be used for

more than one purpose as required in a particular application.

Following reset, the LPC112x will operate from the Internal RC oscillator until switched by

software. This allows systems to operate without any external crystal and the bootloader

code to operate at a known frequency.

See Figure 4 for an overview of the LPC112x clock generation.

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ARM

CORTEX-M0

system clock

SYSTEM CLOCK

DIVIDER

AHB clocks

1 to 18

(memories

and peripherals)

18

SYSAHBCLKDIV

SYSAHBCLKCTRL[1:18]

IRC oscillator

SSP0 PERIPHERAL

CLOCK DIVIDER

SSP0_PCLK

UART0_PCLK

SSP1_PCLK

UART1_PCLK

UART2_PCLK

main clock

watchdog oscillator

UART0 PERIPHERAL

CLOCK DIVIDER

SSP1 PERIPHERAL

CLOCK DIVIDER

MAINCLKSEL

(main clock select)

sys_pllclkout

UART1 PERIPHERAL

CLOCK DIVIDER

IRC oscillator

SYSTEM PLL

sys_pllclkin

system oscillator

UART2 PERIPHERAL

CLOCK DIVIDER

SYSPLLCLKSEL

(system PLL clock select)

IRC oscillator

WDT CLOCK

DIVIDER

WDCLK

watchdog oscillator

WDTUEN

(WDT clock update enable)

IRC oscillator

system oscillator

CLKOUT PIN CLOCK

DIVIDER

CLKOUT pin

watchdog oscillator

CLKOUTUEN

(CLKOUT update enable)

aaa-016177

Fig 4. LPC112x clock generation block diagram

7.15.1.1 Internal RC oscillator

The IRC may be used as the clock source for the WDT, and/or as the clock that drives the

PLL and subsequently the CPU. The nominal IRC frequency is 12 MHz.

Upon power-up or any chip reset, the LPC112x use the IRC as the clock source. Software

may later switch to one of the other available clock sources.

7.15.1.2 System oscillator

The system oscillator can be used as the clock source for the CPU, with or without using

the PLL.

The system oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be

boosted to a higher frequency, up to the maximum CPU operating frequency, by the

system PLL.

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7.15.1.3 Watchdog oscillator

The watchdog oscillator can be used as a clock source that directly drives the CPU, the

watchdog timer, or the CLKOUT pin. The watchdog oscillator nominal frequency is

programmable between 9.4 kHz and 2.3 MHz. The frequency spread over processing and

temperature is 40 %.

7.15.2 System PLL

The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input

frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO).

The multiplier can be an integer value from 1 to 32. The CCO operates in the range of

156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within

its frequency range while the PLL is providing the desired output frequency. The PLL

output frequency must be lower than 100 MHz. The output divider may be set to divide by

2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2, it is

insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed

following a chip reset and may be enabled by software. The program must configure and

activate the PLL, wait for the PLL to lock, and then connect to the PLL as a clock source.

The PLL settling time is 100 s.

7.15.3 Clock output

The LPC112x features a clock output function that routes the IRC oscillator, the system

oscillator, the watchdog oscillator, or the main clock to an output pin.

7.15.4 Wake-up process

The LPC112x begin operation at power-up and when awakened from Deep power-down

mode by using the 12 MHz IRC oscillator as the clock source. This allows chip operation

to resume quickly. If the system oscillator or the PLL is needed by the application,

software will need to enable these features and wait for them to stabilize before they are

used as a clock source.

7.15.5 Power control

The LPC112x support a variety of power control features. There are three special modes

of processor power reduction: Sleep mode, Deep-sleep mode, and Deep power-down

mode. The CPU clock rate may also be controlled as needed by changing clock sources,

reconfiguring PLL values, and/or altering the CPU clock divider value. This allows a

trade-off of power versus processing speed based on application requirements. In

addition, a register is provided for shutting down the clocks to individual on-chip

peripherals, allowing fine tuning of power consumption by eliminating all dynamic power

use in any peripherals that are not required for the application. Selected peripherals have

their own clock divider which provides even better power control.

7.15.5.1 Power profiles

The power consumption in Active and Sleep modes can be optimized for the application

through simple calls to the power profile. The power configuration routine configures the

LPC112x for one of the following power modes:

• Default mode corresponding to power configuration after reset.

• CPU performance mode corresponding to optimized processing capability.

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• Efficiency mode corresponding to optimized balance of current consumption and CPU

performance.

• Low-current mode corresponding to lowest power consumption.

In addition, the power profile includes routines to select the optimal PLL settings for a

given system clock and PLL input clock.

7.15.5.2 Sleep mode

When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep

mode does not need any special sequence but re-enabling the clock to the ARM core.

In Sleep mode, execution of instructions is suspended until either a reset or interrupt

occurs. Peripheral functions continue operation during Sleep mode and may generate

interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic

power used by the processor itself, memory systems and related controllers, and internal

buses.

7.15.5.3 Deep-sleep mode

In Deep-sleep mode, the chip is in Sleep mode, and in addition all analog blocks are shut

down. As an exception, the user has the option to keep the watchdog oscillator and the

BOD circuit running for self-timed wake-up and BOD protection. Deep-sleep mode allows

for additional power savings.

Up to 13 pins total serve as external wake-up pins to the start logic to wake up the chip

from Deep-sleep mode.

Unless the watchdog oscillator is selected to run in Deep-sleep mode, the clock source

should be switched to IRC before entering Deep-sleep mode, because the IRC can be

switched on and off glitch-free.

7.15.5.4 Deep power-down mode

In Deep power-down mode, power is shut off to the entire chip with the exception of the

WAKEUP pin. The LPC112x can wake up from Deep power-down mode via the WAKEUP

pin.

A LOW-going pulse as short as 50 ns wakes up the part from Deep power-down mode.

When entering Deep power-down mode, an external pull-up resistor is required on the

WAKEUP pin to hold it HIGH. The RESET pin must also be held HIGH to prevent it from

floating while in Deep power-down mode.

7.16 System control

7.16.1 Start logic

The start logic connects external pins to corresponding interrupts in the NVIC. Each pin

shown in Table 3 as input to the start logic has an individual interrupt in the NVIC interrupt

vector table. The start logic pins can serve as external interrupt pins when the chip is

running. In addition, an input signal on the start logic pins can wake up the chip from

Deep-sleep mode when all clocks are shut down.

The start logic must be configured in the system configuration block and in the NVIC

before being used.

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7.16.2 Reset

32-bit ARM Cortex-M0 microcontroller

Reset has four sources on the LPC112x: the RESET pin, the Watchdog reset, Power-On

Reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt

trigger input pin. Assertion of chip reset by any source, once the operating voltage attains

a usable level, starts the IRC and initializes the flash controller.

A LOW-going pulse as short as 50 ns resets the part.

When the internal Reset is removed, the processor begins executing at address 0, which

is initially the Reset vector mapped from the boot block. At that point, all of the processor

and peripheral registers have been initialized to predetermined values.

An external pull-up resistor is required on the RESET pin if Deep power-down mode is

used.

7.16.3 Brownout detection

The LPC112x includes up to four levels for monitoring the voltage on the V_DDpin. If this

voltage falls below one of the selected levels, the BOD asserts an interrupt signal to the

NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC

in order to cause a CPU interrupt; if not, software can monitor the signal by reading a

dedicated status register. Four threshold levels can be selected to cause a forced reset of

the chip.

7.16.4 Code security (Code Read Protection - CRP)

This feature of the LPC112x allows user to enable different levels of security in the system

so that access to the on-chip flash and use of the Serial Wire Debugger (SWD) and

In-System Programming (ISP) can be restricted. When needed, CRP is invoked by

programming a specific pattern into a dedicated flash location. IAP commands are not

affected by the CRP.

In addition, ISP entry via the PIO0_1 pin can be disabled without enabling CRP. For

details see the LPC111x user manual.

There are three levels of Code Read Protection:

1. CRP1 disables access to the chip via the SWD and allows partial flash update

(excluding flash sector 0) using a limited set of the ISP commands. This mode is

useful when CRP is required and flash field updates are needed but all sectors can

not be erased.

2. CRP2 disables access to the chip via the SWD and only allows full flash erase and

update using a reduced set of the ISP commands.

3. Running an application with level CRP3 selected fully disables any access to the chip

via the SWD pins and the ISP. This mode effectively disables ISP override using

PIO0_1 pin, too. It is up to the user’s application to provide (if needed) flash update

mechanism using IAP calls or call reinvoke ISP command to enable flash update via

the UART.

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CAUTION

If level three Code Read Protection (CRP3) is selected, no future factory testing can be

performed on the device.

In addition to the three CRP levels, sampling of pin PIO0_1 for valid user code can be

disabled. For details see the LPC112x user manual.

7.16.5 APB interface

The APB peripherals are located on one APB bus.

7.16.6 AHBLite

The AHBLite connects the CPU bus of the ARM Cortex-M0 to the flash memory, the main

static RAM, and the Boot ROM.

7.16.7 External interrupt inputs

All GPIO pins can be level or edge sensitive interrupt inputs. In addition, start logic inputs

serve as external interrupts (see Section 7.16.1).

7.17 Emulation and debugging

Debug functions are integrated into the ARM Cortex-M0. Serial wire debug with four

breakpoints and two watchpoints is supported.

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8. Limiting values

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).^[1]

Symbol

V_DD

Parameter

Conditions

Min

0.5

Max

+4.6

+5.5

Unit

V

[2]

supply voltage (core and external rail)

analog supply voltage

reference voltage

V_DDA

V_ref

V

on pin VREFP

V

[5][2]

V_I

input voltage

5 V tolerant I/O

pins; only valid

when the V_DD

supply voltage is

present

V

[2][4]

5 V tolerant

open-drain pins

PIO0_4 and

PIO0_5

0.5

+5.5

4.6

V

[2]

[3]

V_IA

analog input voltage

pin configured as

analog input

I_DD

supply current

per supply pin

per ground pin

-

100

mA

I_SS

ground current

I/O latch-up current

I_latch

(0.5V_DD) < V_I<

(1.5V_DD);

T_j< 125 C

[6]

T_stg

storage temperature

non-operating

65

+150

150

1.5

C

W

T_j(max)

P_tot(pack)

maximum junction temperature

total power dissipation (per package)

-

based on package

heat transfer, not

device power

consumption

[7]

V_ESD

electrostatic discharge voltage

human body

+6500

V

model; all pins

[1] The following applies to the limiting values:

a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated

maximum.

b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V_SSunless

otherwise noted.

c) The limiting values are stress ratings only. Operating the part at these values is not recommended, and proper operation is not

guaranteed. The conditions for functional operation are specified in Table 6.

[2] Maximum/minimum voltage above the maximum operating voltage (see Table 6) and below ground that can be applied for a short time

(< 10 ms) to a device without leading to irrecoverable failure. Failure includes the loss of reliability and shorter lifetime of the device.

[3] See Table 6 for maximum operating voltage.

[4]

V

_DDpresent or not present. Compliant with the I²C-bus standard. 5.5 V can be applied to this pin when V_DDis powered down.

[5] Including voltage on outputs in 3-state mode.

[6] The maximum non-operating storage temperature is different than the temperature for required shelf life which should be determined

based on required shelf lifetime. Please refer to the JEDEC spec (J-STD-033B.1) for further details.

[7] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.

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9. Thermal characteristics

The average chip junction temperature, T_j(C), can be calculated using the following

equation:

T_j= T_amb+ P_D R_{thj – a}

(1)

• T_amb= ambient temperature (C)

• R_th(j-a)= the package junction-to-ambient thermal resistance (C/W)

• P_D= sum of internal and I/O power dissipation

The internal power dissipation is the product of I_DDand V_DD. The I/O power dissipation of

the I/O pins is often small and many times can be negligible. However it can be significant

in some applications.

Table 5.

LQFP48

ja

Thermal resistance value (C/W): ±15 %

JEDEC (4.5 in  4 in)

0 m/s

82.1

73.7

68.2

1 m/s

2.5 m/s

8-layer (4.5 in  3 in)

0 m/s

1 m/s

2.5 m/s

jc

115.2

94.7

86.3

29.6

34.2

jb

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10. Static characteristics

Table 6.

Static characteristics

T_amb= 40 C to +105 C, unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ^[1]

Max

Unit

V_DD

supply voltage (core

and external rail)

1.8

3.3

3.6

V

V_DDA

V_ref

analog supply voltage

2.4

3.3

-

3.6

V

reference voltage

on pin VREFP

V_DDA

Power consumption in low-current mode^[11]

I_DD

supply current

Active mode; code

while(1){}

executed from flash

system clock = 1 MHz

[2][3][5][6][7]

-

0.7

1.0

1.5

6.0

0.8

-

mA

V_DD= 3.3 V

[2][3][5]

[6][7]

system clock = 6 MHz

V_DD= 3.3 V

[2][3][4]

[6][7]

system clock = 12 MHz

V

_DD= 3.3 V

system clock = 50 MHz

_DD= 3.3 V

[2][3][6]

[7][8]

V

[2][3][4]

[6][7]

Sleep mode;

system clock = 12 MHz

V

_DD= 3.3 V

system clock = 50 MHz

_DD= 3.3 V

[2][3][4]

[6][7]

-

2.4

-

mA

V

[2][3][9]

I_DD

supply current

Deep-sleep mode;

V_DD= 3.3 V;

T_amb= 25 C

-

1.8

-

8

A

T_amb= 105 C

65

[2][10]

I_DD

Deep power-down mode;

V_DD= 3.3 V;

T

_amb= 25 C

-

220

-

900

3.5

nA

T_amb= 105 C

A

Standard port pins, RESET

I_IL

LOW-level input

current

V_I= 0 V; on-chip pull-up

resistor disabled

-

0.5

10^[17]

nA

I_IH

HIGH-level input

current

V_I= V_DD; on-chip

pull-down resistor

disabled

I_OZ

OFF-state output

current

V_O= 0 V; V_O= V_DD

on-chip pull-up/down

resistors disabled

;

-

0.5

-

10^[17]

5.0

nA

V

[12]

[14]

V_I

input voltage

pin configured to provide

a digital function;

V_DD 1.8 V

0

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Table 6.

Static characteristics …continued

T_amb= 40 C to +105 C, unless otherwise specified.

Symbol

Parameter

Conditions

VDD = 0 V

Min

Typ^[1]

Max

3.6

V_DD

-

Unit

V

0

-

V_O

output voltage

output active

0

V

V_IH

HIGH-level input

voltage

0.7 V_DD

V

V_IL

LOW-level input

voltage

-

0.3V_DD

V

V_hys

V_OH

hysteresis voltage

-

0.4

-

V

HIGH-level output

voltage

2.5 V  V_DD 3.6 V;

I_OH= 4 mA

V_DD 0.4

1.8 V  V_DD< 2.5 V;

I_OH= 3 mA

V_DD 0.4

-

V

V_OL

LOW-level output

voltage

2.5 V  V_DD 3.6 V;

-

0.4

-

V

I

_OL= 4 mA

1.8 V  V_DD< 2.5 V;

I_OL= 3 mA

-

V

I_OH

HIGH-level output

current

V_OH= V_DD 0.4 V;

1.8 V  V_DD 3.6 V

V_OL= 0.4 V

3

mA

I_OL

LOW-level output

current

3

-

mA

1.8 V  V_DD 3.6 V

V_OH= 0 V

[15]

I_OHS

HIGH-level

45

short-circuit output

current

I_OLS

LOW-level

V_OL= V_DD

-

50

mA

short-circuit output

current

I_pd

I_pu

pull-down current

pull-up current

V_I= 5 V

10

50

150

A

V_I= 0 V;

15

50

85

2.0 V  V_DD 3.6 V

1.8 V  V_DD< 2.0 V

V_DD< V_I< 5 V

10

50

85

A

0

High-drive output pin (PIO0_7)

I_IL

LOW-level input

current

V_I= 0 V; on-chip pull-up

resistor disabled

-

0.5

10^[17]

nA

I_IH

HIGH-level input

current

V_I= V_DD; on-chip

pull-down resistor

disabled

I_OZ

OFF-state output

current

V_O= 0 V; V_O= V_DD

on-chip pull-up/down

resistors disabled

;

-

0.5

-

10^[17]

5.0

nA

V

[12]

[14]

V_I

input voltage

pin configured to provide

a digital function;

V_DD 1.8 V

0

V

_DD= 0 V

0

-

3.6

V

V_O

output voltage

output active

V_DD

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Table 6.

Static characteristics …continued

T_amb= 40 C to +105 C, unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ^[1]

Max

Unit

V_IH

HIGH-level input

voltage

0.7V_DD

-

V

V_IL

LOW-level input

voltage

-

0.3V_DD

V

V_hys

V_OH

hysteresis voltage

0.4

-

V

HIGH-level output

voltage

2.5 V  V_DD 3.6 V;

I_OH= 20 mA

V_DD 0.5

1.8 V  V_DD< 2.5 V;

V_DD 0.5

-

V

I

_OH= 12 mA

2.5 V  V_DD 3.6 V;

_OL= 4 mA

V_OL

LOW-level output

voltage

-

0.4

-

V

I

1.8 V  V_DD< 2.5 V;

I_OL= 3 mA

-

V

I_OH

HIGH-level output

current

V_OH= V_DD 0.5 V;

2.5 V  V_DD 3.6 V

20

mA

1.8 V  V_DD< 2.5 V

V_OL= 0.4 V

12

4

-

mA

I_OL

LOW-level output

current

2.5 V  V_DD 3.6 V

1.8 V  V_DD< 2.5 V

V_OL= V_DD

3

-

mA

[15]

I_OLS

LOW-level

50

short-circuit output

current

I_pd

I_pu

pull-down current

pull-up current

V_I= 5 V

10

50

150

A

V_I= 0 V

15

50

85

2.0 V  V_DD 3.6 V

1.8 V  V_DD< 2.0 V

V_DD< V_I< 5 V

10

50

85

A

0

I²C-bus pins (PIO0_4 and PIO0_5)

V_IH

HIGH-level input

voltage

0.7V_DD

-

V

V_IL

LOW-level input

voltage

0.3V_DD

V_hys

I_OL

hysteresis voltage

-

0.05V_DD

-

V

LOW-level output

current

V_OL= 0.4 V; I²C-bus pins

configured as standard

mode pins

3.5

mA

2.5 V  V_DD 3.6 V

1.8 V  V_DD< 2.5 V

3

-

I_OL

LOW-level output

current

V_OL= 0.4 V; I²C-bus pins

configured as Fast-mode

Plus pins

20

mA

2.5 V  V_DD 3.6 V

1.8 V  V_DD< 2.5 V

16

-

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Table 6.

Static characteristics …continued

T_amb= 40 C to +105 C, unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ^[1]

2

Max

4

Unit

A

[16]

I_LI

input leakage current V_I= V_DD

V_I= 5 V

-

10

22

A

Oscillator pins

V_i(xtal)

crystal input voltage

crystal output voltage

0.5

1.8

1.95

V

V_o(xtal)

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Table 6.

Static characteristics …continued

T_amb= 40 C to +105 C, unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ^[1]

Max

Unit

Pin capacitance

C_io

input/output

capacitance

pins configured for analog

function

I²C-bus pins (PIO0_4 and

PIO0_5)

-

7.1

2.5

2.8

pF

pins configured as GPIO

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.

[2] _amb= 25 C.

T

[3] I_DDmeasurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled.

[4] IRC enabled; system oscillator disabled; system PLL disabled.

[5] System oscillator enabled; IRC disabled; system PLL disabled.

[6] BOD disabled.

[7] All peripherals disabled in the SYSAHBCLKCTRL register. Peripheral clocks to UART and SSP0/1 disabled in system configuration

block.

[8] IRC disabled; system oscillator enabled; system PLL enabled.

[9] All oscillators and analog blocks turned off in the PDSLEEPCFG register; PDSLEEPCFG = 0x0000 18FF.

[10] WAKEUP pin pulled HIGH externally.

[11] Low-current mode PWR_LOW_CURRENT selected when running the set_power routine in the power profiles.

[12] Including voltage on outputs in 3-state mode.

[13] V_DDsupply voltage must be present.

[14] 3-state outputs go into 3-state mode in Deep power-down mode.

[15] Allowed as long as the current limit does not exceed the maximum current allowed by the device.

[16] To V_SS

.

[17] Characterized on samples. Not tested in production.

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10.1 Power consumption

Power measurements in Active, Sleep, and Deep-sleep modes were performed under the

following conditions (see LPC112x user manual):

• Configure all pins as GPIO with pull-up resistor disabled in the IOCON block.

• Configure GPIO pins as outputs using the GPIOnDIR registers.

• Write 0 to all GPIOnDATA registers to drive the outputs LOW.

aaa-016554

7

48MHz

I

DD

36MHz

24MHz

12MHz

6MHz

(mA)

6

4

3

1

0

1MHz

-40

-10

20

50

80

110

Temperature (°C)

Conditions: V_DD= 3.3 V; active mode entered executing code while(1){} from flash; all

peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral

clocks disabled; internal pull-up resistors disabled; BOD disabled; low-current mode.

3 MHz - 6 MHz: system oscillator enabled; PLL, IRC disabled.

12 MHz: IRC enabled; system oscillator, PLL disabled.

24 MHz - 48 MHz: IRC disabled; system oscillator, PLL enabled.

Fig 5. Active mode: Typical supply current I_DDversus temperature for different system

clock frequencies

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aaa-016555

2.5

48MHz

I

DD

36MHz

24MHz

12MHz

6MHz

(mA)

2

1MHz

1.5

1

0.5

0

-40

-10

20

50

80

110

Temperature (°C)

Conditions: V_DD= 3.3 V; sleep mode entered from flash; all peripherals disabled in the

SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal

pull-up resistors disabled; BOD disabled; low-current mode.

3 MHz - 6 MHz: system oscillator enabled; PLL, IRC disabled.

12 MHz: IRC enabled; system oscillator, PLL disabled.

24 MHz - 48 MHz: IRC disabled; system oscillator, PLL enabled.

Fig 6. Sleep mode: Typical supply current I_DDversus temperature for different system

clock frequencies

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DDDꢀꢁꢂꢃꢃꢂꢃ

ꢄꢅ

ꢄꢂ

ꢃꢅ

ꢃꢂ

ꢅ

,

''

ꢈ$ꢉ

ꢊꢋꢌ9

ꢊꢋꢊ9

ꢃꢋꢆ9

ꢂ

ꢀꢁꢂ

ꢀꢃꢂ

ꢄꢂ

ꢅꢂ

ꢆꢂ

ꢃꢃꢂ

7HPSHUDWXUHꢇꢈ&ꢉ

Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register

(PDSLEEPCFG = 0x0000 18FF).

Fig 7. Deep-sleep mode: Typical supply current I_DDversus temperature for different

supply voltages V_DD

DDDꢀꢁꢂꢃꢃꢂꢄ

ꢃꢋꢄ

,

''

ꢈ$ꢉ

ꢂꢋꢍ

ꢂꢋꢌ

ꢂꢋꢊ

ꢂ

ꢊꢋꢌ9

ꢊꢋꢊ9

ꢃꢋꢆ9

ꢀꢁꢂ

ꢀꢃꢂ

ꢄꢂ

ꢅꢂ

ꢆꢂ

ꢃꢃꢂ

7HPSHUDWXUHꢇꢈ&ꢉ

Fig 8. Deep power-down mode: Typical supply current I_DDversus temperature for

different supply voltages V_DD

10.2 CoreMark data

Remark: All CoreMark data were taken with the Keil uVision v. 5.1.0 tool.

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aaa-016556

2

CM

((iterations/s)/MHz)

1.6

1.2

0.8

0.4

CPU performance

Efficiency

Default

Low Power

0

10

20

30

40

50

Frequency (MHz)

V_DD= 3.3 V; T = 25 °C; active mode; typical samples.

Fig 9. CoreMark score for different Power API modes

aaa-016557

12

I

DD

(mA)

10

8

Default

CPU performance

Efficiency

Low Power

6

4

2

0

10

20

30

40

Frequency (MHz)

50

V_DD= 3.3 V; T = 25 °C; active mode; typical samples. System oscillator enabled; main clock

derived from external clock signal; PLL and SYSAHBCLKDIV enabled for frequencies > 20 MHz.

Fig 10. CoreMark current consumption for different power modes using external clock

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10.3 Peripheral power consumption

The supply current per peripheral is measured as the difference in supply current between

the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG

and PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both

registers and no code is executed. Measured on a typical sample at T_amb= 25 C. Unless

noted otherwise, the system oscillator and PLL are running in both measurements.

The supply currents are shown for system clock frequencies of 12 MHz and 48 MHz.

Table 7.

Power consumption for individual analog and digital blocks

Peripheral

Typical supply current in

mA

Notes

n/a

12 MHz 48 MHz

IRC

0.212

-

System oscillator running; PLL off; independent

of main clock frequency.

System oscillator 0.1928

at 12 MHz

IRC running; PLL off; independent of main clock

frequency.

Watchdog

oscillator at

500 kHz/2

0.002

System oscillator running; PLL off; independent

of main clock frequency.

BOD

0.051

-

Independent of main clock frequency.

Main PLL

ADC

-

0.0686

0.0532 0.2074

CLKOUT

0.0104 0.0392 Main clock divided by 4 in the CLKOUTDIV

register.

CT16B0

CT16B1

CT32B0

CT32B1

GPIO

-

0.0266 0.1028

0.025

0.026

0.0956

0.0998

0.0246 0.0956

0.2252 0.8754 GPIO pins configured as outputs and set to

LOW. Direction and pin state are maintained if

the GPIO is disabled in the SYSAHBCLKCFG

register.

IOCON

I2C

-

0.0324 0.1262

0.0384 0.1484

ROM

0.017

0.0482 0.187

0.048 0.1862

0.0658

SSP0

SSP1

UART0

UART1

UART2

WWDT

0.0862 0.334

0.0836 0.3236

0.0818 0.3176

0.039

0.1964 Main clock selected as clock source for the

WDT.

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10.4 Electrical pin characteristics

aaa-013973

aaa-013974

1.8

OLH

3.5

V

OHL

(V)

V

(V)

1.7

1.6

1.5

1.4

1.3

1.2

3.2

2.9

2.6

2.3

2

-40 °CC

25 °CC

90 °CC

105 °CC

-40 °CC

25 °CC

90 °CC

105 °CC

0

4

8

12

16

20

24

0

20

40

60

OH

80

I

(mA)

I

(mA)

OH

Conditions: V_DD= 1.8 V; on pin PIO0_7.

Conditions: V_DD= 3.3 V; on pin PIO0_7.

Fig 11. High-drive output: Typical HIGH-level output voltage V_OHversus HIGH-level output current I_OH

aaa-013964

aaa-013972

40

30

20

10

0

60

45

30

15

0

I

OLL

(mA)

OLL

(mA)

-40 °CC

25 °CC

90 °CC

105 °CC

-40 °CC

25 °CC

90 °CC

105 °CC

0

0.1

0.2

0.3

0.4

0.5

(V)

0.6

0

0.1

0.2

0.3

0.4

0.5

(V)

0.6

V

OL

Conditions: V_DD= 1.8 V; on pins PIO0_4 and PIO0_5.

Conditions: V_DD= 3.3 V; on pins PIO0_4 and PIO0_5.

Fig 12. I²C-bus pins (high current sink): Typical LOW-level output current I_OLversus LOW-level output voltage

V_OL

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aaa-013975

aaa-013976

10

15

12

9

I

OLL

(mA)

OLL

(mA)

8

6

4

2

0

-40 °CC

25 °CC

90 °CC

105 °CC

-40 °CC

25 °CC

90 °CC

105 °CC

6

3

0

0.1

0.2

0.3

0.4

0.5

(V)

0.6

0

0.1

0.2

0.3

0.4

0.5

(V)

0.6

V

OL

Conditions: V_DD= 1.8 V; standard port pins and

high-drive pin PIO0_7.

Conditions: V_DD= 3.3 V; standard port pins and

high-drive pin PIO0_7.

Fig 13. Typical LOW-level output current I_OLversus LOW-level output voltage V_OL

aaa-013977

aaa-013978

1.8

OHH

3.5

-40 °CC

25 °CC

90 °CC

105 °CC

V

(V)

V

OHH

(V)

1.7

1.6

1.5

1.4

1.3

1.2

3.2

2.9

2.6

2.3

2

-40 °CC

25 °CC

90 °CC

105 °CC

0

1.5

3

4.5

OH

6

0

8

16

24

I

(mA)

I

(mA)

OH

Conditions: V_DD= 1.8 V; standard port pins.

Conditions: V_DD= 3.3 V; standard port pins.

Fig 14. Typical HIGH-level output voltage V_OHversus HIGH-level output source current I_OH

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aaa-013979

aaa-013980

0

I

pu

(μuAA))

pu

(uμAA))

-14

-28

-42

-56

-70

-4

-8

-40 °CC

105 °CC

90 °CC

25 °CC

105 °CC

-40 °CC

90 °CC

25 °CC

-12

-16

0

0.7

1.4

2.1

2.8

V (V)

3.5

0

1

2

3

4

5

V (V)

I

Conditions: V_DD= 1.8 V; standard port pins.

Conditions: V_DD= 3.3 V; standard port pins.

Fig 15. Typical pull-up current I_PUversus input voltage V_I

aaa-013981

aaa-013982

35

80

60

40

20

0

I

pd

(μuAA))

puud

(uμAA))

28

21

14

7

-40 °CC

25 °CC

90 °CC

105 °CC

-40 °CC

25 °CC

90 °CC

105 °CC

0

0.7

1.4

2.1

2.8

3.5

0

1

2

3

4

5

V (V)

I

Conditions: V_DD= 1.8 V; standard port pins.

Conditions: V_DD= 3.3 V; standard port pins.

Fig 16. Typical pull-down current I_PDversus input voltage V_I

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11. Dynamic characteristics

11.1 Flash memory

Table 8.

Flash characteristics

T_amb= 40 C to +105 C, unless otherwise specified.

Symbol

N_endu

t_ret

Parameter

endurance

Conditions

Min

10000

10

Typ

Max

Unit

[1]

100000

-

cycles

years

ms

retention time

powered

-

unpowered

20

-

t_er

erase time

sector or multiple

consecutive

sectors

95

100

105

[2]

t_prog

programming

time

0.95

1

1.05

ms

[1] Number of program/erase cycles.

[2] Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash

in blocks of 256 bytes.

11.2 External clock

Table 9.

Dynamic characteristic: external clock

T_amb= 40 C to +105 C; V_DDover specified ranges.^[1]

Symbol

f_osc

Parameter

Min

Typ^[2]

Max

Unit

MHz

ns

oscillator frequency

clock cycle time

clock HIGH time

clock LOW time

clock rise time

clock fall time

1

-

25

T_cy(clk)

t_CHCX

t_CLCX

t_CLCH

t_CHCL

40

1000

T_cy(clk) 0.4

-

ns

T_cy(clk) 0.4

-

ns

-

5

ns

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply

voltages.

t

CHCX

t

CHCL

CLCX

CLCH

T

cy(clk)

002aaa907

Fig 17. External clock timing (with an amplitude of at least V_i(RMS)= 200 mV)

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11.3 Internal oscillators

Table 10. Dynamic characteristics: IRC

T_amb= 40 C to +105 C; 2.7 V  V_DD 3.6 V^[1]

.

Symbol Parameter

Conditions

Min

Typ^[2]Max

12 12 + 1 %

12 + 1 %

Unit

MHz

f_osc(RC)

internal RC oscilla- 25 C  T_amb +85 C 12 - 1 %

tor frequency

40 C  T_amb< 25 C 12 - 2.5 % 12

85 C < T_amb 105 C 12 - 1.5 % 12

12 + 1.5 % MHz

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are for room temperature (25 C), nominal supply

voltages.

DDDꢀꢁꢂꢁꢁꢅꢆ

ꢃꢄꢋꢃꢅ

I

ꢊꢋꢌꢇ9

ꢈ0+]ꢉ

ꢊꢋꢊꢇ9

ꢊꢋꢂꢇ9

ꢄꢋꢎꢇ9

ꢃꢄꢋꢂꢆ

ꢃꢄ

ꢃꢃꢋꢍꢊ

ꢃꢃꢋꢆꢅ

ꢀꢁꢂ

ꢀꢃꢂ

ꢄꢂ

ꢅꢂ

ꢆꢂ

ꢃꢃꢂ

WHPSHUDWXUHꢇꢈ&ꢉ

Conditions: Frequency values are typical values. 12 MHz  1 % accuracy is guaranteed for

2.7 V  V_DD 3.6 V and T_amb= 25 C to +85 C. Variations between parts may cause the IRC to

fall outside the 12 MHz  1 % accuracy specification for voltages below 2.7 V.

Fig 18. Typical Internal RC oscillator frequency versus temperature

Table 11. Dynamic characteristics: WatchDog oscillator

Symbol Parameter

Conditions

Min Typ^[1]Max Unit

[2][3]

f_osc(int)internal oscillator DIVSEL = 0x1F, FREQSEL = 0x1

-

9.4

-

kHz

frequency

in the WDTOSCCTRL register;

DIVSEL = 0x00, FREQSEL = 0xF

in the WDTOSCCTRL register

-

2300

-

kHz

[1] Typical ratings are not guaranteed. The values listed are at nominal supply voltages.

[2] The typical frequency spread over processing and temperature (T_amb= 40 C to +105 C) is 40 %.

[3] See the LPC112x user manual.

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11.4 I/O pins

Table 12. Dynamic characteristic: I/O pins^[1]

T_amb= 40 C to +105 C; 3.0 V  V_DD 3.6 V.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

t_r

rise time

pin configured 3.0

as output

-

5.0

ns

t_f

fall time

pin configured 2.5

as output

-

5.0

ns

[1] Applies to standard port pins and RESET pin.

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11.5 I²C-bus

Table 13. Dynamic characteristic: I²C-bus pins^[1]

T_amb= 40 C to +105 C.^[2]

Symbol

Parameter

Conditions

Min

Max

100

400

1

Unit

kHz

MHz

ns

f_SCL

SCL clock

frequency

Standard-mode

Fast-mode

0

-

Fast-mode Plus

[4][5][6][7]

t_f

fall time

of both SDA and

SCL signals

300

Standard-mode

Fast-mode

20 + 0.1  C_b300

ns

s

ns

Fast-mode Plus

Standard-mode

Fast-mode

-

120

t_LOW

LOW period of

the SCL clock

4.7

1.3

0.5

4.0

0.6

0.26

0

-

Fast-mode Plus

Standard-mode

Fast-mode

t_HIGH

HIGH period of

the SCL clock

Fast-mode Plus

Standard-mode

Fast-mode

[3][4][8]

[9][10]

t_HD;DAT

data hold time

0

Fast-mode Plus

Standard-mode

Fast-mode

0

t_SU;DAT

data set-up

time

250

100

50

Fast-mode Plus

[1] See the I²C-bus specification UM10204 for details.

[2] Parameters are valid over operating temperature range unless otherwise specified.

[3] _HD;DATis the data hold time that is measured from the falling edge of SCL; applies to data in transmission

and the acknowledge.

t

[4] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the

V_IH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL.

[5] C_b= total capacitance of one bus line in pF.

[6] The maximum t_ffor the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA

output stage t_fis specified at 250 ns. This allows series protection resistors to be connected in between the

SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified t_f.

[7] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors

are used, designers should allow for this when considering bus timing.

[8] The maximum t_HD;DATcould be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than

the maximum of t_VD;DATor t_VD;ACKby a transition time (see UM10204). This maximum must only be met if

the device does not stretch the LOW period (t_LOW) of the SCL signal. If the clock stretches the SCL, the

data must be valid by the set-up time before it releases the clock.

[9]

t

_SU;DATis the data set-up time that is measured with respect to the rising edge of SCL; applies to data in

transmission and the acknowledge.

[10] A Fast-mode I²C-bus device can be used in a Standard-mode I²C-bus system but the requirement

_SU;DAT= 250 ns must then be met. This will automatically be the case if the device does not stretch the

t

LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must

output the next data bit to the SDA line t_r(max)+ t_SU;DAT= 1000 + 250 = 1250 ns (according to the

Standard-mode I²C-bus specification) before the SCL line is released. Also the acknowledge timing must

meet this set-up time.

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t

f

t

SU;DAT

70 %

30 %

70 %

30 %

SDA

SCL

t

HD;DAT

VD;DAT

t

f

t

HIGH

70 %

30 %

70 %

30 %

70 %

30 %

70 %

30 %

t

LOW

1 / f

S

SCL

002aaf425

Fig 19. I²C-bus pins clock timing

11.6 SSP interfaces

Table 14. Dynamic characteristics of SSP pins in SPI mode

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

SSP master (in SPI mode)

[1]

[2]

T_cy(clk)

clock cycle time

data set-up time

full-duplex mode

when only transmitting

in SPI mode

50

40

20

-

ns

t_DS

2.4 V  V_DD 3.6 V

2.0 V  V_DD< 2.4 V

1.8 V  V_DD< 2.0 V

in SPI mode

[2]

25

29

0

ns

-

t_DH

data hold time

-

t_v(Q)

t_h(Q)

data output valid time in SPI mode

data output hold time in SPI mode

-

10

-

0

SSP slave (in SPI mode)

T_cy(PCLK)PCLK cycle time

20

0

-

ns

[3][4]

t_DS

data set-up time

data hold time

in SPI mode

-

t_DH

3  T_cy(PCLK)+ 4

-

t_v(Q)

t_h(Q)

data output valid time in SPI mode

data output hold time in SPI mode

-

3  T_cy(PCLK)+ 11

2  T_cy(PCLK)+ 5

[1] T_cy(clk)= (SSPCLKDIV  (1 + SCR)  CPSDVSR) / f_main. The clock cycle time derived from the SSP bit rate T_cy(clk)is a function of the

main clock frequency f_main, the SSP peripheral clock divider (SSPCLKDIV), the SSP SCR parameter (specified in the SSP0CR0

register), and the SSP CPSDVSR parameter (specified in the SSP clock prescale register).

[2] T_amb= 40 C to 105 C.

[3]

T_cy(clk)= 12  T_cy(PCLK).

[4] T_amb= 25 C; for normal voltage supply range: V_DD= 3.3 V.

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T

cy(clk)

SCK (CPOL = 0)

SCK (CPOL = 1)

MOSI

t

h(Q)

v(Q)

DATA VALID

CPHA = 1

t

DH

DS

DATA VALID

MISO

t

h(Q)

v(Q)

DATA VALID

t

MOSI

MISO

t

CPHA = 0

DS

DH

DATA VALID

002aae829

Pin names SCK, MISO, and MOSI refer to pins for both SSP peripherals, SSP0 and SSP1.

Fig 20. SSP master timing in SPI mode

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T

cy(clk)

SCK (CPOL = 0)

SCK (CPOL = 1)

t

DH

DS

MOSI

MISO

DATA VALID

t

h(Q)

v(Q)

CPHA = 1

DATA VALID

t

DH

DS

MOSI

MISO

DATA VALID

t

h(Q)

CPHA = 0

v(Q)

DATA VALID

002aae830

Pin names SCK, MISO, and MOSI refer to pins for both SSP peripherals, SSP0 and SSP1.

Fig 21. SSP slave timing in SPI mode

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12. Analog characteristics

12.1 BOD static characteristics

Table 15. BOD static characteristics^[1]

T_amb= 25 C.

Symbol Parameter

V_ththreshold voltage

Conditions

Min

Typ

Max

Unit

interrupt level 1

assertion

-

2.22

2.35

-

V

de-assertion

interrupt level 2

assertion

-

2.52

2.66

-

V

de-assertion

interrupt level 3

assertion

-

2.80

2.90

-

V

de-assertion

reset level 0

assertion

-

1.46

1.63

-

V

de-assertion

reset level 1

assertion

-

2.06

2.15

-

V

de-assertion

reset level 2

assertion

-

2.35

2.43

-

V

de-assertion

reset level 3

assertion

-

2.63

2.71

-

V

de-assertion

[1] Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see LPC111x

user manual.

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12.2 12-bit ADC

Table 16. 12-bit ADC static characteristics

T_amb= 40 C to +105 C; V_DD= 2.4 V to 3.6 V; VREFP = V_DDA; V_SSA= 0; VREFN = V_SSA

.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

[1]

V_IA

analog input voltage

0

-

V_DDA

V

C_ia

analog input capacitance

ADC clock frequency

2.5

50

25

2

1

-

pF

[8]

[9]

[8]

[9]

[2]

[3]

[4]

[5]

f_clk(ADC)

V_DDA2.7 V

V_DDA2.4 V

V_DDA2.7 V

V_DDA2.4 V

MHz

f_s

sampling frequency

-

Msamples/s

LSB

E_D

differential linearity error

integral non-linearity

offset error

+/- 2

E_L(adj)

E_O

+/- 2

-

LSB

+/- 3

-

LSB

V_err(fs)

full-scale error voltage

2 Msamples/s

1 Msamples/s

f_s= 2 Msamples/s

+/- 0.12

+/- 0.07

-

%

-

%

[6][7]

Z_i

input impedance

0.1

-

M

[1] The input resistance of ADC channel 0 is higher than for all other channels.

[2] The differential linearity error (E_D) is the difference between the actual step width and the ideal step width.

See Figure 22.

[3] The integral non-linearity (E_L(adj)) is the peak difference between the center of the steps of the actual and

the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 22.

[4] The offset error (E_O) is the absolute difference between the straight line which fits the actual curve and the

straight line which fits the ideal curve. See Figure 22.

[5] The full-scale error voltage or gain error (E_G) is the difference between the straight line fitting the actual

transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. See

Figure 22.

[6] T_amb= 25 C; maximum sampling frequency f_s= 2 Msamples/s and analog input capacitance C_ia= 0.32 pF.

[7] Input impedance Z_iis inversely proportional to the sampling frequency and the total input capacity including

C_iaand C_io: Z_i 1 / (f_s C_i). See Table 6 for C_io.

[8] In the ADC TRM register, set VRANGE = 0 (default).

[9] In the ADC TRM register, set VRANGE = 1.

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offset

error

O

gain

error

E

G

4095

4094

4093

4092

4091

4090

(2)

7

code

out

(1)

6

5

4

3

2

1

0

(5)

(4)

(3)

1 LSB

(ideal)

4090 4091 4092 4093 4094 4095 4096

1

2

3

4

5

6

7

V

IA

(LSB

)

ideal

offset error

E

O

VREFP - VREFN

1 LSB =

4096

aaa-016908

(1) Example of an actual transfer curve.

(2) The ideal transfer curve.

(3) Differential linearity error (E_D).

(4) Integral non-linearity (E_L(adj)).

(5) Center of a step of the actual transfer curve.

Fig 22. 12-bit ADC characteristics

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ADC

R

= 0.25 kΩ...2.5 kΩ

ADCn_0

1

C

io

R

= 5 Ω...25 Ω

sw

ADCn_[1:11]

DAC

C

ia

C

io

aaa-016869

Fig 23. ADC input impedance

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13. Application information

13.1 ADC usage notes

The following guidelines show how to increase the performance of the ADC in a noisy

environment beyond the ADC specifications listed in Table 6:

• The ADC input trace must be short and as close as possible to the LPC112x chip.

• The ADC input traces must be shielded from fast switching digital signals and noisy

power supply lines.

• Because the ADC and the digital core share the same power supply, the power supply

line must be adequately filtered.

• To improve the ADC performance in a very noisy environment, put the device in Sleep

mode during the ADC conversion.

13.2 XTAL input

The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a

clock in slave mode, it is recommended that the input be coupled through a capacitor with

C_i= 100 pF. To limit the input voltage to the specified range, choose an additional

capacitor to ground C_gwhich attenuates the input voltage by a factor C_i/(C_i+ C_g). In slave

mode, a minimum of 200 mV (RMS) is needed.

LPC1xxx

XTALIN

C

i

C

g

100 pF

002aae788

Fig 24. Slave mode operation of the on-chip oscillator

In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF

(Figure 24), with an amplitude between 200 mV (RMS) and 1000 mV (RMS). This

corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V.

The XTALOUT pin in this configuration can be left unconnected.

External components and models used in oscillation mode are shown in Figure 25 and in

Table 17 and Table 18. Since the feedback resistance is integrated on chip, only a crystal

and the capacitances C_X1and C_X2need to be connected externally in case of

fundamental mode oscillation (the fundamental frequency is represented by L, C_Land

R_S). Capacitance C_Pin Figure 25 represents the parallel package capacitance and should

not be larger than 7 pF. Parameters F_OSC, C_L, R_Sand C_Pare supplied by the crystal

manufacturer (see Table 17).

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LPC1xxx

L

XTALIN

XTALOUT

C

L

C

P

=

XTAL

R

S

C

X2

C

X1

002aaf424

Fig 25. Oscillator modes and models: oscillation mode of operation and external crystal

model used for C_X1/C_X2evaluation

Table 17. Recommended values for C_X1/C_X2in oscillation mode (crystal and external

components parameters) low frequency mode

Fundamental oscillation Crystal load

Maximum crystal

External load

frequency F_OSC

capacitance C_L

series resistance R_S

capacitors C_X1, C_X2

1 MHz to 5 MHz

10 pF

< 300 

< 200 

< 100 

< 160 

< 60 

18 pF, 18 pF

39 pF, 39 pF

57 pF, 57 pF

18 pF, 18 pF

39 pF, 39 pF

57 pF, 57 pF

18 pF, 18 pF

39 pF, 39 pF

18 pF, 18 pF

20 pF

30 pF

5 MHz to 10 MHz

10 pF

20 pF

30 pF

10 MHz to 15 MHz

15 MHz to 20 MHz

10 pF

20 pF

10 pF

< 80 

Table 18. Recommended values for C_X1/C_X2in oscillation mode (crystal and external

components parameters) high frequency mode

Fundamental oscillation Crystal load

Maximum crystal

External load

frequency F_OSC

capacitance C_L

series resistance R_S

capacitors C_X1, C_X2

15 MHz to 20 MHz

10 pF

< 180 

< 100 

< 160 

< 80 

18 pF, 18 pF

39 pF, 39 pF

18 pF, 18 pF

39 pF, 39 pF

20 pF

20 MHz to 25 MHz

10 pF

20 pF

13.3 XTAL Printed Circuit Board (PCB) layout guidelines

The crystal should be connected on the PCB as close as possible to the oscillator input

and output pins of the chip. Take care that the load capacitors C_X1, C_X2, and C_X3in case

of third overtone crystal usage have a common ground plane. The external components

must also be connected to the ground plain. Loops must be made as small as possible in

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order to keep the noise coupled in via the PCB as small as possible. Also parasitics

should stay as small as possible. Values of C_X1and C_X2should be chosen smaller

accordingly to the increase in parasitics of the PCB layout.

13.4 Connecting power, clocks, and debug functions

Figure 26 shows the basic board connections used to power the LPC112x and provide

debug capabilities via the serial wire port.

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3.3 V

SWD connector

Note 4

3.3 V

~10 kΩ - 100 kΩ

SWDIO/PIO1_3

SWCLK/PIO0_10

1

2

4

3

5

7

XTALIN

~10 kΩ - 100 kΩ

n.c.

6

8

C1

Note 1

n.c.

DGND

C2

XTALOUT

RESET/PIO0_0

DGND

9

10

V

SS

DGND

Note 2

3.3 V

V

(2 pins)

DD

V

SSA

LPC112x

0.1 μF

0.01 μF

AGND

DGND

PIO0_1

ISP select pin

Note 5

ADC_0

Note 3

3.3 V

VREFP

0.1 μF

10 μF

0.1 μF

VREFN

AGND

DGND

aaa-014718

(1) See Section 13.2 “XTAL input” for the values of C1 and C2.

(2) Position the decoupling capacitors of 0.1 μF and 0.01 μF as close as possible to the V_DDpin. Add one set of decoupling

capacitors to each V_DDpin.

(3) Position the decoupling capacitors of 0.1 μF as close as possible to the VREFN and V_DDpins. The 10 μF bypass capacitor

filters the power line. Tie VREFP to V_DDif the ADC is not used. Tie VREFN to V_SSif ADC is not used.

(4) Uses the ARM 10-pin interface for SWD.

(5) When measuring signals of low frequency, use a low-pass filter to remove noise and to improve ADC performance. Also see

Ref. 4.

Fig 26. Power, clock, and debug connections

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13.5 Termination of unused pins

Table 19 shows how to terminate pins that are not used in the application. In many cases,

unused pins may should be connected externally or configured correctly by software to

minimize the overall power consumption of the part.

Unused pins with GPIO function should be configured as outputs set to LOW with their

internal pull-up disabled. To configure a GPIO pin as output and drive it LOW, select the

GPIO function in the IOCON register, select output in the GPIO DIR register, and write a 0

to the GPIO PORT register for that pin. Disable the pull-up in the pin’s IOCON register.

In addition, it is recommended to configure all GPIO pins that are not bonded out on

smaller packages as outputs driven LOW with their internal pull-up disabled.

Table 19. Termination of unused pins

Default Recommended termination of unused pins

state^[1]

RESET/PIO0_0

I; PU

In an application that does not use the RESET pin or its GPIO function, the

termination of this pin depends on whether Deep power-down mode is used:

• Deep power-down used: Connect an external pull-up resistor and keep pin in

default state (input, pull-up enabled) during all other power modes.

• Deep power-down not used and no external pull-up connected: can be left

unconnected if internal pull-up is disabled and pin is driven LOW and

configured as output by software.

all PIOn_m (not

open-drain)

I; PU

Can be left unconnected if driven LOW and configured as GPIO output with pull-up

disabled by software.

PIOn_m (I2C open-drain)

VREFP

IA

-

Can be left unconnected if driven LOW and configured as GPIO output by software.

Tie to VDD.

Tie to VSS.

VREFN

-

[1] I = Input, O = Output, IA = Inactive (no pull-up/pull-down enabled), F = floating, PU = Pull-Up.

13.6 Pin states in different power modes

Table 20. Pin states in different power modes

Active

Sleep

Deep-sleep/Power- Deep power-down

down

PIOn_m pins (not As configured in the IOCON^[1]. Default: internal pull-up

I2C) enabled.

Floating.

PIO0_4, PIO0_5 As configured in the IOCON^[1].

Floating.

(open-drain

I2C-bus pins)

RESET

Reset function enabled. Default: input, internal pull-up

enabled.

Reset function disabled; floating; if the part

is in deep power-down mode, the RESET

pin needs an external pull-up to reduce

power consumption.

PIO1_4/

WAKEUP

As configured in the IOCON^[1]. WAKEUP function inactive. Wake-up function enabled; can be disabled

by software.

[1] Default and programmed pin states are retained in sleep, deep-sleep, and power-down modes.

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13.7 Standard I/O pad configuration

Figure 27 shows the possible pin modes for standard I/O pins with analog input function:

• Digital output driver.

• Digital input: Pull-up enabled/disabled.

• Digital input: Pull-down enabled/disabled.

• Digital input: Repeater mode enabled/disabled.

• Digital output: Pseudo open-drain mode enable/disabled.

• Analog input.

V

DD

V

DD

open-drain enable

output enable

data output

strong

pull-up

ESD

pin configured

as digital output

driver

strong

pull-down

ESD

V

SS

V

DD

weak

pull-up

pull-up enable

weak

pull-down

repeater mode

enable

pin configured

as digital input

pull-down enable

data input

select analog input

pin configured

as analog input

analog input

002aah159

Fig 27. Standard I/O pad configuration

LPC112x

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Product data sheet

Rev. 1. — 24 February 2015

54 of 63

LPC112x

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

13.8 Reset pad configuration

V

DD

V

DD

V

DD

R

pu

ESD

20 ns RC

GLITCH FILTER

reset

ESD

V

SS

002aaf274

Fig 28. Reset pad configuration

LPC112x

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Product data sheet

Rev. 1. — 24 February 2015

55 of 63

LPC112x

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

14. Package outline

LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm

SOT313-2

c

y

X

36

25

A

E

37

24

Z

E

e

H

E

A

2

A

(A )

3

A

1

w M

p

θ

pin 1 index

b

L

p

L

13

48

detail X

1

12

Z

v M

D

A

e

w M

b

p

D

B

H

v

M

B

D

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

D

H

L

v

w

y

Z

E

θ

1

2

3

p

E

p

D

max.

7^o

0^o

0.20 1.45

0.05 1.35

0.27 0.18 7.1

0.17 0.12 6.9

7.1

6.9

9.15 9.15

8.85 8.85

0.75

0.45

0.95 0.95

0.55 0.55

1.6

mm

0.25

0.5

1

0.2 0.12 0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

00-01-19

03-02-25

SOT313-2

136E05

MS-026

Fig 29. LQFP48 package outline

LPC112x

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Product data sheet

Rev. 1. — 24 February 2015

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LPC112x

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

15. Soldering

Footprint information for reflow soldering of LQFP48 package

SOT313-2

Hx

Gx

(0.125)

P2

P1

Hy Gy

By

Ay

C

D2 (8×)

D1

Bx

Ax

Generic footprint pattern

Refer to the package outline drawing for actual layout

solder land

occupied area

DIMENSIONS in mm

P1 P2 Ax

Ay

Bx

By

C

D1

D2

Gx

Gy

Hx

Hy

0.500 0.560 10.350 10.350 7.350 7.350 1.500 0.280 0.500 7.500 7.500 10.650 10.650

sot313-2_fr

Fig 30. Reflow soldering of the LQFP48 package

LPC112x

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Product data sheet

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NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

16. Abbreviations

Table 21. Abbreviations

Acronym

ADC

AHB

APB

BOD

GPIO

PLL

Description

Analog-to-Digital Converter

Advanced High-performance Bus

Advanced Peripheral Bus

BrownOut Detection

General Purpose Input/Output

Phase-Locked Loop

RC

Resistor-Capacitor

SPI

Serial Peripheral Interface

Serial Synchronous Interface

Synchronous Serial Port

Transverse ElectroMagnetic

SSI

SSP

TEM

UART

Universal Asynchronous Receiver/Transmitter

17. References

[1] User manual UM10839.

[2] Errata sheet ES_LPC112x.

[3] I2C-bus specification UM10204.

[4] Technical note ADC design guidelines:

http://www.nxp.com/documents/technical_note/TN00009.pdf

LPC112x

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Product data sheet

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LPC112x

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

18. Revision history

Table 22. Revision history

Document ID

Release date

Data sheet status

Change notice Supersedes

LPC112x v.1.0

20150224

Product data sheet

-

LPC112x

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Product data sheet

Rev. 1. — 24 February 2015

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LPC112x

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

19. Legal information

19.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

Suitability for use — NXP Semiconductors products are not designed,

19.2 Definitions

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer’s own

risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

19.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

LPC112x

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Product data sheet

Rev. 1. — 24 February 2015

60 of 63

LPC112x

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

19.4 Trademarks

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

I²C-bus — logo is a trademark of NXP Semiconductors N.V.

20. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

LPC112x

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Product data sheet

Rev. 1. — 24 February 2015

61 of 63

LPC112x

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

21. Contents

1

General description. . . . . . . . . . . . . . . . . . . . . . 1

7.15.5.3 Deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 20

7.15.5.4 Deep power-down mode . . . . . . . . . . . . . . . . 20

2

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 3

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

7.16

System control . . . . . . . . . . . . . . . . . . . . . . . . 20

Start logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Brownout detection . . . . . . . . . . . . . . . . . . . . 21

Code security

3

7.16.1

7.16.2

7.16.3

7.16.4

4

4.1

5

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6

(Code Read Protection - CRP) . . . . . . . . . . . 21

APB interface. . . . . . . . . . . . . . . . . . . . . . . . . 22

AHBLite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

External interrupt inputs. . . . . . . . . . . . . . . . . 22

Emulation and debugging . . . . . . . . . . . . . . . 22

7.16.5

7.16.6

7.16.7

7.17

7

Functional description . . . . . . . . . . . . . . . . . . 11

ARM Cortex-M0 processor. . . . . . . . . . . . . . . 11

On-chip flash program memory . . . . . . . . . . . 11

On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 11

Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 11

Nested Vectored Interrupt Controller

(NVIC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 13

IOCON block . . . . . . . . . . . . . . . . . . . . . . . . . 13

Fast general purpose parallel I/O . . . . . . . . . . 13

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

SSP controller. . . . . . . . . . . . . . . . . . . . . . . . . 14

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

I²C-bus serial I/O controller . . . . . . . . . . . . . . 14

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Analog-to-Digital Converter

(ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

General purpose external event

counter/timers. . . . . . . . . . . . . . . . . . . . . . . . . 16

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

System tick timer . . . . . . . . . . . . . . . . . . . . . . 16

Windowed WatchDog Timer . . . . . . . . . . . . . 16

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Clocking and power control . . . . . . . . . . . . . . 17

Crystal oscillators . . . . . . . . . . . . . . . . . . . . . . 17

7.1

7.2

7.3

7.4

7.5

8

9

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 23

Thermal characteristics . . . . . . . . . . . . . . . . . 24

10

Static characteristics . . . . . . . . . . . . . . . . . . . 25

Power consumption . . . . . . . . . . . . . . . . . . . 30

CoreMark data . . . . . . . . . . . . . . . . . . . . . . . . 32

Peripheral power consumption . . . . . . . . . . . 34

Electrical pin characteristics. . . . . . . . . . . . . . 35

10.1

10.2

10.3

10.4

7.5.1

7.5.2

7.6

7.7

7.7.1

7.8

7.8.1

7.9

7.9.1

7.10

7.10.1

7.11

11

Dynamic characteristics. . . . . . . . . . . . . . . . . 38

Flash memory . . . . . . . . . . . . . . . . . . . . . . . . 38

External clock. . . . . . . . . . . . . . . . . . . . . . . . . 38

Internal oscillators . . . . . . . . . . . . . . . . . . . . . 39

I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

I²C-bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

SSP interfaces . . . . . . . . . . . . . . . . . . . . . . . . 42

11.1

11.2

11.3

11.4

11.5

11.6

12

12.1

12.2

Analog characteristics . . . . . . . . . . . . . . . . . . 45

BOD static characteristics . . . . . . . . . . . . . . . 45

12-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

7.11.1

7.12

13

Application information . . . . . . . . . . . . . . . . . 49

ADC usage notes. . . . . . . . . . . . . . . . . . . . . . 49

XTAL input . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

XTAL Printed Circuit Board (PCB) layout

guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Connecting power, clocks, and debug

functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Termination of unused pins . . . . . . . . . . . . . . 53

Pin states in different power modes. . . . . . . . 53

Standard I/O pad configuration . . . . . . . . . . . 54

Reset pad configuration. . . . . . . . . . . . . . . . . 55

13.1

13.2

13.3

7.12.1

7.13

7.14

7.14.1

7.15

7.15.1

13.4

13.5

13.6

13.7

13.8

7.15.1.1 Internal RC oscillator . . . . . . . . . . . . . . . . . . . 18

7.15.1.2 System oscillator . . . . . . . . . . . . . . . . . . . . . . 18

7.15.1.3 Watchdog oscillator . . . . . . . . . . . . . . . . . . . . 19

7.15.2

7.15.3

7.15.4

7.15.5

14

15

16

17

18

Package outline. . . . . . . . . . . . . . . . . . . . . . . . 56

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 58

References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Revision history . . . . . . . . . . . . . . . . . . . . . . . 59

System PLL . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Wake-up process . . . . . . . . . . . . . . . . . . . . . . 19

Power control . . . . . . . . . . . . . . . . . . . . . . . . . 19

7.15.5.1 Power profiles . . . . . . . . . . . . . . . . . . . . . . . . 19

7.15.5.2 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 20

continued >>

LPC112x

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Product data sheet

Rev. 1. — 24 February 2015

62 of 63

LPC112x

NXP Semiconductors

32-bit ARM Cortex-M0 microcontroller

19

Legal information. . . . . . . . . . . . . . . . . . . . . . . 60

19.1

19.2

19.3

19.4

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 60

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 61

20

21

Contact information. . . . . . . . . . . . . . . . . . . . . 61

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 24 February 2015

Document identifier: LPC112x


型号：	LPC1124JBD48/303
厂家：	NXP
描述：	32-bit ARM Cortex-M0 microcontroller; 64 kB flash and 8 kB SRAM; 12-bit ADC 静态存储器
文件：	总63页 (文件大小：1445K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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