LPC11A14FBD48/301 [NXP]
IC 32-BIT, FLASH, 50 MHz, RISC MICROCONTROLLER, PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT313-2, LQFP-48, Microcontroller;
| 型号： | LPC11A14FBD48/301 |
| 厂家： | 
NXP |
| 描述： | IC 32-BIT, FLASH, 50 MHz, RISC MICROCONTROLLER, PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT313-2, LQFP-48, Microcontroller 微控制器 |
| 文件： | 总84页 (文件大小：1761K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LPC11Axx
32-bit ARM Cortex-M0 microcontroller; up to 32 kB flash, 8 kB
SRAM, 4 kB EEPROM; configurable analog/mixed-signal
Rev. 4 — 30 October 2012
Product data sheet
1. General description
The LPC11Axx are an ARM Cortex-M0 based, low-cost 32-bit MCU family, designed for
8/16-bit microcontroller applications, offering performance, low power, simple instruction
set and memory addressing together with reduced code size compared to existing 8/16-bit
architectures.
The LPC11Axx operate at CPU frequencies of up to 50 MHz.
Analog/mixed-signal subsystems can be configured by software from interconnected
digital and analog peripherals.
The digital peripherals on the LPC11Axx include up to 32 kB of flash memory, up to 4 kB
of EEPROM data memory, up to 8 kB of SRAM data memory, a Fast-mode Plus I2C-bus
interface, a RS-485/EIA-485 USART, two SSP controllers, four general purpose
counter/timers, and up to 42 general purpose I/O pins.
Analog peripherals include a 10-bit ADC, a 10-bit DAC, an analog comparator, a
temperature sensor, an internal voltage reference, and UnderVoltage LockOut (UVLO)
protection.
2. Features and benefits
System:
ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.
ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).
Serial Wire Debug (SWD)
JTAG boundary scan.
System tick timer.
Memory:
Up to 32 kB on-chip flash program memory.
Up to 4 kB on-chip EEPROM data memory; byte erasable and byte programmable.
Up to 8 kB SRAM data memory.
16 kB boot ROM.
In-System Programming (ISP) for flash and In-Application Programming (IAP) for
flash and EEPROM via on-chip bootloader software.
Includes ROM-based 32-bit integer division and I2C-bus driver routines.
Digital peripherals:
Up to 42 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down
resistors, repeater mode, and open-drain mode.
LPC11Axx
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Up to 16 pins are configurable with a digital input glitch filter for removing glitches
with widths of 10 ns or less and two pins are configurable for 50 ns glitch filters.
GPIO pins can be used as edge and level sensitive interrupt sources.
High-current source output driver (20 mA) on one pin (PIO0_21).
High-current sink driver (20 mA) on true open-drain pins (PIO0_2 and PIO0_3).
Four general purpose counter/timers with a total of up to 16 capture inputs and 14
match outputs.
Programmable Windowed WatchDog Timer (WWDT) with a dedicated, internal
low-power WatchDog Oscillator (WDOsc).
Analog peripherals:
10-bit ADC with input multiplexing among 8 pins.
10-bit DAC with flexible conversion triggering.
Highly flexible analog comparator with a programmable voltage reference.
Integrated temperature sensor.
Internal voltage reference.
UnderVoltage Lockout (UVLO) protection against power-supply droop below 2.4 V.
Serial interfaces:
USART with fractional baud rate generation, internal FIFO, support for
RS-485/9-bit mode and synchronous mode.
Two SSP controllers with FIFO and multi-protocol capabilities. Support data rates
of up to 25 Mbit/s.
I2C-bus interface supporting the full I2C-bus specification and Fast-mode Plus with
a data rate of 1 Mbit/s with multiple address recognition and monitor mode.
Clock generation:
Crystal Oscillator (SysOsc) with an operating range of 1 MHz to 25 MHz.
12 MHz internal RC Oscillator (IRC) trimmed to 1% accuracy that can optionally be
used as a system clock.
Internal low-power, Low-Frequency Oscillator (LFOsc) with programmable
frequency output.
Clock input for external system clock (25 MHz typical).
PLL allows CPU operation up to the maximum CPU rate with the IRC, the external
clock, or the SysOsc as clock sources.
Clock output function with divider that can reflect the SysOsc, the IRC, the main
clock, or the LFOsc.
Power control:
Supports one reduced power mode: The ARM Sleep mode.
Power profiles residing in boot ROM allowing to optimize performance and
minimize power consumption for any given application through one simple function
call.
Processor wake-up from reduced power mode using any interrupt.
Power-On Reset (POR).
Brown-Out Detect (BOD) with two programmable thresholds for interrupt and one
hardware controlled reset trip point.
POR and BOD are always enabled for rapid UVLO protection against power supply
voltage droop below 2.4 V.
Unique device serial number for identification.
LPC11AXX
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 30 October 2012
2 of 84
LPC11Axx
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Single 3.3 V power supply (2.6 V to 3.6 V).
Temperature range 40 C to +85 C.
Available as LQFP48 package, HVQFN33 (7 7) and HVQFN33 (5 5) packages, and
in a very small WLCSP20 package.
3. Applications
Power management
Gaming equipment
Motion control
Industrial control
Remote monitoring
Medical instrumentation
Fire and security
Point-of-sale
Test and measurement equipment
Network appliances and services
Factory automation
Sensors
Precision instrumentation
HVAC and building control
4. Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
Version
LPC11A02UK
LPC11A04UK
WLCSP20 wafer level chip-size package; 20 bumps; 2.5 2.5 0.6 mm
WLCSP20 wafer level chip-size package; 20 bumps; 2.5 2.5 0.6 mm
-
-
LPC11A11FHN33/001 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 n/a
terminals; body 7 7 0.85 mm
LPC11A12FHN33/101 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 n/a
terminals; body 7 7 0.85 mm
LPC11A13FHI33/201 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 n/a
terminals; body 5 5 0.85 mm
LPC11A14FHN33/301 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 n/a
terminals; body 7 7 0.85 mm
LPC11A12FBD48/101 LQFP48
LPC11A14FBD48/301 LQFP48
LQFP48: plastic low profile quad flat package; 48 leads; body 7 7
1.4 mm
SOT313-2
SOT313-2
LQFP48: plastic low profile quad flat package; 48 leads; body 7 7
1.4 mm
LPC11AXX
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 30 October 2012
3 of 84
LPC11Axx
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
4.1 Ordering options
Table 2.
Ordering options
Type number
Flash
SRAM EEPROM
Package
LPC11A02UK
LPC11A04UK
16 kB 4 kB
32 kB 8 kB
2 kB
4 kB
512 B
1 kB
1 kB
2 kB
4 kB
4 kB
8
8
8
8
8
8
8
8
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
1
1
1
1
1
1
1
1
18
18
28
28
42
28
28
42
WLCSP20
WLCSP20
HVQFN33
HVQFN33
LQFP48
LPC11A11FHN33/001 8 kB
2 kB
LPC11A12FHN33/101 16 kB 4 kB
LPC11A12FBD48/101 16 kB 4 kB
LPC11A13FHI33/201
24 kB 6 kB
HVQFN33
HVQFN33
LQFP48
LPC11A14FHN33/301 32 kB 8 kB
LPC11A14FBD48/301 32 kB 8 kB
LPC11AXX
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 30 October 2012
4 of 84
LPC11Axx
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
5. Block diagram
SWD
XTALIN XTALOUT
RESET
CLOCK
LPC11Axx
(3)
SysOsc
GENERATION,
IRC, LFOSC, WDOSC
CLKOUT
TEST/DEBUG
INTERFACE
POWER CONTROL,
CLKIN
SYSTEM
BOD
POR
FUNCTIONS
ARM
CORTEX-M0
EEPROM
512 B/
1/4 kB
clocks, internal voltage reference,
and controls
FLASH
8/16/24/32 kB
SRAM
2/4/6/8 kB
ROM
16 kB
system bus
slave
slave
slave
slave
HIGH-SPEED
AHB-LITE BUS
GPIO ports
GPIO
slave
AHB TO APB
BRIDGE
RXD
TXD
AD[7:0]
ATRG[1:0]
(4)
CTS, DCD, DSR, RI
RTS, DTR
USART
10-bit ADC
SCLK
TEMPERATURE SENSOR
CT32B0_MAT[3:0]
CT32B0_CAP[2:0]
CT32B1_MAT[3:0]
CT32B1_CAP[2:0]
32-bit COUNTER/TIMER 0
32-bit COUNTER/TIMER 1
16-bit COUNTER/TIMER 0
16-bit COUNTER/TIMER 1
ACMP_I[5:1]
ACMP_O
ANALOG COMPARATOR
10-bit DAC
VDDCMP
CT16B0_MAT[3:0]
CT16B0_CAP[2:0]
AOUT
CT16B1_MAT[3:0]
CT16B1_CAP[2:0]
(1)
SCL, SDA
(2)
SCL, SDA
2
I C-BUS
WINDOWED WATCHDOG
TIMER
(2)
(2)
SCL, SDA
SCL, SDA
IOCONFIG
SSP0
PMU
SCK0, SSEL0,
MISO0, MOSI0
SYSTEM CONTROL
SCK1, SSEL1,
MISO1, MOSI1
(3)
SSP1
002aaf428
(1) Open-drain pins.
(2) Standard I/O pins.
(3) Not available on WLCSP packages.
(4) Modem control pins not available on WLCSP packages.
Fig 1. LPC11Axx block diagram
LPC11AXX
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 30 October 2012
5 of 84
LPC11Axx
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
6. Pinning information
6.1 Pinning
1
2
36
35
34
33
32
31
30
29
28
27
26
25
PIO0_26
PIO0_28
PIO1_1
TRST/PIO0_9
TDO/PIO0_8
TMS/PIO0_7
TDI/PIO0_6
PIO1_0
3
RESET/PIO0_0
PIO0_1
4
5
V
SS(IO)
LPC11A12FBD48/101
LPC11A14FBD48/301
6
XTALIN
7
XTALOUT
PIO0_14
8
V
TCK/SWCLK/PIO0_5
PIO0_4
DD(IO)
9
PIO0_24
PIO0_18
PIO1_6
PIO1_9
10
11
12
PIO0_22
PIO1_8
PIO1_7
002aaf499
Fig 2. Pin configuration LQFP48 package
LPC11AXX
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 30 October 2012
6 of 84
LPC11Axx
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
terminal 1
index area
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
PIO0_26
RESET/PIO0_0
PIO0_1
TRST/PIO0_9
TDO/PIO0_8
TMS/PIO0_7
TDI/PIO0_6
PIO0_14
XTALIN
XTALOUT
V
TCK/SWCLK/PIO0_5
PIO0_4
DD(IO)
PIO0_24
PIO0_18
33 V
SS
PIO0_22
002aaf500
Transparent top view
Parts: LPC11A11FHN33/001, LPC11A12FHN33/101, LPC11A13FHI33/201,
LPC11A14FHN33/301
Fig 3. Pin configuration HVQFN 33 package
E
D
C
B
A
1
2
3
4
002aaf175
Parts: LPC11A02UK, LPC11A04UK
Fig 4. Pin configuration WLCSP20 package
6.2 Pin description
All functional pins on the LPC11Axx are mapped to GPIO port 0 and port 1 (see Table 4).
The port pins are multiplexed to accommodate more than one function (see Table 3).
The pin function is controlled by the pin’s IOCON register (see the LPC11Axx user
manual). The standard I/O pad configuration is illustrated in Figure 31 and a detailed pin
description is given in Table 4.
LPC11AXX
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 30 October 2012
7 of 84
LPC11Axx
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Table 3.
Function
Pin multiplexing
Type
LQFP48
Glitch filter Pin
HVQFN33
Pin
WCSP20
Ball
Port
System clocks, reset, and wake-up
CLKIN
I
PIO0_1
PIO0_12
PIO0_19
PIO0_24
PIO0_1
PIO0_19
-
no
no
no
no
no
no
-
4
3
B2
E1
-
46
14
9
31
9
7
-
CLKOUT
O
4
3
B2
-
14
6
9
XTALIN
XTALOUT
RESET
I
4
-
(analog)
O
-
-
7
3
5
2
-
(analog)
I
PIO0_0
20 ns[1]
C1
Serial Wire Debug (SWD) and JTAG
TRST
TCK
I
PIO0_9
PIO0_5
PIO0_6
PIO0_8
PIO0_7
PIO0_2
PIO0_5
PIO0_3
PIO0_10
10 ns[2]
10 ns[2]
10 ns[2]
no
10 ns[2]
50 ns[2]
10 ns[2]
50 ns[2]
10 ns[2]
35
29
32
34
33
15
29
16
38
24
19
21
23
22
10
19
11
25
D4
B3
C3
C2
C4
A1
B3
B1
D3
I
TDI
I
TDO
O
I
TMS
SWCLK
I
SWDIO
I/O
Analog peripherals (ADC, DAC, comparator)
ACMP_I1
ACMP_I2
ACMP_I3
ACMP_I4
ACMP_I5
ACMP_O
I
PIO0_27
PIO0_13
PIO0_16
PIO0_17
PIO0_22
no
no
no
no
no
43
47
18
21
27
28
32
13
14
17
-
(analog)
I
D1
A2
A3
-
(analog)
I
(analog)
I
(analog)
I
(analog)
O
PIO0_2
PIO0_3
PIO0_12
PIO0_21
PIO0_23
PIO0_6
no
no
no
no
no
no
15
16
46
23
45
32
10
11
31
16
30
21
A1
B1
E1
-
(digital)
-
AD0
AD1
I
C3
(analog)
I
PIO0_7
no
33
22
C4
(analog)
LPC11AXX
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 30 October 2012
8 of 84
LPC11Axx
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Table 3.
Pin multiplexing
Type
Function
LQFP48
Glitch filter Pin
HVQFN33
Pin
WCSP20
Ball
Port
AD2
AD3
AD4
AD5
AD6
AD7
AOUT
I
PIO0_8
PIO0_9
PIO0_10
PIO0_11
PIO0_14
PIO0_15
PIO0_4
no
no
no
no
no
no
no
34
35
38
39
30
41
28
23
C2
(analog)
I
24
25
26
20
27
18
D4
D3
D2
B4
E4
A4
(analog)
I
(analog)
I
(analog)
I
(analog)
I
(analog)
O
(analog)
ATRG0
I
I
PIO0_16
PIO0_17
PIO0_14
PIO0_5
10 ns[2]
10 ns[2]
no
18
21
30
-
13
14
20
-
A2
A3
-
ATRG1
VDDCMP
I
(analog)
no
B3
I2C-bus interface
SCL
SDA
I/O
PIO0_2
50 ns[2]
no
10 ns[2]
15
46
18
9
10
31
13
7
A1
E1
A2
-
PIO0_12
PIO0_16
PIO0_24
PIO0_3
no
I/O
50 ns[2]
10 ns[2]
10 ns[2]
no
16
47
41
17
11
32
27
12
B1
D1
E4
-
PIO0_13
PIO0_15
PIO0_25
SSP0 controller
MISO0
I/O
I/O
PIO0_6
PIO0_22
PIO1_2
PIO0_4
PIO0_19
PIO1_3
PIO1_7
PIO0_5
PIO0_20
PIO1_0
PIO0_1
PIO0_18
PIO1_1
10 ns[2]
10 ns[2]
no
32
27
37
28
14
48
25
29
22
31
4
21
17
-
C3
-
-
MOSI0
10 ns[2]
18
9
A4
no
-
no
-
-
no
10 ns[2]
-
-
SCK0
I/O
I/O
19
15
-
B3
no
-
no
-
SSEL0
no
3
B2
no
10
36
8
-
-
no
-
LPC11AXX
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 30 October 2012
9 of 84
LPC11Axx
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Table 3.
Function
Pin multiplexing
Type
LQFP48
Glitch filter Pin
HVQFN33
Pin
WCSP20
Ball
Port
SSP1 controller
MISO1
I/O
I/O
PIO0_14
PIO0_26
PIO1_8
10 ns[2]
no
30
1
20
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
no
10 ns[2]
26
43
24
40
11
34
20
13
17
19
2
MOSI1
PIO0_27
PIO0_31
PIO0_30
PIO1_6
28
-
no
no
-
no
10 ns[2]
-
SCK1
I/O
I/O
PIO0_8
23
-
PIO1_5
no
PIO0_29
PIO0_25
PIO1_4
no
-
SSEL1
no
12
-
no
PIO0_28
no
-
USART
RXD
I
PIO0_1
PIO0_12
PIO1_4
PIO1_8
PIO0_13
PIO0_15
PIO0_26
PIO1_5
PIO0_11
PIO0_21
PIO0_23
PIO0_9
PIO0_21
PIO1_7
PIO0_10
PIO0_23
PIO1_6
PIO1_9
PIO1_0
PIO0_29
PIO1_2
PIO0_28
PIO1_1
no
4
3
B2
no
46
19
26
47
41
1
31
-
E1
no
-
no
-
-
TXD
O
no
32
27
1
D1
no
E4
no
-
no
10 ns[2]
20
39
23
45
35
23
25
38
45
11
12
31
13
37
2
-
-
SCLK
CTS
RTS
I/O
I
26
16
30
24
16
-
D2
no
-
no
10 ns[2]
-
D4
no
-
no
-
O
no
25
30
-
D3
-
no
no
-
DCD
DSR
DTR
I
no
-
-
no
-
-
I
no
-
-
no
-
-
O
no
-
-
no
36
-
-
LPC11AXX
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 30 October 2012
10 of 84
LPC11Axx
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Table 3.
Pin multiplexing
Type
Function
LQFP48
Glitch filter Pin
HVQFN33
WCSP20
Port
Pin
Ball
RI
I
PIO0_30
PIO0_31
PIO1_3
no
no
no
40
24
48
-
-
-
-
-
-
16-bit counter/timer CT16B0
CT16B0_CAP0 I
PIO0_2
50 ns[2]
no
15
10
40
18
19
21
20
33
21
11
28
35
31
29
38
25
10
8
A1
-
PIO0_18
PIO0_30
PIO0_16
PIO1_4
PIO0_17
PIO1_5
PIO0_7
PIO0_17
PIO1_6
PIO0_4
PIO0_9
PIO1_0
PIO0_5
PIO0_10
PIO1_7
no
10 ns[2]
-
-
CT16B0_CAP1 I
CT16B0_CAP2 I
CT16B0_MAT0 O
13
-
A2
-
no
10 ns[2]
no
14
-
A3
-
no
22
14
-
C4
A3
-
no
no
CT16B0_MAT1 O
CT16B0_MAT2 O
no
18
24
-
A4
D4
-
no
no
no
19
25
-
B3
D3
-
no
no
16-bit counter/timer CT16B1
CT16B1_CAP0 I
PIO0_3
50 ns[2]
no
16
9
11
7
-
B1
PIO0_24
PIO1_3
PIO0_18
PIO0_26
PIO0_31
PIO0_27
PIO1_7
PIO0_19
PIO0_25
PIO1_1
PIO0_14
PIO1_2
PIO1_8
PIO0_20
PIO1_2
PIO1_9
-
no
48
10
1
-
CT16B1_CAP1 I
no
8
1
-
-
no
-
no
10 ns[2]
24
43
25
14
17
36
30
37
26
22
37
12
-
CT16B1_CAP2 I
CT16B1_MAT0 O
28
-
-
no
-
no
9
12
-
-
no
-
no
-
CT16B1_MAT1 O
CT16B1_MAT2 O
no
20
-
B4
-
no
no
-
-
no
15
-
-
no
-
no
-
-
LPC11AXX
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 30 October 2012
11 of 84
LPC11Axx
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Table 3.
Function
Pin multiplexing
Type
LQFP48
Glitch filter Pin
HVQFN33
Pin
WCSP20
Ball
Port
32-bit counter/timer CT32B0
CT32B0_CAP0 I
PIO0_11
10 ns[2]
no
39
45
2
26
30
-
D2
-
PIO0_23
PIO0_28
PIO0_14
PIO0_29
PIO0_15
PIO0_26
PIO0_12
PIO0_30
PIO0_13
PIO1_4
no
10 ns[2]
-
CT32B0_CAP1 I
CT32B0_CAP2 I
CT32B0_MAT0 O
CT32B0_MAT1 O
CT32B0_MAT2 O
CT32B0_MAT3 O
30
13
41
1
20
-
B4
-
no
10 ns[2]
no
27
1
E4
-
no
46
40
47
19
4
31
-
E1
-
no
no
32
-
D1
-
no
PIO0_1
no
3
B2
-
PIO1_5
no
20
32
11
-
PIO0_6
no
21
-
C3
-
PIO1_6
no
32-bit counter/timer CT32B1
CT32B1_CAP0 I
PIO0_7
10 ns[2]
no
33
22
19
23
20
27
11
34
24
26
35
43
25
38
27
12
39
36
31
22
15
-
C4
PIO0_20
PIO1_4
PIO0_21
PIO1_5
PIO0_22
PIO1_6
PIO0_8
PIO0_31
PIO1_8
PIO0_9
PIO0_27
PIO1_7
PIO0_10
PIO0_22
PIO1_9
PIO0_11
PIO1_1
PIO1_0
-
no
-
CT32B1_CAP1 I
CT32B1_CAP2 I
CT32B1_MAT0 O
no
16
-
-
no
10 ns[2]
-
17
-
-
no
-
no
23
-
C2
no
-
no
-
-
CT32B1_MAT1 O
CT32B1_MAT2 O
CT32B1_MAT3 O
Supply and ground pins
no
24
28
-
D4
no
-
no
-
no
25
17
-
D3
no
-
no
-
no
26
-
D2
no
-
-
no
-
VDD(IO)
Supply
-
-
8
6
E2
LPC11AXX
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 30 October 2012
12 of 84
LPC11Axx
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Table 3.
Pin multiplexing
Type
Function
LQFP48
Glitch filter Pin
HVQFN33
WCSP20
Ball
E2
Port
Pin
29
33
33
VDD(3V3)
VSS
Supply
Ground
Ground
-
-
-
-
44
42
5
-
-
E3
VSS(IO)
E3
[1] Always on.
[2] Programmable on/off. By default, the glitch filter is disabled.
Table 4 shows all pins in order of their port number. The default function after reset is
listed first. All port pins PIO0_0 to PIO1_9 have internal pull-up resistors enabled after
reset with the exception of the true open-drain pins PIO0_2 and PIO0_3.
Pull-up/pull-down configuration, repeater, and open-drain modes can be programmed
through the IOCON registers for each of the port pins.
Table 4.
Symbol
LPC11Axx pin description table
Pin/Ball
Type Reset Description
state
[1]
[2]
[3]
RESET/PIO0_0
3
2
3
C1
B2
I
I; PU RESET — External reset input with fixed 20 ns glitch filter: A
LOW on this pin resets the device, causing I/O ports and
peripherals to take on their default states and processor
execution to begin at address 0.
I/O
I/O
-
PIO0_0 — General purpose digital input/output pin.
PIO0_1/RXD/CLKOUT/ 4
CT32B0_MAT2/SSEL0/
CLKIN
I; PU PIO0_1 — General purpose digital input/output pin. A LOW
level on this pin during reset starts the ISP command handler.
I
-
RXD — Receiver data input for USART.
CLKOUT — Clock output.
O
O
I/O
I
-
-
CT32B0_MAT2 — Match output 2 for 32-bit timer 0.
SSEL0 — Slave Select for SSP0.
CLKIN — External clock input.
-
-
[4][5]
PIO0_2/SCL/ACMP_O/ 15 10 A1
TCK/SWCLK/
CT16B0_CAP0
I/O
I; IA
PIO0_2 — General purpose digital input/output pin.
High-current sink (20 mA) or standard-current sink (4 mA)
programmable; true open-drain for all pin functions. Input
glitch filter (50 ns) capable.
I/O
-
SCL — I2C-bus clock (true open-drain) input/output. Input
glitch filter (50 ns) capable.
O
I
-
-
ACMP_O — Analog comparator output.
TCK/SWCLK — Serial Wire Debug Clock (secondary for
LQFP and HVQFN packages). Input glitch filter (50 ns)
capable. For the WLCSP20 package only, this pin is
configured to the SWCLK function by the boot loader after
reset.
I
-
CT16B0_CAP0 — Capture input 0 for 16-bit timer 0. Input
glitch filter (50 ns) capable.
LPC11AXX
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 30 October 2012
13 of 84
LPC11Axx
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Table 4.
Symbol
LPC11Axx pin description table
Pin/Ball
Type Reset Description
state
[1]
[4][6]
PIO0_3/SDA/ACMP_O/ 16 11 B1
SWDIO/CT16B1_CAP0
I/O
I/O
I; IA
PIO0_3 — General purpose digital input/output pin.
High-current sink (20 mA) or standard-current sink (4 mA)
programmable; true open-drain for all pin functions. Input
glitch filter (50 ns) capable.
-
SDA — I2C-bus data (true open-drain) input/output. Input
glitch filter (50 ns) capable.
O
-
-
ACMP_O — Analog comparator output.
I/O
SWDIO — Serial Wire Debug I/O (secondary for LQFP and
HVQFN packages). Input glitch filter (50 ns) capable. For the
WLCSP20 package only, this pin is configured to the SWDIO
function by the boot loader after reset.
I
-
CT16B1_CAP0 — Capture input 0 for 16-bit timer 1. Input
glitch filter (50 ns) capable.
[7]
PIO0_4/R/AOUT/
28 18 A4
I/O
I; PU PIO0_4 — General purpose digital input/output pin. Input
CT16B0_MAT1/MOSI0
glitch filter (10 ns) capable.
-
-
-
-
-
R — Reserved.
O
O
I/O
AOUT — D/A converter output.
CT16B0_MAT1 — Match output 1 for 16-bit timer 0.
MOSI0 — Master Out Slave In for SSP0. Input glitch filter
(10 ns) capable.
[9]
TCK/SWCLK/PIO0_5/ 29 19
R/CT16B0_MAT2/
SCK0
-
I
I; PU TCK/SWCLK — Test clock TCK for JTAG interface and
primary (default) Serial Wire Debug Clock. Input glitch filter (10
ns) capable.
I/O
-
PIO0_5 — General purpose digital input/output pin. Input
glitch filter (10 ns) capable.
-
-
-
-
R — Reserved.
O
I/O
CT16B0_MAT2 — Match output 2 for 16-bit timer 0.
SCK0 — Serial clock for SSP0. Input glitch filter (10 ns)
capable.
[7][8]
TCK/SWCLK/PIO0_5/
VDDCMP/
CT16B0_MAT2/
SCK0
-
-
B3
I
I; PU TCK/SWCLK — Test clock TCK for JTAG interface and
secondary Serial Wire Debug ClocK. Use PIO0_2 for the
default TCK/SWCLK function. Input glitch filter (10 ns)
capable.
I/O
-
PIO0_5 — General purpose digital input/output pin. Input
glitch filter (10 ns) capable.
I
-
-
-
VDDCMP — Analog comparator alternate reference voltage.
CT16B0_MAT2 — Match output 2 for 16-bit timer 0.
O
I/O
SCK0 — Serial clock for SSP0. Input glitch filter (10 ns)
capable.
LPC11AXX
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 30 October 2012
14 of 84
LPC11Axx
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Table 4.
Symbol
LPC11Axx pin description table
Pin/Ball
Type Reset Description
state
[1]
[9]
TDI/PIO0_6/AD0/
32 21 C3
I
I; PU TDI — Test Data In for JTAG interface. Input glitch filter (10 ns)
CT32B0_MAT3/MISO0
capable.
I/O
-
PIO0_6 — General purpose digital input/output pin. Input
glitch filter (10 ns) capable.
I
-
-
-
AD0 — A/D converter input 0.
O
I/O
CT32B0_MAT3 — Match output 3 for 32-bit timer 0.
MISO0 — Master In Slave Out for SSP0. Input glitch filter
(10 ns) capable.
[9]
TMS/PIO0_7/AD1/
CT32B1_CAP0/
CT16B0_MAT0
33 22 C4
I
I; PU TMS — Test Mode Select for JTAG interface. Input glitch filter
(10 ns) capable.
I/O
-
PIO0_7 — General purpose digital input/output pin. Input
glitch filter (10 ns) capable.
I
I
-
-
AD1 — A/D converter input 1.
CT32B1_CAP0 — Capture input 0 for 32-bit timer 1. Input
glitch filter (10 ns) capable.
O
-
CT16B0_MAT0 — Match output 2 for 16-bit timer 0.
[9]
TDO/PIO0_8/AD2/
34 23 C2
O
I; PU TDO — Test Data Out for JTAG interface.
CT32B1_MAT0/SCK1
I/O
-
PIO0_8 — General purpose digital input/output pin. Input
glitch filter (10 ns) capable.
I
-
-
-
AD2 — A/D converter input 2.
O
I/O
CT32B1_MAT0 — Match output 0 for 32-bit timer 1.
SCK1 — Serial clock for SSP1. Input glitch filter (10 ns)
capable.
[9]
TRST/PIO0_9/AD3/
CT32B1_MAT1/
35 24 D4
I
I; PU TRST — Test Reset for JTAG interface. Input glitch filter
(10 ns) capable.
CT16B0_MAT1/CTS
I/O
-
PIO0_9 — General purpose digital input/output pin. Input
glitch filter (10 ns) capable.
I
-
-
-
-
AD3 — A/D converter, input 3.
O
O
I
CT32B1_MAT1 — Match output 1 for 32-bit timer 1.
CT16B0_MAT1 — Match output 1 for 16-bit timer 0.
CTS — Clear To Send input for USART. Input glitch filter
(10 ns) capable.
LPC11AXX
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 30 October 2012
15 of 84
LPC11Axx
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Table 4.
Symbol
LPC11Axx pin description table
Pin/Ball
Type Reset Description
state
[1]
[9]
SWDIO/PIO0_10/AD4/ 38 25 D3
CT32B1_MAT2/
CT16B0_MAT2/RTS
I/O
I/O
I; PU SWDIO — Primary (default) Serial Wire Debug I/O for the
LQFP48 and HVQFN33 packages. For the WLCSP20
package, use PIO0_3. Input glitch filter (10 ns) capable.
-
PIO0_10 — General purpose digital input/output pin. Input
glitch filter (10 ns) capable.
I
-
-
-
-
AD4 — A/D converter, input 4.
O
O
O
I/O
CT32B1_MAT2 — Match output 2 for 32-bit timer 1.
CT16B0_MAT2 — Match output 2 for 16-bit timer 0.
RTS — Request To Send output for USART.
[9]
PIO0_11/SCLK/
AD5/CT32B1_MAT3/
CT32B0_CAP0
39 26 D2
I; PU PIO0_11 — General purpose digital input/output pin. Input
glitch filter (10 ns) capable.
I/O
-
SCLK — Serial clock for USART. Input glitch filter (10 ns)
capable.
I
-
-
-
AD5 — A/D converter, input 5.
O
I
CT32B1_MAT3 — Match output 3 for 32-bit timer 1.
CT32B0_CAP0 — Capture input 0 for 32-bit timer 0. Input
glitch filter (10 ns) capable.
[3]
PIO0_12/RXD/
ACMP_O/
CT32B0_MAT0/SCL/
CLKIN
46 31 E1
I/O
I
I; PU PIO0_12 — General purpose digital input/output pin.
-
RXD — Receiver data input for USART. This pin is used for
ISP communication.
O
-
-
-
ACMP_O — Analog comparator output.
O
CT32B0_MAT0 — Match output 0 for 32-bit timer 0.
SCL — I2C-bus clock input/output. This is not an I2C-bus
I/O
open-drain pin[10]
.
I
-
CLKIN — External clock input.
[9]
PIO0_13/TXD/
ACMP_I2/
47 32 D1
I/O
I; PU PIO0_13 — General purpose digital input/output pin. Input
glitch filter (10 ns) capable.
CT32B0_MAT1/SDA
O
-
TXD — Transmitter data output for USART. This pin is used
for ISP communication.
I
-
-
-
ACMP_I2 — Analog comparator input 2.
O
I/O
CT32B0_MAT1 — Match output 1 for 32-bit timer 0.
SDA — I2C-bus data input/output. This is not an I2C-bus
open-drain pin[10]. Input glitch filter (10 ns) capable.
LPC11AXX
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 30 October 2012
16 of 84
LPC11Axx
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Table 4.
Symbol
LPC11Axx pin description table
Pin/Ball
Type Reset Description
state
[1]
[7]
PIO0_14/MISO1/AD6/ 30 20
CT32B0_CAP1/
CT16B1_MAT1/
-
I/O
I/O
I; PU PIO0_14 — General purpose digital input/output pin. Input
glitch filter (10 ns) capable.
-
MISO1 — Master In Slave Out for SSP1. Input glitch filter
VDDCMP
(10 ns) capable.
I
I
-
-
AD6 — A/D converter, input 6.
CT32B0_CAP1 — Capture input 1 for 32-bit timer 0. Input
glitch filter (10 ns) capable.
O
I
-
-
CT16B1_MAT1 — Match output 1 for 16-bit timer 1.
VDDCMP — Analog comparator alternate reference voltage.
[9]
[9]
[9]
PIO0_14/MISO1/AD6/
CT32B0_CAP1/
CT16B1_MAT1
-
-
B4
I/O
I; PU PIO0_14 — General purpose digital input/output pin. Input
glitch filter (10 ns) capable.
I/O
-
MISO1 — Master In Slave Out for SSP1. Input glitch filter
(10 ns) capable.
I
I
-
-
AD6 — A/D converter, input 6.
CT32B0_CAP1 — Capture input 1 for 32-bit timer 0. Input
glitch filter (10 ns) capable.
O
-
CT16B1_MAT1 — Match output 1 for 16-bit timer 1.
PIO0_15/TXD/AD7/
CT32B0_CAP2/SDA
41 27 E4
I/O
I; PU PIO0_15 — General purpose digital input/output pin. Input
glitch filter (10 ns) capable.
O
I
-
-
-
TXD — Transmitter data output for USART.
AD7 — A/D converter, input 7.
I
CT32B0_CAP2 — Capture input 2 for 32-bit timer 0. Input
glitch filter (10 ns) capable.
I/O
I/O
I
-
SDA — I2C-bus data input/output. This is not an I2C-bus
open-drain pin[10]. Input glitch filter (10 ns) capable.
PIO0_16/
ATRG0/ACMP_I3/
CT16B0_CAP1/SCL
18 13 A2
I; PU PIO0_16 — General purpose digital input/output pin. Input
glitch filter (10 ns) capable.
-
ATRG0 — Conversion trigger 0 for ADC or DAC. Input glitch
filter (10 ns) capable.
I
I
-
-
ACMP_I3 — Analog comparator input 3.
CT16B0_CAP1 — Capture input 1 for 16-bit timer 0. Input
glitch filter (10 ns) capable.
I/O
-
SCL — I2C-bus clock input/output. This is not an I2C-bus
open-drain pin[10]. Input glitch filter (10 ns) capable.
LPC11AXX
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 30 October 2012
17 of 84
LPC11Axx
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Table 4.
Symbol
LPC11Axx pin description table
Pin/Ball
Type Reset Description
state
[1]
[9]
PIO0_17/
21 14 A3
I/O
I
I; PU PIO0_17 — General purpose digital input/output pin. Input
ATRG1/ACMP_I4/
CT16B0_CAP2/
CT16B0_MAT0
glitch filter (10 ns) capable.
-
ATRG1 — Conversion trigger 1 for ADC or DAC. Input glitch
filter (10 ns) capable.
I
I
-
-
ACMP_I4 — Analog comparator input 4.
CT16B0_CAP2 — Capture input 2 for 16-bit timer 0. Input
glitch filter (10 ns) capable.
O
I/O
-
-
CT16B0_MAT0 — Match output 0 for 16-bit timer 0.
[3]
[3]
[3]
[3]
PIO0_18/R/SSEL0/
CT16B0_CAP0/
CT16B1_CAP1
10
14
8
9
-
-
-
-
I; PU PIO0_18 — General purpose digital input/output pin.
-
-
-
-
R — Reserved.
I/O
I
SSEL0 — Slave Select for SSP0.
CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.
CT16B1_CAP1 — Capture input 1 for 16-bit timer 1.
I
PIO0_19/CLKIN/
CLKOUT/
MOSI0/CT16B1_MAT0
I/O
I
I; PU PIO0_19 — General purpose digital input/output pin.
-
-
-
-
CLKIN — External clock input.
O
I/O
O
I/O
-
CLKOUT — Clock output.
MOSI0 — Master Out Slave In for SSP0.
CT16B1_MAT0 — Match output 0 for 16-bit timer 1.
PIO0_20/R/SCK0/
CT32B1_CAP0/
CT16B1_MAT2
22 15
I; PU PIO0_20 — General purpose digital input/output pin.
-
-
-
-
R — Reserved.
I/O
I
SCK0 — Serial clock for SSP0.
CT32B1_CAP0 — Capture input 0 for 32-bit timer 1.
CT16B1_MAT2 — Match output 2 for 16-bit timer 1.
O
I/O
PIO0_21/CTS/
ACMP_O/
CT32B1_CAP1/SCLK
23 16
I; PU PIO0_21 — General purpose digital input/output pin. If
configured as output, this pin is a high-current source output
driver (20 mA).
I
-
-
-
-
CTS — Clear To Send input for USART.
ACMP_O — Analog comparator output.
CT32B1_CAP1 — Capture input 1 for 32-bit timer 1.
SCLK — Serial clock for USART.
O
I
I/O
I/O
[9]
PIO0_22/MISO0/
ACMP_I5/
27 17
-
I; PU PIO0_22 — General purpose digital input/output pin. Input
glitch filter (10 ns) capable.
CT32B1_MAT2/
CT32B1_CAP2
I/O
-
MISO0 — Master In Slave Out for SSP0. Input glitch filter
(10 ns) capable.
I
-
-
-
ACMP_I5 — Analog comparator input 5.
O
I
CT32B1_MAT2 — Match output 2 for 32-bit timer 1.
CT32B1_CAP2 — Capture input 2 for 32-bit timer 1. Input
glitch filter (10 ns) capable.
LPC11AXX
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 30 October 2012
18 of 84
LPC11Axx
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Table 4.
Symbol
LPC11Axx pin description table
Pin/Ball
Type Reset Description
state
[1]
[3]
PIO0_23/RTS/
ACMP_O/
CT32B0_CAP0/SCLK
45 30
-
I/O
O
I; PU PIO0_23 — General purpose digital input/output pin.
-
-
-
-
RTS — Request To Send output for USART.
ACMP_O — Analog comparator output.
CT32B0_CAP0 — Capture input 0 for 32-bit timer 0.
SCLK — Serial clock for USART.
O
I
I/O
I/O
I/O
[3]
[3]
[3]
PIO0_24/SCL/CLKIN/
CT16B1_CAP0
9
7
-
-
-
I; PU PIO0_24 — General purpose digital input/output pin.
-
SCL — I2C-bus clock input/output. This is not an I2C-bus
open-drain pin[10]
.
I
-
-
CLKIN — External clock input.
I
CT16B1_CAP0 — Capture input 0 for 16-bit timer 1.
PIO0_25/SDA/SSEL1/ 17 12
CT16B1_MAT0
I/O
I/O
I; PU PIO0_25 — General purpose digital input/output pin.
-
SDA — I2C-bus data input/output. This is not an I2C-bus
open-drain pin[10]
.
I/O
O
-
-
SSEL1 — Slave Select for SSP1.
CT16B1_MAT0 — Match output 0 for 16-bit timer 1.
PIO0_26/TXD/MISO1/
CT16B1_CAP1/
CT32B0_CAP2
1
1
I/O
O
I; PU PIO0_26 — General purpose digital input/output pin.
-
-
-
-
TXD — Transmitter data output for USART.
MISO1 — Master In Slave Out for SSP1.
I/O
I
CT16B1_CAP1 — Capture input 1 for 16-bit timer 1.
CT32B0_CAP2 — Capture input 2 for 32-bit timer 0.
I
[9]
PIO0_27/MOSI1/
ACMP_I1/
43 28
-
I/O
I; PU PIO0_27 — General purpose digital input/output pin. Input
glitch filter (10 ns) capable.
CT32B1_MAT1/
CT16B1_CAP2
I/O
-
MOSI1 — Master Out Slave In for SSP1. Input glitch filter
(10 ns) capable.
I
-
-
-
ACMP_I1 — Analog comparator input 1.
O
I
CT32B1_MAT1 — Match output 1 for 32-bit timer 1.
CT16B1_CAP2 — Capture input 2 for 16-bit timer 1. Input
glitch filter (10 ns) capable.
[3]
[3]
PIO0_28/DTR/SSEL1/
CT32B0_CAP0
2
-
-
-
-
I/O
O
I; PU PIO0_28 — General purpose digital input/output pin.
-
-
-
DTR — Data Terminal Ready output for USART.
SSEL1 — Slave Select for SSP1.
I/O
I
CT32B0_CAP0 — Capture input 0 for 32-bit timer 0.
PIO0_29/DSR/SCK1/
CT32B0_CAP1
13
I/O
I
I; PU PIO0_29 — General purpose digital input/output pin.
-
-
-
DSR — Data Set Ready input for USART.
SCK1 — Serial clock for SSP1.
I/O
I
CT32B0_CAP1 — Capture input 1 for 32-bit timer 0.
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Table 4.
Symbol
LPC11Axx pin description table
Pin/Ball
Type Reset Description
state
[1]
[3]
[3]
[3]
[3]
[3]
PIO0_30/RI/MOSI1/
CT32B0_MAT0/
CT16B0_CAP0
40
24
31
36
37
-
-
-
-
-
-
-
-
-
-
I/O
I
I; PU PIO0_30 — General purpose digital input/output pin.
-
-
-
-
RI — Ring Indicator input for USART.
I/O
O
I
MOSI1 — Master Out Slave In for SSP1.
CT32B0_MAT0 — Match output 0 for 32-bit timer 0.
CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.
PIO0_31/RI/MOSI1/
CT32B1_MAT0/
CT16B1_CAP1
I/O
I
I; PU PIO0_31 — General purpose digital input/output pin.
-
-
-
-
RI — Ring Indicator input for USART.
I/O
O
I
MOSI1 — Master Out Slave In for SSP1.
CT32B1_MAT0 — Match output 0 for 32-bit timer 1.
CT16B1_CAP1 — Capture input 1 for 16-bit timer 1.
PIO1_0/DCD/SCK0/
CT32B1_MAT3/
CT16B0_MAT1
I/O
I
I; PU PIO1_0 — General purpose digital input/output pin.
-
-
-
-
DCD — Data Carrier Detect input for USART.
SCK0 — Serial clock for SSP0.
I/O
O
O
I/O
O
I/O
O
O
I/O
I
CT32B1_MAT3 — Match output 3 for 32-bit timer 1.
CT16B0_MAT1 — Match output 1 for 16-bit timer 0.
PIO1_1/DTR/SSEL0/
CT32B1_MAT3/
CT16B1_MAT0
I; PU PIO1_1 — General purpose digital input/output pin.
-
-
-
-
DTR — Data Terminal Ready output for USART.
SSEL0 — Slave Select for SSP0.
CT32B1_MAT3 — Match output 3 for 32-bit timer 1.
CT16B1_MAT0 — Match output 0 for 16-bit timer 1.
PIO1_2/DSR/MISO0/
CT16B1_MAT2/
CT16B1_MAT1
I; PU PIO1_2 — General purpose digital input/output pin.
-
-
-
-
DSR — Data Set Ready input for USART.
I/O
O
O
I/O
I
MISO0 — Master In Slave Out for SSP0.
CT16B1_MAT2 — Match output 2 for 16-bit timer 1.
CT16B1_MAT1 — Match output 1 for 16-bit timer 1.
[3]
[3]
PIO1_3/RI/MOSI0/
CT16B1_CAP0
48
19
-
-
-
-
I; PU PIO1_3 — General purpose digital input/output pin.
-
-
-
RI — Ring Indicator input for USART.
I/O
I
MOSI0 — Master Out Slave In for SSP0.
CT16B1_CAP0 — Capture input 0 for 16-bit timer 1.
PIO1_4/RXD/SSEL1/
CT32B0_MAT1/
CT32B1_CAP0/
CT16B0_CAP1
I/O
I
I; PU PIO1_4 — General purpose digital input/output pin.
-
-
-
-
-
RXD — Receiver data input for USART.
I/O
O
I
SSEL1 — Slave Select for SSP1.
CT32B0_MAT1 — Match output 1 for 32-bit timer 0.
CT32B1_CAP0 — Capture input 0 for 32-bit timer 1.
CT16B0_CAP1 — Capture input 1 for 16-bit timer 0.
I
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Table 4.
Symbol
LPC11Axx pin description table
Pin/Ball
Type Reset Description
state
[1]
[3]
[3]
[3]
PIO1_5/TXD/SCK1/
CT32B0_MAT2/
CT32B1_CAP1/
CT16B0_CAP2
20
11
25
-
-
-
-
-
-
I/O
O
I/O
O
I
I; PU PIO1_5 — General purpose digital input/output pin.
-
-
-
-
-
TXD — Transmitter data output for USART.
SCK1 — Serial clock for SSP1.
CT32B0_MAT2 — Match output 2 for 32-bit timer 0.
CT32B1_CAP1 — Capture input 1 for 32-bit timer 1.
CT16B0_CAP2 — Capture input 2 for 16-bit timer 0.
I
PIO1_6/RTS/MOSI1/
CT32B0_MAT3/
CT32B1_CAP2/
CT16B0_MAT0
I/O
O
I/O
O
I
I; PU PIO1_6 — General purpose digital input/output pin.
-
-
-
-
-
RTS — Request To Send output for USART.
MOSI1 — Master Out Slave In for SSP1.
CT32B0_MAT3 — Match output 3 for 32-bit timer 0.
CT32B1_CAP2 — Capture input 2 for 32-bit timer 1.
CT16B0_MAT0 — Match output 0 for 16-bit timer 0.
O
I/O
I
PIO1_7/CTS/MOSI0/
CT32B1_MAT1/
CT16B0_MAT2/
CT16B1_CAP2
I; PU PIO1_7 — General purpose digital input/output pin.
-
-
-
-
-
CTS — Clear To Send input for USART.
I/O
O
O
I
MOSI0 — Master Out Slave In for SSP0.
CT32B1_MAT1 — Match output 1 for 32-bit timer 1.
CT16B0_MAT2 — Match output 2 for 16-bit timer 0.
CT16B1_CAP2 — Capture input 2 for 16-bit timer 1.
[3]
PIO1_8/RXD / MISO1/ 26
CT32B1_MAT0/
CT16B1_MAT1
-
-
-
-
I/O
I
I; PU PIO1_8 — General purpose digital input/output pin.
-
-
-
-
RXD — Receiver data input for USART.
I/O
O
O
I/O
I
MISO1 — Master In Slave Out for SSP1.
CT32B1_MAT0 — Match output 0 for 32-bit timer 1.
CT16B1_MAT1 — Match output 1 for 16-bit timer 1.
[3]
PIO1_9/DCD/R/
CT32B1_MAT2 /
CT16B1_MAT2
12
-
I; PU PIO1_9 — General purpose digital input/output pin.
-
-
-
-
-
DCD — Data Carrier Detect input for USART.
R — Reserved.
-
O
O
-
CT32B1_MAT2 — Match output 2 for 32-bit timer 1.
CT16B1_MAT2 — Match output 2 for 16-bit timer 1.
[11]
[11]
XTALIN
6
4
Input to the oscillator circuit and internal clock generator
circuits. Input voltage must not exceed 1.8 V.
XTALOUT
VDD(IO)
7
8
5
6
-
-
-
-
-
Output from the oscillator amplifier.
3.3 V input/output supply voltage.
[12]
[13]
E2
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Table 4.
Symbol
LPC11Axx pin description table
Pin/Ball
Type Reset Description
state
[1]
[14]
VSS(IO)
5
33 E3
-
-
-
-
Ground.
[12]
[13]
VDD(3V3)
44 29 E2
3.3 V supply voltage to the analog blocks, internal regulator,
and internal clock generator circuits. Also used as the ADC
reference voltage.
[14]
VSS
42 33 E3
-
-
Ground.
[1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up resistor (weak PMOS device) enabled; IA = inactive, no
pull-up/down enabled.
[2] See Figure 32 for the reset configuration.
[3] 5 V tolerant pin providing standard digital I/O functions with configurable modes and configurable hysteresis (Figure 31).
[4] I2C-bus pins compliant with the I2C-bus specification for I2C standard mode, I2C Fast-mode, and I2C Fast-mode Plus.
[5] For the SWD function, a pull-up resistor is recommended for the SWCLK pin (WLCSP20 parts only).
[6] For the SWD function, a pull-up resistor is recommended for the SWDIO pin (WLCSP20 parts only).
[7] Not a 5 V tolerant pin due to special analog functionality. Pin provides standard digital I/O functions with configurable modes,
configurable hysteresis, and analog I/O. When configured as an analog I/O, the digital section of the pin is disabled (Figure 31).
[8] If this pin is configured for its VDDCMP function, it cannot be used for SWCLK when the part is on the board. The bypass filter of the
power supply filters out the SWCLK clock input signal.
[9] 5 V tolerant pin providing standard digital I/O functions with configurable modes, configurable hysteresis, and analog I/O. When
configured as an analog I/O, digital section of the pin is disabled, and the pin is not 5 V tolerant (Figure 31).
[10] I2C-bus pins are standard digital I/O pins and have limited performance and electrical characteristics compared to the full I2C-bus
specification. Pins can be configured with an on-chip pull-up resistor (pMOS device) and with open-drain mode. In this mode, typical bit
rates of up to 100 kbit/s with 20 pF load are supported if the internal pull-ups are enabled. Higher bit rates can be achieved with an
external resistor.
[11] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded
(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating. See Section 12.3 if an external clock is
connected to the XTALIN pin.
[12] If separate supplies are used for VDD(3V3) and VDD(IO), ensure that the power supply pins are filtered for noise with respect to their
corresponding grounds VSS and VSS(IO) (LQFP48 package). Using separate filtered supplies reduces the noise to the analog blocks (see
also Section 12.1).
[13] If separate supplies are used for VDD(3V3) and VDD(IO), ensure that the voltage difference between both supplies is smaller than or equal
to 0.5 V.
[14] Thermal pad (HVQFN33 pin package). Connect to ground.
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7. Functional description
7.1 ARM Cortex-M0 processor
The ARM Cortex-M0 is a general purpose, 32-bit microprocessor, which offers high
performance and very low power consumption.
7.2 On-chip flash program memory
The LPC11Axx contain up to 32 kB of on-chip flash program memory.
7.3 On-chip EEPROM data memory
The LPC11Axx contain up to 4 kB of on-chip EEPROM data memory.
Remark: The top 64 bytes of the 4 kB EEPROM memory are reserved and cannot be
written to. The entire EEPROM is writable for smaller EEPROM sizes.
7.4 On-chip SRAM
The LPC11Axx contain a total of 8 kB, 4 kB, or 2 kB on-chip static RAM data memory.
7.5 On-chip ROM
The on-chip ROM contains the boot loader and the following Application Programming
Interfaces (API):
• In-System Programming (ISP) and In-Application Programming (IAP) support for flash
programming
• Power profiles for configuring power consumption and PLL settings
• 32-bit integer division routines
• I2C-bus driver routines
7.6 Memory map
The LPC11Axx incorporates several distinct memory regions, shown in the following
figures. Figure 5 shows the overall map of the entire address space from the user
program viewpoint following reset. The interrupt vector area supports address remapping.
The AHB peripheral area is 2 MB in size, and is divided to allow for up to 128 peripherals.
The APB peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals.
Each peripheral of either type is allocated 16 kB of space. This allows simplifying the
address decoding for each peripheral.
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LPC11Axx
4 GB
0xFFFF FFFF
reserved
0xE010 0000
0xE000 0000
private peripheral bus
reserved
APB peripherals
0x4008 0000
0x5004 0000
0x5000 0000
GPIO
25 - 31 reserved
24
23
GPIO GROUP1 INT
GPIO GROUP0 INT
SSP1
reserved
0x4005 C000
0x4005 8000
22
21
0x4008 0000
0x4000 0000
reserved
reserved
0x4005 4000
0x4005 0000
APB peripherals
reserved
1 GB
20
19
GPIO interrupts
0x4004 C000
0x4004 8000
system control
IOCONFIG
SSP0
18
17
16
0x4004 4000
0x4004 0000
0x4003 C000
0x4003 8000
0x2000 0000
0.5 GB
15 flash/EEPROM controller
reserved
14
reserved
0x1FFF 4000
0x1FFF 0000
16 kB boot ROM
11 - 13 reserved
0x4002 C000
analog comparator
DAC
10
0x4002 8000
0x4002 4000
0x4002 0000
reserved
9
8
7
6
5
4
3
2
reserved
0x1000 2000
8 kB SRAM (LPC11A1x/301, LPC11A04)
ADC
0x4001 C000
0x4001 8000
0x1000 1800
0x1000 1000
0x1000 0800
0x1000 0000
32-bit counter/timer 1
6 kB SRAM (LPC11A1x/201)
4 kB SRAM (LPC11Ax/101, LPC11A02))
2 kB SRAM (LPC11Ax/001)
32-bit counter/timer 0
16-bit counter/timer 1
16-bit counter/timer 0
USART
0x4001 4000
0x4001 0000
0x4000 C000
0x4000 8000
reserved
0x0000 8000
0x0000 6000
0x0000 4000
0x0000 2000
WWDT
1
0
0x4000 4000
0x4000 0000
32 kB on-chip flash (LPC11A14, LPC11A04)
24 kB on-chip flash (LPC11A13)
2
I C-bus
16 kB on-chip flash (LPC11A12, LPC11A02)
0x0000 00C0
active interrupt vectors
0x0000 0000
8 kB on-chip flash (LPC11A11)
0x0000 0000
0 GB
002aaf429
Fig 5. LPC11Axx memory map
7.7 Nested Vectored Interrupt Controller (NVIC)
The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M0. The
tight coupling to the CPU allows for low interrupt latency and efficient processing of late
arriving interrupts.
7.7.1 Features
• Controls system exceptions and peripheral interrupts.
• In the LPC11Axx, the NVIC supports 32 vectored interrupts including up to 8 inputs to
the start logic from the individual GPIO pins.
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• Four programmable interrupt priority levels with hardware priority level masking.
• Software interrupt generation.
7.7.2 Interrupt sources
Each peripheral device has one interrupt line connected to the NVIC but may have several
interrupt flags. Individual interrupt flags may also represent more than one interrupt
source.
Up to eight GPIO pins, regardless of the selected function, can be programmed to
generate an interrupt on a level, or rising edge or falling edge, or both. The interrupt
generating GPIOs can be selected from the GPIO pins with a configurable input glitch
filter.
7.8 IOCON block
The IOCON block allows selected pins of the microcontroller to have more than one
function. Configuration registers control the multiplexers to allow connection between the
pin and the on-chip peripherals.
Peripherals should be connected to the appropriate pins prior to being activated and prior
to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is
not mapped to a related pin should be considered undefined.
Up to 16 pins can be configured with a digital input glitch filter for removing voltage
glitches with widths of 10 ns or less (see Table 3 and Table 4), two pins (PIO0_2 and
PIO0_3) can be configured with a 50 ns digital input glitch filter.
7.9 Fast general purpose parallel I/O
Device pins that are not connected to a specific peripheral function are controlled by the
GPIO registers. Pins may be dynamically configured as inputs or outputs. Multiple outputs
can be set or cleared in one write operation.
LPC11Axx use accelerated GPIO functions:
• GPIO registers are a dedicated AHB peripheral so that the fastest possible I/O timing
can be achieved.
• An entire port value can be written in one instruction.
Additionally, any GPIO pin (total of up to 42 pins) providing a digital function can be
programmed to generate an interrupt on a level, a rising or falling edge, or both.
7.9.1 Features
• Bit level port registers allow a single instruction to set and clear any number of bits in
one write operation.
• Direction control of individual bits.
• All I/O default to inputs with internal pull-up resistors enabled after reset - except for
the I2C-bus true open-drain pins PIO0_2 and PIO0_3.
• Pull-up/pull-down configuration, repeater, and open-drain modes can be programmed
through the IOCON block for each GPIO pin (see Figure 31 and Figure 32 for
functional diagrams).
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• Control of the digital output slew rate allowing to switch more outputs simultaneously
without degrading the power/ground distribution of the device.
7.10 USART
The LPC11Axx contains one USART.
Support for RS-485/9-bit mode allows both software address detection and automatic
address detection using 9-bit mode.
The USART includes a fractional baud rate generator. Standard baud rates such as
115200 Bd can be achieved with any crystal frequency above 2 MHz.
7.10.1 Features
• Maximum USART data bit rate of 3.125 MBit/s.
• 16-byte Receive and Transmit FIFOs.
• Register locations conform to 16C550 industry standard.
• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.
• Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
• FIFO control mechanism that enables software flow control implementation.
• Support for RS-485/9-bit mode.
• Supports a full modem control handshake interface.
• Support for synchronous mode.
7.11 SSP serial I/O controller
The LPC11Axx contain two SSP controllers.
The SSP controller is capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can
interact with multiple masters and slaves on the bus. Only a single master and a single
slave can communicate on the bus during a given data transfer. The SSP supports full
duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the
slave and from the slave to the master. In practice, often only one of these data flows
carries meaningful data.
7.11.1 Features
• Maximum SSP speed of 25 Mbit/s (master) or 4.17 Mbit/s (slave) (in SPI mode)
• Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National
Semiconductor Microwire buses
• Synchronous serial communication
• Master or slave operation
• 8-frame FIFOs for both transmit and receive
• 4-bit to 16-bit frame
7.12 I2C-bus serial I/O controller
The LPC11Axx contains one I2C-bus controller.
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The I2C-bus is bidirectional for inter-IC control using only two wires: a serial clock line
(SCL) and a serial data line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the
capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be
controlled by more than one bus master connected to it.
Remark: On the WLCSP package, the bootloader configures the open-drain pins
(PIO0_2 and PIO0_3) for the Serial Wire Debug (SWD) function.
7.12.1 Features
• The I2C-interface is a standard I2C-bus compliant interface with open-drain pins
(PIO0_2 and PIO0_3). The I2C-bus interface also supports Fast-mode Plus with bit
rates up to 1 Mbit/s. For the I2C-bus specification, see UM10204.
• The true open-drain pins PIO0_2 and PIO0_3 can be configured with a 50 ns digital
input glitch filter.
• If the true open-drain pins are used for other purposes, a limited-performance I2C-bus
interface can be configured from a choice of six GPIO pins configured in open-drain
mode and with a pull-up resistor. In this mode, typical bit rates of up to 100 kbit/s with
20 pF load are supported if the internal pull-ups are enabled. Higher bit rates can be
achieved with an external resistor.
• Fail-safe operation: When the power to an I2C-bus device is switched off, the SDA
and SCL pins connected to the I2C-bus are floating and do not disturb the bus.
• Easy to configure as master, slave, or master/slave.
• ROM-based I2C-bus driver routines to easily create applications.
• Programmable clocks allow versatile rate control.
• Bidirectional data transfer between masters and slaves.
• Multi-master bus (no central master).
• Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
• Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
• Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
• The I2C-bus can be used for test and diagnostic purposes.
• The I2C-bus controller supports multiple address recognition and a bus monitor mode.
7.13 Configurable analog/mixed-signal subsystems
Multiple analog/mixed-signal subsystems can be configured by software from
interconnected digital and analog peripherals. See Figure 6.
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CONFIGURABLE ANALOG/MIXED-SIGNAL SUBSYSTEM
AD[7:0]
10-bit ADC
ATRG[1:0]
TRIG
TEMPERATURE
SENSOR
32-bit TIMER
CAP MAT
0.9 V VOLTAGE
REFERENCE
16-bit TIMER
CAP MAT
10-bit
DAC
TRIG
AOUT
VDD(3V3)
VDDCMP
VOLTAGE
DIVIDER REF
ANALOG
COMPARATOR
ACMP_O
ACMP_I[5:1]
INTERRUPT
CONTROLLER
EDGE DETECT
ARM
CORTEX-M0
analog
digital
SIGNAL LEGEND:
aaa-003042
Fig 6. Configurable analog/mixed signal subsystem
7.14 10-bit ADC
The LPC11Axx contains one ADC. It is a single 10-bit successive approximation ADC with
eight channels.
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TEMPERATURE
SENSOR
to
10-bit ADC
comparator
INPUT
MUX
SENSOR
AD7
to
IOCONFIG
comparator
INTERNAL
VOLTAGE REFERENCE
AD6
ADC
IOCONFIG
IOCONFIG
AD5
AD0
ADC control
register
IOCONFIG
aaa-003043
Fig 7. ADC block diagram
7.14.1 Features
• 10-bit successive approximation ADC.
• Input multiplexing among 8 pins.
• Power-down mode.
• Measurement range 0 V to VDD(3V3)
.
• 10-bit conversion time 2.44 s (up to 400 kSamples/s).
• Burst conversion mode for single or multiple inputs.
• Optional conversion on transition of input pins ATRG0 or ATRG1, timer match signal,
or comparator output. (Input signals must be held for a minimum of three system clock
periods). Also see Section 12.2.
• Individual result registers for each ADC channel to reduce interrupt overhead.
7.15 Internal voltage reference
The internal voltage reference is an accurate 0.9 V and is the output of a low voltage band
gap circuit. A typical value at Tamb = 25 C is 0.903 V and varies typically only 3 mV over
the 0 C to 85 C temperature range (see Table 21 and Figure 27). The internal voltage
reference can be used in the following applications:
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• When the supply voltage VDD(3V3) is known accurately, the internal voltage reference
can be used to reduce the offset error EO of the ADC code output. The ADC error
correction then increases the accuracy of temperature sensor voltage output
measurements.
• When the ADC is accurately calibrated, the internal voltage reference can be used to
measure the power supply voltage. This requires calibration by recording the ADC
code of the internal voltage reference at different power supply levels yielding a
different ADC code value for each supply voltage level. In a particular application, the
internal voltage reference can be measured and the actual power supply voltage can
be determined from the stored calibration values. The calibration values can be stored
in the EEPROM for easy access.
After power-up and after switching the input channels of the ADC or the comparator, the
internal voltage reference must be allowed to settle to its stable value before it can be
used as an ADC reference voltage input. Settling times are given in Table 21.
For an accurate measurement of the internal voltage reference by the ADC, the ADC must
be configured in single-channel burst mode. The last value of a nine-conversion (or more)
burst provides an accurate result.
7.16 Temperature sensor
The temperature sensor transducer uses an intrinsic pn-junction diode reference and
outputs a CTAT voltage (Complement To Absolute Temperature). The output voltage
varies inversely with device temperature with an absolute accuracy of better than 3 C
over the full temperature range (40 C to +85 C). The temperature sensor is only
approximately linear with a slight curvature. The output voltage is measured over different
ranges of temperatures and fit with linear-least-square lines. See Table 23 and Figure 28.
For a voltage to temperature conversion, the temperature for a given voltage is calculated
using the parameters of the linear-least-square line (see Table 23).
After power-up and after switching the input channels of the ADC or the comparator, the
temperature sensor output must be allowed to settle to its stable value before it can be
used as an accurate ADC input. Settling times are given in Table 22.
For an accurate measurement of the temperature sensor by the ADC, the ADC must be
configured in single-channel burst mode. The last value of a nine-conversion (or more)
burst provides an accurate result.
7.17 10-bit DAC
The DAC allows generation of a variable, rail-to-rail analog output.
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APB REGISTERS
10
INPUT
REGISTER
10
DAC
AOUT
D/A
CONVERTER
CONTROL
AND DATA
REGISTER
aaa-003044
Fig 8. DAC block diagram
7.17.1 Features
• 10-bit DAC.
• Resistor string architecture.
• Buffered output.
• Power-down mode.
• Conversion speed controlled via a programmable bias current.
• Optional output update modes:
– write operations to the DAC register.
– a transition of pins ATRG0 or ATRG1. Input signals must be held for a minimum of
three system clock periods.
– a timer match signal.
– a comparator output signal held for a minimum of two system clock periods.
• Holds output value during Sleep mode if the DAC is not powered down.
7.18 Analog comparator
The analog comparator with selectable hysteresis can compare voltage levels on external
pins and internal voltages. See Table 24.
After power-up and after switching the input channels of the comparator, the output of the
voltage ladder must be allowed to settle to its stable value before it can be used as a
comparator reference input. Settling times are given in Table 25.
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COMPARATOR ANALOG BLOCK
COMPARATOR DIGITAL BLOCK
V
DD
VDDCMP
to ADC and DAC
5
32
comparator
level
sync
edge detect
comparator
edge
internal
voltage
reference
temperature
sensor
5
ACMPI[5:1]
aaa-003045
Fig 9. Comparator block diagram
7.18.1 Features
• Selectable 0 mV, 10 mV ( 5 mV), and 20 mV ( 10 mV), 40 mV ( 20 mV) input
hysteresis.
• Five selectable external voltages; fully configurable on either positive or negative
input channel.
• Internal voltage reference from band gap and temperature sensor selectable on either
positive or negative input channel.
• 32-stage voltage ladder with the internal reference voltage selectable on either the
positive or the negative input channel. See Table 24 to Table 26.
• Voltage ladder source voltage is selectable from an external pin or the main 3.3 V
supply voltage rail.
• Voltage ladder can be separately powered down for applications only requiring the
comparator function.
• Interrupt output is connected to NVIC.
• Comparator level output is connected to output pin ACMP_O.
• Comparator output is internally connected to the ADC and DAC and can be used to
trigger a conversion.
• The comparator output is also connected internally to capture channel 3 on each of
the 32-bit and 16-bit counter/timers.
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7.19 General purpose external event counter/timers
The LPC11Axx includes two 32-bit counter/timers and two 16-bit counter/timers. The
counter/timer is designed to count cycles of the system derived clock. It can optionally
generate interrupts or perform other actions at specified timer values, based on four
match registers. Each counter/timer also includes four capture inputs to trap the timer
value when an input signal transitions, optionally generating an interrupt.
7.19.1 Features
• A 32-bit/16-bit timer/counter with a programmable 32-bit/16-bit prescaler.
• Counter or timer operation.
• Four capture channels per timer, that can take a snapshot of the timer value when an
input signal transitions. A capture event may also generate an interrupt. Up to three
capture channels are pinned out. One channel is internally connected to the
comparator output ACMP_O.
• Four match registers per timer that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
• Up to four external outputs corresponding to match registers, with the following
capabilities:
– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.
7.20 System tick timer
The ARM Cortex-M0 includes a system tick timer (SYSTICK) that is intended to generate
a dedicated SYSTICK exception at a fixed time interval (typically 10 ms).
7.21 Windowed WatchDog Timer (WWDT)
The purpose of the watchdog is to reset the controller if software fails to periodically
service it within a programmable time window.
7.21.1 Features
• Internally resets chip if not periodically reloaded during the programmable time-out
period.
• Optional windowed operation requires reload to occur between a minimum and
maximum time period, both programmable.
• Optional warning interrupt can be generated at a programmable time prior to
watchdog time-out.
• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
• Incorrect feed sequence causes reset or interrupt if enabled.
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• Flag to indicate watchdog reset.
• Programmable 24-bit timer with internal prescaler.
• Selectable time period from (Tcy(WDCLK) 256 4) to (Tcy(WDCLK) 224 4) in
multiples of Tcy(WDCLK) 4.
• The Watchdog Clock (WDCLK) source can be selected from the internal RC oscillator
(IRC), or the dedicated watchdog oscillator (WDOsc). This gives a wide range of
potential timing choices of watchdog operation under different power conditions.
7.22 Clocking and power control
7.22.1 Crystal and internal oscillators
The LPC11Axx include four independent oscillators.
1. The crystal oscillator (SysOsc) operating at frequencies between 1 MHz and 25 MHz.
2. The internal RC Oscillator (IRC) with a fixed frequency of 12 MHz, trimmed to 1%
accuracy.
3. The internal low-power, Low-Frequency Oscillator (LFOsc) with a programmable
nominal frequency between 9.4 kHz and 2.3 MHz with 40% accuracy.
4. The dedicated Watchdog Oscillator (WDOsc) with a programmable nominal
frequency between 9.4 kHz and 2.3 MHz with 40% accuracy.
Each oscillator, except the WDOsc, can be used for more than one purpose as required in
a particular application.
Following reset, the LPC11Axx will operate from the IRC until switched by software. This
allows systems to operate without any external crystal and the bootloader code to operate
at a known frequency.
See Figure 10 for an overview of the LPC11Axx clock generation.
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system
system clock
SYSTEM CLOCK
DIVIDER
18
memories
and peripherals
SYSCLKCTRL[1:18]
SSP0 PERIPHERAL
CLOCK DIVIDER
SSP0
IRC
main clock
USART PERIPHERAL
CLOCK DIVIDER
USART
SSP1
LFOsc
SSP1 PERIPHERAL
CLOCK DIVIDER
MAINCLKSEL
(main clock select)
IRC
SysOsc
CLKIN
IRC
SysOsc
LFOsc
SYSTEM PLL
CLKOUT PIN CLOCK
DIVIDER
CLKOUT pin
SYSPLLCLKSEL
(system PLL clock select)
CLKOUTUEN
(CLKOUT update enable)
IRC
WWDT CLOCK
DIVIDER
WWDT
WDOsc
WDCLKSEL
002aaf430
Fig 10. LPC11Axx clock generation block diagram
7.22.1.1 Internal RC Oscillator (IRC)
The IRC may be used as the clock source for the WWDT, and/or as the clock that drives
the PLL and subsequently the CPU. The nominal IRC frequency is 12 MHz. The IRC is
trimmed to 1 % accuracy over the entire voltage and temperature range.
The IRC can be used as a clock source for the CPU with or without using the PLL. The
IRC frequency can be boosted to a higher frequency, up to the maximum CPU operating
frequency, by the system PLL.
Upon power-up or any chip reset, the LPC11Axx use the IRC as the clock source.
Software may later switch to one of the other available clock sources.
7.22.1.2 Crystal Oscillator (SysOsc)
The crystal oscillator can be used as the clock source for the CPU, with or without using
the PLL.
The SysOsc operates at frequencies of 1 MHz to 25 MHz. This frequency can be boosted
to a higher frequency, up to the maximum CPU operating frequency, by the system PLL.
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7.22.1.3 Internal Low-Frequency Oscillator (LFOsc) and Watchdog Oscillator (WDOsc)
The LFOsc and the WDOsc are identical internal oscillators. The nominal frequency is
programmable between 9.4 kHz and 2.3 MHz. The frequency spread over silicon process
variations is 40%.
The WDOsc is a dedicated oscillator for the windowed WWDT.
The LFOsc can be used as a clock source that directly drives the CPU or the CLKOUT
pin.
7.22.2 Clock input
A 3.3 V external clock source (25 MHz typical) can be supplied on the selected CLKIN pin
or a 1.8 V external clock source can be supplied on the XTALIN pin (see Section 12.3).
7.22.3 System PLL
The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input
frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO).
The multiplier can be an integer value from 1 to 32. The CCO operates in the range of
156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within
its frequency range while the PLL is providing the desired output frequency. The output
divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the
minimum output divider value is 2, it is insured that the PLL output has a 50 % duty cycle.
The PLL is turned off and bypassed following a chip reset and may be enabled by
software. The program must configure and activate the PLL, wait for the PLL to lock, and
then connect to the PLL as a clock source. The PLL settling time is 100 s.
7.22.4 Clock output
The LPC11Axx features a clock output function that routes the IRC, the SysOsc, the
LFOsc, or the main clock to an output pin.
7.22.5 Wake-up process
The LPC11Axx begin operation at power-up by using the IRC as the clock source. This
allows chip operation to resume quickly. If the SysOsc, the external clock source, or the
PLL is needed by the application, software will need to enable these features and wait for
them to stabilize before they are used as a clock source.
7.22.6 Power control
The LPC11Axx supports the ARM Cortex-M0 Sleep mode. The CPU clock rate may also
be controlled as needed by changing clock sources, reconfiguring PLL values, and/or
altering the CPU clock divider value. This allows a trade-off of power versus processing
speed based on application requirements. In addition, a register is provided for shutting
down the clocks to individual on-chip peripherals, allowing fine tuning of power
consumption by eliminating all dynamic power use in any peripherals that are not required
for the application. Selected peripherals have their own clock divider which provides even
better power control.
7.22.6.1 Sleep mode
When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep
mode does not need any special sequence but re-enabling the clock to the ARM core.
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In Sleep mode, execution of instructions is suspended until either a reset or interrupt
occurs. Peripheral functions continue operation during Sleep mode and may generate
interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic
power used by the processor itself, memory systems and related controllers, and internal
buses.
7.22.6.2 Power profiles
The power consumption in Active and Sleep modes can be optimized for the application
through simple calls to the power profile. The power configuration routine configures the
LPC11Axx for one of the following power modes:
• Default mode corresponding to power configuration after reset.
• CPU performance mode corresponding to optimized processing capability.
• Efficiency mode corresponding to optimized balance of current consumption and CPU
performance.
• Low-current mode corresponding to lowest power consumption.
In addition, the power profile includes routines to select the optimal PLL settings for a
given system clock and PLL input clock.
7.23 System control
7.23.1 UnderVoltage LockOut (UVLO) protection
The BOD and POR circuits remain enabled at all times to provide UVLO protection from
an unexpected power supply droop below a typical threshold level of 2.4 V (see also the
LPC11Axx user manual). UVLO protection means that the LPC11Axx is held in reset
whenever the supply voltage falls below 2.4 V.
See also Section 10.1 “Power supply fluctuations”, Section 12.7 “UVLO protection and
reset timer circuit”, and Section 12.8 “Guidelines for selecting a power supply filter for
UVLO protection”.
7.23.2 Reset
Reset has several sources on the LPC11Axx: the RESET pin, the Watchdog reset,
power-on reset (POR), the ARM SYSRESETREQ software request, and the Brown-Out
Detection (BOD) circuit. After the BOD and the POR resets are released, the internal reset
timer counts for 100 μs until the internal reset is removed.
Assertion of chip reset by any source (after the operating voltage attains a usable level)
starts the IRC and initializes the flash memory controller.
When the internal Reset is removed, the processor begins executing at address 0, which
is initially the Reset vector mapped from the boot block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.
Writing to a special function register allows the software to reset the following peripherals:
the I2C-bus interface, the USART, both SSP controllers, the four counter/timers, the
comparator, the ADC, and the DAC.
The RESET pin is a Schmitt trigger input pin and uses a special pad. See Figure 32.
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7.23.3 Brown-out detection
The LPC11Axx include two programmable levels for monitoring the voltage on the
DD(3V3) pin. If this voltage falls below the selected level, the BOD asserts an interrupt
V
signal to the NVIC. This signal can be enabled for interrupt in the Interrupt Enable
Register in the NVIC in order to cause a CPU interrupt; alternatively, software can monitor
the signal by reading a dedicated status register. In addition, the BOD circuit supports one
hardware controlled voltage level for triggering a chip reset.
7.23.4 Code security (Code Read Protection - CRP)
This feature of the LPC11Axx allows user to enable different levels of security in the
system so that access to the on-chip flash and use of the Serial Wire Debugger (SWD)
and In-System-Programming (ISP) can be restricted. When needed, CRP is invoked by
programming a specific pattern into a dedicated flash location. IAP commands are not
affected by the CRP.
In addition, ISP entry via the PIO0_1 pin can be disabled without enabling CRP. For
details see the LPC11Axx user manual.
There are three levels of Code Read Protection:
1. CRP1 disables access to the chip via the SWD and allows partial flash update
(excluding flash sector 0) using a limited set of the ISP commands. This mode is
useful when CRP is required and flash field updates are needed but all sectors can
not be erased.
2. CRP2 disables access to the chip via the SWD and only allows full flash erase and
update using a reduced set of the ISP commands.
3. Running an application with level CRP3 selected fully disables any access to the chip
via the SWD pins and the ISP. This mode effectively disables ISP override using
PIO0_1 pin, too. It is up to the user’s application to provide (if needed) flash update
mechanism using IAP calls or call reinvoke ISP command to enable flash update via
the USART.
CAUTION
If level three Code Read Protection (CRP3) is selected, no future factory testing can be
performed on the device.
In addition to the three CRP levels, sampling of pin PIO0_1 for valid user code can be
disabled. For details see the LPC11Axx user manual.
7.23.5 APB interface
The APB peripherals are located on one APB bus.
7.23.6 AHBLite
The AHBLite connects the CPU bus of the ARM Cortex-M0 to the flash memory, the main
static RAM, and the Boot ROM.
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7.23.7 External interrupt inputs
All GPIO pins can be level or edge sensitive interrupt inputs.
7.24 Emulation and debugging
Debug functions are integrated into the ARM Cortex-M0. JTAG and Serial Wire Debug
(SWD) with four breakpoints and two watchpoints are supported.
The RESET pin selects between the JTAG boundary scan (RESET = LOW) and the ARM
SWD debug (RESET = HIGH). The ARM SWD debug port is disabled while the
LPC11Axx is in reset.
To perform boundary scan testing, follow these steps:
1. Erase any user code residing in flash.
2. Power up the part with the RESET pin pulled HIGH externally.
3. Wait for at least 250 s.
4. Pull the RESET pin LOW externally.
5. Perform boundary scan operations.
6. Once the boundary scan operations are completed, assert the TRST pin to enable the
SWD debug mode and release the RESET pin (pull HIGH).
Remark: The JTAG interface cannot be used for debug purposes.
On the WLCSP package, the TCK signal is shared with the VDDCMP input on pin
PIO0_5. To perform a boundary scan on a blank device, make sure that the PIO0_5 pin is
not filtered on the board. The bypass filter usually added to the comparator voltage
reference input (VDDCMP) filters out the SWCLK/TCK input signal.
For SWD debug, an alternative TCK/SWCLK clock pin is available on pin PIO0_2. This is
the default function after booting for the WLCSP package.
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8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).[1]
Symbol
VDD(3V3)
VDD(IO)
VI
Parameter
Conditions
Min
0.5
0.5
0.5
Max
4.6
Unit
V
[2]
[2]
supply voltage (3.3 V)
input/output supply voltage
input voltage
4.6
V
[3][4]
5 V tolerant I/O
pins; only valid
when the VDD(IO)
supply voltage is
present
+5.5
V
[5]
[6]
on pins PIO0_2
and PIO0_3
0.5
0.5
+5.5
+3.6
V
V
3 V tolerant I/O
pins without
over-voltage
protection
[7][8]
[9]
VIA
analog input voltage
0.5 V
4.6
V
[2]
Vi(xtal)
IDD
crystal input voltage
supply current
0.5
+2.5
100
100
100
V
per supply pin
per ground pin
-
-
-
mA
mA
mA
ISS
ground current
Ilatch
I/O latch-up current
(0.5VDD(IO)) < VI <
(1.5VDD(IO));
Tj < 125 C
[10]
Tstg
storage temperature
65
+150
150
1.5
C
C
W
Tj(max)
Ptot(pack)
maximum junction temperature
total power dissipation (per package)
-
-
based on package
heat transfer, not
device power
consumption
[11]
[12]
Vesd
Vtrig
electrostatic discharge voltage
trigger voltage
human body
model; all pins
6.5
+6.5
-
kV
V
for LVTSCR based
ESD pin protection;
8.2
1 ns to 10 ns rise
time
10 ns rise time
8.5
-
V
[1] The following applies to the limiting values:
a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive
static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated
maximum.
b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless
otherwise noted.
[2] Maximum/minimum voltage above the maximum operating voltage (see Table 6) and below ground that can be applied for a short time
(< 10 ms) to a device without leading to irrecoverable failure. Failure includes the loss of reliability and shorter lifetime of the device.
[3] Applies to all 5 V tolerant I/O pins except true open-drain pins PIO0_2 and PIO0_3 and except the 3 V tolerant pins PIO0_4 and
PIO0_14 (LQFP and HVQFN packages) or PIO0_5 (WLCSP package).
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[4] Including the voltage on outputs in 3-state mode.
[5]
V
DD(IO) present or not present. Compliant with the I2C-bus standard. 5.5 V can be applied to this pin when VDD(IO) is powered down.
[6] Applies to 3 V tolerant pins PIO0_4 and PIO0_14 (LQFP and HVQFN packages) or PIO0_5 (WLCSP package).
[7] An ADC input voltage above 3.6 V can be applied for a short time without leading to immediate, unrecoverable failure. Accumulated
exposure to elevated voltages at 4.6 V must be less than 106 s total over the lifetime of the device. Applying an elevated voltage to the
ADC inputs for a long time affects the reliability of the device and reduces its lifetime.
[8] If the comparator is configured with the common mode input VIC = VDD, the other comparator input can be up to 0.2 V above or below
VDD without affecting the hysteresis range of the comparator function.
[9] It is recommended to connect an overvoltage protection diode between the analog input pin and the voltage supply pin.
[10] Dependent on package type.
[11] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.
[12] Not characterized.
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9. Static characteristics
Table 6.
Static characteristics
Tamb = 40 C to +85 C, unless otherwise specified.
Symbol
VDD(3V3)
VDD(IO)
Parameter
Conditions
Min
2.6
2.6
Typ[1]
3.3
Max
3.6
Unit
V
supply voltage (3.3 V)
input/output supply
voltage
3.3
3.6
V
IDD
supply current
Active mode; code
while(1){}
executed from flash;
VDD(3V3) = VDD(IO) = 3.3 V;
low-current mode (see
Section 7.22.6.2)
[2][4][5]
[2][6][5]
systemclock = 12 MHz;
all peripherals disabled
-
-
3
8
-
-
mA
mA
systemclock = 48 MHz;
all peripherals disabled
Sleep mode;
system clock = 12 MHz;
VDD(3V3) = VDD(IO) = 3.3 V;
low-current mode (see
Section 7.22.6.2)
[2][4][5]
[2][4][5]
all peripherals disabled;
12 MHz
-
-
2
5
-
-
mA
mA
all peripherals disabled;
48 MHz
Standard port pins, RESET
IIL
LOW-level input current VI = 0 V; on-chip pull-up
resistor disabled
-
-
0.5
0.5
1000
1000
nA
nA
IIH
HIGH-level input
current
VI = VDD(IO); on-chip
pull-down resistor
disabled
IOZ
OFF-state output
current
VO = 0 V; VO = VDD(IO)
on-chip pull-up/down
resistors disabled
;
-
0.5
-
1000
5.0
nA
V
[7][8]
[7][8]
VI
input voltage
pin configured to provide
a digital function
0
5 V tolerant pins
3 V tolerant pins:
VDD(IO)
PIO0_4 and PIO0_14
(LQFP and HVQFN
packages) or PIO0_5
(HVQFN package)
VO
output voltage
output active
0
-
-
VDD(IO)
-
V
V
VIH
HIGH-level input
voltage
0.7VDD(IO)
VIL
LOW-level input voltage
hysteresis voltage
-
-
-
0.3VDD(IO)
-
V
V
Vhys
3.0 V VDD(IO) 3.6 V
0.4
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Table 6.
Static characteristics …continued
Tamb = 40 C to +85 C, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
VOH
HIGH-level output
voltage
2.6 V VDD(IO) 3.6 V;
IOH = 4 mA
0.85VDD(IO)
-
-
V
VOL
IOH
LOW-level output
voltage
2.6 V VDD(IO) 3.6 V;
-
-
-
0.15VDD(IO)
-
V
I
OL = 4 mA
HIGH-level output
current
VOH = VDD(IO) 0.4 V;
2.6 V VDD(IO) 3.6 V
VOL = 0.4 V
4
mA
IOL
LOW-level output
current
4
-
-
mA
2.6 V VDD(IO) 3.6 V
[9]
[9]
IOHS
IOLS
HIGH-level short-circuit VOH = 0 V
output current
-
-
-
-
45
mA
mA
LOW-level short-circuit VOL = VDD(IO)
output current
50
[10]
Ipd
Ipu
pull-down current
pull-up current
VI = 5 V
VI = 0 V;
10
50
150
A
A
15
50
85
2.6 V VDD(IO) 3.6 V
VDD(IO) < VI < 5 V
0
0
0
A
High-drive output pin (PIO0_21)
IIL
LOW-level input current VI = 0 V; on-chip pull-up
resistor disabled
-
-
0.5
0.5
10
10
nA
nA
IIH
HIGH-level input
current
VI = VDD(IO); on-chip
pull-down resistor
disabled
IOZ
OFF-state output
current
VO = 0 V; VO = VDD(IO)
on-chip pull-up/down
resistors disabled
;
-
0.5
-
10
nA
V
[7][8]
VI
input voltage
pin configured to provide
a digital function
0
5.0
VO
output voltage
output active
0
-
-
VDD(IO)
-
V
V
VIH
HIGH-level input
voltage
0.7VDD(IO)
VIL
LOW-level input voltage
hysteresis voltage
-
-
-
-
0.3VDD(IO)
V
V
V
Vhys
VOH
0.4
-
-
HIGH-level output
voltage
2.6 V VDD(IO) 3.6 V;
IOH = 20 mA
VDD(IO)
0.4
2.6 V VDD(IO) 2.5 V;
VDD(IO)
0.4
-
-
-
V
V
I
OH = 12 mA
VOL
LOW-level output
voltage
2.6 V VDD(IO) 3.6 V;
IOL = 4 mA
-
0.4
IOH
HIGH-level output
current
VOH = VDD(IO) 0.4 V;
2.6 V VDD(IO) 3.6 V
VOL = 0.4 V
20
4
-
-
-
-
mA
mA
IOL
LOW-level output
current
2.6 V VDD(IO) 3.6 V
LPC11AXX
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Table 6.
Static characteristics …continued
Tamb = 40 C to +85 C, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
[9]
[9]
IOHS
HIGH-level short-circuit VOH = 0 V
output current
-
-
160
mA
IOLS
LOW-level short-circuit VOL = VDD(IO)
output current
-
-
50
mA
Ipd
Ipu
pull-down current
pull-up current
VI = 5 V
VI = 0 V
10
50
150
A
A
15
50
85
2.6 V VDD(IO) 3.6 V
VDD(IO) < VI < 5 V
0
0
-
0
-
A
I2C-bus pins (PIO0_2 and PIO0_3)
VIH
HIGH-level input
voltage
0.7VDD(IO)
V
VIL
LOW-level input voltage
hysteresis voltage
-
-
0.3VDD(IO)
V
Vhys
IOL
-
0.05VDD(IO)
-
-
-
V
LOW-level output
current
VOL = 0.4 V; I2C-bus pins
configured as standard
mode pins
4
mA
2.6 V VDD(IO) 3.6 V
IOL
LOW-level output
current
VOL = 0.4 V; I2C-bus pins
configured as high-current
sink pins
20
-
-
mA
2.6 V VDD(IO) 3.6 V
VI = VDD(IO)
[11]
ILI
input leakage current
-
-
2
4
A
A
VI = 5 V
10
22
Oscillator pins
Vi(xtal)
crystal input voltage
crystal output voltage
0.5
0.5
1.8
1.8
1.95
1.95
V
V
Vo(xtal)
[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.
[2] Tamb = 25 C.
[3]
IDD measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled.
[4] IRC enabled; SysOsc disabled; system PLL disabled.
[5] All digital peripherals disabled in the SYSCLKCTRL register except ROM, RAM, and flash. Peripheral clocks to USART and SSP0/1
disabled in system configuration block. Analog peripherals disabled in the PDRUNCFG register except flash memory.
[6] IRC disabled; SysOsc enabled; system PLL enabled.
[7] Including voltage on outputs in 3-state mode.
[8] All supply voltages must be present.
[9] Allowed as long as the current limit does not exceed the maximum current allowed by the device.
[10] Does not apply to 3 V tolerant pins PIO0_4 and PIO0_14 (LQFP and HVQFN packages) or PIO0_5 (HVQFN package).
[11] To VSS
.
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9.1 Power consumption
Power measurements in Active and Sleep modes were performed under the following
conditions (see LPC11Axx user manual):
• Configure all pins as GPIO with pull-up resistor disabled in the IOCON block.
• Configure GPIO pins as outputs using the GPIOnDIR registers.
• Write 0 to all GPIO DIR registers to drive the outputs LOW.
002aah184
8
I
DD
(2)
(2)
48 MHz
36 MHz
(mA)
6.4
4.8
3.2
1.6
0
(2)
(1)
24 MHz
12 MHz
-40
-15
10
35
60
85
temperature (°C)
Conditions: VDD(3V3) = 3.3 V; active mode entered executing code while(1){} from flash; all
peripherals disabled in the SYSAHBCLKCTRL register; all peripheral clocks disabled; all analog
peripherals disabled in the PDRUNCFG register; low-current mode (see Section 7.22.6.2).
(1) SysOsc and system PLL disabled; IRC enabled.
(2) SysOsc and system PLL enabled; IRC disabled.
Fig 11. Active mode: Typical supply current IDD versus temperature for different system
clock frequencies (all peripherals disabled)
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LPC11Axx
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
002aah185
8
I
DD
(2)
(2)
48 MHz
36 MHz
(mA)
6.4
4.8
3.2
1.6
0
(2)
(1)
24 MHz
12 MHz
2.7
3
3.3
3.6
V
(V)
DD(3V3)
Conditions: Tamb = 25 °C; active mode entered executing code while(1){} from flash; all peripherals
disabled in the SYSAHBCLKCTRL register; all peripheral clocks disabled; all analog peripherals
disabled in the PDRUNCFG register; low-current mode (see Section 7.22.6.2).
(1) SysOsc and system PLL disabled; IRC enabled.
(2) SysOsc and system PLL enabled; IRC disabled.
Fig 12. Active mode: Typical supply current IDD versus core voltage VDD(3V3) for different
system clock frequencies (all peripherals disabled)
002aah186
8
I
DD
(mA)
6.4
(2)
(2)
4.8
3.2
1.6
0
48 MHz
36 MHz
(2)
(1)
24 MHz
12 MHz
-40
-15
10
35
60
85
temperature (°C)
Conditions: VDD(3V3) = 3.3 V; sleep mode entered from flash; all peripherals disabled in the
SYSAHBCLKCTRL register and PDRUNCFG register; all peripheral clocks disabled; BOD
disabled; low-current mode (see Section 7.22.6.2).
(1) SysOsc and system PLL disabled; IRC enabled.
(2) SysOsc and system PLL enabled; IRC disabled.
Fig 13. Sleep mode: Typical supply current IDDversus temperature for different system
clock frequencies (all peripherals disabled)
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NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
9.2 Peripheral power consumption
The supply current per peripheral is measured as the difference in supply current between
the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG
and PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both
registers and no code is executed. Measured on a typical sample at Tamb = 25 C.
Table 7.
Power consumption for individual analog and digital blocks
Peripheral
Typical supply
current in mA
12 MHz[1]
Average A/MHz
Analog peripherals
BOD
0.05
0.14
0.40
0.26
0.01
0.01
-
-
-
-
-
-
BOD, comparator
BOD, comparator, ADC, DAC, temperature sensor
DAC
ADC
Temperature sensor, ADC
Digital peripherals
USART
0.15
0.02
0.02
0.02
0.02
12
2
I2C
16-bit counter/timer 0/1
32-bit counter/timer 0/1
WWDT
2
2
2
[1] IRC on; PLL off.
9.3 Electrical pin characteristics
002aae990
3.6
V
(V)
OH
T = 85 °C
25 °C
−40 °C
3.2
2.8
2.4
2
0
10
20
30
40
50
60
I
(mA)
OH
Conditions: VDD(IO) = 3.3 V; on pin PIO0_21.
Fig 14. High-current source output driver: Typical HIGH-level output voltage VOH versus
HIGH-level output current IOH
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32-bit ARM Cortex-M0 microcontroller
002aaf019
60
I
T = 85 °C
25 °C
−40 °C
OL
(mA)
40
20
0
0
0.2
0.4
0.6
V
(V)
OL
Conditions: VDD(IO) = 3.3 V; on pins PIO0_2 and PIO0_3.
Fig 15. High-current sink pins: Typical LOW-level output current IOL versus LOW-level
output voltage VOL
002aae991
15
I
OL
T = 85 °C
25 °C
−40 °C
(mA)
10
5
0
0
0.2
0.4
0.6
V
(V)
OL
Conditions: VDD(IO) = 3.3 V; standard port pins and PIO0_21.
Fig 16. Typical LOW-level output current IOL versus LOW-level output voltage VOL
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002aae992
3.6
V
OH
(V)
T = 85 °C
25 °C
−40 °C
3.2
2.8
2.4
2
0
8
16
24
I
(mA)
OH
Conditions: VDD(IO) = 3.3 V; standard port pins.
Fig 17. Typical HIGH-level output voltage VOH versus HIGH-level output source current
IOH
002aae988
10
I
pu
(μA)
−10
−30
−50
−70
T = 85 °C
25 °C
−40 °C
0
1
2
3
4
5
V (V)
I
Conditions: VDD(IO) = 3.3 V; standard port pins.
Fig 18. Typical pull-up current Ipu versus input voltage VI
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32-bit ARM Cortex-M0 microcontroller
002aae989
80
T = 85 °C
25 °C
−40 °C
I
pd
(μA)
60
40
20
0
0
1
2
3
4
5
V (V)
I
Conditions: VDD(IO) = 3.3 V; standard port pins.
Fig 19. Typical pull-down current Ipd versus input voltage VI
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10. Dynamic characteristics
10.1 Power supply fluctuations
If the input voltage (VDD(3V3)) to the internal regulator fluctuates, the LPC11Axx is held in
reset during a brown-out condition as long as the UVLO circuit is operating. The settling
times of the BOD and POR circuits, which constitute the UVLO, determine the minimum
time the supply level must remain in the shallow or deep brown-out condition to ensure
that the internal reset is asserted properly.
See also Section 7.23.1, Section 12.7, and Section 12.8.
Table 8.
Symbol Parameter
ts settling time power droop:
from active level to shallow
UVLO circuits settling characteristics
Conditions
Min
Typ Max Unit
5
-
-
s
brown-out level
(0.9 V VDD(3V3) 2.4 V)
from active level to deep brown-out
level (0 < VDD(3V3) < 0.9 V)
12
-
-
s
supply
voltage
V
DD(3V3)
cold
start-up
brown-out
shallow
brown-out
deep
External
power supply
BOD trip point
(typical)
2.4 V
> 5 μs
POR trip point
(typical)
0.9 V
0 V
> 12 μs
internal reset
time
002aah326
Fig 20. UVLO timing
10.2 Flash/EEPROM memory
Table 9.
Flash characteristics
Tamb = 40 C to +85 C. Based on JEDEC NVM qualification. Failure rate < 10 ppm for parts as
specified below.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
[2][1]
Nendu
endurance
10000
100000
-
cycles
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Table 9.
Flash characteristics
Tamb = 40 C to +85 C. Based on JEDEC NVM qualification. Failure rate < 10 ppm for parts as
specified below.
Symbol
Parameter
Conditions
powered
Min
10
Typ
20
Max
Unit
years
years
ms
[2]
[2]
[2]
tret
retention time
-
unpowered
20
40
-
ter
erase time
sector or multiple
consecutive
sectors
95
100
105
[2][3]
tprog
programming
time
0.95
1
1.05
ms
[1] Number of program/erase cycles.
[2] Min and max values are valid for Tamb = 40 C to +85 C only.
[3] Programming times are given for writing 256 bytes to the flash. Tamb < +85 C. Data must be written to the
flash in blocks of 256 bytes. Flash programming is accomplished via IAP calls (see LPC11Axx user
manual). Execution time of IAP calls depends on the system clock and is typically between 1.5 and 2 ms
per 256 bytes.
Table 10. EEPROM characteristics
Tamb = 55 C to +125 C; VDD(3V3) = 2.7 V to 3.6 V. Based on JEDEC NVM qualification. Failure
rate < 10 ppm for parts as specified below.
Symbol
Nendu
tret
Parameter
endurance
Conditions
Min
100000
100
150
-
Typ
Max
Unit
[1]
[1]
[1]
[2]
1000000
200
-
-
-
-
cycles
years
years
ms
retention time
powered
unpowered
64 bytes
300
tprog
programming
time
1.1
[1] Min and max values are valid for Tamb = 40 C to +85 C only.
[2] Tamb < +85 C.
10.3 External clock for oscillator in slave mode
Remark: The input voltage on the XTALIN pin must be 1.95 V (see Table 6). For
connecting the oscillator to the XTALIN/XTALOUT pins also see Section 12.3.
Table 11. Dynamic characteristic: external clock (XTALIN or CLKIN pin)
Tamb = 40 C to +85 C; VDD(3V3) over specified ranges.[1]
Symbol
fosc
Parameter
Conditions
Min
Typ[2]
Max
Unit
MHz
ns
oscillator frequency
clock cycle time
clock HIGH time
clock LOW time
clock rise time
clock fall time
1
-
-
-
-
-
-
25
Tcy(clk)
tCHCX
tCLCX
tCLCH
tCHCL
40
1000
Tcy(clk) 0.4
-
ns
Tcy(clk) 0.4
-
ns
-
-
5
5
ns
ns
[1] Parameters are valid over operating temperature range unless otherwise specified.
[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply
voltages.
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t
CHCX
t
t
t
CHCL
CLCX
CLCH
T
cy(clk)
002aaa907
Fig 21. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV)
10.4 Internal oscillators
Table 12. Dynamic characteristic: IRC
amb = 40 C to +85 C; 2.7 V VDD(3V3) 3.6 V.[1]
T
Symbol Parameter Conditions
fosc(RC) internal RC oscillator frequency -
Min
Typ[2]
Max
Unit
11.88
12
12.12
MHz
[1] Parameters are valid over operating temperature range unless otherwise specified.
[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply
voltages.
002aah011
12.15
f
(MHz)
VDD = 3.6 V
3.3 V
3.0 V
12.05
2.7 V
11.95
11.85
-40
-15
10
35
60
85
temperature (°C)
Conditions: Frequency values are typical values. 12 MHz 1% accuracy is guaranteed for
2.7 V VDD(3V3) 3.6 V and Tamb = 40 C to +85 C. Variations between parts may cause the
IRC to fall outside the 12 MHz 1% accuracy specification for voltages below 2.7 V.
Fig 22. Internal IRC frequency vs. temperature
Table 13. Dynamic characteristics: WDOsc and LFOsc
Symbol Parameter
Conditions
Min Typ[1]
Max Unit
[2][3]
[2][3]
fosc internal oscillator DIVSEL = 0x1F, FREQSEL = 0x1
-
9.4
-
kHz
frequency
in the WDTOSCCTRL register;
DIVSEL = 0x00, FREQSEL = 0xF
in the WDTOSCCTRL register
-
2300
-
kHz
[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply
voltages.
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[2] The typical frequency spread over processing and temperature (Tamb = 40 C to +85 C) is 40%.
[3] See the LPC11Axx user manual.
10.5 I/O pins
Table 14. Dynamic characteristic: digital I/O pins[1]
Tamb = 40 C to +85 C; 3.0 V VDD(IO) 3.6 V; load capacitor = 30 pF.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tr
rise time
pin
configured as
output
[2][3]
[2][3]
[2][4]
[2][3]
SSO = 1
SSO = 6
SSO = 16
2.5
2.5
3.0
-
-
-
5.0
4.5
5.0
ns
ns
ns
tf
fall time
pin
configured as
output
SSO = 1
SSO = 6
SSO = 16
2.0
2.0
2.5
-
-
-
4.5
4.5
5.0
ns
ns
ns
[2][3]
[2][4]
[1] Applies to standard port pins and RESET pin. Simulated results.
[2] SSO indicates maximum number of simultaneously switching digital output pins. The pins are optimized for
half of the maximum SSO.
[3] Set SLEW bit in the IOCON register to 1.
[4] Set SLEW bit in the IOCON register to 0.
10.6 I2C-bus
Remark: All I2C modes (Standard-mode, Fast-mode, Fast-mode Plus) can be configured
for the true open-drain pins PIO0_2 and PIO0_3. If the limited-performance I2C-bus pins
are used (I2C-bus functions on standard I/O pins), only Standard-mode with internal
pull-up enabled or Fast-mode with external pull-up resistor are supported.
Table 15. Dynamic characteristic: I2C-bus pins[1]
Tamb = 40 C to +85 C.[2]
Symbol
Parameter
Conditions
Min
Max
100
400
1
Unit
kHz
kHz
MHz
ns
fSCL
SCL clock
frequency
Standard-mode
Fast-mode
0
0
0
-
Fast-mode Plus
[4][5][6][7]
tf
fall time
of both SDA and
SCL signals
300
Standard-mode
Fast-mode
20 + 0.1 Cb 300
ns
ns
s
s
s
Fast-mode Plus
Standard-mode
Fast-mode
-
120
tLOW
LOW period of
the SCL clock
4.7
1.3
0.5
-
-
-
Fast-mode Plus
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NXP Semiconductors
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Table 15. Dynamic characteristic: I2C-bus pins[1]
Tamb = 40 C to +85 C.[2]
Symbol
Parameter
Conditions
Min
4.0
0.6
0.26
0
Max
Unit
s
s
s
s
s
s
ns
ns
ns
tHIGH
HIGH period of
the SCL clock
Standard-mode
Fast-mode
-
-
-
-
-
-
-
-
-
Fast-mode Plus
Standard-mode
Fast-mode
[3][4][8]
[9][10]
tHD;DAT
data hold time
0
Fast-mode Plus
Standard-mode
Fast-mode
0
tSU;DAT
data set-up
time
250
100
50
Fast-mode Plus
[1] See the I2C-bus specification UM10204 for details.
[2] Parameters are valid over operating temperature range unless otherwise specified.
[3] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission
and the acknowledge.
[4] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the
VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL.
[5] Cb = total capacitance of one bus line in pF.
[6] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA
output stage tf is specified at 250 ns. This allows series protection resistors to be connected in between the
SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf.
[7] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors
are used, designers should allow for this when considering bus timing.
[8] The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than
the maximum of tVD;DAT or tVD;ACK by a transition time (see UM10204). This maximum must only be met if
the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the
data must be valid by the set-up time before it releases the clock.
[9] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in
transmission and the acknowledge.
[10] A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement tSU;DAT
=
250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period
of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next
data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus
specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.
LPC11AXX
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32-bit ARM Cortex-M0 microcontroller
t
t
SU;DAT
f
70 %
30 %
70 %
30 %
SDA
SCL
t
t
HD;DAT
VD;DAT
t
f
t
HIGH
70 %
30 %
70 %
30 %
70 %
30 %
70 %
30 %
t
LOW
1 / f
S
SCL
002aaf425
Fig 23. I2C-bus pins clock timing
10.7 SSP interfaces
Table 16. Dynamic characteristics of SSP pins in SPI mode
2.6 V <= VDD(3V3) = VDD(IO) <= 3.6 V.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
SPI master (in SPI mode)
[1]
Tcy(clk)
clock cycle time
data set-up time
full-duplex mode
when only transmitting
in SPI mode
50
40
15
-
-
-
-
ns
ns
ns
[1][1]
[1][2]
tDS
[1][2]
[1][2]
[1][2]
tDH
data hold time
in SPI mode
0
-
-
-
-
-
ns
ns
ns
tv(Q)
th(Q)
data output valid time in SPI mode
data output hold time in SPI mode
10
-
0
SPI slave (in SPI mode)
Tcy(PCLK) PCLK cycle time
20
0
-
-
-
-
-
-
ns
ns
ns
ns
ns
[3][4]
[3][4]
[3][4]
[3][4]
tDS
data set-up time
data hold time
in SPI mode
in SPI mode
-
tDH
3 Tcy(PCLK) + 4
-
tv(Q)
th(Q)
data output valid time in SPI mode
data output hold time in SPI mode
-
-
3 Tcy(PCLK) + 11
2 Tcy(PCLK) + 5
[1] Tcy(clk) = (SSPCLKDIV (1 + SCR) CPSDVSR) / fmain. The clock cycle time derived from the SPI bit rate Tcy(clk) is a function of the
main clock frequency fmain, the SPI peripheral clock divider (SSPCLKDIV), the SPI SCR parameter (specified in the SSP0CR0 register),
and the SPI CPSDVSR parameter (specified in the SPI clock prescale register).
[2] Tamb = 40 C to 85 C.
[3]
Tcy(clk) = 12 Tcy(PCLK).
[4] Tamb = 25 C; for normal voltage supply range: VDD(io) = vdd(3v3) = 3.3 V.
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T
t
t
clk(L)
cy(clk)
clk(H)
SCK (CPOL = 0)
SCK (CPOL = 1)
MOSI
t
t
h(Q)
v(Q)
DATA VALID
DATA VALID
CPHA = 1
t
t
DH
DS
DATA VALID
DATA VALID
MISO
t
t
h(Q)
v(Q)
DATA VALID
DATA VALID
t
MOSI
MISO
t
CPHA = 0
DS
DH
DATA VALID
DATA VALID
002aae829
Pin names SCK, MISO, and MOSI refer to pins for both SSP peripherals, SSP0 and SSP1.
Fig 24. SSP master timing in SPI mode
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T
t
t
clk(L)
cy(clk)
clk(H)
SCK (CPOL = 0)
SCK (CPOL = 1)
t
t
DH
DS
MOSI
MISO
DATA VALID
DATA VALID
t
t
h(Q)
v(Q)
CPHA = 1
DATA VALID
DATA VALID
t
t
DH
DS
MOSI
MISO
DATA VALID
DATA VALID
DATA VALID
t
t
h(Q)
CPHA = 0
v(Q)
DATA VALID
002aae830
Pin names SCK, MISO, and MOSI refer to pins for both SSP peripherals, SSP0 and SSP1.
Fig 25. SSP slave timing in SPI mode
11. Characteristics of analog peripherals
Table 17. BOD static characteristics[1]
Tamb = 25 C.
Symbol Parameter
Vth threshold voltage
Conditions
Min
Typ
Max
Unit
interrupt level 2
assertion
-
-
2.52
2.66
-
-
V
V
de-assertion
interrupt level 3
assertion
-
-
2.80
2.90
-
-
V
V
de-assertion
[1] Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see
LPC11Axx user manual.
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Table 18. ADC static characteristics
Tamb = 40 C to +85 C unless otherwise specified; ADC frequency 4.5 MHz, VDD(3V3) = 2.7 V to
3.6 V; VSS = 0 V.
Symbol
VIA
Parameter
Conditions
Min Typ Max
Unit
V
analog input voltage
analog input capacitance
differential linearity error
integral non-linearity
offset error
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VDD(3V3)
4
Cia
pF
[1][2]
[3]
ED
1
LSB
LSB
mV
mV
LSB
M
EL(adj)
EO
1.5
20
20
4
[4]
[5]
Verr(FS)
ET
full-scale error voltage
absolute error
[6]
[7][8]
Ri
input resistance
2.5
[1] The ADC is monotonic, there are no missing codes.
[2] The differential linearity error (ED) is the difference between the actual step width and the ideal step width.
See Figure 26.
[3] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and
the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 26.
[4] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the
straight line which fits the ideal curve. See Figure 26.
[5] The full-scale error voltage or gain error (EG) is the difference between the straight line fitting the actual
transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. See
Figure 26.
[6] The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer
curve of the non-calibrated ADC and the ideal transfer curve. See Figure 26.
[7] Tamb = 25 C; maximum sampling frequency fs = 400 kSamples/s and analog input capacitance Cia = 1pF.
[8] Input resistance Ri depends on the sampling frequency fs: Ri = 1 / (fs Cia).
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Table 19. DAC static and dynamic characteristics
VDD(3V3) = 2.7 V to 3.6 V; Tamb = 40 C to +85 C unless otherwise specified
Symbol Parameter
Conditions
Min
Typ Max
Unit
ED
differential
-
-
1
LSB
linearity error
EL(adj)
integral
-
-
1.5
LSB
non-linearity
EO
offset error
-
-
-
20
20
200
-
mV
mV
pF
EG
gain error
-
CL
load capacitance
load resistance
output resistance
-
-
RL
1
-
-
k
[1]
RO
< 40
0.4
fc(DAC)
DAC conversion
frequency
-
1
1
MHz
ts
settling time
-
-
-
s
VO
output voltage
Output voltage range with
less than 1 LSB deviation;
with minimum RL
0.3
VDD(3V3)
0.3
V
connected to ground or
power supply
with minimum RL
connected to ground or
power supply
0.175
-
VDD(3V3)
0.175
V
[1] Measured on typical samples.
Table 20. DAC sampling frequency range and power consumption
Bias bit
Maximum current
700 A
DAC sampling frequency range
0 MHz to 1 MHz
0
1
350 A
0 MHz to 400 kHz
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offset
error
O
gain
error
E
E
G
1023
1022
1021
1020
1019
1018
(2)
7
code
out
(1)
6
5
4
3
2
1
0
(5)
(4)
(3)
1 LSB
(ideal)
1018 1019 1020 1021 1022 1023 1024
1
2
3
4
5
6
7
V
IA
(LSB
)
ideal
offset error
E
O
V
- V
DD(3V3) SS
1024
1 LSB =
002aah327
(1) Example of an actual transfer curve.
(2) The ideal transfer curve.
(3) Differential linearity error (ED).
(4) Integral non-linearity (EL(adj)).
(5) Center of a step of the actual transfer curve.
Fig 26. ADC characteristics
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Table 21. Internal voltage reference static and dynamic characteristics
Symbol Parameter
Conditions
output voltage Tamb = 40 C to +85 C
Tamb = 70 C to 85 C
Tamb = 50 C
Min
Typ
Max
Unit
V
[1]
[2]
[2]
[3]
[2]
[2]
[2]
[3]
VO
0.855 0.900
0.945
-
-
0.906
0.905
-
V
-
V
Tamb = 25 C
0.893 0.903
0.913
V
Tamb = 0 C
-
-
-
-
0.902
0.899
0.896
155
-
V
Tamb = 20 C
-
V
Tamb = 40 C
-
V
ts(pu)
ts(sw)
power-up
settling time
to 99% of VO
195
s
[3]
[4]
switching
to 99% of VO
-
50
75
s
settling time
[1] Characterized through simulation.
[2] Characterized on a typical silicon sample.
[3] Typical values are derived from nominal simulation (VDD(3V3) = 3.3 V; Tamb = 27 C; nominal process
models). Maximum values are derived from worst case simulation (VDD(3V3) = 2.6 V; Tamb = 85 C; slow
process models).
[4] Settling time applies to switching between comparator and ADC channels.
002aag063
910
V
O
(mV)
905
900
895
890
-40
-15
10
35
60
85
temperature (°C)
VDD(3V3) = 3.3 V
Fig 27. Typical internal voltage reference output voltage
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Table 22. Temperature sensor static and dynamic characteristics
VDD(3V3) = 2.6 V to 3.6 V
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
[1]
DTsen
sensor
Tamb = 40 C to +85 C
-
-
3
C
temperature
accuracy
EL
linearity error
Tamb = 40 C to +85 C
-
-
-
1.1
C
s
[2]
ts(pu)
power-up
settling time
to 99% of temperature
sensor output value
81
85
[2][3]
ts(sw)
switching
settling time
to 99% of temperature
sensor output value
-
1.5
2
s
[1] Absolute temperature accuracy.
[2] Typical values are derived from nominal simulation (VDD(3V3) = 3.3 V; Tamb = 27 C; nominal process
models). Maximum values are derived from worst case simulation (VDD(3V3) = 2.6 V; Tamb = 85 C; slow
process models).
[3] Settling time applies to switching between comparator and ADC channels.
Table 23. Temperature sensor Linear-Least-Square (LLS) fit parameters
VDD(3V3) = 2.6 V to 3.6 V
Fit parameter
Range
Min
Typ
Max
Unit
LLS slope
Tamb = 0 C to 85 C
Tamb = 40 C to +85 C
Tamb = 0 C to 85 C
Tamb = 40 C to +85C
-
-
-
-
2.36
2.36
577
-
-
-
-
mV/C
mV/C
mV
LLS intercept
576
mV
002aag064
800
V
O
(mV)
600
400
200
y = -2.366x + 578.34
2
R
= 0.9995
-40
-15
10
35
60
85
temperature (°C)
VDD(3V3) = 3.3 V; measured on a typical silicon sample.
Fig 28. Typical LLS fit of the temperature sensor output voltage
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Table 24. Comparator characteristics
VDD(3V3)= 3.0 V and Tamb = 25 C unless noted otherwise.
Symbol Parameter
Static characteristics
Conditions
Min Typ
Max
Unit
IDD
supply current
-
55
-
A
V
VIC
common-mode input voltage
output voltage variation
offset voltage
0
0
-
-
VDD(3V3)
DVO
Voffset
-
VDD(3V3)
V
VIC = 0.1 V
VIC = 1.5 V
VIC = 2.8 V
4 to +4.2
2
-
-
mV
mV
mV
-
-
2.5
Dynamic characteristics
tstartup
tPD
start-up time
nominal process
-
-
4
-
s
propagation delay
HIGH to LOW; VDD(3V3) = 3.0 V;
[1]
[1]
[1]
[1]
[1]
[1]
V
IC = 0.1 V; 50 mV overdrive input
IC = 0.1 V; rail-to-rail input
129
210
112
127
151
57
140
250
130
160
170
70
ns
ns
ns
ns
ns
ns
V
-
-
-
-
-
-
VIC = 1.5 V; 50 mV overdrive input
VIC = 1.5 V; rail-to-rail input
VIC = 2.9 V; 50 mV overdrive input
VIC = 2.9 V; rail-to-rail input
tPD
propagation delay
LOW to HIGH; VDD(3V3) = 3.0 V;
VIC = 0.1 V; 50 mV overdrive input
VIC = 0.1 V; rail-to-rail input
[1]
[1]
[1]
[1]
[1]
[1]
[2]
232
240
60
ns
ns
ns
ns
ns
ns
mV
-
-
-
-
-
-
58
VIC = 1.5 V; 50 mV overdrive input
VIC = 1.5 V; rail-to-rail input
210
230
200
190
550
-
178
VIC = 2.9 V; 50 mV overdrive input
VIC = 2.9 V; rail-to-rail input
166
333
Vhys
Vhys
Rlad
hysteresis voltage
hysteresis voltage
ladder resistance
positive hysteresis; VDD(3V3) = 3.0 V;
VIC = 1.5 V
5, 10, 20
[2]
negative hysteresis; VDD(3V3) = 3.0 V;
VIC = 1.5 V
-
-
5, 10, 20
1.034
-
-
mV
-
M
[1] CL = 10 pF; results from measurements on silicon samples over process corners and over the full temperature range Tamb = -40 C to
+85 C.
[2] Input hysteresis is relative to the reference input channel and is software programmable.
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Table 25. Comparator voltage ladder dynamic characteristics
Symbol Parameter
Conditions
Min Typ
Max
Unit
[1]
ts(pu)
power-up settling
time
to 99% of voltage
ladder output
value
-
-
30
s
[1]
[2]
ts(sw)
switching settling
time
to 99% of voltage
ladder output
value
-
-
15
s
[1] Maximum values are derived from worst case simulation (VDD(3V3) = 2.6 V; Tamb = 85 C; slow process
models).
[2] Settling time applies to switching between comparator and ADC channels.
Table 26. Comparator voltage ladder reference static characteristics
VDD(3V3) = 3.3 V; Tamb = -40 C to + 85C.
Symbol
Parameter
Conditions
Min
Typ
Max[1]
Unit
EV(O)
output voltage error
Internal VDD(3V3) supply
decimal code = 00
decimal code = 08
decimal code = 16
decimal code = 24
decimal code = 30
decimal code = 31
[2]
-
-
-
-
-
-
0
0
%
%
%
%
%
%
0
0.4
0.2
0.2
0.1
0.1
0.2
0.2
0.1
0.1
EV(O)
output voltage error
External VDDCMP
supply
decimal code = 00
decimal code = 08
decimal code = 16
decimal code = 24
decimal code = 30
decimal code = 31
-
-
-
-
-
-
0
0
%
%
%
%
%
%
0.1
0.2
0.2
0.2
0.1
0.5
0.4
0.3
0.2
0.1
[1] Measured over a polyresistor matrix lot with a 2 kHz input signal and overdrive < 100 V.
[2] All peripherals except comparator, temperature sensor, and IRC turned off.
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12. Application information
12.1 ADC usage notes
The following guidelines show how to increase the performance of the ADC in a noisy
environment beyond the ADC specifications listed in Table 18:
• The ADC input trace must be short and as close as possible to the LPC11Axx chip.
• The ADC input traces must be shielded from fast switching digital signals and noisy
power supply lines.
• Because the ADC and the digital core share the same power supply, the power supply
line must be adequately filtered.
• To improve the ADC performance in a very noisy environment, put the device in Sleep
mode during the ADC conversion.
12.2 Use of ADC input trigger signals
For applications that use trigger signals to start conversions and require a precise sample
frequency, ensure that the period of the trigger signal is an integral multiple of the period
of the ADC clock.
12.3 XTAL input
The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a
clock in slave mode, it is recommended that the input be coupled through a capacitor with
Ci = 100 pF. To limit the input voltage to the specified range, choose an additional
capacitor to ground Cg which attenuates the input voltage by a factor Ci/(Ci + Cg). In slave
mode, a minimum of 200 mV(RMS) is needed.
LPC1xxx
XTALIN
C
i
C
g
100 pF
002aae788
Fig 29. Slave mode operation of the on-chip oscillator
In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF
(Figure 29), with an amplitude between 200 mV (RMS) and 1000 mV (RMS). This
corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V.
The XTALOUT pin in this configuration can be left unconnected.
External components and models used in oscillation mode are shown in Figure 30 and in
Table 27 and Table 28. Since the feedback resistance is integrated on chip, only a crystal
and the capacitances CX1 and CX2 need to be connected externally in case of
fundamental mode oscillation (the fundamental frequency is represented by L, CL and
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RS). Capacitance CP in Figure 30 represents the parallel package capacitance and should
not be larger than 7 pF. Parameters FOSC, CL, RS and CP are supplied by the crystal
manufacturer (see Table 27).
LPC1xxx
L
XTALIN
XTALOUT
C
L
C
P
=
XTAL
R
S
C
X2
C
X1
002aaf424
Fig 30. Oscillator modes and models: oscillation mode of operation and external crystal
model used for CX1/CX2 evaluation
Table 27. Recommended values for CX1/CX2 in oscillation mode (crystal and external
components parameters) low frequency mode
Fundamental oscillation Crystal load
Maximum crystal
External load
frequency FOSC
capacitance CL
series resistance RS
capacitors CX1, CX2
1 MHz - 5 MHz
10 pF
< 300
< 300
< 300
< 300
< 200
< 100
< 160
< 60
18 pF, 18 pF
39 pF, 39 pF
57 pF, 57 pF
18 pF, 18 pF
39 pF, 39 pF
57 pF, 57 pF
18 pF, 18 pF
39 pF, 39 pF
18 pF, 18 pF
20 pF
30 pF
5 MHz - 10 MHz
10 pF
20 pF
30 pF
10 MHz - 15 MHz
15 MHz - 20 MHz
10 pF
20 pF
10 pF
< 80
Table 28. Recommended values for CX1/CX2 in oscillation mode (crystal and external
components parameters) high frequency mode
Fundamental oscillation Crystal load
Maximum crystal
External load
frequency FOSC
capacitance CL
series resistance RS
capacitors CX1, CX2
15 MHz - 20 MHz
10 pF
< 180
< 100
< 160
< 80
18 pF, 18 pF
39 pF, 39 pF
18 pF, 18 pF
39 pF, 39 pF
20 pF
20 MHz - 25 MHz
10 pF
20 pF
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12.4 XTAL Printed Circuit Board (PCB) layout guidelines
The crystal should be connected on the PCB as close as possible to the oscillator input
and output pins of the chip. Take care that the load capacitors Cx1,Cx2, and Cx3 in case of
third overtone crystal usage have a common ground plane. The external components
must also be connected to the ground plain. Loops must be made as small as possible in
order to keep the noise coupled in via the PCB as small as possible. Also parasitics
should stay as small as possible. Values of Cx1 and Cx2 should be chosen smaller
accordingly to the increase in parasitics of the PCB layout.
12.5 Standard I/O pad configuration
Figure 31 shows the possible pin modes for standard I/O pins with analog input function:
• Digital output driver with configurable open-drain output
• Digital input: Weak pull-up resistor (PMOS device) enabled/disabled
• Digital input: Weak pull-down resistor (NMOS device) enabled/disabled
• Digital input: Repeater mode enabled/disabled
• Digital input: Input glitch filter selectable on 17 pins.
• Analog input
V
DD
V
DD
open-drain enable
output enable
data output
strong
pull-up
ESD
pin configured
as digital output
driver
PIN
strong
pull-down
ESD
V
SS
V
DD
weak
pull-up
pull-up enable
weak
pull-down
repeater mode
enable
pin configured
as digital input
pull-down enable
data input
10 ns RC
GLITCH FILTER
select data
inverter
select glitch
filter
select analog input
pin configured
as analog input
analog input
002aaf695
Fig 31. Standard I/O pad configuration
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12.6 Reset pad configuration
V
DD
V
DD
V
DD
R
pu
ESD
20 ns RC
GLITCH FILTER
reset
PIN
ESD
V
SS
002aaf274
Fig 32. Reset pad configuration
12.7 UVLO protection and reset timer circuit
V
INTERNAL
REGULATOR
V
INT
1.8 V
EXT
3.3 V
V
EXT
V
INT
OR
UVLO
BOD
analog reset
internal reset
OR
POR
V
REF
V
INT
100 μs RESET
TIMER
POR
002aah324
Fig 33. Functional diagram of the UVLO protection and reset timer circuit
12.8 Guidelines for selecting a power supply filter for UVLO protection
For the UVLO circuits to hold the part in reset during shallow and deep brown-out
conditions, you must filter the power supply line to allow for the BOD and POR circuits to
settle when short voltage drops occur (see Section 10.1 “Power supply fluctuations”).
Select the capacitance of the decoupling/bypass capacitor according to the following
guidelines:
C >> IDD ts/VDD(3V3) with
• VDD(3V3) 100 mV for the voltage drop below the BOD or POR trip points.
• IDD 3 mA with the IRC running and PLL/SysOsc off (see Figure 12).
LPC11AXX
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LPC11Axx
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32-bit ARM Cortex-M0 microcontroller
• ts = 5 s for shallow brown-out (see Table 8).
• ts = 12 s for deep brown-out (see Table 8).
With these parameters, the decoupling/bypass capacitor to add to the supply line is:
• C 0.15 F for shallow brown-out
• C >> 0.36 F for deep brown-out
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13. Package outline
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
SOT313-2
c
y
X
36
25
A
E
37
24
Z
E
e
H
E
A
2
A
(A )
3
A
1
w M
p
θ
pin 1 index
b
L
p
L
13
48
detail X
1
12
Z
v M
D
A
e
w M
b
p
D
B
H
v
M
B
D
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
7o
0o
0.20 1.45
0.05 1.35
0.27 0.18 7.1
0.17 0.12 6.9
7.1
6.9
9.15 9.15
8.85 8.85
0.75
0.45
0.95 0.95
0.55 0.55
1.6
mm
0.25
0.5
1
0.2 0.12 0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
00-01-19
03-02-25
SOT313-2
136E05
MS-026
Fig 34. Package outline LQFP48
LPC11AXX
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NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
HVQFN33: plastic thermal enhanced very thin quad flat package; no leads;
33 terminals; body 7 x 7 x 0.85 mm
D
B
A
terminal 1
index area
E
A
A
1
c
detail X
e
1
C
v
C
C
A
B
e
b
y
1
y
w
C
9
16
L
8
17
e
E
e
2
h
33
1
24
X
terminal 1
index area
32
25
0
D
h
2.5
scale
5 mm
v
Dimensions
Unit
(1)
(1)
(1)
A
A
b
c
D
D
E
E
e
e
1
e
2
L
w
y
y
1
1
h
h
max 1.00 0.05 0.35
mm nom 0.85 0.02 0.28 0.2 7.0 4.70 7.0 4.70 0.65 4.55 4.55 0.60 0.1 0.05 0.08 0.1
min 0.80 0.00 0.23 6.9 4.55 6.9 4.55 0.45
7.1 4.85 7.1 4.85
0.75
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
hvqfn33_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
- - -
09-03-17
09-03-23
Fig 35. Package outline HVQFN33 (7x7)
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NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
HVQFN33: plastic thermal enhanced very thin quad flat package; no leads;
32 terminals; body 5 x 5 x 0.85 mm
D
B
A
terminal 1
index area
A
A
1
E
c
detail X
C
e
1
y
y
v
w
C
C
A
B
C
1
e
1/2 e
b
9
16
L
17
8
e
e
E
h
2
1/2 e
24
1
terminal 1
index area
32
25
X
D
h
0
2.5
scale
5 mm
Dimensions (mm are the original dimensions)
(1)
(1)
(1)
(1)
Unit
A
A
1
b
c
D
D
E
E
h
e
e
e
L
v
w
y
y
1
h
1
2
max
0.05 0.30
5.1 3.75 5.1 3.75
0.5
mm nom 0.85
min
0.2
0.5 3.5 3.5
0.1 0.05 0.05 0.1
0.00 0.18
4.9 3.45 4.9 3.45
0.3
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
hvqfn33f_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
11-10-11
11-10-17
MO-220
Fig 36. Package outline HVQFN33 (5x5)
LPC11AXX
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NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
WLCSP20: wafer level chip-size package; 20 bumps; 2.5 x 2.5 x 0.6 mm
LPC11AxxUK
D
B
A
E
ball A1
index area
A
2
A
A
1
detail X
C
e
1
Ø v
Ø w
C
C
A
B
e
y
1
y
b
C
E
D
C
B
A
e
e
2
ball A1
index area
1
2
3
4
X
0
e
0.5
1 mm
y
scale
Dimensions (mm are the original dimensions)
Unit
A
A
1
A
2
b
D
E
e
e
1
v
w
2
max 0.65 0.27 0.38 0.35 2.60 2.60
mm nom 0.60 0.24 0.36 0.32 2.55 2.55 0.5 1.5 2.0 0.15 0.05 0.05
0.55 0.21 0.34 0.29 2.50 2.50
min
wlcsp20_lpc11axxuk_po
Issue date
References
Outline
version
European
projection
IEC
JEDEC
JEITA
12-03-26
LPC11AxxUK
Fig 37. Package outline (WLCSP20)
LPC11AXX
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32-bit ARM Cortex-M0 microcontroller
14. Soldering
Footprint information for reflow soldering of LQFP48 package
SOT313-2
Hx
Gx
(0.125)
P2
P1
Hy Gy
By
Ay
C
D2 (8×)
D1
Bx
Ax
Generic footprint pattern
Refer to the package outline drawing for actual layout
solder land
occupied area
DIMENSIONS in mm
P1 P2 Ax
Ay
Bx
By
C
D1
D2
Gx
Gy
Hx
Hy
0.500 0.560 10.350 10.350 7.350 7.350 1.500 0.280 0.500 7.500 7.500 10.650 10.650
sot313-2_fr
Fig 38. Reflow soldering of the LQFP48 package
LPC11AXX
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NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Footprint information for reflow soldering of HVQFN33 package
OID = 8.20 OA
PID = 7.25 PA+OA
OwDtot = 5.10 OA
evia = 4.25
0.20 SR
chamfer (4×)
W = 0.30 CU
e = 0.65
SPD = 1.00 SP
0.45 DM
GapD = 0.70 SP
evia = 2.40
B-side
SDhtot = 2.70 SP
Solder resist
covered via
4.55 SR
DHS = 4.85 CU
LbD = 5.80 CU
LaD = 7.95 CU
0.30 PH
0.60 SR cover
0.60 CU
(A-side fully covered)
number of vias: 20
solder land
solder land plus solder paste
solder paste deposit
occupied area
solder resist
Remark:
Stencil thickness: 0.125 mm
Dimensions in mm
001aao134
Fig 39. Reflow soldering of the HVQFN33(7x7) package
LPC11AXX
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NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Footprint information for reflow soldering of HVQFN33 package
Hx
Gx
see detail X
P
nSPx
Ay
By
SLy
Hy Gy
nSPy
C
D
SLx
Bx
Ax
0.60
0.30
solder land
solder paste
occupied area
detail X
Dimensions in mm
P
Ax
Ay
Bx
By
C
D
Gx
Gy
Hx
Hy
6.2
SLx
SLy
nSPx nSPy
0.5
5.95
5.95
4.25
4.25
0.85
0.27
5.25
5.25
6.2
3.75
3.75
3
3
11-11-15
11-11-20
Issue date
002aag766
Fig 40. Reflow soldering of the HVQFN33(5x5) package
LPC11AXX
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NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
15. Abbreviations
Table 29. Abbreviations
Acronym
ADC
Description
Analog-to-Digital Converter
Advanced High-performance Bus
AHB
AMBA
APB
Advanced Microcontroller Bus Architecture
Advanced Peripheral Bus
BOD
Brown-Out Detection
GPIO
I2C
General Purpose Input/Output
Inter Integrated Circuit
JEDEC
LVTSCR
NVM
Joint Electron Devices Engineering Council
Low-Voltage Triggered Silicon-Controlled Rectifier
Non-Volatile Memory
PLL
Phase-Locked Loop
SPI
Serial Peripheral Interface
SSI
Serial Synchronous Interface
Transistor-Transistor Logic
TTL
USART
UVLO
Universal Synchronous/Asynchronous Receiver/Transmitter
Under-Voltage LockOut
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16. Revision history
Table 30. Revision history
Document ID
Release date
Data sheet status
Change notice Supersedes
LPC11AXX v.4
20121030
Product data sheet
-
LPC11AXX v.3
• Parameter tPD corrected in Table 25.
• Editorial updates.
• Maximum and minimum values for VDD and VDD(IO) updated in Table 5 “Limiting
values”.
• Limiting values for parameter VI added for open-drain pins PIO0_2 and PIO0_3 in
Table 5 “Limiting values”.
• Table 26 “Comparator voltage ladder reference static characteristics” updated.
• Parameters ts(pu) and ts(sw) added to Table 21 “Internal voltage reference static and
dynamic characteristics”.
• Parameters VIA and Vtrig and Vi(xtal) added to Table 5.
LPC11AXX v.3
20120907
Product data sheet
-
LPC11AXX v.2.1
• Section 10.1 abbreviated for clarity.
• UVLO description including description of cold start-up behavior moved to the
LPC11Axx user manual.
• Table “Slew rate for the internal regulator power-up from ground” removed. This
specification is included in the cold start-up description in the LPC11Axx user manual.
• Details regarding boundary scan added to Section 7.24 “Emulation and debugging”.
• Figure 33 “Functional diagram of the UVLO protection and reset timer circuit” updated
to include the reset timer circuit.
• Section 12.8 “Guidelines for selecting a power supply filter for UVLO protection”
added.
• Section 7.23.2 updated to include internal reset timer.
• Parameter tPD corrected in Table 24.
• Parameter EV(O) corrected in Table 26.
LPC11AXX v.2.1
20120704
Product data sheet
-
LPC11AXX v.2
• Data sheet status changed to Product.
• Changed Table note [2] in Table 24.
• Changed Table note [1] in Table 8.
• Added Table note [1] in Table 9.
• Moved DTsen and EL values from typ to max in Table 22.
• Corrected Vesd in Table 5.
• Added Table note [5] and Table note [6] to Table 4.
LPC11AXX
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32-bit ARM Cortex-M0 microcontroller
Table 30. Revision history …continued
Document ID
Release date
20120625
Data sheet status
Change notice Supersedes
LPC11AXX v.2
Preliminary data sheet -
LPC11AXX v.1
• Data sheet status changed to Preliminary.
• Parameter fclk removed from Table 11.
• ter removed in Table 11.
• Writable EEPROM size specified in Section 7.3.
• Section 10.3 “UVLO reset behavior” added.
• Power consumption data updated for active mode and sleep mode (see Figure 11 to
Figure 13).
• Power consumption data for active and sleep modes with all peripherals enabled
removed in Table 6 and Section 9.1.
• Parameters ts(pu) and ts(sw) removed from Section 7.15.
• Parameter tPD updated in Table 25.
• SSP dynamic characteristics added in Table 17.
• WDOsc and LFOsc max and min frequency values updated throughout the data sheet.
• Section 12.7 “UVLO protection circuit” added.
• Typical values for parameters ED, EL(adj), EO, EG, and CL in Table 20 “DAC static and
dynamic characteristics” changed to maximum values.
• Parameter VO corrected for condition Tamb = 40 C to +85 C in Table 22.
LPC11AXX v.1
20120322
Objective data sheet
-
-
LPC11AXX
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17. Legal information
17.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use — NXP Semiconductors products are not designed,
17.2 Definitions
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
17.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
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LPC11Axx
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
17.4 Trademarks
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
18. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
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32-bit ARM Cortex-M0 microcontroller
19. Contents
1
General description. . . . . . . . . . . . . . . . . . . . . . 1
7.22.1.2 Crystal Oscillator (SysOsc) . . . . . . . . . . . . . . 35
7.22.1.3 Internal Low-Frequency Oscillator (LFOsc)
and Watchdog Oscillator (WDOsc) . . . . . . . . 36
2
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering information. . . . . . . . . . . . . . . . . . . . . 3
Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 4
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
7.22.2
7.22.3
7.22.4
7.22.5
7.22.6
Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
System PLL . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Clock output. . . . . . . . . . . . . . . . . . . . . . . . . . 36
Wake-up process . . . . . . . . . . . . . . . . . . . . . . 36
Power control. . . . . . . . . . . . . . . . . . . . . . . . . 36
4
4.1
5
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 6
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7
7.22.6.1 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.22.6.2 Power profiles . . . . . . . . . . . . . . . . . . . . . . . . 37
7.23
System control . . . . . . . . . . . . . . . . . . . . . . . . 37
UnderVoltage LockOut (UVLO) protection. . . 37
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Brown-out detection. . . . . . . . . . . . . . . . . . . . 38
Code security (Code Read Protection - CRP) 38
APB interface. . . . . . . . . . . . . . . . . . . . . . . . . 38
AHBLite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
External interrupt inputs. . . . . . . . . . . . . . . . . 39
Emulation and debugging . . . . . . . . . . . . . . . 39
7
7.1
7.2
7.3
7.4
7.5
7.6
7.7
Functional description . . . . . . . . . . . . . . . . . . 23
ARM Cortex-M0 processor . . . . . . . . . . . . . . . 23
On-chip flash program memory . . . . . . . . . . . 23
On-chip EEPROM data memory. . . . . . . . . . . 23
On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 23
On-chip ROM . . . . . . . . . . . . . . . . . . . . . . . . . 23
Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 23
Nested Vectored Interrupt Controller (NVIC) . 24
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 25
IOCON block . . . . . . . . . . . . . . . . . . . . . . . . . 25
Fast general purpose parallel I/O . . . . . . . . . . 25
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
SSP serial I/O controller . . . . . . . . . . . . . . . . . 26
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
I2C-bus serial I/O controller . . . . . . . . . . . . . . 26
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Configurable analog/mixed-signal
subsystems. . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Internal voltage reference. . . . . . . . . . . . . . . . 29
Temperature sensor . . . . . . . . . . . . . . . . . . . . 30
10-bit DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Analog comparator . . . . . . . . . . . . . . . . . . . . . 31
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
General purpose external event
7.23.1
7.23.2
7.23.3
7.23.4
7.23.5
7.23.6
7.23.7
7.24
7.7.1
7.7.2
7.8
8
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 40
9
Static characteristics . . . . . . . . . . . . . . . . . . . 42
Power consumption . . . . . . . . . . . . . . . . . . . 45
Peripheral power consumption . . . . . . . . . . . 47
Electrical pin characteristics. . . . . . . . . . . . . . 47
7.9
9.1
9.2
9.3
7.9.1
7.10
7.10.1
7.11
7.11.1
7.12
7.12.1
7.13
10
Dynamic characteristics. . . . . . . . . . . . . . . . . 51
Power supply fluctuations . . . . . . . . . . . . . . . 51
Flash/EEPROM memory . . . . . . . . . . . . . . . . 51
External clock for oscillator in slave mode. . . 52
Internal oscillators . . . . . . . . . . . . . . . . . . . . . 53
I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
I2C-bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
SSP interfaces . . . . . . . . . . . . . . . . . . . . . . . . 56
10.1
10.2
10.3
10.4
10.5
10.6
10.7
7.14
7.14.1
7.15
7.16
7.17
7.17.1
7.18
7.18.1
7.19
11
Characteristics of analog peripherals. . . . . . 58
12
Application information . . . . . . . . . . . . . . . . . 66
ADC usage notes. . . . . . . . . . . . . . . . . . . . . . 66
Use of ADC input trigger signals . . . . . . . . . . 66
XTAL input . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
XTAL Printed Circuit Board (PCB) layout
guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Standard I/O pad configuration . . . . . . . . . . . 68
Reset pad configuration. . . . . . . . . . . . . . . . . 69
UVLO protection and reset timer circuit. . . . . 69
Guidelines for selecting a power supply filter
for UVLO protection . . . . . . . . . . . . . . . . . . . . 69
12.1
12.2
12.3
12.4
12.5
12.6
12.7
12.8
counter/timers. . . . . . . . . . . . . . . . . . . . . . . . . 33
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
System tick timer . . . . . . . . . . . . . . . . . . . . . . 33
Windowed WatchDog Timer (WWDT) . . . . . . 33
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Clocking and power control . . . . . . . . . . . . . . 34
Crystal and internal oscillators . . . . . . . . . . . . 34
7.19.1
7.20
7.21
7.21.1
7.22
7.22.1
13
14
Package outline. . . . . . . . . . . . . . . . . . . . . . . . 71
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
7.22.1.1 Internal RC Oscillator (IRC) . . . . . . . . . . . . . . 35
continued >>
LPC11AXX
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 30 October 2012
83 of 84
LPC11Axx
NXP Semiconductors
32-bit ARM Cortex-M0 microcontroller
15
16
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 78
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 79
17
Legal information. . . . . . . . . . . . . . . . . . . . . . . 81
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 81
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 82
17.1
17.2
17.3
17.4
18
19
Contact information. . . . . . . . . . . . . . . . . . . . . 82
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2012.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 30 October 2012
Document identifier: LPC11AXX
相关型号：
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