LPC11C14FBD48/301 [NXP]
32-bit ARM Cortex-M0 microcontroller; 16/32 kB flash, 8 kB SRAM; C_CAN; 32位ARM Cortex -M0微控制器; 16/32 KB闪存, 8 KB的SRAM ; C_CAN型号: | LPC11C14FBD48/301 |
厂家: | NXP |
描述: | 32-bit ARM Cortex-M0 microcontroller; 16/32 kB flash, 8 kB SRAM; C_CAN |
文件: | 总49页 (文件大小:304K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LPC11C12/C14
32-bit ARM Cortex-M0 microcontroller; 16/32 kB flash, 8 kB
SRAM; C_CAN
Rev. 00.05 — 6 May 2010
Preliminary data sheet
1. General description
The LPC11C12/C14 are an ARM Cortex-M0 based, low-cost 32-bit MCU family, designed
for 8/16-bit microcontroller applications, offering performance, low power, simple
instruction set and memory addressing together with reduced code size compared to
existing 8/16-bit architectures.
The LPC11C12/C14 operate at CPU frequencies of up to 50 MHz.
The peripheral complement of the LPC11C12/C14 includes 16/32 kB of flash memory,
8 kB of data memory, one C_CAN controller, one Fast-mode Plus I2C-bus interface, one
RS-485/EIA-485 UART, two SPI interfaces with SSP features, four general purpose
counter/timers, a 10-bit ADC, and 40 general purpose I/O pins.
On-chip C_CAN drivers and flash In-System Programming tools via C_CAN are included.
2. Features and benefits
System:
ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.
ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).
Serial Wire Debug.
System tick timer.
Memory:
32 kB (LPC11C14) or 16 kB (LPC11C12) on-chip flash programming memory.
8 kB SRAM.
In-System Programming (ISP) and In-Application Programming (IAP) via on-chip
bootloader software.
Flash ISP commands can be issued via UART or C_CAN.
Digital peripherals:
40 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors.
GPIO pins can be used as edge and level sensitive interrupt sources.
High-current output driver (20 mA) on one pin.
High-current sink drivers (20 mA) on two I2C-bus pins in Fast-mode Plus.
Four general purpose counter/timers with a total of four capture inputs and 13
match outputs.
Programmable WatchDog Timer (WDT).
Analog peripherals:
10-bit ADC with input multiplexing among 8 pins.
LPC11C12/C14
NXP Semiconductors
Serial interfaces:
UART with fractional baud rate generation, internal FIFO, and RS-485 support.
Two SPI controllers with SSP features and with FIFO and multi-protocol
capabilities.
I2C-bus interface supporting full I2C-bus specification and Fast-mode Plus with a
data rate of 1 Mbit/s with multiple address recognition and monitor mode.
C_CAN controller. On-chip C_CAN drivers included.
Clock generation:
12 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used
as a system clock.
Crystal oscillator with an operating range of 1 MHz to 25 MHz.
Programmable watchdog oscillator with a frequency range of 7.8 kHz to 1.8 MHz.
PLL allows CPU operation up to the maximum CPU rate without the need for a
high-frequency crystal. May be run from the system oscillator or the internal RC
oscillator.
Clock output function with divider that can reflect the system oscillator, IRC, CPU
clock, or the Watchdog clock.
Power control:
Integrated PMU (Power Management Unit) to minimize power consumption during
Sleep, Deep-sleep, and Deep power-down modes.
Three reduced power modes: Sleep, Deep-sleep, and Deep power-down.
Processor wake-up from Deep-sleep mode via a dedicated start logic using 13 of
the GPIO pins.
Power-On Reset (POR).
Brownout detect with four separate thresholds for interrupt and forced reset.
Unique device serial number for identification.
Single 3.3 V power supply (1.8 V to 3.6 V).
Available as 48-pin LQFP package.
3. Applications
eMetering
Elevator systems
Industrial and sensor based networks
White goods
4. Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
Version
LPC11C12FBD48/301
LPC11C14FBD48/301
LQFP48
LQFP48: plastic low profile quad flat package; 48 leads; body 7 × 7 × sot313-2
1.4 mm
LQFP48
LQFP48: plastic low profile quad flat package; 48 leads; body 7 × 7 × sot313-2
1.4 mm
LPC11C12_C14_0
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© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 00.05 — 6 May 2010
2 of 49
LPC11C12/C14
NXP Semiconductors
4.1 Ordering options
Table 2.
Ordering options
Type number
Flash
Total
UART
I2C/
SPI
C_CAN
ADC
Package
SRAM
RS-485
Fast+
channels
LPC11C12FBD48/301
LPC11C14FBD48/301
16 kB
32 kB
8 kB
8 kB
1
1
1
1
2
2
1
1
8
8
LQFP48
LQFP48
5. Block diagram
XTALIN
XTALOUT
SWD
RESET
LPC11C12/C14
IRC
CLOCK
GENERATION,
POWER CONTROL,
SYSTEM
CLKOUT
TEST/DEBUG
INTERFACE
POR
FUNCTIONS
ARM
CORTEX-M0
clocks and
controls
FLASH
16/32 kB
SRAM
8 kB
ROM
system bus
slave
slave
slave
slave
HIGH-SPEED
GPIO
GPIO ports
PIO0/1/2/3
AHB-LITE BUS
slave
AHB TO APB
BRIDGE
RXD
TXD
DTR, DSR, CTS,
DCD, RI, RTS
UART
AD[7:0]
10-bit ADC
SCK0, SSEL0
MISO0, MOSI0
SPI0
SPI1
CT32B0_MAT[3:0]
CT32B0_CAP0
32-bit COUNTER/TIMER 0
32-bit COUNTER/TIMER 1
16-bit COUNTER/TIMER 0
16-bit COUNTER/TIMER 1
SCK1, SSEL1
MISO1, MOSI1
CT32B1_MAT[3:0]
CT32B1_CAP0
SCL
SDA
2
I C-BUS
CT16B0_MAT[2:0]
CT16B0_CAP0
CT16B1_MAT[1:0]
CT16B1_CAP0
WDT
IOCONFIG
CAN_TXD
CAN_RXD
C_CAN
SYSTEM CONTROL
PMU
002aaf265
Fig 1. LPC11C12/C14 block diagram
LPC11C12_C14_0
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© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 00.05 — 6 May 2010
3 of 49
LPC11C12/C14
NXP Semiconductors
6. Pinning information
6.1 Pinning
1
2
36
35
34
33
32
31
30
29
28
27
26
25
PIO2_6
PIO2_0/DTR/SSEL1
PIO3_0/DTR
R/PIO1_2/AD3/CT32B1_MAT1
R/PIO1_1/AD2/CT32B1_MAT0
R/PIO1_0/AD1/CT32B1_CAP0
R/PIO0_11/AD0/CT32B0_MAT3
PIO2_11/SCK0
3
RESET/PIO0_0
4
PIO0_1/CLKOUT/CT32B0_MAT2
5
V
SS
6
XTALIN
LPC11C12FBD48/301
LPC11C14FBD48/301
7
XTALOUT
PIO1_10/AD6/CT16B1_MAT1
SWCLK/PIO0_10/SCK0/CT16B0_MAT2
PIO0_9/MOSI0/CT16B0_MAT1
PIO0_8/MISO0/CT16B0_MAT0
PIO2_2/DCD/MISO1
8
V
DD
9
PIO1_8/CT16B1_CAP0
PIO0_2/SSEL0/CT16B0_CAP0
PIO2_7
10
11
12
PIO2_8
PIO2_10
002aaf266
Fig 2. Pin configuration LQFP48 package
LPC11C12_C14_0
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Preliminary data sheet
Rev. 00.05 — 6 May 2010
4 of 49
LPC11C12/C14
NXP Semiconductors
6.2 Pin description
Table 3.
LPC11C14 pin description table (LQFP48 package)
Symbol
Pin
Type
Description
PIO0_0 to PIO0_11
I/O
Port 0 — Port 0 is a 12-bit I/O port with individual direction and function
controls for each bit. The operation of port 0 pins depends on the function
selected through the IOCONFIG register block.
RESET/PIO0_0
3[1][2]
I
RESET — External reset input: A LOW on this pin resets the device,
causing I/O ports and peripherals to take on their default states, and
processor execution to begin at address 0.
I/O
I/O
PIO0_0 — General purpose digital input/output pin.
PIO0_1/CLKOUT/
CT32B0_MAT2
4[3][2]
PIO0_1 — General purpose digital input/output pin. A LOW level on this pin
during reset starts the flash ISP command handler via UART (if PIO0_3 is
HIGH) or via C_CAN (if PIO0_3 is LOW).
O
O
CLKOUT — Clockout pin.
CT32B0_MAT2 — Match output 2 for 32-bit timer 0.
PIO0_2 — General purpose digital input/output pin.
SSEL0 — Slave Select for SPI0.
PIO0_2/SSEL0/
CT16B0_CAP0
10[3][2] I/O
O
I
CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.
PIO0_3
14[3][2] I/O
PIO0_3 — General purpose digital input/output pin. This pin is monitored
during reset: Together with a LOW level on pin PIO0_1, a LOW level starts
the flash ISP command handler via C_CAN and a HIGH level starts the
flash ISP command handler via UART.
PIO0_4/SCL
PIO0_5/SDA
15[4][2] I/O
I/O
PIO0_4 — General purpose digital input/output pin (open-drain).
SCL — I2C-bus, open-drain clock input/output. High-current sink only if I2C
Fast-mode Plus is selected in the I/O configuration register.
16[4][2] I/O
I/O
PIO0_5 — General purpose digital input/output pin (open-drain).
SDA — I2C-bus, open-drain data input/output. High-current sink only if I2C
Fast-mode Plus is selected in the I/O configuration register.
PIO0_6/SCK0
PIO0_7/CTS
22[3][2] I/O
I/O
23[3][2] I/O
PIO0_6 — General purpose digital input/output pin.
SCK0 — Serial clock for SPI0.
PIO0_7 — General purpose digital input/output pin (high-current output
driver).
I
CTS — Clear To Send input for UART.
PIO0_8/MISO0/
CT16B0_MAT0
27[3][2] I/O
PIO0_8 — General purpose digital input/output pin.
MISO0 — Master In Slave Out for SPI0.
I/O
O
CT16B0_MAT0 — Match output 0 for 16-bit timer 0.
PIO0_9 — General purpose digital input/output pin.
MOSI0 — Master Out Slave In for SPI0.
PIO0_9/MOSI0/
CT16B0_MAT1
28[3][2] I/O
I/O
O
CT16B0_MAT1 — Match output 1 for 16-bit timer 0.
SWCLK — Serial wire clock.
SWCLK/PIO0_10/
29[3][2]
I
SCK0/CT16B0_MAT2
I/O
I/O
O
PIO0_10 — General purpose digital input/output pin.
SCK0 — Serial clock for SPI0.
CT16B0_MAT2 — Match output 2 for 16-bit timer 0.
LPC11C12_C14_0
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© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 00.05 — 6 May 2010
5 of 49
LPC11C12/C14
NXP Semiconductors
Table 3.
Symbol
LPC11C14 pin description table (LQFP48 package) …continued
Pin
Type
Description
R/PIO0_11/
AD0/CT32B0_MAT3
32[5][2]
I
R — Reserved. Configure for an alternate function in the IOCONFIG block.
PIO0_11 — General purpose digital input/output pin.
AD0 — A/D converter, input 0.
I/O
I
O
I/O
CT32B0_MAT3 — Match output 3 for 32-bit timer 0.
PIO1_0 to PIO1_11
Port 1 — Port 1 is a 12-bit I/O port with individual direction and function
controls for each bit. The operation of port 1 pins depends on the function
selected through the IOCONFIG register block.
R/PIO1_0/
AD1/CT32B1_CAP0
33[5][2]
34[5]
35[5]
39[5]
40[5]
I
R — Reserved. Configure for an alternate function in the IOCONFIG block.
PIO1_0 — General purpose digital input/output pin.
AD1 — A/D converter, input 1.
I/O
I
I
CT32B1_CAP0 — Capture input 0 for 32-bit timer 1.
R — Reserved. Configure for an alternate function in the IOCONFIG block.
PIO1_1 — General purpose digital input/output pin.
AD2 — A/D converter, input 2.
R/PIO1_1/
AD2/CT32B1_MAT0
O
I/O
I
O
I
CT32B1_MAT0 — Match output 0 for 32-bit timer 1.
R — Reserved. Configure for an alternate function in the IOCONFIG block.
PIO1_2 — General purpose digital input/output pin.
AD3 — A/D converter, input 3.
R/PIO1_2/
AD3/CT32B1_MAT1
I/O
I
O
I/O
I/O
I
CT32B1_MAT1 — Match output 1 for 32-bit timer 1.
SWDIO — Serial wire debug input/output.
SWDIO/PIO1_3/AD4/
CT32B1_MAT2
PIO1_3 — General purpose digital input/output pin.
AD4 — A/D converter, input 4.
O
I/O
I
CT32B1_MAT2 — Match output 2 for 32-bit timer 1.
PIO1_4 — General purpose digital input/output pin.
AD5 — A/D converter, input 5.
PIO1_4/AD5/
CT32B1_MAT3/WAKEUP
O
I
CT32B1_MAT3 — Match output 3 for 32-bit timer 1.
WAKEUP — Deep power-down mode wake-up pin. This pin must be pulled
HIGH externally to enter Deep power-down mode and pulled LOW to exit
Deep power-down mode.
PIO1_5/RTS/
CT32B0_CAP0
45[3]
46[3]
47[3]
I/O
O
PIO1_5 — General purpose digital input/output pin.
RTS — Request To Send output for UART.
I
CT32B0_CAP0 — Capture input 0 for 32-bit timer 0.
PIO1_6 — General purpose digital input/output pin.
RXD — Receiver input for UART.
PIO1_6/RXD/
CT32B0_MAT0
I/O
I
O
CT32B0_MAT0 — Match output 0 for 32-bit timer 0.
PIO1_7 — General purpose digital input/output pin.
TXD — Transmitter output for UART.
PIO1_7/TXD/
CT32B0_MAT1
I/O
O
O
CT32B0_MAT1 — Match output 1 for 32-bit timer 0.
PIO1_8 — General purpose digital input/output pin.
CT16B1_CAP0 — Capture input 0 for 16-bit timer 1.
PIO1_9 — General purpose digital input/output pin.
CT16B1_MAT0 — Match output 0 for 16-bit timer 1.
PIO1_8/CT16B1_CAP0
PIO1_9/CT16B1_MAT0
9[3]
I/O
I
17[3]
I/O
O
LPC11C12_C14_0
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© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 00.05 — 6 May 2010
6 of 49
LPC11C12/C14
NXP Semiconductors
Table 3.
Symbol
LPC11C14 pin description table (LQFP48 package) …continued
Pin
Type
I/O
I
Description
PIO1_10/AD6/
CT16B1_MAT1
30[5]
PIO1_10 — General purpose digital input/output pin.
AD6 — A/D converter, input 6.
O
CT16B1_MAT1 — Match output 1 for 16-bit timer 1.
PIO1_11 — General purpose digital input/output pin.
AD7 — A/D converter, input 7.
PIO1_11/AD7
42[5]
I/O
I
PIO2_0 to PIO2_11
I/O
Port 2 — Port 2 is a 12-bit I/O port with individual direction and function
controls for each bit. The operation of port 2 pins depends on the function
selected through the IOCONFIG register block.
PIO2_0/DTR/SSEL1
PIO2_1/DSR/SCK1
PIO2_2/DCD/MISO1
PIO2_3/RI/MOSI1
2[3]
I/O
O
PIO2_0 — General purpose digital input/output pin.
DTR — Data Terminal Ready output for UART.
SSEL1 — Slave Select for SPI1.
O
13[3]
26[3]
38[3]
I/O
I
PIO2_1 — General purpose digital input/output pin.
DSR — Data Set Ready input for UART.
I/O
I/O
I
SCK1 — Serial clock for SPI1.
PIO2_2 — General purpose digital input/output pin.
DCD — Data Carrier Detect input for UART.
MISO1 — Master In Slave Out for SPI1.
I/O
I/O
I
PIO2_3 — General purpose digital input/output pin.
RI — Ring Indicator input for UART.
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
MOSI1 — Master Out Slave In for SPI1.
PIO2_4
18[3]
21[3]
1[3]
11[3]
12[3]
24[3]
25[3]
31[3]
PIO2_4 — General purpose digital input/output pin.
PIO2_5 — General purpose digital input/output pin.
PIO2_6 — General purpose digital input/output pin.
PIO2_7 — General purpose digital input/output pin.
PIO2_8 — General purpose digital input/output pin.
PIO2_9 — General purpose digital input/output pin.
PIO2_10 — General purpose digital input/output pin.
PIO2_11 — General purpose digital input/output pin.
SCK0 — Serial clock for SPI0.
PIO2_5
PIO2_6
PIO2_7
PIO2_8
PIO2_9
PIO2_10
PIO2_11/SCK0
PIO3_0 to PIO3_5
Port 3 — Port 3 is a 12-bit I/O port with individual direction and function
controls for each bit. The operation of port 3 pins depends on the function
selected through the IOCONFIG register block. Pins PIO3_6 to PIO3_11
are not available.
PIO3_0/DTR
PIO3_1/DSR
PIO3_2/DCD
PIO3_3/RI
36[3]
37[3]
43[3]
48[3]
19[6]
I/O
O
I/O
I
PIO3_0 — General purpose digital input/output pin.
DTR — Data Terminal Ready output for UART.
PIO3_1 — General purpose digital input/output pin.
DSR — Data Set Ready input for UART.
I/O
I
PIO3_2 — General purpose digital input/output pin.
DCD — Data Carrier Detect input for UART.
PIO3_3 — General purpose digital input/output pin.
RI — Ring Indicator input for UART.
I/O
I
CAN_RXD
I
CAN_RXD — C_CAN receive data input.
LPC11C12_C14_0
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© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 00.05 — 6 May 2010
7 of 49
LPC11C12/C14
NXP Semiconductors
Table 3.
Symbol
CAN_TXD
VDD
LPC11C14 pin description table (LQFP48 package) …continued
Pin
Type
Description
20[6]
O
I
CAN_TXD — C_CAN transmit data output.
8;44
Supply voltage to the internal regulator, the external rail, and the ADC. Also
used as the ADC reference voltage.
XTALIN
6[7]
I
Input to the oscillator circuit and internal clock generator circuits. Input
voltage must not exceed 1.8 V.
XTALOUT
VSS
7[7]
O
I
Output from the oscillator amplifier.
Ground.
5; 41
[1] See Figure 25 for reset pad configuration. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to
reset the chip and wake up from Deep power-down mode.
[2] Serves as Deep-sleep wake-up input pin to the start logic independently of selected pin function (see the LPC111x/11C1x user manual).
[3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 24).
[4] I2C-bus pads compliant with the I2C-bus specification for I2C standard mode and I2C Fast-mode Plus.
[5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.
When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see Figure 24).
[6] 5 V tolerant digital I/O pad without pull-up/pull-down resistors.
[7] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded
(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.
LPC11C12_C14_0
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© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 00.05 — 6 May 2010
8 of 49
LPC11C12/C14
NXP Semiconductors
7. Functional description
7.1 ARM Cortex-M0 processor
The ARM Cortex-M0 is a general purpose, 32-bit microprocessor, which offers high
performance and very low power consumption.
7.2 On-chip flash program memory
The LPC11C12/C14 contain 32 kB (LPC11C14) or 16 kB (LPC11C12) of on-chip flash
memory.
7.3 On-chip SRAM
The LPC11C12/C14 contain a total of 8 kB on-chip static RAM memory.
7.4 Memory map
The LPC11C12/C14 incorporates several distinct memory regions, shown in the following
figures. Figure 3 shows the overall map of the entire address space from the user
program viewpoint following reset. The interrupt vector area supports address remapping.
The AHB peripheral area is 2 megabyte in size, and is divided to allow for up to 128
peripherals. The APB peripheral area is 512 kB in size and is divided to allow for up to 32
peripherals. Each peripheral of either type is allocated 16 kilobytes of space. This allows
simplifying the address decoding for each peripheral.
LPC11C12_C14_0
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© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 00.05 — 6 May 2010
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LPC11C12/C14
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AHB peripherals
LPC11C12/C14
0x5020 0000
4 GB
0xFFFF FFFF
127- 4 reserved
reserved
0x5004 0000
0x5003 0000
0x5002 0000
GPIO PIO3
GPIO PIO2
3
2
1
0
0x5020 0000
0x5000 0000
AHB peripherals
reserved
GPIO PIO1
0x5001 0000
0x5000 0000
GPIO PIO0
APB peripherals
0x4008 0000
23 - 31 reserved
0x4005 C000
0x4005 8000
SPI1
22
20
0x4008 0000
0x4000 0000
APB peripherals
reserved
reserved
1 GB
0x4005 4000
0x4005 0000
C_CAN
reserved
0x4004 C000
0x4004 8000
0x4004 4000
0x4004 0000
system control
IOCONFIG
18
17
SPI0
16
15
0x2000 0000
flash controller
0.5 GB
0x4003 C000
0x4003 8000
14
PMU
reserved
10 - 13 reserved
0x1FFF 4000
0x1FFF 0000
0x4002 8000
0x4002 4000
0x4002 0000
16 kB boot ROM
reserved
reserved
9
8
7
6
5
4
3
2
ADC
0x4001 C000
0x4001 8000
reserved
32-bit counter/timer 1
32-bit counter/timer 0
16-bit counter/timer 1
16-bit counter/timer 0
UART
0x4001 4000
0x4001 0000
0x4000 C000
0x4000 8000
0x1000 2000
0x1000 0000
8 kB SRAM
reserved
WDT
1
0
0x4000 4000
0x4000 0000
2
I C-bus
0x0000 8000
0x0000 4000
+ 512 byte
active interrupt vectors
0x0000 0200
32 kB on-chip flash (LPC11C14)
16 kB on-chip flash (LPC11C12)
0x0000 0000
0x0000 0000
0 GB
002aaf268
Fig 3. LPC11C12/C14 memory map
7.5 Nested Vectored Interrupt Controller (NVIC)
The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M0. The
tight coupling to the CPU allows for low interrupt latency and efficient processing of late
arriving interrupts.
7.5.1 Features
• Controls system exceptions and peripheral interrupts.
• In the LPC11C12/C14, the NVIC supports 32 vectored interrupts including 13 inputs to
the start logic from individual GPIO pins.
LPC11C12_C14_0
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© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 00.05 — 6 May 2010
10 of 49
LPC11C12/C14
NXP Semiconductors
• Four programmable interrupt priority levels, with hardware priority level masking.
• Relocatable vector table.
• Software interrupt generation.
7.5.2 Interrupt sources
Each peripheral device has one interrupt line connected to the NVIC but may have several
interrupt flags. Individual interrupt flags may also represent more than one interrupt
source.
Any GPIO pin (total of 40 pins) regardless of the selected function, can be programmed to
generate an interrupt on a level, or rising edge or falling edge, or both.
7.6 IOCONFIG block
The IOCONFIG block allows selected pins of the microcontroller to have more than one
function. Configuration registers control the multiplexers to allow connection between the
pin and the on-chip peripherals.
Peripherals should be connected to the appropriate pins prior to being activated and prior
to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is
not mapped to a related pin should be considered undefined.
7.7 Fast general purpose parallel I/O
Device pins that are not connected to a specific peripheral function are controlled by the
GPIO registers. Pins may be dynamically configured as inputs or outputs. Multiple outputs
can be set or cleared in one write operation.
LPC11C12/C14 use accelerated GPIO functions:
• GPIO registers are a dedicated AHB peripheral so that the fastest possible I/O timing
can be achieved.
• Entire port value can be written in one instruction.
Additionally, any GPIO pin (total of 40 pins) providing a digital function can be
programmed to generate an interrupt on a level, a rising or falling edge, or both.
7.7.1 Features
• Bit level port registers allow a single instruction to set or clear any number of bits in
one write operation.
• Direction control of individual bits.
• All GPIO pins default to inputs with pull-ups enabled after reset except for the I2C-bus
true open-drain pins PIO0_4 and PIO0_5.
• Pull-up/pull-down resistor configuration can be programmed through the IOCONFIG
block for each GPIO pin (except PIO0_4 and PIO0_5).
7.8 UART
The LPC11C12/C14 contain one UART.
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Support for RS-485/9-bit mode allows both software address detection and automatic
address detection using 9-bit mode.
The UART includes a fractional baud rate generator. Standard baud rates such as
115200 Bd can be achieved with any crystal frequency above 2 MHz.
7.8.1 Features
• Maximum UART data bit rate of 3.125 MBit/s.
• 16 Byte Receive and Transmit FIFOs.
• Register locations conform to 16C550 industry standard.
• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.
• Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
• FIFO control mechanism that enables software flow control implementation.
• Support for RS-485/9-bit mode.
• Support for modem control.
7.9 SPI serial I/O controller
The LPC11C12/C14 contain two SPI controllers. Both SPI controllers support SSP
features.
The SPI controller is capable of operation on a SSP, 4-wire SSI, or Microwire bus. It can
interact with multiple masters and slaves on the bus. Only a single master and a single
slave can communicate on the bus during a given data transfer. The SPI supports full
duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the
slave and from the slave to the master. In practice, often only one of these data flows
carries meaningful data.
7.9.1 Features
• Maximum SPI speed of 25 Mbit/s (master) or 4.17 Mbit/s (slave) (in SSP mode)
• Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National
Semiconductor Microwire buses
• Synchronous serial communication
• Master or slave operation
• 8-frame FIFOs for both transmit and receive
• 4-bit to 16-bit frame
7.10 I2C-bus serial I/O controller
The LPC11C12/C14 contain one I2C-bus controller.
The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock line
(SCL) and a Serial Data line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the
capability to both receive and send information (such as memory). Transmitters and/or
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receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be
controlled by more than one bus master connected to it.
7.10.1 Features
• The I2C-interface is a standard I2C-bus compliant interface with open-drain pins. The
I2C-bus interface also supports Fast-mode Plus with bit rates up to 1 Mbit/s.
• Easy to configure as master, slave, or master/slave.
• Programmable clocks allow versatile rate control.
• Bidirectional data transfer between masters and slaves.
• Multi-master bus (no central master).
• Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
• Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
• Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
• The I2C-bus can be used for test and diagnostic purposes.
• The I2C-bus controller supports multiple address recognition and a bus monitor mode.
7.11 C_CAN controller
Controller Area Network (CAN) is the definition of a high performance communication
protocol for serial data communication. The C_CAN controller is designed to provide a full
implementation of the CAN protocol according to the CAN Specification Version 2.0B. The
C_CAN controller allows to build powerful local networks with low-cost multiplex wiring by
supporting distributed real-time control with a very high level of security.
On-chip C_CAN drivers provide an API for initialization and communication using CAN
and CANopen standards.
7.11.1 Features
• Conforms to protocol version 2.0 parts A and B.
• Supports bit rate of up to 1 Mbit/s.
• Supports 32 Message Objects.
• Each Message Object has its own identifier mask.
• Provides programmable FIFO mode (concatenation of Message Objects).
• Provides maskable interrupts.
• Supports Disabled Automatic Retransmission (DAR) mode for time-triggered CAN
applications.
• Provides programmable loop-back mode for self-test operation.
• The C_CAN API includes the following functions:
– C_CAN set-up and initialization
– C_CAN send and receive messages
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– C_CAN status
– CANopen object dictionary
– CANopen SDO expedited communication
– CANopen SDO segmented communication primitives
– CANopen SDO fall-back handler
• Flash ISP programming via C_CAN supported.
7.12 10-bit ADC
The LPC11C12/C14 contains one ADC. It is a single 10-bit successive approximation
ADC with eight channels.
7.12.1 Features
• 10-bit successive approximation ADC.
• Input multiplexing among 8 pins.
• Power-down mode.
• Measurement range 0 V to VDD
.
• 10-bit conversion time ≥ 2.44 μs.
• Burst conversion mode for single or multiple inputs.
• Optional conversion on transition of input pin or timer match signal.
• Individual result registers for each ADC channel to reduce interrupt overhead.
7.13 General purpose external event counter/timers
The LPC11C12/C14 includes two 32-bit counter/timers and two 16-bit counter/timers. The
counter/timer is designed to count cycles of the system derived clock. It can optionally
generate interrupts or perform other actions at specified timer values, based on four
match registers. Each counter/timer also includes one capture input to trap the timer value
when an input signal transitions, optionally generating an interrupt.
7.13.1 Features
• A 32-bit/16-bit timer/counter with a programmable 32-bit/16-bit prescaler.
• Counter or timer operation.
• One capture channel per timer, that can take a snapshot of the timer value when an
input signal transitions. A capture event may also generate an interrupt.
• Four match registers per timer that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
• Up to four external outputs corresponding to match registers, with the following
capabilities:
– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
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– Do nothing on match.
7.14 System tick timer
The ARM Cortex-M0 includes a system tick timer (SYSTICK) that is intended to generate
a dedicated SYSTICK exception at a fixed time interval (typically 10 ms).
7.15 Watchdog timer
The purpose of the watchdog is to reset the microcontroller within a selectable time
period.
7.15.1 Features
• Internally resets chip if not periodically reloaded.
• Debug mode.
• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
• Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.
• Flag to indicate watchdog reset.
• Programmable 32-bit timer with internal prescaler.
• Selectable time period from (Tcy(WDCLK) × 256 × 4) to (Tcy(WDCLK) × 232 × 4) in
multiples of Tcy(WDCLK) × 4.
• The Watchdog Clock (WDCLK) source can be selected from the Internal RC oscillator
(IRC), the Watchdog oscillator, or the main clock. This gives a wide range of potential
timing choices of Watchdog operation under different power reduction conditions. It
also provides the ability to run the WDT from an entirely internal source that is not
dependent on an external crystal and its associated components and wiring for
increased reliability.
7.16 Clocking and power control
7.16.1 Crystal oscillators
The LPC11C12/C14 include three independent oscillators. These are the system
oscillator, the Internal RC oscillator (IRC), and the Watchdog oscillator. Each oscillator can
be used for more than one purpose as required in a particular application.
Following reset, the LPC11C12/C14 will operate from the Internal RC oscillator until
switched by software. This allows systems to operate without any external crystal and the
bootloader code to operate at a known frequency.
See Figure 4 for an overview of the LPC11C12/C14 clock generation.
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AHB clock 0
(system)
system clock
SYSTEM CLOCK
DIVIDER
18
AHB clocks 1 to 18
(memories
and peripherals)
AHBCLKCTRL[1:18]
(AHB clock enable)
SPI0 PERIPHERAL
SPI0
CLOCK DIVIDER
IRC oscillator
main clock
UART PERIPHERAL
UART
CLOCK DIVIDER
watchdog oscillator
SPI1 PERIPHERAL
SPI1
CLOCK DIVIDER
MAINCLKSEL
(main clock select)
IRC oscillator
SYSTEM PLL
system oscillator
IRC oscillator
WDT CLOCK
DIVIDER
WDT
SYSPLLCLKSEL
(system PLL clock select)
watchdog oscillator
WDTUEN
(WDT clock update enable)
IRC oscillator
CLKOUT PIN CLOCK
CLKOUT pin
system oscillator
watchdog oscillator
DIVIDER
CLKOUTUEN
(CLKOUT update enable)
002aae514
Fig 4. LPC11C12/C14 clock generation block diagram
7.16.1.1 Internal RC oscillator
The IRC may be used as the clock source for the WDT, and/or as the clock that drives the
PLL and subsequently the CPU. The nominal IRC frequency is 12 MHz. The IRC is
trimmed to 1 % accuracy over the entire voltage and temperature range.
Upon power-up or any chip reset, the LPC11C12/C14 use the IRC as the clock source.
Software may later switch to one of the other available clock sources.
7.16.1.2 System oscillator
The system oscillator can be used as the clock source for the CPU, with or without using
the PLL.
The system oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be
boosted to a higher frequency, up to the maximum CPU operating frequency, by the
system PLL.
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7.16.1.3 Watchdog oscillator
The watchdog oscillator can be used as a clock source that directly drives the CPU, the
watchdog timer, or the CLKOUT pin. The watchdog oscillator nominal frequency is
programmable between 7.8 kHz and 1.7 MHz. The frequency spread over processing and
temperature is ±40 % (see Table 11).
7.16.2 System PLL
The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input
frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO).
The multiplier can be an integer value from 1 to 32. The CCO operates in the range of
156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within
its frequency range while the PLL is providing the desired output frequency. The output
divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the
minimum output divider value is 2, it is insured that the PLL output has a 50 % duty cycle.
The PLL is turned off and bypassed following a chip reset and may be enabled by
software. The program must configure and activate the PLL, wait for the PLL to lock, and
then connect to the PLL as a clock source. The PLL settling time is 100 μs.
7.16.3 Clock output
The LPC11C12/C14 features a clock output function that routes the IRC oscillator, the
system oscillator, the watchdog oscillator, or the main clock to an output pin.
7.16.4 Wake-up process
The LPC11C12/C14 begin operation at power-up and when awakened from Deep
power-down mode by using the 12 MHz IRC oscillator as the clock source. This allows
chip operation to resume quickly. If the system oscillator or the PLL is needed by the
application, software will need to enable these features and wait for them to stabilize
before they are used as a clock source.
7.16.5 Power control
The LPC11C12/C14 support a variety of power control features. There are three special
modes of processor power reduction: Sleep mode, Deep-sleep mode, and Deep
power-down mode. The CPU clock rate may also be controlled as needed by changing
clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value. This
allows a trade-off of power versus processing speed based on application requirements.
In addition, a register is provided for shutting down the clocks to individual on-chip
peripherals, allowing fine tuning of power consumption by eliminating all dynamic power
use in any peripherals that are not required for the application. Selected peripherals have
their own clock divider which provides even better power control.
7.16.5.1 Sleep mode
When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep
mode does not need any special sequence but re-enabling the clock to the ARM core.
In Sleep mode, execution of instructions is suspended until either a reset or interrupt
occurs. Peripheral functions continue operation during Sleep mode and may generate
interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic
power used by the processor itself, memory systems and related controllers, and internal
buses.
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7.16.5.2 Deep-sleep mode
In Deep-sleep mode, the chip is in Sleep mode, and in addition analog blocks can be shut
down for increased power savings. The user can configure the Deep-sleep mode to a
large extent, selecting any of the oscillators, the PLL, BOD, the ADC, and the flash to be
shut down or remain powered during Deep-sleep mode. The user can also select which of
the oscillators and analog blocks will be powered up after the chip exits from Deep-sleep
mode.
The GPIO pins (13 pins total: PIO0_0 to PIO0_11 and PIO1_1) serve as external wake-up
pins to a dedicated start logic to wake up the chip from Deep-sleep mode.
The timing of the wake-up process from Deep-sleep mode depends on which blocks are
selected to be powered down during deep-sleep.
For lowest power consumption, the clock source should be switched to IRC before
entering Deep-sleep mode, all oscillators and the PLL should be turned off during
deep-sleep, and the IRC should be selected as clock source when the chip wakes up from
deep-sleep. The IRC can be switched on and off glitch-free and provides a clean clock
signal after start-up.
If power consumption is not a concern, any of the oscillators and/or the PLL can be left
running in Deep-sleep mode to obtain short wake-up times when waking up from
deep-sleep.
7.16.5.3 Deep power-down mode
In Deep power-down mode, power is shut off to the entire chip with the exception of the
WAKEUP pin. The LPC11C12/C14 can wake up from Deep power-down mode via the
WAKEUP pin.
7.17 System control
7.17.1 Reset
Reset has four sources on the LPC11C12/C14: the RESET pin, the Watchdog reset,
power-on reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a
Schmitt trigger input pin. Assertion of chip reset by any source, once the operating voltage
attains a usable level, starts the IRC and initializes the flash controller.
When the internal Reset is removed, the processor begins executing at address 0, which
is initially the Reset vector mapped from the boot block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.
7.17.2 Brownout detection
The LPC11C12/C14 includes four levels for monitoring the voltage on the VDD pin. If this
voltage falls below one of the four selected levels, the BOD asserts an interrupt signal to
the NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the
NVIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading
a dedicated status register. Four additional threshold levels can be selected to cause a
forced reset of the chip.
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7.17.3 Code security (Code Read Protection - CRP)
This feature of the LPC11C12/C14 allows user to enable different levels of security in the
system so that access to the on-chip flash and use of the Serial Wire Debugger (SWD)
and In-System Programming (ISP) can be restricted. When needed, CRP is invoked by
programming a specific pattern into a dedicated flash location. IAP commands are not
affected by the CRP.
In addition, ISP entry via the PIO0_1 pin can be disabled without enabling CRP. For
details see the LPC11Cx user manual.
There are three levels of Code Read Protection:
1. CRP1 disables access to the chip via the SWD and allows partial flash update
(excluding flash sector 0) using a limited set of the ISP commands. This mode is
useful when CRP is required and flash field updates are needed but all sectors can
not be erased.
2. CRP2 disables access to the chip via the SWD and only allows full flash erase and
update using a reduced set of the ISP commands.
3. Running an application with level CRP3 selected fully disables any access to the chip
via the SWD pins and the ISP. This mode effectively disables ISP override using
PIO0_1 pin, too. It is up to the user’s application to provide (if needed) flash update
mechanism using IAP calls or call reinvoke ISP command to enable flash update via
the UART.
CAUTION
If level three Code Read Protection (CRP3) is selected, no future factory testing can be
performed on the device.
In addition to the three CRP levels, sampling of pin PIO0_1 for valid user code can be
disabled. For details see the LPC11Cx user manual.
7.17.4 Boot loader
The boot loader controls initial operation after reset and also provides the means to
program the flash memory. This could be initial programming of a blank device, erasure
and re-programming of a previously programmed device, or programming of the flash
memory by the application program in a running system.
The boot loader code is executed every time the part is reset or powered up. The loader
can either execute the user application code or the ISP command handler via UART or
C_CAN. A LOW level during reset applied to the PIO0_1 pin is considered as an external
hardware request to start the ISP command handler. The state of PIO0_3 at reset
determines whether the UART (PIO0_3 HIGH) or the C_CAN (PIO0_3 LOW) interface will
be used.
The C_CAN ISP command handler uses the CANopen protocol and data organization
method. C_CAN ISP commands have the same functionality as UART ISP commands.
7.17.5 APB interface
The APB peripherals are located on one APB bus.
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7.17.6 AHBLite
The AHBLite connects the CPU bus of the ARM Cortex-M0 to the flash memory, the main
static RAM, and the Boot ROM.
7.17.7 External interrupt inputs
All GPIO pins can be level or edge sensitive interrupt inputs.
7.17.8 Memory mapping control
The Cortex-M0 incorporates a mechanism that allows remapping the interrupt vector table
to alternate locations in the memory map. This is controlled via the Vector Table Offset
Register contained in the NVIC.
The vector table may be located anywhere within the bottom 1 GB of Cortex-M0 address
space. The vector table must be located on a 128 word (512 byte) boundary.
7.18 Emulation and debugging
Debug functions are integrated into the ARM Cortex-M0. Serial wire debug with four
breakpoints and two watchpoints is supported.
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8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).[1]
Symbol
VDD
Parameter
Conditions
Min
1.8
Max
3.6
Unit
V
supply voltage (core and external rail)
input voltage
[2]
VI
5 V tolerant I/O
pins; only valid
when the VDD
supply voltage is
present
−0.5
+5.5
V
[3]
[3]
IDD
supply current
per supply pin
per ground pin
-
-
-
100
100
100
mA
mA
mA
ISS
ground current
I/O latch-up current
Ilatch
−(0.5VDD) < VI <
(1.5VDD);
Tj < 125 °C
[4]
Tstg
storage temperature
−65
+150
150
1.5
°C
°C
W
Tj(max)
Ptot(pack)
maximum junction temperature
total power dissipation (per package)
-
-
based on package
heat transfer, not
device power
consumption
[5]
VESD
electrostatic discharge voltage
human body
−5000
+5000
V
model; all pins
[1] The following applies to the limiting values:
a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive
static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated
maximum.
b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless
otherwise noted.
[2] Including voltage on outputs in 3-state mode.
[3] The peak current is limited to 25 times the corresponding maximum current.
[4] Dependent on package type.
[5] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.
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9. Static characteristics
Table 5.
Static characteristics
Tamb = −40 °C to +85 °C, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
VDD
supply voltage (core
and external rail)
1.8
3.3
3.6
V
IDD
supply current
Active mode; code
while(1){}
executed from flash
system clock = 12 MHz
VDD = 3.3 V
[2][3][4]
[5][6][7]
-
-
-
3
9
2
-
-
-
mA
mA
mA
[2][3][6]
[5][7][8]
system clock = 50 MHz
VDD = 3.3 V
[2][3][4]
[5][6][7]
Sleep mode;
system clock = 12 MHz
VDD = 3.3 V
[2][3][5]
[9]
Deep-sleep mode;
VDD = 3.3 V
-
-
6
-
-
μA
[2][10]
Deep power-down mode;
VDD = 3.3 V
220
nA
Standard port pins, RESET
IIL
LOW-level input current VI = 0 V; on-chip pull-up
resistor disabled
-
-
0.5
0.5
10
10
nA
nA
IIH
HIGH-level input
current
VI = VDD; on-chip
pull-down resistor
disabled
IOZ
OFF-state output
current
VO = 0 V; VO = VDD
on-chip pull-up/down
resistors disabled
;
-
0.5
-
10
nA
V
[11][12]
[13]
VI
input voltage
pin configured to provide
a digital function
0
5.0
VO
output voltage
output active
0
-
-
VDD
-
V
V
VIH
HIGH-level input
voltage
0.7VDD
VIL
LOW-level input voltage
hysteresis voltage
-
-
0.3VDD
V
V
V
Vhys
VOH
-
0.4
-
-
-
[14]
[14]
[14]
[14]
HIGH-level output
voltage
2.0 V ≤ VDD ≤ 3.6 V;
IOH = −4 mA
VDD − 0.4
1.8 V ≤ VDD < 2.0 V;
IOH = −3 mA
VDD − 0.4
-
-
-
-
V
V
V
VOL
LOW-level output
voltage
2.0 V ≤ VDD ≤ 3.6 V;
IOL = 4 mA
-
-
0.4
0.4
1.8 V ≤ VDD < 2.0 V;
IOL = 3 mA
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Table 5.
Static characteristics …continued
Tamb = −40 °C to +85 °C, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
[14]
IOH
HIGH-level output
current
VOH = VDD − 0.4 V;
2.0 V ≤ VDD ≤ 3.6 V
1.8 V ≤ VDD < 2.0 V
VOL = 0.4 V
−4
-
-
mA
[14]
[14]
−3
-
-
-
-
mA
mA
IOL
LOW-level output
current
4
2.0 V ≤ VDD ≤ 3.6 V
1.8 V ≤ VDD < 2.0 V
[14]
[15]
3
-
-
-
-
mA
mA
IOHS
IOLS
HIGH-level short-circuit VOH = 0 V
output current
−45
[15]
LOW-level short-circuit VOL = VDD
output current
-
-
50
mA
Ipd
Ipu
pull-down current
pull-up current
VI = 5 V
VI = 0 V;
10
50
150
μA
μA
−15
−50
−85
2.0 V ≤ VDD ≤ 3.6 V
1.8 V ≤ VDD < 2.0 V
−10
−50
−85
μA
μA
VDD < VI < 5 V
0
0
0
High-drive output pin (PIO0_7)
IIL
LOW-level input current VI = 0 V; on-chip pull-up
resistor disabled
-
-
0.5
0.5
10
10
nA
nA
IIH
HIGH-level input
current
VI = VDD; on-chip
pull-down resistor
disabled
IOZ
OFF-state output
current
VO = 0 V; VO = VDD
on-chip pull-up/down
resistors disabled
;
-
0.5
-
10
nA
V
[11][12]
[13]
VI
input voltage
pin configured to provide
a digital function
0
5.0
VO
output voltage
output active
0
-
-
VDD
-
V
V
VIH
HIGH-level input
voltage
0.7VDD
VIL
LOW-level input voltage
hysteresis voltage
-
-
-
-
0.3VDD
V
V
V
Vhys
VOH
0.4
-
-
[14]
[14]
[14]
[14]
[14]
[14]
HIGH-level output
voltage
2.0 V ≤ VDD ≤ 3.6 V;
IOH = −4 mA
VDD − 0.4
1.8 V ≤ VDD < 2.0 V;
VDD − 0.4
-
-
-
-
-
-
V
I
OH = −3 mA
VOL
LOW-level output
voltage
2.0 V ≤ VDD ≤ 3.6 V;
IOL = 4 mA
-
0.4
0.4
-
V
1.8 V ≤ VDD < 2.0 V;
-
V
I
OL = 3 mA
IOH
IOL
HIGH-level output
current
VOH = VDD − 0.4 V;
VDD ≥ 2.5 V
20
4
mA
mA
LOW-level output
current
VOL = 0.4 V
-
2.0 V ≤ VDD ≤ 3.6 V
1.8 V ≤ VDD < 2.0 V
[14]
3
-
-
mA
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Table 5.
Static characteristics …continued
Tamb = −40 °C to +85 °C, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
[15]
[15]
IOHS
HIGH-level short-circuit VOH = 0 V
output current
-
-
−45
mA
IOLS
LOW-level short-circuit VOL = VDD
output current
-
-
50
mA
Ipd
Ipu
pull-down current
pull-up current
VI = 5 V
VI = 0 V
10
50
150
μA
μA
−15
−50
−85
2.0 V ≤ VDD ≤ 3.6 V
1.8 V ≤ VDD < 2.0 V
−10
−50
−85
μA
μA
VDD < VI < 5 V
0
0
0
I2C-bus pins (PIO0_4 and PIO0_5)
VIH
HIGH-level input
voltage
0.7VDD
-
-
V
VIL
LOW-level input voltage
hysteresis voltage
-
-
0.3VDD
V
Vhys
IOL
-
0.5VDD
-
-
-
V
[14]
LOW-level output
current
VOL = 0.4 V; I2C-bus pins
configured as standard
mode pins
4
mA
2.0 V ≤ VDD ≤ 3.6 V
1.8 V ≤ VDD < 2.0 V
VOL = 0.4 V; I2C-bus pins
configured as Fast-mode
Plus pins
[14]
[14]
3
-
-
-
-
IOL
LOW-level output
current
20
mA
2.0 V ≤ VDD ≤ 3.6 V
1.8 V ≤ VDD < 2.0 V
VI = VDD
[14]
[16]
16
-
-
-
ILI
input leakage current
2
4
μA
μA
VI = 5 V
-
10
22
Oscillator pins
Vi(xtal)
crystal input voltage
crystal output voltage
−0.5
−0.5
1.8
1.8
1.95
1.95
V
V
Vo(xtal)
[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages.
[2] Tamb = 25 °C.
[3] IDD measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled.
[4] IRC enabled; system oscillator disabled; system PLL disabled.
[5] Pin CAN_RXD pulled LOW externally.
[6] BOD disabled.
[7] All peripherals disabled in the AHBCLKCTRL register. Peripheral clocks to UART and SPI0/1 disabled in system configuration block.
[8] IRC disabled; system oscillator enabled; system PLL enabled.
[9] All oscillators and analog blocks turned off in the PDSLEEPCFG register; PDSLEEPCFG = 0xFFFF FDFF.
[10] WAKEUP pin pulled HIGH externally.
[11] Including voltage on outputs in 3-state mode.
[12] VDD supply voltage must be present.
[13] 3-state outputs go into 3-state mode in Deep power-down mode.
[14] Accounts for 100 mV voltage drop in all supply lines.
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[15] Allowed as long as the current limit does not exceed the maximum current allowed by the device.
[16] To VSS
.
Table 6.
ADC static characteristics
Tamb = −40 °C to +85 °C unless otherwise specified; ADC frequency 4.5 MHz, VDD = 2.5 V to 3.6 V.
Symbol
Parameter
Conditions
Min
Typ
Max
VDD
1
Unit
V
VIA
Cia
analog input voltage
analog input capacitance
differential linearity error
integral non-linearity
offset error
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
pF
[1][2]
[3]
ED
± 1
LSB
LSB
LSB
%
EL(adj)
EO
± 1.5
± 3.5
0.6
[4]
[5]
EG
gain error
[6]
ET
absolute error
± 4
LSB
kΩ
Rvsi
voltage source interface
resistance
40
[7][8]
Ri
input resistance
-
-
2.5
MΩ
[1] The ADC is monotonic, there are no missing codes.
[2] The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 5.
[3] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
appropriate adjustment of gain and offset errors. See Figure 5.
[4] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the
ideal curve. See Figure 5.
[5] The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset
error, and the straight line which fits the ideal transfer curve. See Figure 5.
[6] The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated
ADC and the ideal transfer curve. See Figure 5.
[7] Tamb = 25 °C; maximum sampling frequency fs = 4.5 MHz and analog input capacitance Cia = 1 pF.
[8] Input resistance Ri depends on the sampling frequency fs: Ri = 1 / (fs × Cia).
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offset
error
gain
error
E
E
O
G
1023
1022
1021
1020
1019
1018
(2)
7
code
out
(1)
6
5
4
3
2
1
0
(5)
(4)
(3)
1 LSB
(ideal)
1018 1019 1020 1021 1022 1023 1024
1
2
3
4
5
6
7
V
(LSB
)
ideal
IA
offset error
E
O
V
− V
SS
DD
1 LSB =
1024
002aaf426
(1) Example of an actual transfer curve.
(2) The ideal transfer curve.
(3) Differential linearity error (ED).
(4) Integral non-linearity (EL(adj)).
(5) Center of a step of the actual transfer curve.
Fig 5. ADC characteristics
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9.1 BOD static characteristics
Table 7.
BOD static characteristics[1]
Tamb = 25 °C.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Vth
threshold voltage interrupt level 0
assertion
-
-
1.65
1.80
-
-
V
V
de-assertion
interrupt level 1
assertion
-
-
2.22
2.35
-
-
V
V
de-assertion
interrupt level 2
assertion
-
-
2.52
2.66
-
-
V
V
de-assertion
interrupt level 3
assertion
-
-
2.80
2.90
-
-
V
V
de-assertion
reset level 0
assertion
-
-
1.46
1.63
-
-
V
V
de-assertion
reset level 1
assertion
-
-
2.06
2.15
-
-
V
V
de-assertion
reset level 2
assertion
-
-
2.35
2.43
-
-
V
V
de-assertion
reset level 3
assertion
-
-
2.63
2.71
-
-
V
V
de-assertion
[1] Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see LPC11Cx
user manual.
9.2 Power consumption
Power measurements in Active, Sleep, and Deep-sleep modes were performed under the
following conditions (see LPC11Cx user manual):
• Configure all pins as GPIO with pull-up resistor disabled in the IOCONFIG block.
• Configure GPIO pins as outputs using the GPIOnDIR registers.
• Write 0 to all GPIOnDATA registers to drive the outputs LOW.
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002aaf390
12
I
DD
(mA)
(2)
48 MHz
8
4
0
(2)
36 MHz
(2)
24 MHz
(1)
12 MHz
1.8
2.4
3.0
3.6
V
(V)
DD
Conditions: Tamb = 25 °C; active mode entered executing code while(1){} from flash; all
peripherals disabled in the AHBCLKCTRL register (AHBCLKCTRL = 0x1F); all peripheral clocks
disabled; internal pull-up resistors disabled; BOD disabled; pin CAN_RXD pulled LOW externally.
(1) System oscillator and system PLL disabled; IRC enabled.
(2) System oscillator and system PLL enabled; IRC disabled.
Fig 6. Active mode: Typical supply current IDD versus supply voltage VDD for different
system clock frequencies
002aaf391
12
I
DD
(mA)
(2)
(2)
(2)
48 MHz
36 MHz
24 MHz
8
4
0
(1)
12 MHz
−40
−15
10
35
60
85
temperature (°C)
Conditions: VDD = 3.3 V; active mode entered executing code while(1){} from flash; all
peripherals disabled in the AHBCLKCTRL register (AHBCLKCTRL = 0x1F); all peripheral clocks
disabled; internal pull-up resistors disabled; BOD disabled; pin CAN_RXD pulled LOW externally.
(1) System oscillator and system PLL disabled; IRC enabled.
(2) System oscillator and system PLL enabled; IRC disabled.
Fig 7. Active mode: Typical supply current IDD versus temperature for different system
clock frequencies
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002aaf392
8
6
4
2
0
I
DD
(mA)
(2)
48 MHz
(2)
36 MHz
24 MHz
(2)
(1)
12 MHz
−40
−15
10
35
60
85
temperature (°C)
Conditions: VDD = 3.3 V; sleep mode entered from flash; all peripherals disabled in the
AHBCLKCTRL register (AHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal pull-up
resistors disabled; BOD disabled; pin CAN_RXD pulled LOW externally.
(1) System oscillator and system PLL disabled; IRC enabled.
(2) System oscillator and system PLL enabled; IRC disabled.
Fig 8. Sleep mode: Typical supply current IDDversus temperature for different system
clock frequencies
002aaf394
40
I
DD
(μA)
30
3.6 V
3.3 V
2.0 V
1.8 V
20
10
0
−40
−15
10
35
60
85
temperature (°C)
Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register
(PDSLEEPCFG = 0xFFFF FDFF); pin CAN_RXD pulled LOW externally.
Fig 9. Deep-sleep mode: Typical supply current IDD versus temperature for different
supply voltages VDD
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002aaf457
0.8
I
DD
(μA)
0.6
VDD = 3.6 V
3.3 V
2.0 V
1.8 V
0.4
0.2
0
−40
−15
10
35
60
85
temperature (°C)
Fig 10. Deep power-down mode: Typical supply current IDD versus temperature for
different supply voltages VDD
9.3 Electrical pin characteristics
002aae990
3.6
V
(V)
OH
T = 85 °C
25 °C
−40 °C
3.2
2.8
2.4
2
0
10
20
30
40
50
60
I
(mA)
OH
Conditions: VDD = 3.3 V; on pin PIO0_7.
Fig 11. High-drive output: Typical HIGH-level output voltage VOH versus HIGH-level
output current IOH
.
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002aaf019
60
I
OL
T = 85 °C
(mA)
25 °C
−40 °C
40
20
0
0
0.2
0.4
0.6
V
OL
(V)
Conditions: VDD = 3.3 V; on pins PIO0_4 and PIO0_5.
Fig 12. I2C-bus pins (high current sink): Typical LOW-level output current IOL versus
LOW-level output voltage VOL
002aae991
15
I
OL
T = 85 °C
25 °C
−40 °C
(mA)
10
5
0
0
0.2
0.4
0.6
V
OL
(V)
Conditions: VDD = 3.3 V; standard port pins and PIO0_7.
Fig 13. Typical LOW-level output current IOL versus LOW-level output voltage VOL
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002aae992
3.6
V
OH
(V)
T = 85 °C
25 °C
−40 °C
3.2
2.8
2.4
2
0
8
16
24
I
(mA)
OH
Conditions: VDD = 3.3 V; standard port pins.
Fig 14. Typical HIGH-level output voltage VOH versus HIGH-level output source current
IOH
002aae988
10
I
pu
(μA)
−10
−30
−50
−70
T = 85 °C
25 °C
−40 °C
0
1
2
3
4
5
V (V)
I
Conditions: VDD = 3.3 V; standard port pins.
Fig 15. Typical pull-up current Ipu versus input voltage VI
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002aae989
80
T = 85 °C
25 °C
−40 °C
I
pd
(μA)
60
40
20
0
0
1
2
3
4
5
V (V)
I
Conditions: VDD = 3.3 V; standard port pins.
Fig 16. Typical pull-down current Ipd versus input voltage VI
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10. Dynamic characteristics
10.1 Flash memory
Table 8.
Flash characteristics
Tamb = −40 °C to +85 °C, unless otherwise specified.
Symbol
Nendu
tret
Parameter
endurance
Conditions
Min
10000
10
Typ
Max
Unit
[1]
-
-
cycles
years
years
ms
retention time
powered
-
-
unpowered
20
-
-
ter
erase time
sector or multiple
consecutive
sectors
95
100
105
[2]
tprog
programming
time
0.95
1
1.05
ms
[1] Number of program/erase cycles.
[2] Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash
in blocks of 256 bytes.
10.2 External clock
Table 9.
Dynamic characteristic: external clock
Tamb = −40 °C to +85 °C; VDD over specified ranges.[1]
Symbol
fosc
Parameter
Conditions
Min
Typ[2]
Max
Unit
MHz
ns
oscillator frequency
clock cycle time
clock HIGH time
clock LOW time
clock rise time
clock fall time
1
-
-
-
-
-
-
25
Tcy(clk)
tCHCX
tCLCX
tCLCH
tCHCL
40
1000
Tcy(clk) × 0.4
-
ns
Tcy(clk) × 0.4
-
ns
-
-
5
5
ns
ns
[1] Parameters are valid over operating temperature range unless otherwise specified.
[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply
voltages.
t
CHCX
t
t
t
CHCL
CLCX
CLCH
T
cy(clk)
002aaa907
Fig 17. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV)
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10.3 Internal oscillators
Table 10. Dynamic characteristic: internal oscillators
amb = −40 °C to +85 °C; 2.7 V ≤ VDD ≤ 3.6 V.[1]
T
Symbol Parameter Conditions
fosc(RC) internal RC oscillator frequency -
Min
Typ[2]
Max
Unit
11.88
12
12.12
MHz
[1] Parameters are valid over operating temperature range unless otherwise specified.
[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply
voltages.
002aaf403
12.15
f
(MHz)
VDD = 3.6 V
3.3 V
3.0 V
2.7 V
12.05
2.4 V
2.0 V
11.95
11.85
−40
−15
10
35
60
85
temperature (°C)
Conditions: Frequency values are typical values. 12 MHz ± 1 % accuracy is guaranteed for
2.7 V ≤ VDD ≤ 3.6 V and Tamb = −40 °C to +85 °C. Variations between parts may cause the IRC to
fall outside the 12 MHz ± 1 % accuracy specification for voltages below 2.7 V.
Fig 18. Internal RC oscillator frequency vs. temperature
Table 11. Dynamic characteristics: Watchdog oscillator
Symbol Parameter
Conditions
Min Typ[1]
Max Unit
[2][3]
[2][3]
fosc internal oscillator DIVSEL = 0x1F, FREQSEL = 0x1
-
7.8
-
kHz
frequency
in the WDTOSCCTRL register;
DIVSEL = 0x00, FREQSEL = 0xF
in the WDTOSCCTRL register
-
1700
-
kHz
[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply
voltages.
[2] The typical frequency spread over processing and temperature (Tamb = −40 °C to +85 °C) is ±40 %.
[3] See the LPC11Cx user manual.
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10.4 I/O pins
Table 12. Dynamic characteristic: I/O pins[1]
Tamb = −40 °C to +85 °C; 1.8 V ≤ VDD ≤ 3.6 V.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tr
rise time
pin
3.0
-
5.0
ns
configured as
output
tf
fall time
pin
2.5
-
5.0
ns
configured as
output
[1] Applies to standard port pins and RESET pin.
10.5 I2C-bus
Table 13. Dynamic characteristic: I2C-bus pins[1]
Tamb = −40 °C to +85 °C.[2]
Symbol
Parameter
Conditions
Min
Max
Unit
kHz
kHz
MHz
ns
fSCL
SCL clock
frequency
Standard-mode
Fast-mode
0
0
0
-
100
400
1
Fast-mode Plus
[4][5][6][7]
tf
fall time
of both SDA and
SCL signals
300
Standard-mode
Fast-mode
20 + 0.1 × Cb 300
ns
ns
μs
μs
μs
μs
μs
μs
μs
μs
μs
ns
ns
ns
Fast-mode Plus
Standard-mode
Fast-mode
-
120
tLOW
LOW period of
the SCL clock
4.7
1.3
0.5
4.0
0.6
0.26
0
-
-
-
-
-
-
-
-
-
-
-
-
Fast-mode Plus
Standard-mode
Fast-mode
tHIGH
HIGH period of
the SCL clock
Fast-mode Plus
Standard-mode
Fast-mode
[3][4][8]
[9][10]
tHD;DAT
data hold time
0
Fast-mode Plus
Standard-mode
Fast-mode
0
tSU;DAT
data set-up
time
250
100
50
Fast-mode Plus
[1] See the I2C-bus specification UM10204 for details.
[2] Parameters are valid over operating temperature range unless otherwise specified.
[3] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission
and the acknowledge.
[4] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the
VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL.
[5] Cb = total capacitance of one bus line in pF.
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[6] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA
output stage tf is specified at 250 ns. This allows series protection resistors to be connected in between the
SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf.
[7] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors
are used, designers should allow for this when considering bus timing.
[8] The maximum tHD;DAT could be 3.45 μs and 0.9 μs for Standard-mode and Fast-mode but must be less than
the maximum of tVD;DAT or tVD;ACK by a transition time (see UM10204). This maximum must only be met if
the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the
data must be valid by the set-up time before it releases the clock.
[9] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in
transmission and the acknowledge.
[10] A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement tSU;DAT
=
250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period
of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next
data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus
specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.
t
t
SU;DAT
f
70 %
30 %
70 %
30 %
SDA
SCL
t
t
HD;DAT
VD;DAT
t
f
t
HIGH
70 %
30 %
70 %
30 %
70 %
30 %
70 %
30 %
t
LOW
1 / f
S
SCL
002aaf425
Fig 19. I2C-bus pins clock timing
10.6 SPI interfaces
Table 14. Dynamic characteristics of SPI pins in SPI mode
Symbol
Tcy(PCLK) PCLK cycle time
Tcy(clk) clock cycle time
SPI master (in SPI mode)
Parameter
Conditions
Min
Typ
Max
Unit
ns
20
40
-
-
-
-
[1]
[2]
ns
tDS
data set-up time
in SPI mode
27
-
-
ns
2.0 V ≤ VDD ≤ 3.6 V
1.8 V ≤ VDD < 2.0 V
in SPI mode
36
0
-
-
-
-
-
ns
ns
ns
ns
[2]
[2]
[2]
tDH
data hold time
-
tv(Q)
th(Q)
data output valid time in SPI mode
data output hold time in SPI mode
-
10
-
0
SPI slave (in SPI mode)
[3][4]
tDS
data set-up time
in SPI mode
0
-
-
ns
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Table 14. Dynamic characteristics of SPI pins in SPI mode
Symbol
tDH
Parameter
Conditions
Min
Typ
Max
Unit
ns
[3][4]
[3][4]
[3][4]
data hold time
in SPI mode
3 × Tcy(PCLK) + 4
-
-
-
-
tv(Q)
data output valid time in SPI mode
data output hold time in SPI mode
-
-
3 × Tcy(PCLK) + 11
2 × Tcy(PCLK) + 5
ns
th(Q)
ns
[1] Tcy(clk) = (SSPCLKDIV × (1 + SCR) × CPSDVSR) / fmain. The clock cycle time derived from the SPI bit rate Tcy(clk) is a function of the
main clock frequency fmain, the SPI peripheral clock divider (SSPCLKDIV), the SPI SCR parameter (specified in the SSP0CR0 register),
and the SPI CPSDVSR parameter (specified in the SPI clock prescale register).
[2] Tamb = −40 °C to 85 °C.
[3]
Tcy(clk) = 12 × Tcy(PCLK).
[4] Tamb = 25 °C; for normal voltage supply range: VDD = 3.3 V.
T
t
t
clk(L)
cy(clk)
clk(H)
SCK (CPOL = 0)
SCK (CPOL = 1)
MOSI
t
t
h(Q)
v(Q)
DATA VALID
DATA VALID
CPHA = 1
t
t
DH
DS
DATA VALID
DATA VALID
MISO
t
t
h(Q)
v(Q)
DATA VALID
DATA VALID
t
MOSI
MISO
t
CPHA = 0
DS
DH
DATA VALID
DATA VALID
002aae829
Pin names SCK, MISO, and MOSI refer to pins for both SPI peripherals, SPI0 and SPI1.
Fig 20. SPI master timing in SPI mode
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T
t
t
clk(L)
cy(clk)
clk(H)
SCK (CPOL = 0)
SCK (CPOL = 1)
t
t
DH
DS
MOSI
MISO
DATA VALID
DATA VALID
t
t
h(Q)
v(Q)
CPHA = 1
DATA VALID
DATA VALID
t
t
DH
DS
MOSI
MISO
DATA VALID
DATA VALID
DATA VALID
t
t
h(Q)
CPHA = 0
002aae830
v(Q)
DATA VALID
Pin names SCK, MISO, and MOSI refer to pins for both SPI peripherals, SPI0 and SPI1.
Fig 21. SPI slave timing in SPI mode
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11. Application information
11.1 ADC usage notes
The following guidelines show how to increase the performance of the ADC in a noisy
environment beyond the ADC specifications listed in Table 6:
• The ADC input trace must be short and as close as possible to the LPC11C12/C14
chip.
• The ADC input traces must be shielded from fast switching digital signals and noisy
power supply lines.
• Because the ADC and the digital core share the same power supply, the power supply
line must be adequately filtered.
• To improve the ADC performance in a very noisy environment, put the device in Sleep
mode during the ADC conversion.
11.2 XTAL input
The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a
clock in slave mode, it is recommended that the input be coupled through a capacitor with
Ci = 100 pF. To limit the input voltage to the specified range, choose an additional
capacitor to ground Cg which attenuates the input voltage by a factor Ci/(Ci + Cg). In slave
mode, a minimum of 200 mV(RMS) is needed.
LPC1xxx
XTALIN
C
i
C
g
100 pF
002aae788
Fig 22. Slave mode operation of the on-chip oscillator
In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF
(Figure 22), with an amplitude between 200 mV(RMS) and 1000 mV(RMS). This
corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V.
The XTALOUT pin in this configuration can be left unconnected.
External components and models used in oscillation mode are shown in Figure 23 and in
Table 15 and Table 16. Since the feedback resistance is integrated on chip, only a crystal
and the capacitances CX1 and CX2 need to be connected externally in case of
fundamental mode oscillation (the fundamental frequency is represented by L, CL and
RS). Capacitance CP in Figure 23 represents the parallel package capacitance and should
not be larger than 7 pF. Parameters FOSC, CL, RS and CP are supplied by the crystal
manufacturer (see Table 15).
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LPC1xxx
L
XTALIN
XTALOUT
C
L
C
P
=
XTAL
R
S
C
X2
C
X1
002aaf424
Fig 23. Oscillator modes and models: oscillation mode of operation and external crystal
model used for CX1/CX2 evaluation
Table 15. Recommended values for CX1/CX2 in oscillation mode (crystal and external
components parameters) low frequency mode
Fundamental oscillation Crystal load
Maximum crystal
External load
frequency FOSC
capacitance CL
series resistance RS
capacitors CX1, CX2
1 MHz - 5 MHz
10 pF
< 300 Ω
< 300 Ω
< 300 Ω
< 300 Ω
< 200 Ω
< 100 Ω
< 160 Ω
< 60 Ω
18 pF, 18 pF
39 pF, 39 pF
57 pF, 57 pF
18 pF, 18 pF
39 pF, 39 pF
57 pF, 57 pF
18 pF, 18 pF
39 pF, 39 pF
18 pF, 18 pF
20 pF
30 pF
5 MHz - 10 MHz
10 pF
20 pF
30 pF
10 MHz - 15 MHz
15 MHz - 20 MHz
10 pF
20 pF
10 pF
< 80 Ω
Table 16. Recommended values for CX1/CX2 in oscillation mode (crystal and external
components parameters) high frequency mode
Fundamental oscillation Crystal load
Maximum crystal
External load
frequency FOSC
capacitance CL
series resistance RS
capacitors CX1, CX2
15 MHz - 20 MHz
10 pF
< 180 Ω
< 100 Ω
< 160 Ω
< 80 Ω
18 pF, 18 pF
39 pF, 39 pF
18 pF, 18 pF
39 pF, 39 pF
20 pF
20 MHz - 25 MHz
10 pF
20 pF
11.3 XTAL Printed Circuit Board (PCB) layout guidelines
The crystal should be connected on the PCB as close as possible to the oscillator input
and output pins of the chip. Take care that the load capacitors Cx1, Cx2, and Cx3 in case of
third overtone crystal usage have a common ground plane. The external components
must also be connected to the ground plain. Loops must be made as small as possible in
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order to keep the noise coupled in via the PCB as small as possible. Also parasitics
should stay as small as possible. Values of Cx1 and Cx2 should be chosen smaller
accordingly to the increase in parasitics of the PCB layout.
11.4 Standard I/O pad configuration
Figure 24 shows the possible pin modes for standard I/O pins with analog input function:
• Digital output driver
• Digital input: Pull-up enabled/disabled
• Digital input: Pull-down enabled/disabled
• Digital input: Repeater mode enabled/disabled
• Analog input
V
DD
output enable
ESD
pin configured
as digital output
driver
output
PIN
ESD
V
DD
V
SS
weak
pull-up
pull-up enable
weak
pull-down
repeater mode
enable
pin configured
as digital input
pull-down enable
data input
select analog input
pin configured
as analog input
analog input
002aaf304
Fig 24. Standard I/O pad configuration
LPC11C12_C14_0
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11.5 Reset pad configuration
V
DD
V
DD
V
DD
R
pu
ESD
20 ns RC
GLITCH FILTER
reset
PIN
ESD
V
SS
002aaf274
Fig 25. Reset pad configuration
LPC11C12_C14_0
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12. Package outline
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
SOT313-2
c
y
X
36
25
A
E
37
24
Z
E
e
H
E
A
2
A
(A )
3
A
1
w M
p
θ
pin 1 index
b
L
p
L
13
48
detail X
1
12
Z
v M
D
A
e
w M
b
p
D
B
H
v
M
B
D
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
7o
0o
0.20 1.45
0.05 1.35
0.27 0.18 7.1
0.17 0.12 6.9
7.1
6.9
9.15 9.15
8.85 8.85
0.75
0.45
0.95 0.95
0.55 0.55
1.6
mm
0.25
0.5
1
0.2 0.12 0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
00-01-19
03-02-25
SOT313-2
136E05
MS-026
Fig 26. Package outline SOT313-2 (LQFP48)
LPC11C12_C14_0
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13. Abbreviations
Table 17. Abbreviations
Acronym
ADC
AHB
AMBA
APB
API
Description
Analog-to-Digital Converter
Advanced High-performance Bus
Advanced Microcontroller Bus Architecture
Advanced Peripheral Bus
Application Programming Interface
BrownOut Detection
BOD
CAN
GPIO
PLL
Controller Area Network
General Purpose Input/Output
Phase-Locked Loop
RC
Resistor-Capacitor
SDO
SPI
Service Data Object
Serial Peripheral Interface
Serial Synchronous Interface
Synchronous Serial Port
SSI
SSP
TTL
Transistor-Transistor Logic
Universal Asynchronous Receiver/Transmitter
UART
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14. Revision history
Table 18. Revision history
Document ID
Release date
Data sheet status
Change notice Supersedes
LPC11C12_C14_0.06
Modifications:
<tbd>
Preliminary data sheet
• Corrected pin description: PIO2_4 on pin 18, PIO2_5 on pin 21; PIO3_4 and PIO3_5
are not available.
• Deep-sleep wake-up pins described in Table note 2 and Section 7.16.5.2.
LPC11C12_C14_0.05
<tbd>
Preliminary data sheet -
-
LPC11C12_C14_0
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15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
15.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
15.3 Disclaimers
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
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Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
15.4 Trademarks
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
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17. Contents
1
General description. . . . . . . . . . . . . . . . . . . . . . 1
7.16.5.3 Deep power-down mode . . . . . . . . . . . . . . . . 18
7.17
System control . . . . . . . . . . . . . . . . . . . . . . . . 18
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Brownout detection . . . . . . . . . . . . . . . . . . . . 18
Code security (Code Read Protection - CRP) 19
APB interface. . . . . . . . . . . . . . . . . . . . . . . . . 19
AHBLite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
External interrupt inputs. . . . . . . . . . . . . . . . . 19
Memory mapping control . . . . . . . . . . . . . . . . 19
Emulation and debugging . . . . . . . . . . . . . . . 20
2
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
7.17.1
7.17.2
7.17.3
7.17.4
7.17.5
7.17.6
7.17.7
7.18
3
4
4.1
5
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
8
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 21
7
7.1
7.2
7.3
7.4
7.5
7.5.1
7.5.2
7.6
7.7
7.7.1
7.8
7.8.1
7.9
7.9.1
7.10
7.10.1
7.11
7.11.1
7.12
7.12.1
7.13
Functional description . . . . . . . . . . . . . . . . . . . 9
ARM Cortex-M0 processor. . . . . . . . . . . . . . . . 9
On-chip flash program memory . . . . . . . . . . . . 9
On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . . 9
Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Nested Vectored Interrupt Controller (NVIC) . 10
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 11
IOCONFIG block . . . . . . . . . . . . . . . . . . . . . . 11
Fast general purpose parallel I/O . . . . . . . . . . 11
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
SPI serial I/O controller. . . . . . . . . . . . . . . . . . 12
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
I2C-bus serial I/O controller . . . . . . . . . . . . . . 12
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
C_CAN controller . . . . . . . . . . . . . . . . . . . . . . 13
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
General purpose external event
9
Static characteristics . . . . . . . . . . . . . . . . . . . 22
BOD static characteristics . . . . . . . . . . . . . . . 27
Power consumption . . . . . . . . . . . . . . . . . . . 27
Electrical pin characteristics. . . . . . . . . . . . . . 30
9.1
9.2
9.3
10
Dynamic characteristics. . . . . . . . . . . . . . . . . 34
Flash memory . . . . . . . . . . . . . . . . . . . . . . . . 34
External clock. . . . . . . . . . . . . . . . . . . . . . . . . 34
Internal oscillators . . . . . . . . . . . . . . . . . . . . . 35
I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
I2C-bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
SPI interfaces. . . . . . . . . . . . . . . . . . . . . . . . . 37
10.1
10.2
10.3
10.4
10.5
10.6
11
Application information . . . . . . . . . . . . . . . . . 40
ADC usage notes. . . . . . . . . . . . . . . . . . . . . . 40
XTAL input . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
XTAL Printed Circuit Board (PCB) layout
guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Standard I/O pad configuration . . . . . . . . . . . 42
Reset pad configuration. . . . . . . . . . . . . . . . . 43
11.1
11.2
11.3
11.4
11.5
12
13
14
Package outline. . . . . . . . . . . . . . . . . . . . . . . . 44
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 45
Revision history . . . . . . . . . . . . . . . . . . . . . . . 46
counter/timers. . . . . . . . . . . . . . . . . . . . . . . . . 14
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
System tick timer . . . . . . . . . . . . . . . . . . . . . . 14
Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 14
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Clocking and power control . . . . . . . . . . . . . . 15
Crystal oscillators . . . . . . . . . . . . . . . . . . . . . . 15
7.13.1
7.14
7.15
7.15.1
7.16
7.16.1
15
Legal information . . . . . . . . . . . . . . . . . . . . . . 47
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 47
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 48
15.1
15.2
15.3
15.4
16
17
Contact information . . . . . . . . . . . . . . . . . . . . 48
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.16.1.1 Internal RC oscillator . . . . . . . . . . . . . . . . . . . 16
7.16.1.2 System oscillator . . . . . . . . . . . . . . . . . . . . . . 16
7.16.1.3 Watchdog oscillator . . . . . . . . . . . . . . . . . . . . 17
7.16.2
7.16.3
7.16.4
7.16.5
System PLL . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Wake-up process . . . . . . . . . . . . . . . . . . . . . . 17
Power control . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.16.5.1 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.16.5.2 Deep-sleep mode . . . . . . . . . . . . . . . . . . . . . . 18
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 6 May 2010
Document identifier: LPC11C12_C14_0
相关型号:
LPC11C22FBD48/301
IC 32-BIT, FLASH, 50 MHz, RISC MICROCONTROLLER, PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT313-2, LQFP-48, Microcontroller
NXP
LPC11C24FBD48/301
32-BIT, FLASH, 50MHz, RISC MICROCONTROLLER, PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT313-2, LQFP-48
NXP
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