LPC11U6X_技术文档

LPC11U6x

32-bit ARM Cortex-M0+ microcontroller; up to 256 KB flash

and 36 KB SRAM; 4 KB EEPROM; USB; 12-bit ADC

Rev. 1.5 — 12 August 2020

Product data sheet

1. General description

The LPC11U6x are an ARM Cortex-M0+ based, low-cost 32-bit MCU family operating at

CPU frequencies of up to 50 MHz. The LPC11U6x support up to 256 KB of flash memory,

a 4 KB EEPROM, and 36 KB of SRAM.

The ARM Cortex-M0+ is an easy-to-use, energy-efficient core using a two-stage pipeline

and fast single-cycle I/O access.

The peripheral complement of the LPC11U6x includes a DMA controller, a CRC engine,

one full-speed USB device controller with XTAL-less low-speed mode, two I²C-bus

interfaces, up to five USARTs, two SSP interfaces, PWM/timer subsystem with six

configurable multi-purpose timers, a Real-Time Clock, one 12-bit ADC, temperature

sensor, function-configurable I/O ports, and up to 80 general-purpose I/O pins.

For additional documentation related to the LPC11U6x parts, see Section 17

“References”.

2. Features and benefits

 System:

 ARM Cortex-M0+ processor (version r0p1), running at frequencies of up to 50 MHz

with single-cycle multiplier and fast single-cycle I/O port.

 ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC).

 AHB Multilayer matrix.

 System tick timer.

 Serial Wire Debug (SWD) and JTAG boundary scan modes supported.

 Micro Trace Buffer (MTB) supported.

 Memory:

 Up to 256 KB on-chip flash programming memory with page erase.

 Up to 32 KB main SRAM.

 Up to two additional SRAM blocks of 2 KB each.

 Up to 4 KB EEPROM.

 ROM API support:

 Boot loader.

 USART drivers.

 I2C drivers.

 USB drivers.

 DMA drivers.

LPC11U6x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

 Power profiles.

 Flash In-Application Programming (IAP) and In-System Programming (ISP).

 32-bit integer division routines.

 Digital peripherals:

 Simple DMA engine with 16 channels and programmable input triggers.

 High-speed GPIO interface connected to the ARM Cortex-M0+ IO bus with up to 80

General-Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors,

programmable open-drain mode, input inverter, and programmable glitch filter and

digital filter.

 Pin interrupt and pattern match engine using eight selectable GPIO pins.

 Two GPIO group interrupt generators.

 CRC engine.

 Configurable PWM/timer subsystem (two 16-bit and two 32-bit standard

counter/timers, two State-Configurable Timers (SCTimer/PWM)) that provides:

 Up to four 32-bit and two 16-bit counter/timers or two 32-bit and six 16-bit

counter/timers.

 Up to 21 match outputs and 16 capture inputs.

 Up to 19 PWM outputs with 6 independent time bases.

 Windowed WatchDog timer (WWDT).

 Real-time Clock (RTC) in the always-on power domain with separate battery supply

pin and 32 kHz oscillator.

 Analog peripherals:

 One 12-bit ADC with up to 12 input channels with multiple internal and external

trigger inputs and with sample rates of up to 2 Msamples/s. The ADC supports two

independent conversion sequences.

 Temperature sensor.

 Serial interfaces:

 Up to five USART interfaces, all with DMA, synchronous mode, and RS-485 mode

support. Four USARTs use a shared fractional baud generator.

 Two SSP controllers with DMA support.

 Two I²C-bus interfaces. One I²C-bus interface with specialized open-drain pins

supports I2C Fast-mode plus.

 USB 2.0 full-speed device controller with on-chip PHY. XTAL-less low-speed mode

supported.

 Clock generation:

 12 MHz internal RC oscillator trimmed to 1 % accuracy for 25 C  T_amb +85 C

that can optionally be used as a system clock.

 On-chip 32 kHz oscillator for RTC.

 Crystal oscillator with an operating range of 1 MHz to 25 MHz. Oscillator pins are

shared with the GPIO pins.

 Programmable watchdog oscillator with a frequency range of 9.4 kHz to 2.3 MHz.

 PLL allows CPU operation up to the maximum CPU rate without the need for a

high-frequency crystal.

 A second, dedicated PLL is provided for USB.

 Clock output function with divider that can reflect the crystal oscillator, the main

clock, the IRC, or the watchdog oscillator.

LPC11U6x

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Product data sheet

Rev. 1.5 — 12 August 2020

2 of 97

LPC11U6x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

 Power control:

 Integrated PMU (Power Management Unit) to minimize power consumption.

 Reduced power modes: Sleep mode, Deep-sleep mode, Power-down mode, and

Deep power-down mode.

 Wake-up from Deep-sleep and Power-down modes on external pin inputs and

USART activity.

 Power-On Reset (POR).

 Brownout detect.

 Unique device serial number for identification.

 Single power supply (2.4 V to 3.6 V).

 Separate VBAT supply for RTC.

 Operating temperature range 40 °C to 105 °C.

 Available as LQFP48, LQFP64, and LQFP100 packages.

3. Applications

 Three-phase e-meter

 Car radio

 GPS tracker

 Medical monitor

 PC peripherals

 Gaming accessories

LPC11U6x

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Product data sheet

Rev. 1.5 — 12 August 2020

3 of 97

LPC11U6x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

4. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

Version

LPC11U66JBD48

LPC11U67JBD48

LPC11U67JBD64

LPC11U67JBD100

LPC11U68JBD48

LPC11U68JBD64

LPC11U68JBD100

LQFP48

LQFP64

LQFP100

LQFP48

LQFP64

LQFP100

plastic low profile quad flat package; 48 leads; body 7  7  1.4 mm

plastic low profile quad flat package; 64 leads; body 10  10  1.4 mm

SOT313-2

SOT314-2

plastic low profile quad flat package; 100 leads; body 14  14  1.4 mm SOT407-1

plastic low profile quad flat package; 48 leads; body 7  7  1.4 mm

plastic low profile quad flat package; 64 leads; body 10  10  1.4 mm

SOT313-2

SOT314-2

plastic low profile quad flat package; 100 leads; body 14  14  1.4 mm SOT407-1

4.1 Ordering options

Table 2.

Ordering options

Type number

Flash/ EEPROM/ SRAM/ USB

I²C SSP Timers 12-bit

GPIO

KB

with

ADC

PWM

channels

LPC11U66JBD48

LPC11U67JBD48

LPC11U67JBD64

64

4

12

20

36

1

Y

N

Y

N

Y

N

Y

N

Y

2

6

8

34

48

80

34

48

80

128

8

10

12

8

LPC11U67JBD100 128

LPC11U68JBD48

LPC11U68JBD64

256

10

12

LPC11U68JBD100 256

LPC11U6x

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Product data sheet

Rev. 1.5 — 12 August 2020

4 of 97

LPC11U6x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

5. Marking

n

1

Terminal 1 index area

aaa-011231

aaa-011232

Fig 1. LQFP64/100 package marking

Fig 2. LQFP48 package marking

The LPC11U6x devices typically have the following top-side marking for LQFP100

packages:

LPC11U6xJBD100

xxxxxx xx

xxxyywwxR[x]

The LPC11U6x devices typically have the following top-side marking for LQFP64

packages:

LPC11U6xJ

xxxxxx xx

xxxyywwxR[x]

The LPC11U6x devices typically have the following top-side marking for LQFP48

packages:

LPC11U6xJ

xx xx

xxxyy

wwxR[x]

Field ‘yy’ states the year the device was manufactured. Field ‘ww’ states the week the

device was manufactured during that year. Field ‘R’ states the chip revision.

LPC11U6x

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Product data sheet

Rev. 1.5 — 12 August 2020

5 of 97

LPC11U6x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

6. Block diagram

LPC11U6x

PROCESSOR CORE

SWD TEST/DEBUG

INTERFACE

ARM

CORTEX-M0+

NVIC

SYSTICK

HS GPIO+

MEMORY

PORT0/1/2

256/128/64 KB FLASH

4 KB EEPROM

36/20/12 KB SRAM

ROM

AHB MULTILAYER

MATRIX

PINT/

PATTERN MATCH

PINTSEL

GINT0/1

AHB/APB BRIDGES

ANALOG PERIPHERALS

TEMPERATURE SENSOR

12-bit ADC0

TRIGGER MUX

IOCON

PWM/TIMER SUBSYSTEM

n

pads

SCTIMER0/

PWM

DMA

CT16B0

CT16B1

CT32B0

CT32B1

DMA TRIGGER

SCTIMER1/

PWM

SERIAL PERIPHERALS

USART0

USART1

USART2

SSP0

SSP1

FM+ I2C0

I2C1

FS USB/

PHY

(1)

USART3

USART4

CLOCK

GENERATION

PRECISION

IRC

WATCHDOG

OSCILLATOR

SYSTEM

OSCILLATOR

SYSTEM

PLL

USB

PLL

ALWAYS-ON POWER DOMAIN

SYSTEM TIMER

RTC

GENERAL PURPOSE

BACKUP REGISTERS

WWDT

OSCILLATOR

SYSTEM/MEMORY CONTROL

SYSCON IOCON

PMU

CRC

FLASH CTRL

EEPROM CTRL

aaa-010773

Gray-shaded blocks show peripherals that can provide hardware triggers for DMA transfers or have DMA request lines.

(1) Available on LQFP100 packages only.

Fig 3. LPC11U6x block diagram

LPC11U6x

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Product data sheet

Rev. 1.5 — 12 August 2020

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LPC11U6x

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32-bit ARM Cortex-M0+ microcontroller

7. Pinning information

7.1 Pinning

SWDIO/PIO0_15 37

PIO0_16/WAKEUP 38

PIO0_23 39

24 PIO0_7

23 PIO0_6

22 PIO1_24

21 PIO2_7

20 USB_DP

19 USB_DM

18 PIO1_23

17 PIO0_21

16 PIO0_5

15 PIO0_4

14 PIO0_3

13 PIO1_20

V

40

41

DDA

V

SSA

PIO0_17 42

LPC11U6XJBD48

V

43

44

SS

DD

V

PIO0_18 45

PIO0_19 46

VBAT 47

RTCXIN 48

aaa-007794

Fig 4. LQFP48 pinning

LPC11U6x

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Product data sheet

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LPC11U6x

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PIO1_13 49

32 PIO2_15

31 PIO1_28

30 PIO0_7

29 PIO0_6

28 PIO1_24

27 PIO2_7

26 USB_DP

25 USB_DM

24 PIO2_6

23 PIO1_23

22 PIO0_21

21 PIO0_5

20 PIO0_4

19 PIO0_3

18 PIO1_20

17 PIO1_27

SWDIO/PIIO0_15 50

PIO0_16/WAKEUP 51

PIO0_23 52

V

53

54

DDA

V

SSA

PIO1_9 55

PIO0_17 56

LPC11U6XJBD64

V

57

58

59

SS

V

DD

V

PIO0_18 60

PIO0_19 61

PIO1_0 62

VBAT 63

PIO1_19 64

aaa-007795

Fig 5. LQFP64 pinning

76

50

LPC11U6XJBD100

100

26

aaa-007796

Fig 6. LQFP100 pinning

LPC11U6x

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Product data sheet

Rev. 1.5 — 12 August 2020

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LPC11U6x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

7.2 Pin description

Table 3.

Pin description

Pin functions are selected through the IOCON registers. See Table 2 for availability of USART3 and USART4 pin functions.

Symbol

Reset Type Description of pin functions

state^[1]

[8]

RESET/PIO0_0

3

4

8

I; PU

I

RESET — External reset input with 20 ns glitch filter. A

LOW-going pulse as short as 50 ns on this pin resets the

device, causing I/O ports and peripherals to take on their

default states, and processor execution to begin at address

0. This pin also serves as the debug select input. LOW

level selects the JTAG boundary scan. HIGH level selects

the ARM SWD debug mode.

In deep power-down mode, this pin must be pulled HIGH

externally. The RESET pin can be left unconnected or be

used as a GPIO pin if an external RESET function is not

needed and Deep power-down mode is not used.

IO

PIO0_0 — General-purpose digital input/output pin.

[6]

PIO0_1

4

5

9

I; PU

PIO0_1 — General-purpose digital input/output pin. A LOW

level on this pin during reset starts the ISP command

handler or the USB device enumeration.

O

IO

I

CLKOUT — Clockout pin.

CT32B0_MAT2 — Match output 2 for 32-bit timer 0.

USB_FTOGGLE — USB 1 ms Start-of-Frame signal.

PIO0_2 — General-purpose port 0 input/output 2.

SSP0_SSEL — Slave select for SSP0.

CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.

R_0 — Reserved.

[6]

PIO0_2

PIO0_3

11 14 19

I; PU

-

14 19 30

IO

PIO0_3 — General-purpose digital input/output pin. A LOW

level on this pin during reset starts the ISP command

handler. A HIGH level during reset starts the USB device

enumeration.

I

USB_VBUS — Monitors the presence of USB bus power.

R_1 — Reserved.

-

[7]

PIO0_4

PIO0_5

15 20 31

IA

IO

PIO0_4 — General-purpose port 0 input/output 4

(open-drain).

I2C0_SCL — I²C-bus clock input/output (open-drain).

High-current sink only if I²C Fast-mode Plus is selected in

the I/O configuration register.

IO

-

R_2 — Reserved.

[7]

16 21 32

IO

PIO0_5 — General-purpose port 0 input/output 5

(open-drain).

IO

-

I2C0_SDA — I²C-bus data input/output (open-drain).

High-current sink only if I²C Fast-mode Plus is selected in

the I/O configuration register.

R_3 — Reserved.

LPC11U6x

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Product data sheet

Rev. 1.5 — 12 August 2020

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LPC11U6x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

Table 3.

Pin description

Pin functions are selected through the IOCON registers. See Table 2 for availability of USART3 and USART4 pin functions.

Symbol

Reset Type Description of pin functions

state^[1]

[6]

[5]

PIO0_6

23 29 44

I; PU

IO

-

PIO0_6 — General-purpose port 0 input/output 6.

R — Reserved.

IO

-

SSP0_SCK — Serial clock for SSP0.

R_4 — Reserved.

PIO0_7

24 30 45

I; PU

IO

PIO0_7 — General-purpose port 0 input/output 7

(high-current output driver).

I

U0_CTS — Clear To Send input for USART.

-

R_5 — Reserved.

IO

I2C1_SCL — I²C-bus clock input/output. This pin is not

open-drain.

[6]

PIO0_8

26 37 58

27 38 59

28 39 60

I; PU

IO

O

-

PIO0_8 — General-purpose port 0 input/output 8.

SSP0_MISO — Master In Slave Out for SSP0.

CT16B0_MAT0 — Match output 0 for 16-bit timer 0.

R_6 — Reserved.

PIO0_9

IO

O

-

PIO0_9 — General-purpose port 0 input/output 9.

SSP0_MOSI — Master Out Slave In for SSP0.

CT16B0_MAT1 — Match output 1 for 16-bit timer 0.

R_7 — Reserved.

SWCLK/PIO0_10

IO

SWCLK — Serial Wire Clock. SWCLK is enabled by

default on this pin. In boundary scan mode: TCK (Test

Clock).

IO

O

PIO0_10 — General-purpose digital input/output pin.

SSP0_SCK — Serial clock for SSP0.

CT16B0_MAT2 — 16-bit timer0 MAT2

[3]

TDI/PIO0_11

30 42 64

I; PU

IO

TDI — Test Data In for JTAG interface. In boundary scan

mode only.

IO

AI

O

PIO0_11 — General-purpose digital input/output pin.

ADC_9 — A/D converter, input channel 9.

CT32B0_MAT3 — Match output 3 for 32-bit timer 0.

U1_RTS — Request To Send output for USART1.

O

IO

U1_SCLK — Serial clock input/output for USART1 in

synchronous mode.

[3]

TMS/PIO0_12

31 43 66

I; PU

IO

TMS — Test Mode Select for JTAG interface. In boundary

scan mode only.

IO

AI

I

PIO0_12 — General-purpose digital input/output pin.

ADC_8 — A/D converter, input channel 8.

CT32B1_CAP0 — Capture input 0 for 32-bit timer 1.

U1_CTS — Clear To Send input for USART1.

I

LPC11U6x

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Product data sheet

Rev. 1.5 — 12 August 2020

10 of 97

LPC11U6x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

Table 3.

Pin description

Pin functions are selected through the IOCON registers. See Table 2 for availability of USART3 and USART4 pin functions.

Symbol

Reset Type Description of pin functions

state^[1]

[3]

TDO/PIO0_13

32 45 68

I; PU

IO

TDO — Test Data Out for JTAG interface. In boundary

scan mode only.

IO

AI

O

I

PIO0_13 — General-purpose digital input/output pin.

ADC_7 — A/D converter, input channel 7.

CT32B1_MAT0 — Match output 0 for 32-bit timer 1.

U1_RXD — Receiver input for USART1.

[3]

TRST/PIO0_14

33 46 69

I; PU

IO

TRST — Test Reset for JTAG interface. In boundary scan

mode only.

IO

AI

O

PIO0_14 — General-purpose digital input/output pin.

ADC_6 — A/D converter, input channel 6.

CT32B1_MAT1 — Match output 1 for 32-bit timer 1.

U1_TXD — Transmitter output for USART1.

O

[3]

SWDIO/PIO0_15

37 50 81

I; PU

IO

SWDIO — Serial Wire Debug I/O. SWDIO is enabled by

default on this pin. In boundary scan mode: TMS (Test

Mode Select).

IO

AI

O

PIO0_15 — General-purpose digital input/output pin.

ADC_3 — A/D converter, input channel 3.

CT32B1_MAT2 — Match output 2 for 32-bit timer 1.

[4]

PIO0_16/WAKEUP

38 51 82

I; PU

IO

PIO0_16 — General-purpose digital input/output pin. This

pin also serves as the Deep power-down mode wake-up

pin with 20 ns glitch filter. Pull this pin HIGH externally

before entering Deep power-down mode. Pull this pin LOW

to exit Deep power-down mode. A LOW-going pulse as

short as 50 ns wakes up the part.

AI

O

-

ADC_2 — A/D converter, input channel 2.

CT32B1_MAT3 — Match output 3 for 32-bit timer 1.

R_8 — Reserved.

[6]

PIO0_17

42 56 90

I; PU

IO

O

I

PIO0_17 — General-purpose digital input/output pin.

U0_RTS — Request To Send output for USART0.

CT32B0_CAP0 — Capture input 0 for 32-bit timer 0.

IO

U0_SCLK — Serial clock input/output for USART0 in

synchronous mode.

[6]

PIO0_18

PIO0_19

45 60 94

I; PU

IO

I

PIO0_18 — General-purpose digital input/output pin.

U0_RXD — Receiver input for USART0. Used in UART

ISP mode.

O

CT32B0_MAT0 — Match output 0 for 32-bit timer 0.

PIO0_19 — General-purpose digital input/output pin.

46 61 95

IO

O

U0_TXD — Transmitter output for USART0. Used in UART

ISP mode.

O

CT32B0_MAT1 — Match output 1 for 32-bit timer 0.

LPC11U6x

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Product data sheet

Rev. 1.5 — 12 August 2020

11 of 97

LPC11U6x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

Table 3.

Pin description

Pin functions are selected through the IOCON registers. See Table 2 for availability of USART3 and USART4 pin functions.

Symbol

PIO0_20

PIO0_21

PIO0_22

Reset Type Description of pin functions

state^[1]

[6]

[3]

10 12 17

17 22 33

29 40 62

I; PU

IO

I

PIO0_20 — General-purpose digital input/output pin.

CT16B1_CAP0 — Capture input 0 for 16-bit timer 1.

U2_RXD — Receiver input for USART2.

PIO0_21 — General-purpose digital input/output pin.

CT16B1_MAT0 — Match output 0 for 16-bit timer 1.

SSP1_MOSI — Master Out Slave In for SSP1.

PIO0_22 — General-purpose digital input/output pin.

ADC_11 — A/D converter, input channel 11.

CT16B1_CAP1 — Capture input 1 for 16-bit timer 1.

SSP1_MISO — Master In Slave Out for SSP1.

PIO0_23 — General-purpose digital input/output pin.

ADC_1 — A/D converter, input channel 1.

R_9 — Reserved.

I

IO

O

IO

AI

I

IO

AI

-

[3]

PIO0_23

39 52 83

I; PU

I

U0_RI — Ring Indicator input for USART0.

SSP1_SSEL — Slave select for SSP1.

IO

O

-

[6]

[3]

PIO1_0

PIO1_1

PIO1_2

PIO1_3

-

62 97

I; PU

PIO1_0 — General-purpose digital input/output pin.

CT32B1_MAT0 — Match output 0 for 32-bit timer 1.

R_10 — Reserved.

O

IO

O

-

U2_TXD — Transmitter output for USART2.

PIO1_1 — General-purpose digital input/output pin.

CT32B1_MAT1 — Match output 1 for 32-bit timer 1.

R_11 — Reserved.

-

28

55

72

O

IO

O

-

U0_DTR — Data Terminal Ready output for USART0.

PIO1_2 — General-purpose digital input/output pin.

CT32B1_MAT2 — Match output 2 for 32-bit timer 1.

R_12 — Reserved.

I

U1_RXD — Receiver input for USART1.

PIO1_3 — General-purpose digital input/output pin.

CT32B1_MAT3 — Match output 3 for 32-bit timer 1.

R_13 — Reserved.

IO

O

-

IO

AI

IO

I

I2C1_SDA — I²C-bus data input/output (not open-drain).

ADC_5 — A/D converter, input channel 5.

PIO1_4 — General-purpose digital input/output pin.

CT32B1_CAP0 — Capture input 0 for 32-bit timer 1.

R_14 — Reserved.

[6]

PIO1_4

-

23

I; PU

-

I

U0_DSR — Data Set Ready input for USART0.

LPC11U6x

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Product data sheet

Rev. 1.5 — 12 August 2020

12 of 97

LPC11U6x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

Table 3.

Pin description

Pin functions are selected through the IOCON registers. See Table 2 for availability of USART3 and USART4 pin functions.

Symbol

Reset Type Description of pin functions

state^[1]

[6]

[3]

[6]

PIO1_5

-

47

98

10

61

I; PU

IO

I

PIO1_5 — General-purpose digital input/output pin.

CT32B1_CAP1 — Capture input 1 for 32-bit timer 1.

R_15 — Reserved.

-

I

U0_DCD — Data Carrier Detect input for USART0.

PIO1_6 — General-purpose digital input/output pin.

R_16 — Reserved.

PIO1_6

PIO1_7

PIO1_8

PIO1_9

PIO1_10

-

IO

-

I

U2_RXD — Receiver input for USART2.

CT32B0_CAP2 — Capture input 2 for 32-bit timer 0.

PIO1_7 — General-purpose digital input/output pin.

R_17 — Reserved.

I

6

-

IO

-

I

U2_CTS — Clear To Send input for USART2.

CT16B1_CAP0 — Capture input 0 for 32-bit timer 1.

PIO1_8 — General-purpose digital input/output pin.

R_18 — Reserved.

I

IO

-

O

I

U1_TXD — Transmitter output for USART1.

CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.

PIO1_9 — General-purpose digital input/output pin.

U0_CTS — Clear To Send input for USART0.

CT16B1_MAT1 — Match output 1 for 16-bit timer 1.

ADC_0 — A/D converter, input channel 0.

PIO1_10 — General-purpose digital input/output pin.

U2_RTS — Request To Send output for USART2.

55 86

IO

I

O

I

13 18

IO

O

IO

U2_SCLK — Serial clock input/output for USART2 in

synchronous mode.

O

IO

O

I

CT16B1_MAT0 — Match output 0 for 16-bit timer 1.

PIO1_11 — General-purpose digital input/output pin.

I2C1_SCL — I²C1-bus clock input/output (not open-drain).

CT16B0_MAT2 — Match output 2 for 16-bit timer 0.

U0_RI — Ring Indicator input for USART0.

PIO1_12 — General-purpose digital input/output pin.

SSP0_MOSI — Master Out Slave In for SSP0.

CT16B0_MAT1 — Match output 1 for 16-bit timer 0.

R_21 — Reserved.

[6]

PIO1_11

PIO1_12

PIO1_13

-

65

89

I; PU

IO

O

-

36 49 78

IO

I

PIO1_13 — General-purpose digital input/output pin.

U1_CTS — Clear To Send input for USART1.

SCT0_OUT3 — SCTimer0/PWM output 3.

R_22 — Reserved.

O

-

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Table 3.

Pin description

Pin functions are selected through the IOCON registers. See Table 2 for availability of USART3 and USART4 pin functions.

Symbol

Reset Type Description of pin functions

state^[1]

[6]

[3]

PIO1_14

-

79

87

96

34

43

4

I; PU

IO

O

-

PIO1_14 — General-purpose digital input/output pin.

I2C1_SDA — I²C1-bus data input/output (not open-drain).

CT32B1_MAT2 — Match output 2 for 32-bit timer 1.

R_23 — Reserved.

PIO1_15

PIO1_16

PIO1_17

PIO1_18

PIO1_19

PIO1_20

PIO1_21

PIO1_22

-

IO

O

-

PIO1_15 — General-purpose digital input/output pin.

SSP0_SSEL — Slave select for SSP0.

CT32B1_MAT3 — Match output 3 for 32-bit timer 1.

R_24 — Reserved.

-

IO

O

-

PIO1_16 — General-purpose digital input/output pin.

SSP0_MISO — Master In Slave Out for SSP0.

CT16B0_MAT0 — Match output 0 for 16-bit timer 0.

R_25 — Reserved.

-

IO

I

PIO1_17 — General-purpose digital input/output pin.

CT16B0_CAP2 — Capture input 2 for 16-bit timer 0.

U0_RXD — Receiver input for USART0.

R_26 — Reserved.

I

-

IO

I

PIO1_18 — General-purpose digital input/output pin.

CT16B1_CAP1 — Capture input 1 for 16-bit timer 1.

U0_TXD — Transmitter output for USART0.

R_27 — Reserved.

O

-

64

IO

I

PIO1_19 — General-purpose digital input/output pin.

U2_CTS — Clear To Send input for USART2.

SCT0_OUT0 — SCTimer0/PWM output 0.

R_28 — Reserved.

O

-

13 18 29

IO

I

PIO1_20 — General-purpose digital input/output pin.

U0_DSR — Data Set Ready input for USART0.

SSP1_SCK — Serial clock for SSP1.

IO

O

IO

I

CT16B0_MAT0 — Match output 0 for 16-bit timer 0.

PIO1_21 — General-purpose digital input/output pin.

U0_DCD — Data Carrier Detect input for USART0.

SSP1_MISO — Master In Slave Out for SSP1.

CT16B0_CAP2 — Capture input 2 for 16-bit timer 0.

PIO1_22 — General-purpose digital input/output pin.

SSP1_MOSI — Master Out Slave In for SSP1.

CT32B1_CAP1 — Capture input 1 for 32-bit timer 1.

ADC_4 — A/D converter, input channel 4.

R_29 — Reserved.

25 35 56

IO

I

-

80

IO

I

AI

-

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Table 3.

Pin description

Pin functions are selected through the IOCON registers. See Table 2 for availability of USART3 and USART4 pin functions.

Symbol

Reset Type Description of pin functions

state^[1]

[6]

PIO1_23

18 23 35

I; PU

IO

O

PIO1_23 — General-purpose digital input/output pin.

CT16B1_MAT1 — Match output 1 for 16-bit timer 1.

SSP1_SSEL — Slave select for SSP1.

IO

O

U2_TXD — Transmitter output for USART2.

[6]

PIO1_24

PIO1_25

22 28 42

I; PU

IO

O

PIO1_24 — General-purpose digital input/output pin.

CT32B0_MAT0 — Match output 0 for 32-bit timer 0.

I2C1_SDA — I²C-bus data input/output (not open-drain).

PIO1_25 — General-purpose digital input/output pin.

U2_RTS — Request To Send output for USART2.

IO

O

-

100

IO

U2_SCLK — Serial clock input/output for USART2 in

synchronous mode.

I

SCT0_IN0 — SCTimer0/PWM input 0.

R_30 — Reserved.

-

[6]

PIO1_26

PIO1_27

-

15 20

I; PU

IO

O

I

PIO1_26 — General-purpose digital input/output pin.

CT32B0_MAT2 — Match output 2 for 32-bit timer 0.

U0_RXD — Receiver input for USART0.

R_19 — Reserved.

-

17 22

IO

O

-

PIO1_27 — General-purpose digital input/output pin.

CT32B0_MAT3 — Match output 3 for 32-bit timer 0.

U0_TXD — Transmitter output for USART0.

R_20 — Reserved.

IO

I

SSP1_SCK — Serial clock for SSP1.

PIO1_28 — General-purpose digital input/output pin.

CT32B0_CAP0 — Capture input 0 for 32-bit timer 0.

[6]

PIO1_28

PIO1_29

-

31 46

I; PU

IO

U0_SCLK — Serial clock input/output for USART in

synchronous mode.

O

IO

I

U0_RTS — Request To Send output for USART0.

PIO1_29 — General-purpose digital input/output pin.

SSP0_SCK — Serial clock for SSP0.

[3]

41 63

CT32B0_CAP2 — Capture input 2 for 32-bit timer 0.

U0_DTR — Data Terminal Ready output for USART0.

ADC_10 — A/D converter, input channel 10.

PIO1_30 — General-purpose digital input/output pin.

I2C1_SCL — I²C1-bus clock input/output (not open-drain).

SCT0_IN3 — SCTimer0/PWM input 3.

O

AI

IO

I

[6]

[5]

PIO1_30

PIO1_31

-

44 67

I; PU

-

R_31 — Reserved.

-

48

IO

PIO1_31 — General-purpose digital input/output pin

(high-current output driver).

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Table 3.

Pin description

Pin functions are selected through the IOCON registers. See Table 2 for availability of USART3 and USART4 pin functions.

Symbol

Reset Type Description of pin functions

state^[1]

[10]

PIO2_0

6

7

8

9

12

13

I; PU

IO

AI

PIO2_0 — General-purpose digital input/output pin.

XTALIN — Input to the oscillator circuit and internal clock

generator circuits. Input voltage must not exceed 1.8 V.

[10]

[6]

PIO2_1

PIO2_2

I; PU

IO

AO

IO

O

PIO2_1 — General-purpose digital input/output pin.

XTALOUT — Output from the oscillator amplifier.

PIO2_2 — General-purpose digital input/output pin.

U3_RTS — Request To Send output for USART3.

12 16 21

IO

U3_SCLK — Serial clock input/output for USART3 in

synchronous mode.

SCT0_OUT1 — SCTimer0/PWM output 1.

[6]

PIO2_3

PIO2_4

PIO2_5

PIO2_6

-

36

41

I; PU

IO

I

PIO2_3 — General-purpose digital input/output pin.

U3_RXD — Receiver input for USART3.

O

IO

O

IO

I

CT32B0_MAT1 — Match output 1 for 32-bit timer 0.

PIO2_4 — General-purpose digital input/output pin.

U3_TXD — Transmitter output for USART3.

CT32B0_MAT2 — Match output 2 for 32-bit timer 0.

PIO2_5 — General-purpose digital input/output pin.

U3_CTS — Clear To Send input for USART3.

SCT0_IN1 — SCTimer0/PWM input 1.

-

9

-

11 15

24 37

I

IO

O

IO

PIO2_6 — General-purpose digital input/output pin.

U1_RTS — Request To Send output for USART1.

U1_SCLK — Serial clock input/output for USART1 in

synchronous mode.

I

SCT0_IN2 — SCTimer0/PWM input 2.

[6]

PIO2_7

21 27 40

I; PU

IO

I

PIO2_7 — General-purpose digital input/output pin.

SSP0_SCK — Serial clock for SSP0.

SCT0_OUT2 — SCTimer0/PWM output 2.

PIO2_8 — General-purpose digital input/output pin.

SCT1_IN0 — SCTimer1/PWM input 0.

[6]

PIO2_8

PIO2_9

PIO2_10

-

2

I; PU

IO

I

3

IO

I

PIO2_9 — General-purpose digital input/output pin.

SCT1_IN1 — SCTimer1/PWM_IN1

16

IO

O

IO

PIO2_10 — General-purpose digital input/output pin.

U4_RTS — Request To Send output for USART4.

U4_SCLK — Serial clock input/output for USART4 in

synchronous mode.

[6]

PIO2_11

PIO2_12

-

24

25

I; PU

IO

I

PIO2_11 — General-purpose digital input/output pin.

U4_RXD — Receiver input for USART4.

IO

O

PIO2_12 — General-purpose digital input/output pin.

U4_TXD — Transmitter output for USART4.

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Table 3.

Pin description

Pin functions are selected through the IOCON registers. See Table 2 for availability of USART3 and USART4 pin functions.

Symbol

Reset Type Description of pin functions

state^[1]

[6]

PIO2_13

PIO2_14

PIO2_15

PIO2_16

PIO2_17

PIO2_18

PIO2_19

-

26

27

I; PU

IO

I

PIO2_13 — General-purpose digital input/output pin.

U4_CTS — Clear To Send input for USART4.

PIO2_14 — General-purpose digital input/output pin.

SCT1_IN2 — SCTimer1/PWM input 2.

IO

I

32 49

IO

I

PIO2_15 — General-purpose digital input/output pin.

SCT1_IN3 — SCTimer1/PWM input 3.

-

50

51

IO

O

IO

O

IO

O

IO

O

IO

-

PIO2_16 — General-purpose digital input/output pin.

SCT1_OUT0 — SCTimer1/PWM output 0.

PIO2_17 — General-purpose digital input/output pin.

SCT1_OUT1 — SCTimer1/PWM output 1.

33 52

36 57

PIO2_18 — General-purpose port 2 input/output 18.

SCT1_OUT2 — SCTimer1/PWM output 2.

PIO2_19 — General-purpose port 2 input/output 19.

SCT1_OUT3 — SCTimer1/PWM output 3.

[6]

[9]

PIO2_20

PIO2_21

PIO2_22

PIO2_23

RSTOUT

USB_DP

-

75

76

77

1

I; PU

IA

PIO2_20 — General-purpose port 2 input/output 20.

PIO2_21 — General-purpose port 2 input/output 21.

PIO2_22 — General-purpose port 2 input/output 22.

PIO2_23 — General-purpose port 2 input/output 23.

Internal reset status output.

88

20 26 39

F

USB bidirectional D+ line. Pad includes internal 33 Ω series

termination resistor.

[9]

[2]

USB_DM

RTCXIN

19 25 38

F

-

USB bidirectional D line. Pad includes internal 33 Ω series

termination resistor.

48

1

2

5

6

RTC oscillator input. This input should be grounded if the

RTC is not used.

RTCXOUT

VREFP

-

RTC oscillator output.

34 47 73

35 48 74

40 53 84

ADC positive reference voltage. If the ADC is not used, tie

VREFP to V_DD

ADC negative voltage reference. If the ADC is not used, tie

VREFN to V_SS

.

VREFN

V_DDA

-

.

Analog voltage supply. V_DDAshould typically be the same

voltages as V_DDbut should be isolated to minimize noise

and error. V_DDAshould be tied to V_DDif the ADC is not

used.

V_DD

44, 58, 92,

-

Supply voltage to the internal regulator and the external

rail.

8

10, 14,

34, 71,

59 54,

93

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Table 3.

Pin description

Pin functions are selected through the IOCON registers. See Table 2 for availability of USART3 and USART4 pin functions.

Symbol

Reset Type Description of pin functions

state^[1]

VBAT

V_SSA

47 63 99

41 54 85

-

Battery supply. Supplies power to the RTC. If no battery is

used, tie VBAT to VDD.

Analog ground. V_SSAshould typically be the same voltage

as V_SSbut should be isolated to minimize noise and error.

V_SSAshould be tied to V_SSif the ADC is not used.

V_SS

43, 57, 91,

2, 3, 7,

-

Ground.

5

7

11,

53,

70

[1] Pin state at reset for default function: I = Input; AI = Analog Input; O = Output; PU = internal pull-up enabled; IA = inactive, no

pull-up/down enabled;

F = floating; If the pins are not used, tie floating pins to ground or power to minimize power consumption.

[2] Special analog pad.

[3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.

When configured as analog input, digital section of the pad is disabled and the pin is not 5 V tolerant; includes digital, programmable

filter.

[4] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.

When configured as analog input, digital section of the pad is disabled and the pin is not 5 V tolerant; includes digital input glitch filter.

WAKEUP pin. The wake-up pin function can be disabled and the pin can be used for other purposes if the RTC is enabled for waking up

the part from Deep power-down mode.

[5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis; includes

high-current output driver.

[6] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis.

[7] I²C-bus pin compliant with the I²C-bus specification for I²C standard mode, I²C Fast-mode, and I²C Fast-mode Plus. The pin requires

an external pull-up to provide output functionality. When power is switched off, this pin is floating and does not disturb the I2C lines.

Open-drain configuration applies to all functions on this pin.

[8] 5 V tolerant pad. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up

from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode.

[9] Pad provides USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode

only). This pad is not 5 V tolerant.

[10] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog crystal

oscillator connections. When configured for the crystal oscillator input/output, digital section of the pad is disabled and the pin is not 5 V

tolerant; includes digital, programmable filter.

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8. Functional description

8.1 ARM Cortex-M0+ core

The ARM Cortex-M0+ core runs at an operating frequency of up to 50 MHz using a

two-stage pipeline. Integrated in the core are the NVIC and Serial Wire Debug with four

breakpoints and two watchpoints. The ARM Cortex-M0+ core supports a single-cycle I/O

enabled port for fast GPIO access.

The core includes a single-cycle multiplier and a system tick timer.

8.2 AHB multilayer matrix

The AHB multilayer matrix supports three masters, the M0+ core, the DMA, and the USB.

All masters can access all slaves (peripherals and memories).

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TEST/DEBUG

INTERFACE

ARM

CORTEX-M0+

USB

DMA

masters

System

bus

slaves

FLASH

MAIN SRAM0

SRAM USB

SRAM1

ROM

EEPROM

SCTIMER0/PWM

SCTIMER1/PWM

HS GPIO

PINT/PATTERN MATCH

CRC

USB REGISTERS

DMA REGISTERS

AHB-TO-APB

BRIDGE

WWDT

USART0

CT16B0

CT16B1

I2C0

AHB MULTILAYER MATRIX

CT32B0 CT32B1

ADC

I2C1 RTC

DMA TRIGMUX

SYSCON

PMU

FLASHCTRL

SSP0 IOCON

GROUP0

USART3

USART1

GROUP1

USART4

SSP1

USART2

= master-slave connection

aaa-024616

Fig 7. AHB multilayer matrix

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8.3 On-chip flash programming memory

The LPC11U6x contain up to 256 KB on-chip flash program memory. The flash can be

programmed using In-System Programming (ISP) or In-Application Programming (IAP)

via the on-chip bootloader software.

The flash memory is divided into 24 x 4 KB and 5 x 32 KB sectors. Individual pages of

256 byte each can be erased using the IAP erase page command.

8.4 EEPROM

The LPC11U6x contain 4 KB of on-chip byte-erasable and byte-programmable EEPROM

data memory. The EEPROM can be programmed using In-Application Programming (IAP)

via the on-chip bootloader software.

8.5 SRAM

The LPC11U6x contain a total of up to 36 KB on-chip static RAM memory. The main

SRAM block contains either 8 KB, 16 KB, or 32 KB of main SRAM0. Two additional SRAM

blocks of 2 KB (SRAM1 and USB SRAM) are located in separate areas of the memory

map. See Figure 8.

8.6 On-chip ROM

The on-chip ROM contains the bootloader and the following Application Programming

Interfaces (APIs):

• In-System Programming (ISP) and In-Application Programming (IAP) support for flash

including IAP erase page command.

• IAP support for EEPROM

• USB API

• Power profiles for configuring power consumption and PLL settings

• 32-bit integer division routines

• APIs to use the following peripherals:

– I2C

– USART0 and USART1/2/3/4

– DMA

8.7 Memory mapping

The LPC11U6x incorporates several distinct memory regions, shown in the following

figures. Figure 8 shows the overall map of the entire address space from the user

program viewpoint following reset. The interrupt vector area supports address remapping.

The AHB (Advanced High-performance Bus) peripheral area is 2 MB in size and is divided

to allow for up to 128 peripherals. The APB (Advanced Peripheral Bus) peripheral area is

512 KB in size and is divided to allow for up to 32 peripherals. Each peripheral of either

type is allocated 16 KB of space. This addressing scheme allows simplifying the address

decoding for each peripheral.

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LPC11U6x

4 GB

0xFFFF FFFF

0xE010 0000

0xE000 0000

reserved

private peripheral bus

reserved

0xA000 8000

GPIO PINT

GPIO

0xA000 4000

0xA000 0000

APB peripherals

0x4008 0000

reserved

0x5001 0000

0x5000 E000

0x5000 C000

30 - 31 reserved

SCTIMER1/PWM

SCTIMER0/PWM

reserved

0x4007 8000

USART3

29

0x4007 4000

USART2

USART1

28

27

0x5000 8000

0x5000 4000

0x5000 0000

0x4007 0000

0x4006 C000

DMA

CRC

25 - 26 reserved

GPIO GROUP1 interrupt

GPIO GROUP0 interrupt

0x4006 4000

0x4006 0000

0x4005 C000

24

23

22

reserved

0x4008 4000

SSP1

USB

0x4005 8000

0x4005 0000

0x4008 0000

0x4000 0000

20 - 21 reserved

APB peripherals

1 GB

USART4

19

0x4004 C000

0x4004 8000

0x4004 4000

0x4004 0000

reserved

0x2000 4800

0x2000 4000

system control (SYSCON)

IOCON

18

17

16

2 KB USB SRAM

reserved

SSP0

0x2000 0800

0x2000 0000

15 flash/EEPROM controller

2 KB SRAM1

reserved

0x4003 C000

0x4003 8000

0.5 GB

14

PMU

0x1FFF 8000

0x1FFF 0000

11 - 13 reserved

0x4002 C000

0x4002 8000

32 KB boot ROM

reserved

DMA TRIGMUX

RTC

10

9

0x4002 4000

0x4002 0000

0x1400 1000

0x1400 0000

I2C1

8

4 KB MTB registers

reserved

12-bit ADC

7

0x4001 C000

0x4001 8000

32-bit counter/timer 1

6

0x1000 8000

0x1000 4000

32-bit counter/timer 0

16-bit counter/timer 1

16-bit counter/timer 0

USART0

32 KB MAIN SRAM0 (LPC11U68)

16 KB MAIN SRAM0 (LPC11U67)

8 KB MAIN SRAM0 (LPC11U66)

5

0x4001 4000

0x4001 0000

0x4000 C000

0x4000 8000

4

0x1000 2000

0x1000 0000

3

2

reserved

0x0004 0000

0x0002 0000

WWDT

1

0

0x4000 4000

0x4000 0000

256 KB on-chip flash (LPC11U68)

128 KB on-chip flash (LPC11U67)

I2C0

0x0000 00C0

0x0001 0000

0x0000 0000

active interrupt vectors

64 KB on-chip flash (LPC11U66)

0x0000 0000

0 GB

aaa-010775

Fig 8. LPC11U6x Memory map

8.8 Nested Vectored Interrupt Controller (NVIC)

The Nested Vectored Interrupt Controller (NVIC) is part of the Cortex-M0+. The tight

coupling to the CPU allows for low interrupt latency and efficient processing of late arriving

interrupts.

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8.8.1 Features

• Controls system exceptions and peripheral interrupts.

• In the LPC11U6x, the NVIC supports vectored interrupts for each of the peripherals

and the eight pin interrupts. The following peripheral interrupts are ORed to contribute

to one interrupt in the NVIC:

– USART1, USART4

– USART2, USART3

– SCTimer0/PWM, SCTimer1/PWM

– BOD, WWDT

– ADC end-of-sequence A interrupt, threshold crossing interrupt

– ADC end-of-sequence B interrupt, overrun interrupt

– Flash, EEPROM

• Four programmable interrupt priority levels with hardware priority level masking.

• Software interrupt generation.

8.8.2 Interrupt sources

Each peripheral device has at least one interrupt line connected to the NVIC but can have

several interrupt flags. Individual interrupt flags can also represent more than one interrupt

source.

8.9 IOCON block

The IOCON block allows selected pins of the microcontroller to have more than one

function. Configuration registers control the multiplexers to allow connection between the

pin and the on-chip peripherals.

Connect peripherals to the appropriate pins before activating the peripheral and before

enabling any related interrupt.

Enabling an analog function disables the digital pad. However, the internal pull-up and

pull-down resistors as well as the pin hysteresis must be disabled to obtain an accurate

reading of the analog input.

8.9.1 Features

• Programmable pin function.

• Programmable pull-up, pull-down, or repeater mode.

• All pins (except PIO0_4 and PIO0_5) are pulled up to 3.3 V (V_DD= 3.3 V) if their

pull-up resistor is enabled.

• Programmable pseudo open-drain mode.

• Programmable (on/off) 10 ns glitch filter on pins PIO0_22, PIO0_23, PIO0_11 to

PIO0_16, PIO1_3, PIO1_9, PIO1_22, and PIO1_29. The glitch filter is turned on by

default.

• Programmable hysteresis.

• Programmable input inverter.

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• Digital filter with programmable filter constant on all pins. The minimum filter constant

is 1/50 MHz = 20 ns.

8.9.2 Standard I/O pad configuration

Figure 9 shows the possible pin modes for standard I/O pins with analog input function:

• Digital output driver with configurable open-drain output

• Digital input: Weak pull-up resistor (PMOS device) enabled/disabled

• Digital input: Weak pull-down resistor (NMOS device) enabled/disabled

• Digital input: Repeater mode enabled/disabled

• Digital input: Input digital filter selectable on all pins. In addition, a 10 ns digital glitch

filter is selectable on pins with analog function.

• Analog input

V

DD

open-drain enable

output enable

strong

pull-up

ESD

data output

pin configured

as digital output

driver

strong

pull-down

ESD

V

SS

V

DD

weak

pull-up

pull-up enable

weak

pull-down

repeater mode

enable

pull-down enable

data input

PROGRAMMABLE

DIGITAL FILTER

10 ns GLITCH

FILTER

pin configured

as digital input

select data

inverter

select glitch

filter

select analog input

analog input

pin configured

as analog input

aaa-010776

Fig 9. Standard I/O pin configuration

8.10 Fast General-Purpose parallel I/O (GPIO)

Device pins that are not connected to a specific peripheral function are controlled by the

GPIO registers. Pins may be dynamically configured as inputs or outputs. Multiple outputs

can be set or cleared in one write operation.

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LPC11U6x use accelerated GPIO functions:

• GPIO registers are on the ARM Cortex M0+ IO bus for fastest possible single-cycle

I/O timing, allowing GPIO toggling with rates of up to 25 MHz.

• An entire port value can be written in one instruction.

• Mask, set, and clear operations are supported for the entire port.

8.10.1 Features

• Bit level port registers allow a single instruction to set and clear any number of bits in

one write operation.

• Direction control of individual bits.

8.11 Pin interrupt/pattern match engine

The pin interrupt block configures up to eight pins from all digital pins for providing eight

external interrupts connected to the NVIC.

The pattern match engine can be used, in conjunction with software, to create complex

state machines based on pin inputs.

Any digital pin except pins PIO2_8 and PIO2_23 can be configured through the SYSCON

block as input to the pin interrupt or pattern match engine. The registers that control the

pin interrupt or pattern match engine are on the IO+ bus for fast single-cycle access.

8.11.1 Features

• Pin interrupts

– Up to eight pins can be selected from all digital pins except pins PIO2_8 and

PIO2_23 as edge- or level-sensitive interrupt requests. Each request creates a

separate interrupt in the NVIC.

– Edge-sensitive interrupt pins can interrupt on rising or falling edges or both.

– Level-sensitive interrupt pins can be HIGH- or LOW-active.

– Pin interrupts can wake up the part from sleep mode, deep-sleep mode, and

power-down mode.

• Pin interrupt pattern match engine

– Up to 8 pins can be selected from all digital pins except pins PIO2_8 and PIO2_23

to contribute to a boolean expression. The boolean expression consists of

specified levels and/or transitions on various combinations of these pins.

– Each minterm (product term) comprising the specified boolean expression can

generate its own, dedicated interrupt request.

– Any occurrence of a pattern match can be programmed to generate an RXEV

notification to the ARM CPU as well.

– The pattern match engine does not facilitate wake-up.

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8.12 GPIO group interrupts

The GPIO pins can be used in several ways to set pins as inputs or outputs and use the

inputs as combinations of level and edge sensitive interrupts. For each port/pin connected

to one of the two the GPIO Grouped Interrupt blocks (GINT0 and GINT1), the GPIO

grouped interrupt registers determine which pins are enabled to generate interrupts and w

the active polarities of each of those inputs.

The GPIO grouped interrupt registers also select whether the interrupt output is level or

edge triggered and whether it is based on the OR or the AND of all of the enabled inputs.

When the designated pattern is detected on the selected input pins, the GPIO grouped

interrupt block generates an interrupt. If the part is in a power-savings mode, it first

asynchronously wakes up the part prior to asserting the interrupt request. The interrupt

request line can be cleared by writing a one to the interrupt status bit in the control

register.

8.12.1 Features

• Two group interrupts are supported to reflect two distinct interrupt patterns.

• The inputs from any number of digital pins can be enabled to contribute to a combined

group interrupt.

• The polarity of each input enabled for the group interrupt can be configured HIGH or

LOW.

• Enabled interrupts can be logically combined through an OR or AND operation.

• The grouped interrupts can wake up the part from sleep, deep-sleep or power-down

modes.

8.13 DMA controller

The DMA controller can access all memories and the USART and SSP peripherals using

DMA requests. DMA transfers can also be triggered by internal events like the ADC

interrupts, timer match outputs, the pin interrupts (PINT0 and PINT1) and the SCTimer

DMA requests.

8.13.1 Features

• 16 channels with 14 channels connected to peripheral request inputs.

• DMA operations can be triggered by on-chip events or two pin interrupts. Each DMA

channel can select one trigger input from 12 sources.

• Priority is user selectable for each channel.

• Continuous priority arbitration.

• Address cache with two entries.

• Efficient use of data bus.

• Supports single transfers up to 1,024 words.

• Address increment options allow packing and/or unpacking data.

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8.14 USB interface

The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a

host and one or more (up to 127) peripherals. The host controller allocates the USB

bandwidth to attached devices through a token-based protocol. The bus supports

hot-plugging and dynamic configuration of the devices. All transactions are initiated by the

host controller.

The USB interface consists of a full-speed device controller with on-chip PHY (PHYsical

layer) for device functions.

Remark: Configure the part in default power mode with the power profiles before using

the USB (see Section 8.25.7.1 “Power profiles”). Do not use the USB when the part runs

in performance, efficiency, or low-power mode.

8.14.1 Full-speed USB device controller

The device controller enables 12 Mbit/s data exchange with a USB Host controller. It

consists of a register interface, serial interface engine, and endpoint buffer memory. The

serial interface engine decodes the USB data stream and writes data to the appropriate

endpoint buffer. The status of a completed USB transfer or error condition is indicated via

status registers. An interrupt is also generated if enabled.

8.14.1.1 Features

• Dedicated USB PLL available.

• Fully compliant with USB 2.0 specification (full speed).

• Supports 10 physical (5 logical) endpoints including one control endpoint.

• Single and double buffering supported.

• Each non-control endpoint supports bulk, interrupt, or isochronous endpoint types.

• Supports wake-up from Deep-sleep mode and Power-down mode on USB activity

and remote wake-up.

• Supports SoftConnect functionality through internal pull-up resistor.

• Internal 33 ꢀ series termination resistors on USB_DP and USB_DM lines eliminate

the need for external series resistors.

• Supports Link Power Management (LPM).

• Supports XTAL-less low-speed mode using the 1% accurate IRC as the clock source

for the USB PLL. For board connection changes in low-speed mode, see Section

14.3.1 “USB Low-speed operation”.

8.15 USART0

Remark: The LPC11U6x contains two distinctive types of UART interfaces: USART0 is

software-compatible with the USART interface on the LPC11U1x/LPC11U2x/LPC11U3x

parts. USART1 to USART4 use a different register interface.

The USART0 includes full modem control, support for synchronous mode, and a smart

card interface. The RS-485/9-bit mode allows both software address detection and

automatic address detection using 9-bit mode.

The USART0 uses a fractional baud rate generator. Standard baud rates such as

115200 Bd can be achieved with any crystal frequency above 2 MHz.

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8.15.1 Features

• Maximum USART0 data bit rate of 3.125 Mbit/s in asynchronous mode and 10 Mbit/s

in synchronous slave and master mode.

• 16 byte receive and transmit FIFOs.

• Register locations conform to 16C550 industry standard.

• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.

• Built-in fractional baud rate generator covering wide range of baud rates without a

need for external crystals of particular values.

• Fractional divider for baud rate control, auto baud capabilities and FIFO control

mechanism that enables software flow control implementation.

• Support for RS-485/9-bit mode.

• Support for modem control.

• Support for synchronous mode.

• Includes smart card interface.

• DMA support.

8.16 USART1/2/3/4

Remark: The LPC11U6x contains two distinctive types of UART interfaces: USART0 is

software-compatible with the USART interface on the LPC11U1x/LPC11U2x/LPC11U3x

parts. USART1 to USART4 use a different register interface to achieve the same UART

functionality except for modem and smart card control.

Remark: USART3 and USART4 are available only on part LPC11U68JBD100.

Interrupts generated by the USART1/2/3/4 peripherals can wake up the part from

Deep-sleep and power-down modes if the USART is in synchronous mode, the 32 kHz

mode is enabled, or the CTS interrupt is enabled. This wake-up mechanism is not

available with the USART0 peripheral.

8.16.1 Features

• Maximum bit rates of 3.125 Mbit/s in asynchronous mode and 10 Mbit/s in

synchronous mode.

• 7, 8, or 9 data bits and 1 or 2 stop bits

• Synchronous mode with master or slave operation. Includes data phase selection and

continuous clock option.

• Multiprocessor/multidrop (9-bit) mode with software-address compare feature.

(RS-485 possible with software address detection and transceiver direction control.)

• RS-485 transceiver output enable.

• Autobaud mode for automatic baud rate detection

• Parity generation and checking: odd, even, or none.

• One transmit and one receive data buffer.

• RTS/CTS for hardware signaling for automatic flow control. Software flow control can

be performed using Delta CTS detect, Transmit Disable control, and any GPIO as an

RTS output.

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• Received data and status can optionally be read from a single register

• Break generation and detection.

• Receive data is 2 of 3 sample "voting". Status flag set when one sample differs.

• Built-in Baud Rate Generator with auto-baud function.

• A fractional rate divider is shared among all USARTs.

• Interrupts available for Receiver Ready, Transmitter Ready, Receiver Idle, change in

receiver break detect, Framing error, Parity error, Overrun, Underrun, Delta CTS

detect, and receiver sample noise detected.

• Loopback mode for testing of data and flow control.

• In synchronous slave mode, wakes up the part from deep-sleep and power-down

modes.

• Special operating mode allows operation at up to 9600 baud using the 32 kHz RTC

oscillator as the UART clock. This mode can be used while the device is in

Deep-sleep or Power-down mode and can wake up the device when a character is

received.

• USART transmit and receive functions work with the system DMA controller.

8.17 SSP serial I/O controller (SSP0/1)

The SSP controllers operate on a SSP, 4-wire SSI, or Microwire bus. The controller can

interact with multiple masters and slaves on the bus. Only a single master and a single

slave can communicate on the bus during a given data transfer. The SSP supports full

duplex transfers, with frames of 4 bit to 16 bit of data flowing from the master to the slave

and from the slave to the master. In practice, often only one direction carries meaningful

data.

8.17.1 Features

• Maximum SSP speed of 25 Mbit/s (master) or 4.17 Mbit/s (slave) (in SSP mode)

• Compatible with Motorola SPI (Serial Peripheral Interface), 4-wire Texas Instruments

SSI (Serial Synchronous Interface), and National Semiconductor Microwire buses

• Synchronous serial communication

• Master or slave operation

• 8-frame FIFOs for both transmit and receive

• 4-bit to 16-bit frame

• DMA support

8.18 I²C-bus serial I/O controller

The LPC11U6x contain two I²C-bus controllers.

The I²C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock line

(SCL) and a Serial Data line (SDA). Each device is recognized by a unique address and

can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the

capability to both receive and send information (such as memory). Transmitters and/or

receivers can operate in either master or slave mode, depending on whether the chip has

to initiate a data transfer or is only addressed. The I²C is a multi-master bus and can be

controlled by more than one bus master connected to it.

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8.18.1 Features

• One I²C-interface (I2C0) is an I²C-bus compliant interface with open-drain pins. The

I²C-bus interface supports Fast-mode Plus with bit rates up to 1 Mbit/s.

• One I²C-interface (I2C1) uses standard digital pins. The I²C-bus interface supports bit

rates up to 400 kbit/s.

• Easy to configure as master, slave, or master/slave.

• Programmable clocks allow versatile rate control.

• Bidirectional data transfer between masters and slaves.

• Multi-master bus (no central master).

• Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus.

• Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus.

• Serial clock synchronization can be used as a handshake mechanism to suspend and

resume serial transfer.

• The I²C-bus can be used for test and diagnostic purposes.

• The I²C-bus controller supports multiple address recognition and a bus monitor mode.

8.19 Timer/PWM subsystem

Four standard timers and two state configurable timers can be combined to create

multiple PWM outputs using the match outputs and the match registers for each timer.

Each timer can create multiple PWM outputs with its own time base.

Table 4.

PWM resources

Peripheral

PWM

Pin functions available for PWM

LQFP100 LQFP64

Match

registers

used

outputs

LQFP48

3

CT16B0

CT16B0_MAT0, CT16B0_MAT0, CT16B0_MAT0,

CT16B0_MAT1, CT16B0_MAT1, CT16B0_MAT1,

4

CT16B0_MAT2

2

3

2

3

2

3

CT16B1

CT32B0

CT16B1_MAT0, CT16B1_MAT0, CT16B1_MAT0,

3

4

CT16B1_MAT1

three of

CT16B1_MAT1

three of

CT16B1_MAT1

three of

CT32B0_MAT0, CT32B0_MAT0, CT32B0_MAT0,

CT32B0_MAT1, CT32B0_MAT1, CT32B0_MAT1,

CT32B0_MAT2, CT32B0_MAT2, CT32B0_MAT2,

CT32B0_MAT3

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Table 4.

PWM resources …continued

PWM

outputs

Peripheral

Pin functions available for PWM

Match

registers

used

LQFP100

LQFP64

LQFP48

3

CT32B1

three of

4

CT32B1_MAT0, CT32B1_MAT0, CT32B1_MAT0,

CT32B1_MAT1, CT32B1_MAT1, CT32B1_MAT1,

CT32B1_MAT2, CT32B1_MAT2, CT32B1_MAT2,

CT32B1_MAT3

4

2

3

-

SCTIMER0/ SCT0_OUT0,

SCT0_OUT0,

SCT0_OUT1,

SCT0_OUT2,

SCT0_OUT3

SCT0_OUT1,

SCT0_OUT2,

SCT0_OUT3

up to 5

PWM

SCT0_OUT1,

SCT0_OUT2,

SCT0_OUT3

SCTIMER1/ SCT1_OUT0,

SCT1_OUT2,

SCT1_OUT3

-

PWM

SCT1_OUT1,

SCT1_OUT2,

SCT1_OUT3

The standard timers and the SCTimers combine to up to eight independent timers. Each

SCTimer can be configured either as one 32-bit timer or two independently counting 16-bit

timers which use the same input clock. The following combinations are possible:

Table 5.

Timer configurations

Resources

32-bit

16-bit

Resources

timers

4

CT32B0, CT32B1, SCTimer0/PWM

as 32-bit timer, SCTimer1/PWM as

32-bit timer

2

CT16B0, CT16B1

2

CT32B0, CT32B1

6

CT16B0, CT16B1, SCTimer0/PWM

as two 16-bit timers,

SCTimer1/PWM as two 16-bit

timers

3

CT32B0, CT32B1, SCTimer0/PWM

as 32-bit timer (or SCTimer1/PWM

as 32-bit timer)

4

CT16B0, CT16B1, SCTimer1/PWM

as two 16-bit timers (or

SCTimer0/PWM as two 16-bit

timers)

8.19.1 State Configurable Timers (SCTimer0/PWM and SCTimer1/PWM)

The state configurable timer can create timed output signals such as PWM outputs

triggered by programmable events. Combinations of events can be used to define timer

states. The SCTimer/PWM can control the timer operations, capture inputs, change

states, and toggle outputs triggered only by events entirely without CPU intervention.

If multiple states are not implemented, the SCTimer/PWM simply operates as one 32-bit

or two 16-bit timers with match, capture, and PWM functions.

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8.19.1.1 Features

• Each SCTimer/PWM supports:

– 5 match/capture registers.

– 6 events.

– 8 states.

– 4 inputs and 4 outputs.

• Counter/timer features:

– Each SCTimer is configurable as two 16-bit counters or one 32-bit counter.

– Counters can be clocked by the system clock or selected input.

– Configurable as up counters or up-down counters.

– Configurable number of match and capture registers. Up to five match and capture

registers total.

– Upon match create the following events: interrupt; stop, limit, halt the timer or

change counting direction; toggle outputs.

– Counter value can be loaded into capture register triggered by a match or

input/output toggle.

• PWM features:

– Counters can be used with match registers to toggle outputs and create

time-proportioned PWM signals.

– Up to four single-edge or dual-edge PWM outputs with independent duty cycle and

common PWM cycle length.

• Event creation features:

– The following conditions define an event: a counter match condition, an input (or

output) condition such as a rising or falling edge or level, a combination of match

and/or input/output condition.

– Selected events can limit, halt, start, or stop a counter or change its direction.

– Events trigger state changes, output toggles, interrupts, and DMA transactions.

– Match register 0 can be used as an automatic limit.

– In bidirectional mode, events can be enabled based on the count direction.

– Match events can be held until another qualifying event occurs.

• State control features:

– A state is defined by events that can happen in the state while the counter is

running.

– A state changes into another state as a result of an event.

– Each event can be assigned to one or more states.

– State variable allows sequencing across multiple counter cycles.

• SCTimer match outputs (ORed with the general-purpose timer match outputs) serve

as ADC hardware trigger inputs.

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8.19.2 General purpose external event counter/timers (CT32B0/1 and CT16B0/1)

The LPC11U6x includes two 32-bit counter/timers and two 16-bit counter/timers. The

counter/timer is designed to count cycles of the system derived clock. It can optionally

generate interrupts or perform other actions at specified timer values, based on four

match registers. Each counter/timer also includes one capture input to trap the timer value

when an input signal transitions, optionally generating an interrupt.

8.19.2.1 Features

• A 32-bit/16-bit timer/counter with a programmable 32-bit/16-bit prescaler.

• Counter or timer operation.

• One capture channel per timer, that can take a snapshot of the timer value when an

input signal transitions. A capture event may also generate an interrupt.

• Four match registers per timer that allow:

– Continuous operation with optional interrupt generation on match.

– Stop timer on match with optional interrupt generation.

– Reset timer on match with optional interrupt generation.

• Up to four external outputs corresponding to match registers, with the following

capabilities:

– Set LOW on match.

– Set HIGH on match.

– Toggle on match.

– Do nothing on match.

• The timer and prescaler may be configured to be cleared on a designated capture

event. This feature permits easy pulse-width measurement by clearing the timer on

the leading edge of an input pulse and capturing the timer value on the trailing edge.

• PWM output function.

• Match outputs and capture inputs serve as hardware triggers for ADC conversions.

8.20 System tick timer (SysTick)

The ARM Cortex-M0+ includes a system tick timer (SYSTICK) that is intended to generate

a dedicated SYSTICK exception at a fixed time interval (typically 10 ms).

8.21 Windowed WatchDog Timer (WWDT)

The purpose of the WWDT is to prevent an unresponsive system state. If software fails to

update the watchdog within a programmable time window, the watchdog resets the

microcontroller

8.21.1 Features

• Internally resets chip if not periodically reloaded during the programmable time-out

period.

• Optional windowed operation requires reload to occur between a minimum and

maximum time period, both programmable.

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• Optional warning interrupt can be generated at a programmable time before watchdog

time-out.

• Software enables the WWDT, but a hardware reset or a watchdog reset/interrupt is

required to disable the WWDT.

• Incorrect feed sequence causes reset or interrupt, if enabled.

• Flag to indicate watchdog reset.

• Programmable 24-bit timer with internal prescaler.

• Selectable time period from (T_cy(WDCLK) 256  4) to (T_cy(WDCLK) 2²⁴ 4) in

multiples of T_cy(WDCLK) 4.

• The WatchDog Clock (WDCLK) source can be selected from the IRC or the dedicated

watchdog oscillator (WDOsc). The clock source selection provides a wide range of

potential timing choices of watchdog operation under different power conditions.

8.22 Real-Time Clock (RTC)

The RTC resides in a separate always-on voltage domain with battery back-up. The RTC

uses an independent oscillator, also located in the always-on voltage domain.

8.22.1 Features

• 32-bit, 1 Hz RTC counter and associated match register for alarm generation.

• Separate 16-bit high-resolution/wake-up timer clocked at 1 kHz for 1 ms resolution

with a more that one minute maximum time-out period.

• RTC alarm and high-resolution/wake-up timer time-out each generate independent

interrupt requests. Either time-out can wake up the part from any of the low-power

modes, including Deep power-down.

8.23 Analog-to-Digital Converter (ADC)

The ADC supports a resolution of 12 bit and fast conversion rates of up to 2 MSamples/s.

Sequences of analog-to-digital conversions can be triggered by multiple sources. Possible

trigger sources are the counter/timer match outputs and capture inputs and the ARM

TXEV.

The ADC includes a hardware threshold compare function with zero-crossing detection.

8.23.1 Features

• 12-bit successive approximation analog to digital converter.

• 12-bit conversion rate of up to 2 MSamples/s.

• Temperature sensor voltage output selectable as internal voltage source for

channel 0.

• Two configurable conversion sequences with independent triggers.

• Optional automatic high/low threshold comparison and zero-crossing detection.

• Power-down mode and low-power operating mode.

• Measurement range VREFN to VREFP (typically 3 V; not to exceed V_DDAvoltage

level).

• Burst conversion mode for single or multiple inputs.

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8.24 Temperature sensor

The temperature sensor transducer uses an intrinsic pn-junction diode reference and

outputs a CTAT voltage (Complement To Absolute Temperature). The output voltage

varies inversely with device temperature with an absolute accuracy of better than ±5 C

over the full temperature range (40 C to +105 C) for typical samples. The temperature

sensor is approximately linear with a slight curvature. The output voltage is measured

over different ranges of temperatures and fit with linear-least-square lines.

After power-up and after switching the input channels of the ADC, the temperature sensor

output must be allowed to settle to its stable value before it can be used as an accurate

ADC input.

For an accurate measurement of the temperature sensor by the ADC, the ADC must be

configured in single-channel burst mode. The last value of a nine-conversion (or more)

burst provides an accurate result.

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8.25 Clocking and power control

8.25.1 Clock generation

CPU,

system control,

PMU

system clock

n

SYSTEM CLOCK

DIVIDER

memories,

peripheral clocks

SYSAHBCLKCTRL

(AHB clock enable)

main

clock

IRC

SSP0 PERIPHERAL

CLOCK DIVIDER

SSP0

watchdog oscillator

USART0 PERIPHERAL

CLOCK DIVIDER

USART0

MAINCLKSEL

RTC

(main clock select)

SSP1 PERIPHERAL

CLOCK DIVIDER

oscillator,

32 kHz

output

SSP1

IRC

SYSTEM PLL

system

oscillator

USART1

FRACTIONAL RATE

GENERATOR

CLOCK DIVIDER

FRGCLKDIV

USART2

USART3

USART4

RTCOSCCTRL

(RTC osc enable)

SYSPLLCLKSEL

(system PLL clock select)

7

IOCON

glitch filter

CLOCK DIVIDER

IOCONCLKDIV

IRC

USB PLL

system

oscillator

USB 48 MHz CLOCK

DIVIDER

USB

USBPLLCLKSEL

(USB clock select)

USBCLKSEL

(USB clock select)

IRC oscillator

system oscillator

watchdog oscillator

CLKOUT PIN CLOCK

DIVIDER

CLKOUT pin

CLKOUTSEL

(CLKOUT clock select)

IRC oscillator

WDT

watchdog oscillator

WDCLKSEL

(WDT clock select)

aaa-010817

Fig 10. Clock generation

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8.25.2 Power domains

The LPC11U6x provide two independent power domains that allow the bulk of the device

to have power removed while maintaining operation of the RTC and the backup registers.

The VBAT pin supplies power only to the RTC domain. The RTC requires a minimum of

power to operate, which can be supplied by an external battery. The device core power

(V_DD) is used to operate the RTC whenever V_DDis present. Therefore, there is no power

drain from the RTC battery when V_DDis available and V_DD VBAT + 0.3 V.

LPC11U6x

to I/O pads

to core

VSS

VDD

REGULATOR

to memories,

peripherals,

oscillators,

PLLs

WAKEUP

MAIN POWER DOMAIN

ULTRA LOW-POWER

REGULATOR

VBAT

WAKE-UP

CONTROL

BACKUP REGISTERS

REAL-TIME CLOCK

RTCXIN

32 kHz

OSCILLATOR

RTCXOUT

ALWAYS-ON/RTC POWER DOMAIN

ADC

TEMP SENSE

VDDA

VDD

ADC POWER DOMAIN

VSSA

aaa-010818

Fig 11. Power distribution

8.25.3 Integrated oscillators

The LPC11U6x include the following independent oscillators: the system oscillator, the

Internal RC oscillator (IRC), the watchdog oscillator, and the 32 kHz RTC oscillator. Each

oscillator can be used for more than one purpose as required in a particular application.

Following reset, the LPC11U6x operates from the internal RC oscillator until software

switches to a different clock source. The IRC allows the system to operate without any

external crystal and the bootloader code to operate at a known frequency.

See Figure 10 for an overview of the LPC11U6x clock generation.

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8.25.3.1 Internal RC oscillator

The IRC can be used as the clock source for the WDT, the USB PLL in low-speed USB

applications, or as the clock that drives the system PLL and then the CPU. The nominal

IRC frequency is 12 MHz.

Upon power-up, any chip reset, or wake-up from Deep power-down mode, the LPC11U6x

use the IRC as the clock source. Software can later switch to one of the other available

clock sources.

8.25.3.2 System oscillator

The system oscillator can be used as the clock source for the CPU, with or without using

the PLL. Use the system oscillator to provide the clock source to USB.

The system oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be

boosted to a higher frequency, up to the maximum CPU operating frequency, by the

system PLL.

The system oscillator has a wake-up time of approximately 500 μs.

8.25.3.3 WatchDog oscillator

The watchdog oscillator can be used as a clock source that directly drives the CPU, the

watchdog timer, or the CLKOUT pin. The watchdog oscillator nominal frequency is

programmable between 9.4 kHz and 2.3 MHz. The frequency spread over processing and

temperature is 40 % (see also Table 14).

8.25.3.4 RTC oscillator

The low-power RTC oscillator provides a 1 Hz clock and a 1 kHz clock to the RTC and a

32 kHz clock output that can be used to obtain the main clock (see Figure 10).

8.25.4 System PLL and USB PLL

The LPC11U6x contain a system PLL and a dedicated PLL for generating the 48 MHz

USB clock. The system and USB PLLs are identical.

The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input

frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO).

The multiplier can be an integer value from 1 to 32. The CCO operates in the range of

156 MHz to 320 MHz. To support this frequency range, an additional divider keeps the

CCO within its frequency range while the PLL is providing the desired output frequency.

The output divider can be set to divide by 2, 4, 8, or 16 to produce the output clock. The

PLL output frequency must be lower than 100 MHz. Since the minimum output divider

value is 2, it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off

and bypassed following a chip reset. Software can enable the PLL later. The program

must configure and activate the PLL, wait for the PLL to lock, and then connect to the PLL

as a clock source. The PLL settling time is 100 s.

8.25.5 Clock output

The LPC11U6x feature a clock output function that routes the IRC oscillator, the system

oscillator, the watchdog oscillator, or the main clock to an output pin.

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8.25.6 Wake-up process

The LPC11U6x begin operation by using the 12 MHz IRC oscillator as the clock source at

power-up and when awakened from Deep power-down mode. This mechanism allows

chip operation to resume quickly. If the application uses the main oscillator or the PLL,

software must enable these components and wait for them to stabilize. Only then can the

system use the PLL and main oscillator as a clock source.

8.25.7 Power control

The LPC11U6x support various power control features. There are four special modes of

processor power reduction: Sleep mode, Deep-sleep mode, Power-down mode, and

Deep power-down mode. The CPU clock rate can also be controlled as needed by

changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider

value. This power control mechanism allows a trade-off of power versus processing speed

based on application requirements. In addition, a register is provided for shutting down the

clocks to individual on-chip peripherals. This register allows fine-tuning of power

consumption by eliminating all dynamic power use in any peripherals that are not required

for the application. Selected peripherals have their own clock divider which provides even

better power control.

8.25.7.1 Power profiles

The power consumption in Active and Sleep modes can be optimized for the application

through simple calls to the power profile. The power configuration routine configures the

LPC11U6x for one of the following power modes:

• Default mode corresponding to power configuration after reset.

• CPU performance mode corresponding to optimized processing capability.

• Efficiency mode corresponding to optimized balance of current consumption and CPU

performance.

• Low-current mode corresponding to lowest power consumption.

In addition, the power profile includes routines to select the optimal PLL settings for a

given system clock and PLL input clock.

Remark: When using the USB, configure the LPC11U6x in Default mode.

8.25.7.2 Sleep mode

When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep

mode does not need any special sequence but re-enabling the clock to the ARM core.

In Sleep mode, execution of instructions is suspended until either a reset or interrupt

occurs. Peripheral functions continue operation during Sleep mode and can generate

interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic

power used by the processor itself, by memory systems and related controllers, and by

internal buses.

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8.25.7.3 Deep-sleep mode

In Deep-sleep mode, the LPC11U6x core is in Sleep mode and all peripheral clocks and

all clock sources are off except for the IRC. The IRC output is disabled unless the IRC is

selected as input to the watchdog timer. In addition, all analog blocks are shut down and

the flash is in standby mode. In Deep-sleep mode, the application can keep the watchdog

oscillator and the BOD circuit running for self-timed wake-up and BOD protection.

The LPC11U6x can wake up from Deep-sleep mode via reset, selected GPIO pins, a

watchdog timer interrupt, an interrupt generating USB port activity, an RTC interrupt, or

any interrupts that the USART1 to USART4 interfaces can create in Deep-sleep mode.

The USART wake-up requires the 32 kHz mode, the synchronous mode, or the CTS

interrupt to be set up.

Deep-sleep mode saves power and allows for short wake-up times.

8.25.7.4 Power-down mode

In Power-down mode, the LPC11U6x is in Sleep mode and all peripheral clocks and all

clock sources are off except for watchdog oscillator if selected. In addition, all analog

blocks and the flash are shut down. In Power-down mode, the application can keep the

BOD circuit running for BOD protection.

The LPC11U6x can wake up from Power-down mode via reset, selected GPIO pins, a

watchdog timer interrupt, an interrupt generating USB port activity, an RTC interrupt, or

any interrupts that the USART1 to USART4 interfaces can create in Power-down mode.

The USART wake-up requires the 32 kHz mode, the synchronous mode, or the CTS

interrupt to be set up.

Power-down mode reduces power consumption compared to Deep-sleep mode at the

expense of longer wake-up times.

8.25.7.5 Deep power-down mode

In Deep power-down mode, power is shut off to the entire chip except for the WAKEUP

pin and the always-on RTC power domain. The LPC11U6x can wake up from Deep

power-down mode via the WAKEUP pin or a wake-up signal generated by the RTC

interrupt.

The LPC11U6x can be blocked from entering Deep power-down mode by setting a lock bit

in the PMU block. Blocking the Deep power-down mode enables the application to keep

the watchdog timer or the BOD running at all times.

If the WAKEUP pin is used in the application, an external pull-up resistor is required on

the WAKEUP pin to hold it HIGH while the part is in deep power-down mode. To wake up

from deep power-down mode, pull the WAKEUP pin LOW. In addition, pull the RESET pin

HIGH to prevent it from floating while in Deep power-down mode.

8.26 System control

8.26.1 Reset

Reset has four sources on the LPC11U6x: the RESET pin, the WatchDog reset, power-on

reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt

trigger input pin. Assertion of chip reset by any source, once the operating voltage attains

a usable level, starts the IRC and initializes the flash controller.

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When the internal Reset is removed, the processor begins executing at address 0, which

is initially the Reset vector mapped from the boot block. At that point, all of the processor

and peripheral registers have been initialized to predetermined values. The internal reset

status is reflected on the RSTOUT pin.

In Deep power-down mode, an external pull-up resistor is required on the RESET pin.

The RESET pin is operational in active, sleep, deep-sleep, and power-down modes if the

RESET function is selected in the IOCON register for pin PIO0_0 (this is the default). A

LOW-going pulse as short as 50 ns executes the reset and also wakes up the part if in

sleep, deep-sleep or power-down mode. The RESET pin is not functional in Deep

power-down mode.

V

DD

V

DD

V

DD

R

pu

ESD

20 ns RC

GLITCH FILTER

reset

ESD

V

SS

aaa-004613

Fig 12. RESET pin configuration

8.26.2 Brownout detection

The LPC11U6x includes two levels for monitoring the voltage on the V_DDpin. If this

voltage falls below one of the selected levels, the BOD asserts an interrupt signal to the

NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC

to cause a CPU interrupt. Alternatively, software can monitor the signal by reading a

dedicated status register. Two threshold levels can be selected to cause a forced reset of

the chip.

8.26.3 Code security (Code Read Protection - CRP)

CRP provides different levels of security in the system so that access to the on-chip flash

and use of the Serial Wire Debugger (SWD) and In-System Programming (ISP) can be

restricted. Programming a specific pattern into a dedicated flash location invokes CRP.

IAP commands are not affected by the CRP.

In addition, ISP entry via the PIO0_1 pin can be disabled without enabling CRP. For

details, see the LPC11Uxx user manual.

There are three levels of Code Read Protection:

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1. CRP1 disables access to the chip via the SWD and allows partial flash update

(excluding flash sector 0) using a limited set of the ISP commands. This mode is

useful when CRP is required and flash field updates are needed but all sectors cannot

be erased.

2. CRP2 disables access to the chip via the SWD and only allows full flash erase and

update using a reduced set of the ISP commands.

3. Running an application with level CRP3 selected, fully disables any access to the chip

via the SWD pins and the ISP. This mode effectively disables ISP override using

PIO0_1 pin as well. If necessary, the application must provide a flash update

mechanism using IAP calls or using a call to the reinvoke ISP command to enable

flash update via the USART.

CAUTION

If level three Code Read Protection (CRP3) is selected, no future factory testing can be

performed on the device.

In addition to the three CRP levels, sampling of pin PIO0_1 for valid user code can be

disabled. For details, see the LPC11U6x user manual.

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8.27 Emulation and debugging

Debug functions are integrated into the ARM Cortex-M0+. Serial wire debug functions are

supported in addition to a standard JTAG boundary scan. The ARM Cortex-M0+ is

configured to support up to four breakpoints and two watch points.

The RESET pin selects between the JTAG boundary scan (RESET = LOW) and the ARM

SWD debug (RESET = HIGH). The ARM SWD debug port is disabled while the

LPC11U6x is in reset.

To perform boundary scan testing, follow these steps:

1. Erase any user code residing in flash.

2. Power up the part with the RESET pin pulled HIGH externally.

3. Wait for at least 250 s.

4. Pull the RESET pin LOW externally.

5. Perform boundary scan operations.

6. Once the boundary scan operations are completed, assert the TRST pin to enable the

SWD debug mode, and release the RESET pin (pull HIGH).

Remark: The JTAG interface cannot be used for debug purposes.

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9. Limiting values

Table 6.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).^[1]

Symbol

V_DD

Parameter

Conditions

Min

Max

4.6

Unit

V

[2]

[3][4]

[5]

supply voltage

0.5

V_DDA

V_ref

analog supply voltage

reference voltage

battery supply voltage

input voltage

4.6

V

on pin VREFP

4.6

V

V_BAT

V_I

4.6

V

5 V tolerant I/O

pins; only valid

when the V_DD(IO)

supply voltage is

present

+5.5

V

on open-drain

I2C-bus pins

PIO0_4 and

PIO0_5

0.5

+5.5

V

USB_DM,

USB_DP pins

0.5

V

_DD+ 0.5

V

[6]

[7]

V_IA

analog input voltage

crystal input voltage

4.6

[2]

V_i(xtal)

pins configured for

XTALIN and

XTALOUT

0.5

+2.5

V

V_i(rtcx)

I_DD

32 kHz oscillator input voltage

supply current

0.5

4.6

V

per supply pin

per ground pin

-

100

mA

I_SS

ground current

I_latch

I/O latch-up current

(0.5 V_DD(IO)) < V_I

< (1.5 V_DD(IO));

T_j< 125 C

[8]

T_stg

storage temperature

65

+150

150

1.5

C

W

T_j(max)

P_tot(pack)

maximum junction temperature

total power dissipation (per package)

-

based on package

heat transfer, not

device power

consumption

[9]

V_esd

electrostatic discharge voltage

human body

-

3

kV

model; all pins

[1] The following applies to the limiting values:

a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated

maximum.

b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V_SSunless

otherwise noted.

[2] Maximum/minimum voltage above the maximum operating voltage (see Table 8) and below ground that can be applied for a short time

(< 10 ms) to a device without leading to irrecoverable failure. Failure includes the loss of reliability and shorter lifetime of the device.

[3] Applies to all 5 V tolerant I/O pins except true open-drain pins PIO0_4 and PIO0_5.

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[4] Including the voltage on outputs in 3-state mode.

[5] V_DD(IO)present or not present. Compliant with the I²C-bus standard. 5.5 V can be applied to this pin when V_DD(IO)is powered down.

[6] An ADC input voltage above 3.6 V can be applied for a short time without leading to immediate, unrecoverable failure. Accumulated

exposure to elevated voltages at 4.6 V must be less than 10⁶s total over the lifetime of the device. Applying an elevated voltage to the

ADC inputs for a long time affects the reliability of the device and reduces its lifetime.

[7] It is recommended to connect an overvoltage protection diode between the analog input pin and the voltage supply pin.

[8] Dependent on package type.

[9] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.

10. Thermal characteristics

The average chip junction temperature, T_j(C), can be calculated using the following

equation:

T _j= T_amb+ P_D R_{th j – a}

(1)

• T_amb= ambient temperature (C),

• R_th(j-a)= the package junction-to-ambient thermal resistance (C/W)

• P_D= sum of internal and I/O power dissipation

The internal power dissipation is the product of I_DDand V_DD. The I/O power dissipation of

the I/O pins is often small and many times can be negligible. However it can be significant

in some applications.

Table 7.

Thermal resistance value (C/W): ±15 %

Symbol Parameter

LQFP48

Conditions

Typ

Unit

ja

thermal resistance

junction-to-ambient

JEDEC (4.5 in  4 in)

0 m/s

1 m/s

67

58

53

C/W

2.5 m/s

8-layer (4.5 in  3 in)

0 m/s

100

79

C/W

1 m/s

2.5 m/s

71

jc

jb

thermal resistance junction-to-case

thermal resistance junction-to-board

15

19

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Table 7.

Thermal resistance value (C/W): ±15 %

Symbol Parameter

LQFP64

Conditions

Typ

Unit

ja

thermal resistance

junction-to-ambient

JEDEC (4.5 in  4 in)

0 m/s

1 m/s

58

51

47

C/W

2.5 m/s

8-layer (4.5 in  3 in)

0 m/s

81

66

60

18

23

C/W

1 m/s

2.5 m/s

jc

thermal resistance junction-to-case

thermal resistance junction-to-board

jb

LQFP100

ja

thermal resistance

junction-to-ambient

JEDEC (4.5 in  4 in)

0 m/s

1 m/s

49

44

41

C/W

2.5 m/s

8-layer (4.5 in  3 in)

0 m/s

66

55

51

18

24

C/W

1 m/s

2.5 m/s

jc

jb

thermal resistance junction-to-case

thermal resistance junction-to-board

11. Static characteristics

Table 8.

Static characteristics

T_amb= −40 °C to +105 °C, unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ^[1]Max

Unit

[2]

V_DD

supply voltage (core

and external rail)

2.4

3.3

3.6

V

V_DDA

V_ref

analog supply voltage

reference voltage

2.4

3.3

-

3.6

V

on pin VREFP

V_DDA

3.6

V_BAT

battery supply voltage

3.3

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Table 8.

Static characteristics …continued

T_amb= −40 °C to +105 °C, unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ^[1]Max

Unit

I_DD

supply current

Active mode; code

while(1){}

executed from flash

[3][4][5]

[7][8]

system clock = 12 MHz; default

mode; V_DD= 3.3 V

-

2.3

1.5

7.8

6.4

-

mA

[3][4][5]

[7][8]

system clock = 12 MHz;

low-current mode; V_DD= 3.3 V

[3][4][7]

[8][10]

system clock = 50 MHz; default

mode; V_DD= 3.3 V

[3][4][7]

[8][10]

system clock = 50 MHz;

low-current mode; V_DD= 3.3 V

I_DD

supply current

Sleep mode;

[3][4][5]

[7][8]

system clock = 12 MHz; default

mode; V_DD= 3.3 V

-

1.2

0.8

3.3

2.8

275

-

mA

A

[3][4][5]

[7][8]

system clock = 12 MHz;

low-current mode; V_DD= 3.3 V

-

[3][4][10]

[7][8]

system clock = 50 MHz; default

mode; V_DD= 3.3 V

-

[3][4][10]

[7][8]

system clock = 50 MHz;

low-current mode; V_DD= 3.3 V

-

[3][4][11]

[3][12]

I_DD

supply current

Deep-sleep mode;

_DD= 3.3 V;

350

V

T_amb= 25 C

T_amb= 105 C

-

640

22

A

Power-down mode;

_DD= 3.3 V

5

V

T_amb= 25 C

T_amb= 105 C

-

130

A

Deep power-down mode; V_DD

=

3.3 V; VBAT = 0 or VBAT = 3.0 V

RTC oscillator running

T_amb= 25 C

-

1.2

-

5

14

-

A

T_amb= 105 C

[3][12]

RTC oscillator input grounded

550

0

nA

-

I_BAT

battery supply current

Deep power-down mode; V_DD

=

-

V

_DDA= 3.3 V; VBAT = 3.0 V;

RTC oscillator running

RTC off

-

0

-

I_BAT

V_DD= V_DDA= 0 V; VBAT = 3.0 V

RTC oscillator running

1.2

0.5

-

A

nA

Standard port pins configured as digital pins, RESET; see Figure 13

I_IL

LOW-level input current V_I= 0 V; on-chip pull-up resistor

disabled

10

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Table 8.

Static characteristics …continued

T_amb= −40 °C to +105 °C, unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ^[1]Max

Unit

I_IH

HIGH-level input

current

V_I= V_DD; on-chip pull-down

resistor disabled

-

0.5

-

10

5

nA

I_OZ

V_I

OFF-state output

current

V_O= 0 V; V_O= V_DD; on-chip

pull-up/down resistors disabled

-

nA

V

[14]

[15]

input voltage

V_DD 2.4 V; 5 V tolerant pins

0

V_DD= 0 V

0

-

3.6

V_DD

-

V

V_O

output voltage

output active

0

V_IH

HIGH-level input

voltage

0.7 V_DD

V_IL

LOW-level input voltage

hysteresis voltage

-

0.3 V_DD

V

V_hys

V_OH

0.05 V_DD

-

HIGH-level output

voltage

I_OH= 4 mA

V_DD 0.4 -

V_OL

I_OH

LOW-level output

voltage

I_OL= 4 mA

-

0.4

-

V

HIGH-level output

current

V_OH= V_DD 0.4 V;

V_OL= 0.4 V

4

-

mA

I_OL

LOW-level output

current

-

[16]

I_OHS

I_OLS

HIGH-level short-circuit V_OH= 0 V

output current

45

50

LOW-level short-circuit V_OL= V_DD

output current

-

I_pd

I_pu

pull-down current

pull-up current

V_I= 5 V

V_I= 0 V;

10

50

150

A

10

50

85

2.4 V  V_DD 3.6 V

_DD< V_I< 5 V

V

0

A

High-drive output pins configured as digital pin (PIO0_7 and PIO1_31); see Figure 13

I_IL

LOW-level input current V_I= 0 V; on-chip pull-up resistor

disabled

-

0.5

-

10

5

nA

V

I_IH

I_OZ

V_I

HIGH-level input

current

V_I= V_DD; on-chip pull-down

resistor disabled

-

OFF-state output

current

V_O= 0 V; V_O= V_DD; on-chip

pull-up/down resistors disabled

-

[14]

[15]

input voltage

V_DD 2.4 V

0

V_DD= 0 V

0

-

3.6

V_DD

-

V

V_O

output voltage

output active

0

V_IH

HIGH-level input

voltage

0.7 V_DD

V_IL

LOW-level input voltage

hysteresis voltage

-

0.3 V_DD

-

V

V_hys

0.05 V_DD

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Table 8.

Static characteristics …continued

T_amb= −40 °C to +105 °C, unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ^[1]Max

Unit

V

V_OH

HIGH-level output

voltage

I_OH= 12 mA; 2.4 V  V_DD 2.5 V

I_OH= 20 mA; 2.5 V  V_DD 3.6 V

I_OL= 4 mA

V_DD 0.4 -

-

V

V_OL

I_OH

LOW-level output

voltage

-

0.4

V

HIGH-level output

current

V_OH= V_DD 0.4 V;

2.4 V  V_DD 2.5 V

12

20

4

-

mA

V_OH= V_DD 0.4 V;

2.5 V  V_DD 3.6 V

-

I_OL

LOW-level output

current

V_OL= 0.4 V

-

[16]

I_OHS

I_OLS

HIGH-level short-circuit V_OH= 0 V

output current

-

45

50

LOW-level short-circuit V_OL= V_DD

output current

-

[17]

I_pd

I_pu

pull-down current

pull-up current

V_I= 5 V

10

10

0

50

50

0

150

85

0

A

V_I= 0 V

V_DD< V_I< 5 V

I²C-bus pins (PIO0_4 and PIO0_5); see Figure 13

V_IH

HIGH-level input

voltage

0.7 V_DD

-

V

V_IL

LOW-level input voltage

hysteresis voltage

-

0.3 V_DD

V

V_hys

I_OL

0.05 V_DD

3.5

-

V

LOW-level output

current

V_OL= 0.4 V; I²C-bus pins

configured as standard mode pins

mA

I_OL

LOW-level output

current

V_OL= 0.4 V; I²C-bus pins

configured as Fast-mode Plus

pins

20

-

mA

[18]

[2]

I_LI

input leakage current

V_I= V_DD

V_I= 5 V

-

2

4

A

10

22

USB_DM and USB_DP pins

V_I

input voltage

0

-

V_DD

-

V

V_IH

HIGH-level input

voltage

1.5

V_IL

LOW-level input voltage

hysteresis voltage

-

1.3

-

V

Ω

V

V_hys

Z_out

V_OH

0.32

28

2.9

output impedance

44

-

HIGH-level output

voltage

With 15 kΩ resistor to ground

V_OL

I_OH

I_OL

LOW-level output

voltage

With internal 1.5 kΩ resistor to

3.6 V pull-up enabled

-

0.18

V

[19]

HIGH-level output

current

V_OH= V_DD 0.3 V

4.8

5.0

-

mA

LOW-level output

current

V_OL= 0.3 V

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Table 8.

Static characteristics …continued

T_amb= −40 °C to +105 °C, unless otherwise specified.

Symbol

Parameter

LOW-level short-circuit drive LOW; pad connected to

output current ground

HIGH-level short-circuit drive HIGH; pad connected to

Conditions

Min

Typ^[1]Max

Unit

I_OLS

-

125

mA

I_OHS

-

125

mA

output current

ground

Oscillator pins

V_i(xtal)

V_o(xtal)

V_i(rtcx)

crystal input voltage

0.5

1.8

-

1.95

3.6

V

crystal output voltage

[20]

32 kHz oscillator input

voltage

on pin RTCXIN

V_o(rtcx)

32 kHz oscillator output on pin RTCXOUT

voltage

0.5

-

3.6

V

Pin capacitance

C_ioinput/output

capacitance

[21]

pins with analog and digital

functions

I²C-bus pins (PIO0_4 and

PIO0_5)

-

7.1

2.5

2.8

pF

pins with digital functions only

[1] Typical ratings are not guaranteed. The values listed are for room temperature (25 C), nominal supply voltages.

[2] For USB operation: 3.0 VV_DD 3.6 V.

[3] T_amb= 25 C.

[4] I_DDmeasurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled.

[5] IRC enabled; system oscillator disabled; system PLL disabled.

[6] System oscillator enabled; IRC disabled; system PLL disabled.

[7] BOD disabled.

[8] All peripherals disabled in the SYSAHBCLKCTRL register. Peripheral clocks to USART, CLKOUT, and IOCON disabled in system

configuration block.

[9] IRC enabled; system oscillator disabled; system PLL enabled.

[10] IRC disabled; system oscillator enabled; system PLL enabled.

[11] All oscillators and analog blocks turned off.

[12] WAKEUP pin pulled HIGH externally.

[13] Low-current mode PWR_LOW_CURRENT selected when running the set_power routine in the power profiles.

[14] Including voltage on outputs in tri-state mode.

[15] Tri-state outputs go into tri-state mode in Deep power-down mode.

[16] Allowed as long as the current limit does not exceed the maximum current allowed by the device.

[17] Pull-up and pull-down currents are measured across the weak internal pull-up/pull-down resistors. See Figure 13.

[18] To V_SS

.

[19] The parameter values specified are simulated and absolute values.

[20] The input voltage of the RTC oscillator is limited as follows: V_i(rtcx), V_o(rtcx)< max(VBAT, V_DD).

[21] Including bonding pad capacitance.

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V

DD

I

OL

pd

+

-

pin PIO0_n

A

I

OH

Ipu

-

+

A

aaa-010819

Fig 13. Pin input/output current measurement

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11.1 Power consumption

Power measurements in Active, Sleep, and Deep-sleep modes were performed under the

following conditions:

• Configure all pins as GPIO with pull-up resistor disabled in the IOCON block.

• Configure GPIO pins as outputs using the GPIO DIR register.

• Write 1 to the GPIO CLR register to drive the outputs LOW.

aaa-010026

8

I

DD

(mA)

48 MHz

36 MHz

6

4

2

0

24 MHz

12 MHz

6 MHz

1 MHz

2.4

2.6

2.8

3

3.2

3.4

3.6

V

(V)

DD

Conditions: T_amb= 25 C; active mode entered executing code while(1){} from flash; all

peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F), all peripheral

clocks disabled; internal pull-up resistors disabled; BOD disabled; low-current mode.

1 MHz to 6 MHz: IRC enabled; PLL disabled.

12 MHz: IRC enabled; PLL disabled.

24 MHz to 50 MHz: IRC disabled; PLL enabled; sysosc enabled.

Fig 14. Active mode: Typical supply current I_DDversus supply voltage V_DD

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aaa-010027

8

6

4

2

0

I

DD

(mA)

48 MHz

36 MHz

24 MHz

12 MHz

6 MHz

1 MHz

-40

-10

20

50

80

110

temperature (°C)

Conditions: V_DD= 3.3 V; active mode entered executing code while(1){} from flash; all

peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F; all peripheral

clocks disabled; internal pull-up resistors disabled; BOD disabled; low-current mode.

1 MHz to 6 MHz: IRC enabled; PLL disabled.

12 MHz: IRC enabled; PLL disabled.

24 MHz to 50 MHz: IRC disabled; PLL enabled; sysosc enabled.

Fig 15. Active mode: Typical supply current I_DDversus temperature

aaa-010028

4

1 MHz

(mA)

48 MHz

3

36 MHz

2

24 MHz

12 MHz

1

6 MHz

1 MHz

0

-40

-10

20

50

80

110

(°C)

Conditions: V_DD= 3.3 V; sleep mode entered from flash; all peripherals disabled in the

SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F) all peripheral clocks disabled; internal

pull-up resistors disabled; BOD disabled; low-current mode.

1 MHz to 6 MHz: IRC enabled; PLL disabled.

12 MHz: IRC enabled; PLL disabled.

24 MHz to 48 MHz: IRC disabled; PLL enabled; sysosc enabled.

Fig 16. Sleep mode: Typical supply current I_DDversus temperature for different system

clock frequencies

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aaa-009418

360

I

DD

(μA)

330

3.6 VV

3.3 VV

3.0 VV

2.7 VV

2.4 VV

300

270

-40

-10

20

50

80

110

T (°C)

Conditions: BOD disabled; all oscillators and analog blocks disabled

Fig 17. Deep-sleep mode: Typical supply current I_DDversus temperature for different

supply voltages V_DD

aaa-009419

80

I

DD

(μA)

60

40

20

0

-40

-10

20

50

80

110

T (°C)

Conditions: BOD disabled; all oscillators and analog blocks disabled; V_DD= 2.4 V to 3.6 V.

Fig 18. Power-down mode: Typical supply current I_DDversus temperature for different

supply voltages V_DD

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aaa-009427

4

3

2

1

0

I

DD

(μA)

3.6 VV

3.3 VV

3.0 VV

2.7 VV

2.4 VV

-40

-10

20

50

80

110

T (°C)

Conditions: RTC running; VBAT = 0 V

Fig 19. Deep power-down mode: Typical supply current I_DDversus temperature for

different supply voltages V_DD

aaa-009428

2

I

BAT

(μA)

1.5

1

0.5

0

-40

-10

20

50

80

110

T (°C)

Conditions: RTC not running; V_BAT= 3.0 V; V_DDfloating.

Fig 20. Deep power-down mode: Typical battery supply current I_BATversus temperature

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11.2 CoreMark data

aaa-011173

aaa-011174

2.5

CM

2.5

CM

(((itteeraations/s)/MHz))

2.25

(((iterations/s)/MHz))

2.25

cpu performance

cpu perfoorrmance

efficiency

default/llow-current

efficiency

2

1.75

1.5

default/low-current

2

1.75

1.5

1.25

1

1.25

1

0

10

20

30

40

50

0

10

20

30

40

50

system clock frequency (MHz)

Measured with Keil uVision v.4.72.

Measured with Keil uVision v.4.60.

Conditions: Conditions: V_DD= 3.3 V; active mode; all peripherals except one UART and the SCTimer disabled in the

SYSAHBCLKCTRL register; internal pull-up resistors enabled; BOD disabled.

Fig 21. CoreMark score for different power mode settings of the power profiles

aaa-011175

aaa-011176

15

I

DD

(mA)

DD

(mA)

12.5

10

7.5

5

12.5

10

7.5

5

cpu performance

default

cpu perfoorrmancee

efficiency

low-current

2.5

0

2.5

0

10

20

30

40

50

0

10

20

30

40

50

system clock frequency (MHz)

Measured with Keil uVision v.4.72.

Measured with Keil uVision v.4.60.

Conditions: Conditions: V_DD= 3.3 V; active mode; all peripherals except one UART and the SCTimer/PWM disabled in the

SYSAHBCLKCTRL register; internal pull-up resistors enabled; BOD disabled.

Fig 22. Active mode: CoreMark power consumption I_DDfor different power mode settings of the power profiles

The CoreMark scores serve as a guideline to select the best power mode for a given

application. To find the most suitable power mode, run the application in mode and

compare power consumption and performance.

Remark: Applications using the USB can only run in default mode.

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The power profiles optimize the chip performance for power consumption or core

efficiency by controlling the flash access and core power. As shown in Figure 21 and

Figure 22, different power modes result in different CoreMark scores reflecting the

trade-off of efficiency and power consumption. In CPU and efficiency modes, the power

profiles aim to keep the core efficiency at a maximum for the given system frequency.

Depending on optimal flash access parameters that change with frequency, the CoreMark

score and also the power consumption change. Since the compiled code for CoreMark

testing runs out of flash memory, the CoreMark score depends on the compiler version.

11.3 Peripheral power consumption

The supply current per peripheral is measured as the difference in supply current between

the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG

and PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both

registers and no code accessing the peripheral is executed except for the ADC. Measured

on a typical sample at T_amb= 25 C. Unless noted otherwise, the system oscillator and

PLL are running in both measurements.

The supply currents are shown for system clock frequencies of 12 MHz and 48 MHz.

Table 9.

Power consumption for individual analog and digital blocks

Peripheral

Typical supply current in mA

Notes

n/a

12 MHz

48 MHz

IRC

0.24

-

System oscillator running; PLL off; independent

of main clock frequency.

System oscillator at 12 MHz

0.28

0

-

IRC running; PLL off; independent of main clock

frequency.

WatchDog oscillator at

600 kHz/2

System oscillator running; PLL off; independent

of main clock frequency.

BOD

0.05

-

Independent of main clock frequency.

System PLL

USB PLL

CLKOUT

ROM

0.25

-

0.37

-

0.25

0.09

0.17

0.13

0.15

0.14

0.18

0.89

0.37

0.66

0.52

0.59

0.56

0.69

System PLL is source of CLKOUT.

-

FLASHREG

FLASHARRAY

SRAM1

USB SRAM

GPIO + pin interrupt/pattern

match

GPIO pins configured as outputs and set to

LOW. Direction and pin state are maintained if

the GPIO is disabled in the SYSAHBCLKCFG

register.

IOCON

-

0.08

0.29

0.30

1.1

-

SCTimer0/PWM +

SCTimer1/PWM

CT16B0

CT16B1

CT32B0

CT32B1

-

0.05

0.04

0.03

0.17

0.16

0.13

-

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Table 9.

Power consumption for individual analog and digital blocks …continued

Typical supply current in mA Notes

Peripheral

n/a

12 MHz

0.02

48 MHz

0.10

RTC

-

WWDT

0.05

0.17

Main clock selected as clock source for the

WDT.

I2C0

-

0.05

0.15

0.31

0.12

0.13

0.21

0.43

0.22

0.18

0.59

0.58

1.19

0.50

0.49

0.81

0.72

-

I2C1

SSP0

SSP1

USART0

USART1

USART2

USART3 + USART4

USB

Register interface disabled in

SYSAHBCLKCTRL.

USB PHY

ADC0

0.54

-

2.15

2.68

Register interface disabled in

SYSAHBCLKCTRL and analog block disabled

in PDRUNCFG registers. Power consumption

measured while the ADC is sampling a single

channel with an ADC clock of 12 MHz or

48 MHz.

Temperature sensor

0.18

-

DMA

CRC

-

0.28

0.04

1.1

0.14

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11.4 Electrical pin characteristics

aaa-009384

aaa-009385

2.4

OH

3.3

V

OH

(V)

V

(V)

2.3

2.2

2.1

2

3.2

3.1

3

2.4 V/-4400°CC

3.3 VV//--4400 °CC

3.3 VV//2255 °CC

3.3 VV//9900 °CC

3.3 VV//110055 °CC

2.4 V/25 °CC

2.4 V/ 90 °CC

2.4 V/ 105 °CC

2.9

2.8

2.7

1.9

1.8

0

10

20

30

OH

40

0

10

20

30

40

50

I

(mA)

I

(mA)

OH

Conditions: V_DD= 2.4 V; ON pin PIO0_7 and PIO1_31.

Conditions: V_DD= 3.3 V; ON pin PIO0_7 and PIO1_31.

Fig 23. High-drive output: Typical HIGH-level output voltage V_OHversus HIGH-level output current I_OH

aaa-009382

aaa-009383

50

40

30

20

10

0

50

40

30

20

10

0

2.4 V/-40 °CCC

2.4 V/25 °CC

2.4 V/90 °CC

2.4 V/105 °CC

3.3 VV//--4400 °CC

3.3 VV//2255 °CC

3.3 VV//9900 °CC

3.3 VV//110055 °CC

I

OL

(mA)

OL

(mA)

0

0.1

0.2

0.3

0.4

0.5

(V)

0.6

0

0.1

0.2

0.3

0.4

0.5

(V)

0.6

V

OL

Conditions: V_DD= 2.4 V; on pins PIO0_4 and PIO0_5.

Conditions: V_DD= 3.3 V; on pins PIO0_4 and PIO0_5.

Fig 24. I²C-bus pins (high current sink): Typical LOW-level output current I_OLversus LOW-level output voltage

V_OL

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aaa-009386

aaa-009387

10

15

12

9

I

OL

(mA)

OL

(mA)

8

6

4

2

0

2.4 V/-40 °CCC

2.4 V/25 °CCC

2.4 V/90 °CCC

2.4 V/105 °CC

3.3 VV//--4400 °CCC

3.3 VV//2255 °CCC

3.3 VV//9900 °CCC

3.3 VV//110055 °CC

6

3

0

0.1

0.2

0.3

0.4

0.5

(V)

0.6

0

0.1

0.2

0.3

0.4

0.5

(V)

0.6

V

OL

Conditions: V_DD= 2.4 V; standard port pins and

high-drive pins PIO0_7 and PIO1_31.

Conditions: V_DD= 3.3 V; standard port pins and

high-drive pins PIO0_7 and PIO1_31.

Fig 25. Typical LOW-level output current I_OLversus LOW-level output voltage V_OL

aaa-009388

aaa-009397

2.4

OH

3.3

V

OH

(V)

V

(V)

2.3

2.2

2.1

2

3.2

3.1

3

2.4 V/-40 °CCC

2.4 V/25 °CC

2.4 V/ 90 °CC

2.4 V/ 105 °CCC

3.3 VV//--4400 °CC

3.3 VV//2255 °CC

3.3 VV//9900 °CC

3.3 VV//110055 °CC

2.9

2.8

2.7

1.9

1.8

0

2

4

6

8

10

0

3

6

9

12

15

I

(mA)

I

(mA)

OH

Conditions: V_DD= 2.4 V; standard port pins.

Conditions: V_DD= 3.3 V; standard port pins.

Fig 26. Typical HIGH-level output voltage V_OHversus HIGH-level output source current I_OH

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aaa-009398

aaa-009399

0

I

PU

(μA)

PU

(μA)

-7

-13

-26

-39

-52

-65

-14

-21

-28

-35

3.3 VV//110055 °CC

3.3 VV//9900 °CC

3.3 VV//2255 °CC

3.3 VV//--4400 °CC

2.4 V/105 °CC

2.4 V/90 °CC

2.4 V/25 °CC

2.4 V/-40 °CCC

0

0.5

1

1.5

2

2.5

3

3.5

0

1

2

3

4

5

V (V)

I

Conditions: V_DD= 2.4 V; standard port pins.

Conditions: V_DD= 3.3 V; standard port pins.

Fig 27. Typical pull-up current I_PUversus input voltage V_I

aaa-009416

aaa-009417

50

65

I

PD

(μA)

PD

(μA)

40

30

20

10

0

52

39

26

13

0

2.4 V/-40 °CC

2.4 V/25 °CC

2.4 V/90 °CC

2.4 V/105 °CC

3.3 VV//--4400 °CC

3.3 VV//2255 °CC

3.3 VV//9900 °CC

3.3 VV//110055 °CC

0

0.5

1

1.5

2

2.5

3

3.5

0

1

2

3

4

5

V (V)

I

Conditions: V_DD= 2.4 V; standard port pins.

Conditions: V_DD= 3.3 V; standard port pins.

Fig 28. Typical pull-down current I_PDversus input voltage V_I

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12. Dynamic characteristics

12.1 Flash/EEPROM memory

Table 10. Flash characteristics

T_amb= −40 °C to +105 °C. Based on JEDEC NVM qualification. Failure rate < 10 ppm for parts as

specified below.

Symbol

N_endu

t_ret

Parameter

endurance

Conditions

Min

10000

10

Typ

100000

20

Max

Unit

[1]

-

cycles

years

ms

retention time

powered

-

unpowered

20

40

-

t_er

erase time

page or multiple

consecutivepages,

sector or multiple

consecutive

95

100

105

sectors

[2]

t_prog

programming

time

0.95

1

1.05

ms

[1] Number of program/erase cycles.

[2] Programming times are given for writing 256 bytes to the flash. T_amb<= +85 C. Flash programming with

IAP calls (see LPC11U6x user manual).

Table 11. EEPROM characteristics

T_amb= −40 °C to +85 °C; V_DD= 2.7 V to 3.6 V. Based on JEDEC NVM qualification. Failure rate <

10 ppm for parts as specified below.

Symbol

N_endu

t_ret

Parameter

endurance

Conditions

Min

100000

100

150

-

Typ

Max

Unit

1000000

200

-

cycles

years

ms

retention time

powered

unpowered

64 bytes

300

t_prog

programming

time

2.9

12.2 External clock for the oscillator in slave mode

Remark: The input voltage on the XTAL1/2 pins must be  1.95 V (see Table 8). For

connecting the oscillator to the XTAL pins, also see Section 14.4.

Table 12. Dynamic characteristic: external clock (XTALIN input)

T_amb= −40 °C to +105 °C; V_DDover specified ranges.^[1]

Symbol

f_osc

Parameter

Conditions

Min

Typ^[2]

Max

Unit

MHz

ns

oscillator frequency

clock cycle time

clock HIGH time

clock LOW time

clock rise time

clock fall time

1

-

25

T_cy(clk)

t_CHCX

t_CLCX

t_CLCH

t_CHCL

40

1000

T_cy(clk) 0.4

-

ns

T_cy(clk) 0.4

-

ns

-

5

ns

[1] Parameters are valid over operating temperature range unless otherwise specified.

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[2] Typical ratings are not guaranteed. The values listed are for room temperature (25 C), nominal supply

voltages.

t

CHCX

t

CLCH

CHCL

CLCX

T

cy(clk)

aaa-004648

Fig 29. External clock timing (with an amplitude of at least V_i(RMS)= 200 mV)

12.3 Internal oscillators

Table 13. Dynamic characteristics: IRC

T_amb= −40 °C to +105 °C; 2.7 V ≤ V_DD≤ 3.6 V^[1].

Symbol Parameter

Conditions

Min

Typ^[2]Max

Unit

MHz

f_osc(RC)

internal RC

25 C  T_amb +85 C 12 - 1%

40 C  T_amb< 25 C 12 - 2%

12

12 + 1 %

oscillator frequency

85 C < T_amb 105 C 12 - 1.5 % 12

12 + 1.5 % MHz

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are for room temperature (25 C), nominal supply

voltages.

aaa-010023

12.15

f

3.6 VV

(MHz)

3.3 VV

3.0 VV

2.7 VV

12.08

12

11.93

11.85

-40

-10

20

50

80

temperature (°C)

110

Conditions: Frequency values are typical values. 12 MHz  1 % accuracy is guaranteed for

2.7 V  V_DD 3.6 V and T_amb= 25 C to +85 C. Variations between parts may cause the IRC to

fall outside the 12 MHz  1 % accuracy specification for voltages below 2.7 V.

Fig 30. Typical Internal RC oscillator frequency versus temperature

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Table 14. Dynamic characteristics: WatchDog oscillator

Symbol Parameter

Conditions

Min Typ^[1]Max Unit

[2][3]

f_osc(int)

internal oscillator DIVSEL = 0x1F, FREQSEL = 0x1

-

9.4

-

kHz

frequency

in the WDTOSCCTRL register;

DIVSEL = 0x00, FREQSEL = 0xF

in the WDTOSCCTRL register

-

2300

-

kHz

[1] Typical ratings are not guaranteed. The values listed are at nominal supply voltages.

[2] The typical frequency spread over processing and temperature (T_amb= 40 C to +105 C) is 40 %.

[3] See the LPC11U6x user manual.

12.4 I/O pins

Table 15. Dynamic characteristics: I/O pins^[1]

T_amb= −40 °C to +105 °C; 3.0 V ≤ V_DD≤ 3.6 V.

Symbol Parameter Conditions

Min

3.0

2.5

Typ

Max

5.0

Unit

ns

t_r

t_f

rise time

fall time

pin configured as output

-

5.0

ns

[1] Applies to standard port pins and RESET pin.

12.5 I²C-bus

Table 16. Dynamic characteristic: I²C-bus pins^[1]

T_amb= −40 °C to +105 °C.^[2]

Symbol

Parameter

Conditions

Standard-mode

Fast-mode

Min

Max

Unit

kHz

MHz

f_SCL

SCL clock

frequency

0

100

400

1

Fast-mode Plus; on

pins PIO0_4 and

PIO0_5

[4][5][6][7]

t_f

fall time

of both SDA and

SCL signals

-

300

ns

Standard-mode

Fast-mode

20 + 0.1  C_b300

ns

Fast-mode Plus;

on pins PIO0_4

and PIO0_5

-

120

t_LOW

LOW period of

the SCL clock

Standard-mode

Fast-mode

4.7

1.3

-

s

Fast-mode Plus; on 0.5

pins PIO0_4 and

PIO0_5

t_HIGH

HIGH period of

the SCL clock

Standard-mode

Fast-mode

4.0

0.6

-

s

Fast-mode Plus; on 0.26

pins PIO0_4 and

PIO0_5

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Table 16. Dynamic characteristic: I²C-bus pins^[1]…continued

T_amb= −40 °C to +105 °C.^[2]

Symbol

Parameter

Conditions

Standard-mode

Fast-mode

Min

0

Max

Unit

s

[3][4][8]

t_HD;DAT

data hold time

-

0

s

Fast-mode Plus; on

pins PIO0_4 and

PIO0_5

0

s

[9][10]

t_SU;DAT

data set-up

time

Standard-mode

Fast-mode

250

100

-

ns

Fast-mode Plus; on 50

pins PIO0_4 and

PIO0_5

[1] See the I²C-bus specification UM10204 for details.

[2] Parameters are valid over operating temperature range unless otherwise specified.

[3] t_HD;DATis the data hold time that is measured from the falling edge of SCL; applies to data in transmission

and the acknowledge.

[4] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the

V_IH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL.

[5] C_b= total capacitance of one bus line in pF.

[6] The maximum t_ffor the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA

output stage t_fis specified at 250 ns. This allows series protection resistors to be connected in between the

SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified t_f.

[7] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors

are used, designers should allow for this when considering bus timing.

[8] The maximum t_HD;DATcould be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than

the maximum of t_VD;DATor t_VD;ACKby a transition time (see UM10204). This maximum must only be met if

the device does not stretch the LOW period (t_LOW) of the SCL signal. If the clock stretches the SCL, the

data must be valid by the set-up time before it releases the clock.

[9] t_SU;DATis the data set-up time that is measured with respect to the rising edge of SCL; applies to data in

transmission and the acknowledge.

[10] A Fast-mode I²C-bus device can be used in a Standard-mode I²C-bus system but the requirement

t_SU;DAT= 250 ns must then be met. This will automatically be the case if the device does not stretch the

LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must

output the next data bit to the SDA line t_r(max)+ t_SU;DAT= 1000 + 250 = 1250 ns (according to the

Standard-mode I²C-bus specification) before the SCL line is released. Also the acknowledge timing must

meet this set-up time.

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t

f

t

SU;DAT

70 %

30 %

70 %

30 %

SDA

SCL

t

HD;DAT

VD;DAT

t

f

t

HIGH

70 %

30 %

70 %

30 %

70 %

30 %

70 %

30 %

t

LOW

1 / f

S

SCL

aaa-004643

Fig 31. I²C-bus pins clock timing

12.6 SSP interface

Table 17. Dynamic characteristics of SPI pins in SPI mode

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

SPI master (in SPI mode)

[1]

[2]

T_cy(clk)

clock cycle time

full-duplex mode

when only transmitting

in SPI mode

50

40

15

0

-

ns

t_DS

data set-up time

data hold time

-

t_DH

in SPI mode

-

t_v(Q)

t_h(Q)

data output valid time in SPI mode

data output hold time in SPI mode

-

10

-

0

SPI slave (in SPI mode)

T_cy(PCLK)PCLK cycle time

20

0

-

ns

[3][4]

t_DS

data set-up time

data hold time

in SPI mode

-

t_DH

3  T_cy(PCLK)+ 4

-

t_v(Q)

t_h(Q)

data output valid time in SPI mode

data output hold time in SPI mode

-

3  T_cy(PCLK)+ 11

2  T_cy(PCLK)+ 5

[1] T_cy(clk)= (SSPCLKDIV  (1 + SCR)  CPSDVSR) / f_main. The clock cycle time derived from the SPI bit rate T_cy(clk)is a function of the

main clock frequency f_main, the SPI peripheral clock divider (SSPCLKDIV), the SPI SCR parameter (specified in the SSP0CR0 register),

and the SPI CPSDVSR parameter (specified in the SPI clock prescale register).

[2] T_amb= 40 C to 105 C; 2.4 V  V_DD 3.6 V.

[3] T_cy(clk)= 12  T_cy(PCLK)

.

[4] T_amb= 25 C; for normal voltage supply range: V_DD= 3.3 V.

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T

cy(clk)

SCK (CPOL = 0)

SCK (CPOL = 1)

MOSI

t

h(Q)

v(Q)

DATA VALID

CPHA = 1

t

DH

DS

DATA VALID

MISO

t

h(Q)

v(Q)

DATA VALID

t

MOSI

MISO

t

CPHA = 0

DS

DH

DATA VALID

002aae829

Fig 32. SSP master timing in SPI mode

T

cy(clk)

SCK (CPOL = 0)

SCK (CPOL = 1)

t

DH

DS

MOSI

MISO

DATA VALID

t

h(Q)

v(Q)

CPHA = 1

DATA VALID

t

DH

DS

MOSI

MISO

DATA VALID

t

h(Q)

CPHA = 0

v(Q)

DATA VALID

002aae830

Fig 33. SSP slave timing in SPI mode

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12.7 USART interface

The maximum USART bit rate for all USARTs is 3.125 Mbit/s in asynchronous mode and

10 Mbit/s in synchronous slave and master mode.

Table 18. USART dynamic characteristics USART0

T_amb= −40 °C to 105 °C; 2.4 V <= V_DD<= 3.6 V; C_L= 10 pF. Simulated parameters sampled at the

50 % level of the falling or rising edge; values guaranteed by design.

Symbol

Parameter

Min

Max

Unit

[1]

T_cy(clk)

clock cycle time

100

-

ns

USART master (in synchronous mode)

t_su(D)

t_h(D)

t_v(Q)

t_h(Q)

data input set-up time

data input hold time

data output valid time

data output hold time

44

0

-

ns

-

10

-

0

USART slave (in synchronous mode)

t_su(D)

t_h(D)

t_v(Q)

t_h(Q)

data input set-up time

data input hold time

data output valid time

data output hold time

5

-

ns

20

-

40

-

25

[1] T_cy(clk)= (main clock cycle time)/(UARTCLKDIV x 2 x (256 x DLM + DLL)). See the LPC11U6x User

manual UM10732.

Table 19. USART dynamic characteristics USART1/2/3/4

T_amb= −40 °C to 105 °C; 2.4 V <= V_DD<= 3.6 V; C_L= 10 pF. Simulated parameters sampled at the

50 % level of the falling or rising edge; values guaranteed by design.

Symbol

Parameter

Min

Max

Unit

[1]

T_cy(clk)

clock cycle time

100

-

ns

USART master (in synchronous mode)

t_su(D)

t_h(D)

t_v(Q)

t_h(Q)

data input set-up time

data input hold time

data output valid time

data output hold time

44

0

-

ns

-

10

-

0

USART slave (in synchronous mode)

t_su(D)

t_h(D)

t_v(Q)

t_h(Q)

data input set-up time

data input hold time

data output valid time

data output hold time

5

-

ns

0

-

40

-

20

[1] T_cy(clk)= U_PCLK/BRGVAL. See the LPC11U6x User manual UM10732.

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T

cy(clk)

Un_SCLK (CLKPOL = 0)

Un_SCLK (CLKPOL = 1)

TXD

t

h(Q)

v(Q)

START

BIT0

BIT1

t

su(D) h(D)

BIT1

START

BIT0

RXD

aaa-007001

Fig 34. USART timing

12.8 SCTimer/PWM output timing

Table 20. SCTimer/PWM output dynamic characteristics

T_amb= −40 °C to 105 °C; 2.4 V <= V_DD<= 3.6 V. Simulated skew (over process, voltage, and

temperature) between any two SCT outputs; sampled at the 50 % level of the falling or rising edge;

values guaranteed by design.

Symbol

Parameter

Min

< 1

Max

Unit

SCTimer0/PWM

t_sk(o)

output skew time

2

ns

SCTimer1/PWM

t_sk(o)

2

ns

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13. Characteristics of analog peripherals

Table 21. BOD static characteristics^[1]

T_amb= 25 °C.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

V_th

threshold voltage interrupt level 2

assertion

-

2.54

2.68

-

V

de-assertion

interrupt level 3

assertion

-

2.82

2.93

-

V

de-assertion

reset level 2

assertion

-

2.34

2.49

-

V

de-assertion

reset level 3

assertion

-

2.62

2.77

-

V

de-assertion

[1] Interrupt and reset levels are selected by writing the level value to the BOD control register BODCTRL, see

the LPC11U6x user manual. Interrupt levels 0 and 1 are reserved.

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Table 22. 12-bit ADC static characteristics

T_amb= −40 °C to +105 °C; V_DD= 2.4 V to 3.6 V; VREFP = V_DDA; V_SSA= 0; VREFN = V_SSA. ADC

calibrated at T = 25 °C.

Symbol Parameter

Conditions

Min

Typ

Max

V_DDA

0.32

Unit

[1]

[2]

[3]

V_IA

C_ia

analog input

voltage

0

-

V

analog input

capacitance

pF

f_clk(ADC)ADC clock

frequency

V_DDA2.7 V

V_DDA2.4 V

V_DDA2.7 V

V_DDA2.4 V

50

25

2

MHz

f_s

sampling

frequency

-

Msamples/s

LSB

1

[4]

[5]

E_D

differential

2.5

linearity error

E_L(adj)

integral

-

2.5

LSB

non-linearity

[6]

[7]

E_O

offset error

-

4.5

0.5

LSB

%

V_err(FS)full-scale error

voltage

[8][9]

Z_i

input

f_s= 2 Msamples/s

0.1

-

M

impedance

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply

voltages.

[2] The input resistance of ADC channel 0 is higher than for all other channels.

[3] C_iarepresents the external capacitance on the analog input channel for sampling speeds of 2 Msamples/s.

[4] The differential linearity error (E_D) is the difference between the actual step width and the ideal step width.

See Figure 35.

[5] The integral non-linearity (E_L(adj)) is the peak difference between the center of the steps of the actual and

the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 35.

[6] The offset error (E_O) is the absolute difference between the straight line which fits the actual curve and the

straight line which fits the ideal curve. See Figure 35.

[7] The full-scale error voltage or gain error (E_G) is the difference between the straight-line fitting the actual

transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. See

Figure 35.

[8] T_amb= 25 C; maximum sampling frequency f_s= 2 Msamples/s and analog input capacitance C_ia= 0.32 pF.

[9] Input impedance Z_iis inversely proportional to the sampling frequency and the total input capacity including

C_ia: Z_i 1 / (f_s C_i). See Table 8 for C_io.

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offset

error

O

gain

error

E

G

4095

4094

4093

4092

4091

4090

(2)

7

code

out

(1)

6

5

4

3

2

1

0

(5)

(4)

(3)

1 LSB

(ideal)

4090 4091 4092 4093 4094 4095 4096

1

2

3

4

5

6

7

V

IA

(LSB

)

ideal

offset error

E

O

VREFP - V

4096

SS

1 LSB =

002aaf436

(1) Example of an actual transfer curve.

(2) The ideal transfer curve.

(3) Differential linearity error (E_D).

(4) Integral non-linearity (E_L(adj)).

(5) Center of a step of the actual transfer curve.

Fig 35. 12-bit ADC characteristics

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ADC

R

= 0.25 kΩ...2.5 kΩ

1

ADCn_0

C

io

R

= 5 Ω...25 Ω

sw

ADCn_[1:11]

DAC

C

DAC

C

io

C

ia

aaa-011748

Fig 36. ADC input impedance

Table 23. Temperature sensor static and dynamic characteristics

V_DDA= 2.4 V to 3.6 V

Symbol

Parameter

Conditions

_amb= 40 C to +105 C

Min

Typ

Max

Unit

[1]

[2]

DT_sen

sensor

temperature

accuracy

T

-

5

-

C

E_L

linearity error

T_amb= 40 C to +105 C

-

4

-

C

s

t_s(pu)

power-up

settling time

to 99% of temperature

sensor output value

14

[1] Absolute temperature accuracy.

[2] Typical values are derived from nominal simulation (V_DDA= 3.3 V; T_amb= 27 C; nominal process models).

Table 24. Temperature sensor Linear-Least-Square (LLS) fit parameters

V_DDA= 2.4 V to 3.6 V

Fit parameter

LLS slope

Range

Min

Typ

Max

Unit

mV/C

mV

T_amb= 40 C to +105 C

T_amb= 40 C to +105C

-

-2.36

606

-

LLS intercept

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aaa-009429

800

V

O

(mV)

600

400

200

0

-40

-10

20

50

80

110

temperature (°C)

V_DDA= 3.3 V; measured on a typical silicon sample.

Fig 37. Typical LLS fit of the temperature sensor output voltage

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14. Application information

14.1 ADC usage notes

The following guidelines show how to increase the performance of the ADC in a noisy

environment beyond the ADC specifications listed in Table 22:

• The ADC input trace must be short and as close as possible to the LPC11U6x chip.

• The ADC input traces must be shielded from fast switching digital signals and noisy

power supply lines.

• If the ADC and the digital core share a power supply, the power supply line must be

adequately filtered.

• To improve the ADC performance in a very noisy environment, put the device in Sleep

mode during the ADC conversion.

14.2 Typical wake-up times

Table 25. Typical wake-up times

V_DD= 3.3 V; T_amb= 25 °C

Power modes

Wake-up time

2.6 s

Sleep mode (12 MHz)^[1][2]

Deep-sleep mode^[1][3]

Power-down mode^[1][3]

Deep Power-down mode^[4]

4.4 s

86.8 s

276 s

[1] The wake-up time measured is the time between when a GPIO input pin is triggered to wake up the device

from the low-power modes and from when a GPIO output pin is set in the interrupt service routine (ISR)

wake-up handler.

[2] IRC enabled, all peripherals off.

[3] WatchDog oscillator disabled, Brown-Out Detect (BOD) disabled.

[4] Wake-up from deep power-down causes the part to go through entire reset process. The wake-up time

measured is the time between when a wake-up pin is triggered to wake up the device from the low-power

modes and when a GPIO output pin is set in the reset handler.

14.3 Suggested USB interface solutions

The USB device can be connected to the USB as self-powered device (see Figure 38) or

bus-powered device (see Figure 39).

On the LPC11U6x, the PIO0_3/USB_VBUS pin is 5 V tolerant only when V_DDis applied

and at operating voltage level. Therefore, if the USB_VBUS function is connected to the

USB connector and the device is self-powered, the USB_VBUS pin must be protected for

situations when V_DD= 0 V.

If V_DDis always at operating level while VBUS = 5 V, the USB_VBUS pin can be

connected directly to the VBUS pin on the USB connector.

For systems where V_DDcan be 0 V and VBUS is directly applied to the VBUS pin,

precautions must be taken to reduce the voltage to below 3.6 V, which is the maximum

allowable voltage on the USB_VBUS pin in this case.

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One method is to use a voltage divider to connect the USB_VBUS pin to the VBUS on the

USB connector. The voltage divider ratio should be such that the USB_VBUS pin is

greater than 0.7 V_DDto indicate a logic HIGH while below the 3.6 V allowable maximum

voltage.

For the following operating conditions

VBUS_max= 5.25 V

V_DD= 3.6 V,

the voltage divider should provide a reduction of 3.6 V/5.25 V or ~0.686 V.

LPC1xxx

V

DD

R2

R3

USB_CONNECT

USB

R1

1.5 kΩ

USB_VBUS

D+

D-

R

S

= 33 Ω

USB-B

connector

USB_DP

USB_DM

R

S

V

SS

aaa-010820

Fig 38. USB interface on a self-powered device where USB_VBUS = 5 V

The USB_CONNECT function can be enabled internally by setting the DCON bit in the

DEVCMDSTAT register to prevent the USB from timing out when there is a significant

delay between power-up and handling USB traffic. External circuitry is not required for the

USB_CONNECT functionality.

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LPC1xxx

V

DD

REGULATOR

USB_CONNECT

USB

(1)

(2)

USB_VBUS

R1

1.5 kΩ

VBUS

D+

D-

R

= 33 Ω

USB-B

connector

S

USB_DP

USB_DM

V

SS

aaa-010821

Two options exist for connecting VBUS to the USB_VBUS pin:

(1) Connect the regulator output to USB_VBUS. In this case, the USB_VBUS signal is HIGH whenever the part is powered.

(2) Connect the VBUS signal directly from the connector to the USB_VBUS pin. In this case, 5 V are applied to the USB_VBUS pin

while the regulator is ramping up to supply V_DD. Since the PIO0_3/USB_VBUS pin is only 5 V tolerant when V_DDis at operating

level, this connection can degrade the performance of the part over its lifetime. Simulation shows that lifetime is reduced to

15 years at T_amb= 45 °C and 8 years at T_amb= 55 °C assuming that USB_VBUS = 5 V is applied continuously while V_DD= 0 V.

Fig 39. USB interface on a bus-powered device

Remark: When a self-powered circuit is used without connecting VBUS, configure the

PIO0_3/USB_VBUS pin for GPIO (PIO0_3) and provide software that can detect the host

presence through some other mechanism before enabling USB_CONNECT and the

SoftConnect feature. Enabling the SoftConnect without host presence leads to USB

compliance failure.

14.3.1 USB Low-speed operation

The USB device controller can be used in low-speed mode supporting 1.5 Mbit/s data

exchange with a USB host controller.

Remark: To operate in low-speed mode, change the board connections as follows:

1. Connect USB_DP to the D- pin of the connector.

2. Connect USB_DM to the D+ pin of the connector.

Use the IRC as clock source for the USB PLL to generate 48 MHz, then set the USB clock

divider USBCLKDIV to 8 for a 6 MHz USB clock (see Figure 10 “Clock generation”).

External 10 Ω resistors are recommended in low-speed mode to reduce over-shoots and

accommodate for 5 m cable length required for USB-IF testing.

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SYSCON

12 MHz

IRC

USB PLL

48 MHz

USBCLKDIV

/8

USB main clock

V

DD

= 6 MHz

USB_CONNECT

USB

R1

1.5 kΩ

USB_VBUS

USB_DP

R

= 10 Ω

R

S

= 33 Ω

S

D+

D-

USB-B

connector

R

S

USB_DM

V

SS

aaa-011021

Fig 40. USB interface for low-speed, XTAL-less operation

14.4 XTAL input and crystal oscillator component selection

The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a

clock in slave mode, it is recommended that the input be coupled through a capacitor with

C_i= 100 pF. To limit the input voltage to the specified range, choose an additional

capacitor to ground C_gwhich attenuates the input voltage by a factor C_i/(C_i+ C_g). In slave

mode, a minimum of 200 mV(RMS) is needed.

LPC1xxx

XTALIN

C

i

C

g

100 pF

002aae788

Fig 41. Slave mode operation of the on-chip oscillator

In slave mode the input clock signal should be coupled through a capacitor of 100 pF

(Figure 41), with an amplitude between 200 mV (RMS) and 1000 mV (RMS). This

corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V.

The XTALOUT pin in this configuration can be left unconnected.

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External components and models used in oscillation mode are shown in Figure 42 and in

Table 26 and Table 27. Since the feedback resistance is integrated on chip, only a crystal

and the capacitances C_X1and C_X2must be connected externally in case of fundamental

mode oscillation (the fundamental frequency is represented by L, C_Land R_S).

Capacitance C_Pin Figure 42 represents the parallel package capacitance and should not

be larger than 7 pF. Parameters F_OSC, C_L, R_Sand C_Pare supplied by the crystal

manufacturer (see Table 26).

LPC1xxx

L

XTALIN

XTALOUT

C

L

C

P

=

XTAL

R

S

C

X2

C

X1

002aaf424

Fig 42. Oscillator modes and models: oscillation mode of operation and external crystal

model used for C_X1/C_X2evaluation

Table 26. Recommended values for C_X1/C_X2in oscillation mode (crystal and external

components parameters) low frequency mode

Fundamental oscillation Crystal load

Maximum crystal

External load

frequency F_OSC

capacitance C_L

series resistance R_S

capacitors C_X1, C_X2

1 MHz to 5 MHz

10 pF

< 300 

< 200 

< 100 

< 160 

< 60 

18 pF, 18 pF

39 pF, 39 pF

57 pF, 57 pF

18 pF, 18 pF

39 pF, 39 pF

57 pF, 57 pF

18 pF, 18 pF

39 pF, 39 pF

18 pF, 18 pF

20 pF

30 pF

5 MHz to 10 MHz

10 pF

20 pF

30 pF

10 MHz to 15 MHz

15 MHz to 20 MHz

10 pF

20 pF

10 pF

< 80 

Table 27. Recommended values for C_X1/C_X2in oscillation mode (crystal and external

components parameters) high frequency mode

Fundamental oscillation Crystal load

Maximum crystal

External load

frequency F_OSC

capacitance C_L

series resistance R_S

capacitors C_X1, C_X2

15 MHz to 20 MHz

10 pF

< 180 

< 100 

< 160 

< 80 

18 pF, 18 pF

39 pF, 39 pF

18 pF, 18 pF

39 pF, 39 pF

20 pF

20 MHz to 25 MHz

10 pF

20 pF

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14.5 XTAL Printed-Circuit Board (PCB) layout guidelines

The crystal should be connected on the PCB as close as possible to the oscillator input

and output pins of the chip. Take care that the load capacitors C_x1, C_x2, and C_x3in case of

third overtone crystal usage have a common ground plane. The external components

must also be connected to the ground plane. Loops must be made as small as possible to

keep the noise coupled in via the PCB as small as possible. Also parasitics should stay as

small as possible. Smaller values of C_x1and C_x2should be chosen according to the

increase in parasitics of the PCB layout.

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14.6 RTC oscillator component selection

The 32 kHz crystal must be connected to the part via the RTCXIN and RTCXOUT pins as

shown in Figure 43. If the RTC is not used, the RTCXIN pin can be grounded.

LPC1xxx

L

RTCXIN

RTCXOUT

C

R

C

P

=

L

XTAL

S

C

X2

X1

aaa-010822

Fig 43. RTC oscillator components

Select C_x1and C_x2based on the external 32 kHz crystal used in the application circuitry.

The pad capacitance C_Pof the RTCXIN and RTCXOUT pad is 3 pF. If the load

capacitance of the external crystal is C_L, the optimal C_x1and C_x2can be selected as:

C_x1= C_x2= 2 x C_L– C_P

To achieve the best performance and accurate frequency, it is recommended to use Cx1

= Cx2 = 24 pF and CL = 12 pF.

Please note the actual board layout and placement of external components influences the

optimal values of external load capacitors. Therefore, it is recommended to fine tune the

values of external load capacitors on the hardware board to get the accurate clock

frequency. For fine tuning, measure the clock on the CLOCKOUT pin and optimize the

values of external load capacitors for minimum frequency deviation.

14.7 Connecting power, clocks, and debug functions

Figure 44 shows the basic board connections used to power the LPC11U6x, connect the

external crystal and the 32 kHz oscillator for the RTC, and provide debug capabilities via

the serial wire port.

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3.3 V

SWD connector

Note 6

3.3 V

~10 kΩ - 100 kΩ

SWDIO/PIO0_15

SWCLK/PIO0_10

1

2

4

3

5

7

~10 kΩ - 100 kΩ

PIO2_0/XTALIN

n.c.

6

8

C1

Note 1

n.c.

DGND

C2

PIO2_1/XTALOUT

RESET/PIO0_0

DGND

9

10

RTCXIN

C3

C4

Note 2

DGND

V

SS

RTCXOUT

DGND

Note 3

3.3 V

V

(2 to 5 pins)

DD

V

SSA

0.1 μF

0.01 μF

LPC11U6x

AGND

PIO0_1

DGND

Note 4

3.3 V

V

DDA

ISP select pins

Note 7

PIO0_3

ADC_0

0.1 μF

10 μF

Note 4

3.3 V

VREFP

0.1 μF

10 μF

0.1 μF

VREFN

AGND

Note 5

3.3 V

VBAT

0.1 μF

AGND

DGND

aaa-013306

(1) See Section 14.4 “XTAL input and crystal oscillator component selection” for the values of C1 and C2.

(2) See Section 14.6 “RTC oscillator component selection” for the values of C3 and C4.

(3) Position the decoupling capacitors of 0.1 μF and 0.01 μF as close as possible to the V_DDpin. Add one set of decoupling

capacitors to each V_DDpin.

(4) Position the decoupling capacitors of 0.1 μF as close as possible to the VREFN and V_DDApins. The 10 μF bypass capacitor

filters the power line. Tie V_DDAand VREFP to V_DDif the ADC is not used. Tie VREFN to V_SSif ADC is not used.

(5) Position the decoupling capacitor of 0.1 μF as close as possible to the VBAT pin. Tie VBAT to V_DDif not used.

(6) Uses the ARM 10-pin interface for SWD.

(7) When measuring signals of low frequency, use a low-pass filter to remove noise and to improve ADC performance. Also see

Ref. 3.

Fig 44. Power, clock, and debug connections

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14.8 Termination of unused pins

Table 28 shows how to terminate pins that are not used in the application. In many cases,

unused pins may should be connected externally or configured correctly by software to

minimize the overall power consumption of the part.

Unused pins with GPIO function should be configured as outputs set to LOW with their

internal pull-up disabled. To configure a GPIO pin as output and drive it LOW, select the

GPIO function in the IOCON register, select output in the GPIO DIR register, and write a 0

to the GPIO PORT register for that pin. Disable the pull-up in the pin’s IOCON register.

In addition, it is recommended to configure all GPIO pins that are not bonded out on

smaller packages as outputs driven LOW with their internal pull-up disabled.

Table 28. Termination of unused pins

Default Recommended termination of unused pins

state^[1]

RESET/PIO0_0

I; PU

In an application that does not use the RESET pin or its GPIO function, the

termination of this pin depends on whether Deep power-down mode is used:

• Deep power-down used: Connect an external pull-up resistor and keep pin in

default state (input, pull-up enabled) during all other power modes.

• Deep power-down not used and no external pull-up connected: can be left

unconnected if internal pull-up is disabled and pin is driven LOW and

configured as output by software.

all PIOn_m (not

open-drain)

I; PU

Can be left unconnected if driven LOW and configured as GPIO output with pull-up

disabled by software.

PIOn_m (I2C open-drain)

RSTOUT

IA

Can be left unconnected if driven LOW and configured as GPIO output by software.

IA; O

Can be left unconnected. Not configurable by software.

USB_DP/USB_DM

RTCXIN

F

-

Can be left unconnected. When the USP PHY is disabled, the pins are LOW.

Connect to ground. When grounded, the RTC oscillator is disabled.

RTCXOUT

VREFP

-

Can be left unconnected.

Tie to VDD.

-

VREFN

-

Tie to VSS.

VDDA

-

Tie to VDD.

VBAT

-

Tie to VDD if no external battery connected.

Tie to VSS.

VSSA

-

[1] I = Input, O = Output, IA = Inactive (no pull-up/pull-down enabled), F = floating, PU = Pull-Up.

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14.9 Pin states in different power modes

Table 29. Pin states in different power modes

Pin Active Sleep

Deep-sleep/Power- Deep power-down

down

PIOn_m pins (not As configured in the IOCON^[1]. Default: internal pull-up

I2C) enabled.

Floating.

PIO0_4, PIO0_5 As configured in the IOCON^[1].

Floating.

(open-drain

I2C-bus pins)

RESET

Reset function enabled. Default: input, internal pull-up

enabled.

Reset function disabled; floating; if the part

is in deep power-down mode, the RESET

pin needs an external pull-up to reduce

power consumption.

PIO0_16/

WAKEUP

As configured in the IOCON^[1]. WAKEUP function inactive. Wake-up function enabled; can be disabled

by software.

[1] Default and programmed pin states are retained in sleep, deep-sleep, and power-down modes.

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14.10 ElectroMagnetic Compatibility (EMC)

Radiated emission measurements according to the IEC61967-2 standard using the

TEM-cell method are shown for part LPC11U68JBD100.

Table 30. ElectroMagnetic Compatibility (EMC) for part LPC11U68 (TEM-cell method)

V_DD= 3.3 V; T_amb= 25 °C.

Parameter

Frequency band

System

clock =

Unit

12 MHz

24 MHz

36 MHz

48 MHz

Input clock: IRC (12 MHz)

maximum

peak level

1 MHz to 30 MHz

-5

-1

O

-5

0

-5

dBV

-

30 MHz to 150 MHz

+4

O

+4

O

150 MHz to 1 GHz

-

0

IEC level^[1]

O

Input clock: crystal oscillator (12 MHz)

maximum

peak level

1 MHz to 30 MHz

30 MHz to 150 MHz

150 MHz to 1 GHz

-

-2

-1

-2

O



0

-4

-5

dBV

-

+3

+2

O

+3

+5

O

0

IEC level^[1]

O

[1] IEC levels refer to Appendix D in the IEC61967-2 Specification.

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15. Package outline

LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm

SOT313-2

c

y

X

36

25

A

E

37

24

Z

E

e

H

E

A

2

A

(A )

3

A

1

w

p

M

pin 1 index

b

L

p

L

13

48

detail X

1

12

Z

v

M

D

A

e

w

M

b

p

D

B

H

v

B

D

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

D

H

L

v

w

y

Z

E

1

2

3

p

E

p

D

max.

7^o

0^o

0.20 1.45

0.05 1.35

0.27 0.18 7.1

0.17 0.12 6.9

7.1

6.9

9.15 9.15

8.85 8.85

0.75

0.45

0.95 0.95

0.55 0.55

1.6

mm

0.25

0.5

1

0.2 0.12 0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

00-01-19

03-02-25

SOT313-2

136E05

MS-026

Fig 45. Package outline LQFP48 (SOT313-2)

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LPC11U6x

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LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm

SOT314-2

y

X

A

48

33

Z

49

32

E

e

H

A

E

2

E

A

(A )

3

A

1

w M

p

b

L

p

pin 1 index

L

64

17

detail X

1

16

Z

v

M

A

D

e

w M

b

p

D

B

H

v

M

B

D

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

L

v

w

y

Z

E

1

2

3

p

D

E

p

D

max.

7^o

0^o

0.20 1.45

0.05 1.35

0.27 0.18 10.1 10.1

0.17 0.12 9.9 9.9

12.15 12.15

11.85 11.85

0.75

0.45

1.45 1.45

1.05 1.05

1.6

mm

0.25

0.5

1

0.2 0.12 0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

00-01-19

03-02-25

SOT314-2

136E10

MS-026

Fig 46. Package outline LQFP64 (SOT314-2)

LPC11U6x

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LPC11U6x

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LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm

SOT407-1

y

X

A

51

75

50

26

(1)

76

Z

E

e

H

A

E

2

E

A

(A )

3

A

1

w M

p

b

L

p

pin 1 index

L

detail X

100

1

25

Z

D

v

M

A

B

e

w M

b

p

D

B

H

v

M

5

D

0

10 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

D

H

L

v

w

y

Z

1

2

3

p

E

p

D

E

max.

7^o

0^o

0.15 1.45

0.05 1.35

0.27 0.20 14.1 14.1

0.17 0.09 13.9 13.9

16.25 16.25

15.75 15.75

0.75

0.45

1.15 1.15

0.85 0.85

mm

1.6

0.25

0.5

1

0.2 0.08 0.08

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

00-02-01

03-02-20

SOT407-1

136E20

MS-026

Fig 47. Package outline LQFP100 (SOT407-1)

LPC11U6x

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16. Soldering

Footprint information for reflow soldering of LQFP48 package

SOT313-2

Hx

Gx

(0.125)

P2

P1

Hy Gy

By

Ay

C

D2 (8 )

D1

Bx

Ax

Generic footprint pattern

Refer to the package outline drawing for actual layout

solder land

occupied area

DIMENSIONS in mm

P1 P2 Ax

Ay

Bx

By

C

D1

D2

Gx

Gy

Hx

Hy

0.500 0.560 10.350 10.350 7.350 7.350 1.500 0.280 0.500 7.500 7.500 10.650 10.650

sot313-2_fr

Fig 48. Reflow soldering for the LQFP48 package

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Footprint information for reflow soldering of LQFP64 package

SOT314-2

Hx

Gx

(0.125)

P2

P1

Hy Gy

By

Ay

C

D2 (8 )

D1

Bx

Ax

Generic footprint pattern

Refer to the package outline drawing for actual layout

solder land

occupied area

DIMENSIONS in mm

P1 P2 Ax

Ay

Bx

By

C

D1

D2

Gx

Gy

Hx

Hy

0.500 0.560 13.300 13.300 10.300 10.300 1.500 0.280 0.400 10.500 10.500 13.550 13.550

sot314-2_fr

Fig 49. Reflow soldering for the LQFP64 package

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Footprint information for reflow soldering of LQFP100 package

SOT407-1

Hx

Gx

(0.125)

P2

P1

Hy Gy

By

Ay

C

D2 (8 )

D1

Bx

Ax

Generic footprint pattern

Refer to the package outline drawing for actual layout

solder land

occupied area

DIMENSIONS in mm

P1 P2 Ax

Ay

Bx

By

C

D1

D2

Gx

Gy

Hx

Hy

0.500 0.560 17.300 17.300 14.300 14.300 1.500 0.280 0.400 14.500 14.500 17.550 17.550

sot407-1

Fig 50. Reflow soldering for the LQFP100 package

LPC11U6x

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Product data sheet

Rev. 1.5 — 12 August 2020

91 of 97

LPC11U6x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

17. References

[1] LPC11U6x User manual UM10732:

http://www.nxp.com/documents/user_manual/UM10732.pdf

[2] LPC11U6x Errata sheet:

http://www.nxp.com/documents/errata_sheet/ES_LPC11U6X.pdf

[3] Technical note ADC design guidelines:

http://www.nxp.com/documents/technical_note/TN00009.pdf

LPC11U6x

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Product data sheet

Rev. 1.5 — 12 August 2020

92 of 97

LPC11U6x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

18. Revision history

Table 31. Revision history

Document ID

Release date

Data sheet status

Change notice Supersedes

LPC11U6x v.1.5

20200812

Product data sheet

-

LPC11U6x v.1.4

Modifications:

• Updated Section 14.5 “RTC oscillator component selection” with minor wording

alteration.

LPC11U6x v.1.4

Modifications:

20200724

Product data sheet

-

LPC11U6x v.1.3

• Updated Section 14.6 “RTC oscillator component selection” with frequency

recommendation.

LPC11U6x v.1.3

Modifications:

20160906

Product data sheet

-

LPC11U6x v.1.2

• Section 14.10 “ElectroMagnetic Compatibility (EMC)” added.

• Replaced CT16B0_CAP1 with CT16B0_CAP2 for pin PI01_21. See Table 3 “Pin

description”.

• Replaced CT32B0_CAP1 with CT32B0_CAP2 for pin PIO1_6 and pin PIO1_29. See

Table 3 “Pin description”.

• Updated Figure 7 “AHB multilayer matrix”: HS GPIO connects with M0+ Core, not with

DMA or USB.

LPC11U6x v.1.2

Modifications:

20140526

Product data sheet

-

LPC11U6x v.1.1

• Part marking updated with revision indicator.

• Changed recommendation for VBAT connection if unused: Tie to VDD. See Table 3

“Pin description”.

• Section 14.7 “Connecting power, clocks, and debug functions” added.

• Section 14.9 “Pin states in different power modes” added.

• Remark added about using the regulator in the USB bus-powered set-up. See Section

14.3 “Suggested USB interface solutions”.

• Figure 39 “USB interface on a bus-powered device” changed to show USB_VBUS

connection to part.

• Parts added: LPC11U67JBD100, LPC11U67JBD64, LPC11U66JBD48.

LPC11U6x v.1.1

Modifications:

20140312

Product data sheet

-

LPC11U6x v.1

• Parameter R_Irenamed to Z_I(input impedance) in Table 22.

• Description of the internal USB_CONNECT function clarified in Section 14.3

“Suggested USB interface solutions”. The USB_CONNECT function can be set

internally by software and does not require external circuitry.

• Parameter Cia corrected in Table 22 “12-bit ADC static characteristics”.

• Figure 36 “ADC input impedance” added.

• Parameter pin capacitance added in Table 8.

• Pin description for VBAT updated: If no battery is used, tie VBAT to VDD or to ground.

See Table 3.

• Pin description for RESET/PIO0_0 updated: In deep power-down mode, this pin must

be pulled HIGH externally. The RESET pin can be left unconnected or be used as a

GPIO pin if an external RESET function is not needed. See Table 3.

• Pin functions TMS, TDI, TDO, and TRST changed to default function in Table 3.

• Pin description table updated for clarity (VBAT, I2C-bus pins, WAKEUP pin).

• Section 14.1 “ADC usage notes” added.

• Use of USB_CONNECT signal explained when VBUS is not connected. See

Section 14.3.

LPC11U6x v.1

20140117

Product data sheet

-

LPC11U6x

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Product data sheet

Rev. 1.5 — 12 August 2020

93 of 97

LPC11U6x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

19. Legal information

19.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

Suitability for use — NXP Semiconductors products are not designed,

19.2 Definitions

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer’s own

risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

19.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

LPC11U6x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.5 — 12 August 2020

94 of 97

LPC11U6x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

19.4 Trademarks

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

I²C-bus — logo is a trademark of NXP Semiconductors N.V.

20. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

LPC11U6x

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Product data sheet

Rev. 1.5 — 12 August 2020

95 of 97

LPC11U6x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

21. Contents

1

General description . . . . . . . . . . . . . . . . . . . . . . 1

8.19.1.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

8.19.2

General purpose external event counter/timers

(CT32B0/1 and CT16B0/1) . . . . . . . . . . . . . . 33

2

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Ordering information. . . . . . . . . . . . . . . . . . . . . 4

Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4

Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3

8.19.2.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

8.20

8.21

8.21.1

8.22

8.22.1

8.23

8.23.1

8.24

4

4.1

5

System tick timer (SysTick) . . . . . . . . . . . . . . 33

Windowed WatchDog Timer (WWDT) . . . . . . 33

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Real-Time Clock (RTC) . . . . . . . . . . . . . . . . . 34

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Analog-to-Digital Converter (ADC). . . . . . . . . 34

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Temperature sensor . . . . . . . . . . . . . . . . . . . . 35

Clocking and power control . . . . . . . . . . . . . . 36

Clock generation . . . . . . . . . . . . . . . . . . . . . . 36

Power domains . . . . . . . . . . . . . . . . . . . . . . . 37

Integrated oscillators . . . . . . . . . . . . . . . . . . . 37

6

7

7.1

7.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 7

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 9

8

8.1

8.2

8.3

8.4

8.5

8.6

8.7

Functional description . . . . . . . . . . . . . . . . . . 19

ARM Cortex-M0+ core . . . . . . . . . . . . . . . . . . 19

AHB multilayer matrix . . . . . . . . . . . . . . . . . . . 19

On-chip flash programming memory . . . . . . . 21

EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

On-chip ROM . . . . . . . . . . . . . . . . . . . . . . . . . 21

Memory mapping . . . . . . . . . . . . . . . . . . . . . . 21

Nested Vectored Interrupt Controller (NVIC) . 22

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 23

IOCON block. . . . . . . . . . . . . . . . . . . . . . . . . . 23

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Standard I/O pad configuration. . . . . . . . . . . . 24

Fast General-Purpose parallel I/O (GPIO) . . . 24

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Pin interrupt/pattern match engine . . . . . . . . . 25

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

GPIO group interrupts. . . . . . . . . . . . . . . . . . . 26

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

DMA controller . . . . . . . . . . . . . . . . . . . . . . . . 26

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

USB interface . . . . . . . . . . . . . . . . . . . . . . . . . 27

Full-speed USB device controller . . . . . . . . . . 27

8.25

8.25.1

8.25.2

8.25.3

8.25.3.1 Internal RC oscillator . . . . . . . . . . . . . . . . . . . 38

8.25.3.2 System oscillator . . . . . . . . . . . . . . . . . . . . . . 38

8.25.3.3 WatchDog oscillator . . . . . . . . . . . . . . . . . . . . 38

8.25.3.4 RTC oscillator. . . . . . . . . . . . . . . . . . . . . . . . . 38

8.25.4

8.25.5

8.25.6

8.25.7

8.25.7.1 Power profiles . . . . . . . . . . . . . . . . . . . . . . . . 39

8.25.7.2 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8.25.7.3 Deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 40

8.25.7.4 Power-down mode . . . . . . . . . . . . . . . . . . . . . 40

8.25.7.5 Deep power-down mode . . . . . . . . . . . . . . . . 40

8.8

System PLL and USB PLL . . . . . . . . . . . . . . . 38

Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Wake-up process . . . . . . . . . . . . . . . . . . . . . . 39

Power control . . . . . . . . . . . . . . . . . . . . . . . . . 39

8.8.1

8.8.2

8.9

8.9.1

8.9.2

8.10

8.10.1

8.11

8.11.1

8.12

8.12.1

8.13

8.13.1

8.14

8.14.1

8.26

System control . . . . . . . . . . . . . . . . . . . . . . . . 40

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Brownout detection . . . . . . . . . . . . . . . . . . . . 41

Code security (Code Read Protection - CRP) 41

Emulation and debugging . . . . . . . . . . . . . . . 43

8.26.1

8.26.2

8.26.3

8.27

9

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 44

Thermal characteristics . . . . . . . . . . . . . . . . . 45

10

8.14.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

8.15

8.15.1

8.16

8.16.1

8.17

8.17.1

8.18

8.18.1

8.19

8.19.1

USART0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

USART1/2/3/4. . . . . . . . . . . . . . . . . . . . . . . . . 28

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

SSP serial I/O controller (SSP0/1) . . . . . . . . . 29

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

I²C-bus serial I/O controller . . . . . . . . . . . . . . 29

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Timer/PWM subsystem. . . . . . . . . . . . . . . . . . 30

State Configurable Timers (SCTimer0/PWM and

SCTimer1/PWM). . . . . . . . . . . . . . . . . . . . . . . 31

11

Static characteristics . . . . . . . . . . . . . . . . . . . 46

Power consumption . . . . . . . . . . . . . . . . . . . . 52

CoreMark data . . . . . . . . . . . . . . . . . . . . . . . . 56

Peripheral power consumption. . . . . . . . . . . . 57

Electrical pin characteristics. . . . . . . . . . . . . . 59

11.1

11.2

11.3

11.4

12

Dynamic characteristics. . . . . . . . . . . . . . . . . 62

Flash/EEPROM memory . . . . . . . . . . . . . . . . 62

External clock for the oscillator in slave mode 62

Internal oscillators . . . . . . . . . . . . . . . . . . . . . 63

I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

I²C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

12.1

12.2

12.3

12.4

12.5

continued >>

LPC11U6x

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Product data sheet

Rev. 1.5 — 12 August 2020

96 of 97

LPC11U6x

NXP Semiconductors

32-bit ARM Cortex-M0+ microcontroller

12.6

12.7

12.8

SSP interface . . . . . . . . . . . . . . . . . . . . . . . . . 66

USART interface. . . . . . . . . . . . . . . . . . . . . . . 68

SCTimer/PWM output timing . . . . . . . . . . . . . 69

13

Characteristics of analog peripherals . . . . . . 70

14

Application information. . . . . . . . . . . . . . . . . . 75

ADC usage notes . . . . . . . . . . . . . . . . . . . . . . 75

Typical wake-up times . . . . . . . . . . . . . . . . . . 75

Suggested USB interface solutions . . . . . . . . 75

USB Low-speed operation . . . . . . . . . . . . . . . 77

XTAL input and crystal oscillator component

selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

XTAL Printed-Circuit Board (PCB) layout

14.1

14.2

14.3

14.3.1

14.4

14.5

guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

RTC oscillator component selection . . . . . . . . 81

Connecting power, clocks, and debug functions. .

81

14.6

14.7

14.8

14.9

14.10

Termination of unused pins. . . . . . . . . . . . . . . 83

Pin states in different power modes . . . . . . . . 84

ElectroMagnetic Compatibility (EMC). . . . . . . 85

15

16

17

18

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 86

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 93

19

Legal information. . . . . . . . . . . . . . . . . . . . . . . 94

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 94

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 95

19.1

19.2

19.3

19.4

20

21

Contact information. . . . . . . . . . . . . . . . . . . . . 95

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 12 August 2020

Document identifier: LPC11U6x


型号：	LPC11U6X
厂家：	NXP
描述：	32-bit ARM Cortex-M0 microcontroller; up to 256 KB flash and 36 KB SRAM; 4 KB EEPROM; USB; 12-bit ADC 可编程只读存储器电动程控只读存储器电可擦编程只读存储器静态存储器
文件：	总97页 (文件大小：3036K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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